The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since none of these
are used in multiple places, we can get rid of the names.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's not stricly related to spinlocks. If defined, a better
location should be found and the name collisions with other
barrier() defined in nb/intel solved.
Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not related to spinlocks and the actual implementation
was also guarded by CONFIG(SMP).
With a single call-site in x86-specific code, empty stubs
for other arch are currently not necessary.
Also drop an unused included on a nearby line.
Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.
BUG=b:161923068
Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the binary layout of this struct matters, it should be marked as
packed. Since all struct elements are uint8_t, this shouldn't result in
a different layout though.
BUG=b:161923068
Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.
BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.
Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With the updated FSP UPD headers there are enough DXIO descriptor slots
in the UPD, so we can now add asserts to make sure that the mainboard
doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This
is part of the DXIO/DDI descriptor handling cleanup.
BUG=b:158695393
Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY`
to use `GPIO_INT_ENABLE_DELIVERY` instead of
`GPIO_INT_ENABLE_STATUS_DELIVERY`.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I64d912200779875cf121cec4476fd39de74c0223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.
Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Looks like some preparation is needed before reset. However, Picasso
also needs some special handling and still selects this option without
selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now.
Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PM2_CNT register block is no longer needed, as explained in some
comments. While they may have been copy-pasted around a lot, they are at
least true for Hudson, and it makes sense to assume that they are true
for newer chipsets as well. As per the ACPI specification, version 6.3,
section 4.8.1.3 (PM2 Control Register):
This register block is optional, if not supported its block pointer and
length contain a value of zero.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.
Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):
If the PM1b_EVT_BLK is not supported, its pointer contains a value of
zero in the FADT.
If the PM1b_CNT_BLK is not supported, its pointer contains a value of
zero in the FADT.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:
If a generic register block is not supported then its respective
block pointer and block length values in the FADT table contain zeros.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2S machine device has its own driver now. So, this change drops the
support for adding I2S machine device ACPI node from ACP driver.
BUG=b:157708581
Change-Id: I9069d92ae991e05fddcc7d45a2fd21e98c3b0de8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a macro `PAD_NC` for configuring no-connect pads. This
configures the pad as input with pull-down.
Change-Id: I47c41c88ccfebe2c5dd9a24f85a120af9c8f56b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change drops _INI and OSFL methods under \_SB since they are not doing
anything useful. _INI only calls OSFL and OSFL initializes OSVR if not
already initialized and returns OSVR value. However, OSVR is not used
anywhere and hence both these functions can be dropped.
BUG=b:153879530
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f3e1c93a855006cc115087fded20bfb76c1133e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43515
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Global variable `PMOD` that stores the interrupt mode used by OS is
required by all mainboards. This change moves the variable definition to
globalnvs.asl under picasso.
Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC
until _PIC() method is called by OS. Thus, this change also updates the
default value of PMOD as 0 i.e. PIC mode.
BUG=b:153879530
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I731c03d965882281a7a23f55894451210ba72274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of
a write operation since the other bits in the register are reserved.
Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN
using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable`
in the devicetree. This is required to get I2S_Wake event on headset jack
plug/unplug when using CODEC_GPI pad.
BUG=b:146317284,b:161328042
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 56da63c3dc removed overriding that
field in the FADT.
Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the code and data in psp_verstage is ~59K. Adding the code
to save vbnv to the SPI rom increases that to 66K.
Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to.
BUG=b:161366241
TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This
function call in picasso does not do anything and hence is being dropped.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.
BUG=b:158695393
TEST=Mandolin still boots.
Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This provides the functionality to provide the GPE to the pci_xhci
driver.
BUG=b:154756391, b:160651028
TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and
verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is now a generic xhci driver we can use to generate the xHCI ACPI
nodes.
BUG=b:154756391
TEST=Boot trembyle and look at ACPI table
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Data fabric devices are PCI devices which support PCI configuration
space but do not require any MMIO/IO resources. This change adds a PCI
driver for the data fabric devices which only provides device
operations for adding node to SSDT and returning the ACPI name for the
device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a driver pcie_gpp.c which provides device_operations
for external and internal PCIe GPP bridges. These device operations
include standard PCI bridge operations as well as operations for
generating ACPI node for the device and returning appropriate ACPI
name for it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When entering S3, zork shuts down the i2c controllers to save power.
On resume, we need to re-enable i2c before accessing them, so we need
to map the AOAC registers in verstage.
BUG=b:160834101
TEST=psp_verstage works after resume.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it
there. The soc/amd/* code itself uses the bit definition when accessing
HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition.
Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR,
since that bit isn't in that MSR.
TEST=Checked the code and the corresponding BKDG/PPR.
Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The kernel requires the display oprom is loaded and ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:160560510
TEST=Boot Trembyle in developer mode and normal mode
Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Remove I2C4 since it is a slave device used for USB-C mux control
and should not be included with the other master devices.
BUG=b:160624619 b:160292546
TEST=EC can communicate with AP mux I2C4 slave
Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing. Add dummy spinlock code as the spinlocks
aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the APOB size & base generation the same as all the other command
line arguments to amdfwtool.
BUG=None
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id78383d87bc98dd2c859c75585266411c226f950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This was specifically needed for vboot with psp_verstage, but adding
it to always be built into bootblock if needed like memcpy & memset
makes sense.
TEST=Build & boot trembyle
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Check for the workbuf in bootblock if psp_verstage is being used.
BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can't set the SMI or SCI flags in psp verstage, so skip them.
TEST=Build
BUG=b:154142138
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings. When these are moved to the RW-A & RW-B
regions, the packages need to be recreated for the new addresses.
TEST=Build & boot trembyle. See that we're booting from the correct
region.
BUG=b:158124527
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds the psp_verstage userspace application and the location of
the shared memory area to the amdfw binary tables.
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP. It does a minimal setup of hardware,
then runs verstage_main. It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.
BUG=b:158124527
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.
BUG=b:156315391
TEST=Build, verified the tuning value been applied on Trembyle.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The bootblock must be 16-bit aligned for it to boot.
BUG=b:159081993
TEST=Made sure trembyle still compiles.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Skip sending MboxBiosCmdSxInfo for sleep states other than S3. The
PSP only acts on S3 and ignores all others. As a result, the command
register is not cleared upon return and coreboot reports a timeout.
BUG=b:153622879
TEST=Use halt from command line, verify command skipped.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
eSPI interrupts are active level high. The eSPI polarity register
in the chipset inverts incoming signals if the corresonding bit
is 0 in the register. Therefore, all active high (edge or level)
virtual wire interrupts need to ensure they are not inverted.
And really the sender of the interrupts should be conforming to the
the eSPI spec. As such inverting any signals should not be necessary,
but this register in the chipset allows for fixing up those misbehaviors.
BUG=b:157984427
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds support in ACP device driver to generate I2S machine
device (AMDI5682) in SSDT. It expects mainboard to provide chip config
`dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the
device.
BUG=b:157603026
TEST=Verified that I2S machine device is correctly generated for
trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252557
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ACPI code was not masking off the correct bits for publishing
the SPI bar to the OS.
It resulted in a dmesg messagelike:
system 00:00: [mem 0xfec10002-0xfec11001] has been reserved
And /proc/iomem entry
fec10002-fec11001 : pnp 00:00
These addresses are wrong because they are including bits of a
register that are not a part of the address.
Moreover, the code does not publish the eSPI register area either.
The eSPI registers live at 0x10000 added to the SPI bar. Lastly,
both regions are less than a page so only report a page of usage
for each.
Stoney Ridge's SPI bar register defines the address as 31:6 while
Picasso's SPI bar register defines the address as 31:8. Use Picasso's
valid mask for both cases because no one is assigning addresses
that are aligned to less than 256 bytes.
With the fixes, dmesg reports:
system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved
system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved
And /proc/iomem indicates:
fec10000-fec10fff : pnp 00:00
fec20000-fec20fff : pnp 00:00
BUG=b:160290629
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42959
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change clears interrupt and wake status for a pad when
configuring it. This ensures that stale interrupts/wake notifications
are flushed out and do not cause spurious wakes in future suspends.
BUG=b:159944426
Change-Id: Ia4ebd975312a4136f1d0690d7af7372615e31f0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`flags` field of soc_amd_gpio structure is set only for SCI and SMI
configurations. This change adds a new helper macro
PAD_CFG_STRUCT_FLAGS that allows setting of all soc_amd_gpio members
including `flags` field. This can be used directly by PAD_SCI and
PAD_SMI. For all other pad configurations, PAD_CFG_STRUCT macro uses
PAD_CFG_STRUCT_FLAGS with flags set to 0. This allows dropping of
redundant parameter 0 for flags for all other pad configurations.
BUG=b:159944426
Change-Id: I835b62f5502375ffc4215548b51338a67546d699
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, for Stoneyridge and Picasso mainboards, pads that are
configured for SCI/SMI/WAKE need to have multiple entries in the
configuration table - one for PAD_GPI and other for the special
configuration that is required. This requires a very specific ordering
of pads within the table and is prone to errors because of conflicting
params provided to the different entries for the same pad. This also
does not work very well with the concept of override GPIOs where the
entry in base table is overridden with the first matched entry from
the override table.
This change updates the way GPIO configuration is handled for special
routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of
soc_amd_gpio structure in the macros performing these
configurations. Also, program_gpios() is updated to perform a write to
GPIO control register instead of read-modify-write. This is because
mainboard is expected to provide only a single configuration entry for
each pad within a given table. Thus, there is no need to preserve
earlier configuration.
Mainboards that were providing multiple entries for a single pad are
updated accordingly.
BUG=b:159944426
Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some codepaths want to set selected bits of a hardware register
to match those of a given variable in memory. Provide a helper
function for this purpose and use it in gpio_set(),
gpio_input_pulldown() and gpio_input_pullup().
This change also adds GPIO_PULL_MASK and updates GPIO_OUTPUT_MASK to
include all bits dealing with pull and output respectively.
Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds helper macro PAD_CFG_STRUCT for setting the fields
of `soc_amd_gpio`. Additionally, macros are added for different
operations i.e. pull, output, trigger, int_enable, event_trigger,
wake_enable, debounce, etc. All GPIO configuration macros are updated
to use PAD_CFG_STRUCT instead of setting the fields directly.
BUG=b:159944426
Change-Id: I03535d2da0c05f72c4163fa30d72f9c6df44908b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42872
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the macros for GPIO debounce to add _DEB_ in the
name. This is done to make the names consistent with rest of the GPIO
control field names.
BUG=b:159944426
Change-Id: Ic47678108c871c5f1cd0d512783230f18adf3484
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change renames GPIO macros as follows:
1. Pad filtering macros are renamed to GPIO_TRIGGER_ and
GPIO_ACTIVE_. This determines the filtering applied on the input
signal at the pad.
2. Interrupt enabling macros are renamed to GPIO_INT_ENABLE_.
_INT_ is dropped from pad filtering macros because the filtering
applies to the input signal irrespective of how it is routed. It is
applied at the pad not only for GPIO interrupts but also for other
routes i.e. SCI, SMI, etc.
BUG=b:159944426
Change-Id: Id0ad770be77409aaaae4cc135945e2815ce97030
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42870
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`soc_amd_gpio` structure uses a flag field to store additional
information about GPIO configuration that does not end up directly in
the GPIO control register. However, the naming for these flags is not
consistent across event triggers and special configurations. This
change updates the flag names to be consistent (starting with
GPIO_FLAG_*) and adds some helper functions for GPIO events.
In the following CLs, more changes will be made to drop some of the
special flags which are not really required.
BUG=b:159944426
Change-Id: Idca795c3e594eb956d297d5ba5d08f75b5563ee5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42869
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no GPIO_63 but the register position is used for
interrupt controls.
Change-Id: I754a2f6bbee12d637f8c99a9d330ab0ac8187247
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42686
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The banks are one after each other in the ACPIMMIO space. Also
there is space for more banks and existing ASL takes advantage
of the property.
Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Future implementation of verstage running on PSP will have access
to some of the ACPIMMIO banks, but banks will be mapped runtime
at non-deterministic addresses. Provide preprocessor helpers to
accomplish this.
Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.
Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort
connectivity. While Dali can either be fused-down PCO or RV2 silicon,
Pollock is always RV2 silicon.
Since we have all boards using this code in tree right now,
soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku().
Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 4883252912.
Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as
it does not have the same view of memory space.
The prototypes xx_set/get_bar() are only valid for PSP as x86 cores
will use the constant mapping defined in <amdblocks/acpimmio_map.h>
The selected MMIO base address model depends of the architecture the
stage is built for and, to current knowledge, nothing else. So
the guards should have been with ENV_X86 vs ENV_ARM and not about
CONFIG(VERSTAGE_BEFORE_BOOTBLOCK).
For the ENV_ARM stage builds, <arch/io.h> file referenced in the
previously added mmio_util_psp.c file has not been added to the tree.
So there was some out-of-order submitting, which did not get caught
as the build-testing of mixed-arch stages has not been incorporated
into the tree yet.
The previously added file mmio_util_psp.c is also 90% redundant with
mmio_util.c.
Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The host bridge's resources covering bus numbers assumed
256 buses were being decoded. However, MMCONFIG was only
covering 64 buses. This results in Linux complaining:
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000
[bus 00-3f] only partially covers this bridge
When retrieving the host bridge's resources fix up the
bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't
keep IASL from complaining when trying to do this statically.
BUG=b:158874061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
According to the ACPI specification, version 6.3:
OSPM accesses GPE registers through byte
accesses (regardless of their length).
So, reporting dword-sized access is wrong and means nothing anyway.
Tested on Asus P8Z77-V LX2, Windows 10 still boots.
Change-Id: I965131a28f1a385d065c95f286549665c3f9693e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 9550e97 [acpi: correct the processor devices scope] changed
the default CPU scope from _PR to _SB, but the default prefix in
Stoneyridge's Kconfig was missed, leading to ACPI errors for
'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and
eliminate the errors reported in dmesg.
Test: boot Linux w/5.3 kernel on google/liara, check for errors
Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso's BERT region should not have been moved to cbmem in commit
901cb9c "soc/amd/picasso: Move BERT region to cbmem". This
causes an error of "APEI: Can not request [] for APEI BERT registers.
FSP has been modified to set aside a requested region size for BERT,
simiar to TSEG. Remove the cbmem reservation and locate the region
by searching for the HOB.
BUG=b:136987699
TEST=Check that BERT is allocated
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the kernel to runtime suspend these devices and properly
shut them down. If a tty is not used, the kernel will disable the
device.
I omitted UART0 because the PSP will not power the controller before
accessing it. This causes PSP boot failures. See b/158772504. We also
can't enable UART0 D3 until we stop using the mmio kernel command line
`console=uart,mmio32,0xfedc9000`. The kernel will suspend the UART
controller before it notices that the mmio address matches ttyS0. This
causes the kernel to fail writing to the UART. So we need to move over
to `console=ttyS0`.
BUG=b:153001807, b:157617092, b:157858890, b:158772504
TEST=Boot trembyle and see I2C devices entering and exiting D3.
* See the UART devices entering D3
* Made sure the i2c peripherals were still functional.
* Ran suspend stress test for 40+ iterations.
[ 0.349094] power-0362 __acpi_power_on : Power resource [FUR1] turned on
[ 0.350627] power-0362 __acpi_power_on : Power resource [FUR2] turned on
[ 0.352094] power-0362 __acpi_power_on : Power resource [FUR3] turned on
[ 0.353626] power-0362 __acpi_power_on : Power resource [I2C2] turned on
[ 0.376980] power-0362 __acpi_power_on : Power resource [PRIC] turned on
[ 0.399997] power-0362 __acpi_power_on : Power resource [PRIC] turned on
[ 0.401953] power-0362 __acpi_power_on : Power resource [I2C3] turned on
[ 0.403460] power-0362 __acpi_power_on : Power resource [I2C4] turned on
[ 0.483646] power-0418 __acpi_power_off : Power resource [I2C4] turned off
[ 1.028404] power-0418 __acpi_power_off : Power resource [I2C3] turned off
[ 1.448426] power-0418 __acpi_power_off : Power resource [I2C2] turned off
[ 5.308094] power-0418 __acpi_power_off : Power resource [FUR1] turned off
[ 5.340833] power-0418 __acpi_power_off : Power resource [FUR2] turned off
[ 5.382041] power-0418 __acpi_power_off : Power resource [FUR3] turned off
[ 5.423861] power-0362 __acpi_power_on : Power resource [I2C3] turned on
[ 6.698225] power-0362 __acpi_power_on : Power resource [I2C2] turned on
[ 6.856573] power-0418 __acpi_power_off : Power resource [I2C3] turned off
[ 8.246970] power-0418 __acpi_power_off : Power resource [I2C2] turned off
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change selects IDT_IN_EVERY_STAGE so that the interrupt handlers
are provided for all stages.
Change-Id: I25ced7758264fb14998ab5f31ff778c1af11eb05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Most LAPIC registers are 32bit, and thus the use of long is valid on
x86_32, however it doesn't work on x86_64.
* Don't use long as it is 64bit on x86_64, which breaks interrupts
in QEMU and thus SeaBIOS wouldn't time out the boot menu
* Get rid of unused defines
* Get rid of unused atomic xchg code
Tested on QEMU Q35 with x86_64 enabled: Interrupts work again.
Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working.
Tested on Lenovo T410 with x86_64 enabled.
Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are currently relying on the assumption that the amdcompress tool
will zero out the bss section. Instead of relying on this assumption,
lets explicitly clear it.
The implementation was copied from assembly_entry.S.
BUG=b:147042464
TEST=Cold boot trembyle and also s3 resume trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change is required so we have a defined entry point on S3. Without
this, the S3_RESUME_EIP_MSR register could in theory be written to
later which would be a security risk.
BUG=b:147042464
TEST=Resume trembyle and see bootblock start.
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)...
SMI# #6
SMI#: SLP = 0x0c01
Chrome EC: Set SMI mask to 0x0000000000000000
Chrome EC: Set SCI mask to 0x0000000000000000
Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
EC returned error result code 9
SMI#: Entering S3 (Suspend-To-RAM)
PSP: Prepare to enter sleep state 3... OK
SMU: Put system into S3/S4/S5
Timestamp - start of bootblock: 18446744070740509170
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)...
Family_Model: 00810f81
PMxC0 STATUS: 0x200800 SleepReset BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
Timestamp - end of bootblock: 18446744070804450274
VBOOT: Loading verstage.
FMAP: area COREBOOT found @ c75000 (3715072 bytes)
CBFS: Locating 'fallback/verstage'
CBFS: Found @ offset 61b80 size cee4
PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Files are both identical and common for both SoCs.
Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move uart_platform_base and uart_platform_refclk to their own
compilation unit to avoid preprocessor usage. The newly created
compilation unit is only added to the build when PICASSO_CONSOLE_UART
is selected.
Change-Id: I56911addc8c000a0772156e5166720867cdd26fe
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42517
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we are not using the UARTs or they don't have the correct GPIOs
configured we should let the mainboard disable them.
BUG=b:153001807
TEST=Dump SSDT and see UART device is disabled
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The option to have amdfw outside of CBFS used dd to write amdfw at a
given location overwriting anything that was there before, which may
cause the build to fail due to the FMAP header being overwritten
resulting in a not too obvious error that the image is a legacy image
without FMAP header.
Mandolin was the only board using this functionality, but I fixed the
placement of components in the flash image there, so that amdfw can just
be placed in CBFS avoiding those problems.
Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit d5f1e0f973.
Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.
BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.
Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PICASSO_UART Kconfig option is about using the internal MMIO UART
controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART
Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change includes uart.c in bootblock, romstage, ramstage and
verstage unconditionally because this file is handling more than just
the UART console configuration. This allows boards to take advantage
of picasso_uart_mmio_ops even if PICASSO_UART is not selected.
uart_platform_base and uart_platform_refclk mustn't be provided if
PICASSO_UART is unset, so add an #if around those functions.
BUG=b:158346697
TEST=Mandolin builds again.
Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the PSP maps the MMIO addresses that are used to non-
deterministic addresses, the accesses need to be able to find
the address at runtime.
BUG=b:158124527
TEST=Build & boot with Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need
different video BIOSes. This checks the vendor & device IDs along with
the revision and selects the correct video BIOS to use.
Also add the second VGA BIOS for Raven2-based SoCs and change all VGA
BIOS IDs to the format including the revision number.
Since SeaBIOS still expects the CBFS file name without the revision ID,
it won't find the VBIOS any more. As a temporary workaround add the
VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*.
Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2040455
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This way drivers can wait for their devices to be enabled.
I also rewrote enable_aoac_devices to take advantage of
wait_for_aoac_enabled.
BUG=b:153001807
TEST=Trembyle builds
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If the OS sets the target device state to D3, we need to clear it so we
can reestablish register access.
BUG=b:153001807
TEST=Boot trembyle with I2C powered off and see it power back on.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This functionality is needed in the PSP and I can't include all of
southbridge.c.
BUG=b:153001807
TEST=Made sure trembyle still compiles
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3a38c655588d7836e1bd033e958a505774de871e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The legacy UARTs are supposed to default to off according to the
documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0
is enabled after reset. The PSP might be enabling it or the documentation
might be wrong.
Having it enabled causes problems though. We have ACPI nodes defining
MMIO UARTs, and the kernel also probes for legacy UARTs. This results in
two drivers accessing the same device, one via MMIO and one via IO. I
suspect this was the cause of the garbage serial output.
Before the change you would see the following in the console:
[ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A
After this change, we no longer see it.
BUG=b:152079780, b:157858890
TEST=Boot trembyle and make sure serial is still working.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The start and end bus number in the MCFG ACPI table is inclusive.
Therefore, the number of buses decoded needs to be subtracted by
1.
BUG=b:158874061
Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd".
ramstage is 0xffc90 and adding FSP-S (0x50000) failed. Increase the
reserved region of SMRAM to accommodate both images.
BUG=b:158704095
TEST=Boot Mandolin and check console log
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ALIB function 1 needs to be called every time there is a change in
AC/DC state of the system. This change adds a wrapper method that can
be called by PNOT (method to notify system power state change) to
report to ALIB that system power state has changed i.e. AC <-> DC.
Additionally, this change drops the call to ALIB from _INI method
since the PWRS object might not be initialized correctly at that
point. Instead EC makes a call to PNOT when PWRS is initialized.
This wrapper also fixes the value of power state being passed into
ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports
1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state
before passing into ALIB.
BUG=b:157752693
TEST=Verified that WAL1() gets called on AC connect/disconnect.
Steps followed:
$ echo 1 > /sys/module/acpi/parameters/aml_debug_output
$ dmesg -w | grep ACPI
[ 76.306947] ACPI Debug: "EC: AC DISCONNECTED"
[ 76.307064] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01"
[ 82.264946] ACPI Debug: "EC: GOT PD EVENT"
[ 82.539833] ACPI Debug: "EC: GOT PD EVENT"
[ 82.753721] ACPI Debug: "EC: GOT PD EVENT"
[ 82.843676] ACPI Debug: "EC: GOT PD EVENT"
[ 82.970596] ACPI Debug: "EC: AC CONNECTED"
[ 82.970659] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00"
[ 83.047598] ACPI Debug: "EC: GOT PD EVENT"
[ 84.804733] ACPI Debug: "EC: GOT PD EVENT"
[ 86.317934] ACPI Debug: "EC: GOT PD EVENT"
[ 86.385920] ACPI Debug: "EC: GOT PD EVENT"
[ 86.515830] ACPI Debug: "EC: AC DISCONNECTED"
[ 86.515922] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01"
[ 90.089062] ACPI Debug: "EC: GOT PD EVENT"
[ 90.357914] ACPI Debug: "EC: GOT PD EVENT"
[ 90.573812] ACPI Debug: "EC: GOT PD EVENT"
[ 90.662744] ACPI Debug: "EC: GOT PD EVENT"
[ 90.788706] ACPI Debug: "EC: AC CONNECTED"
[ 90.788835] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00"
[ 90.865675] ACPI Debug: "EC: GOT PD EVENT"
[ 92.621793] ACPI Debug: "EC: GOT PD EVENT"
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change updates memlayout.ld for Picasso to place all early
stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot
workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at
the bottom of DRAM starting at 32MiB. This uses static allocation for
most components by defining Kconfig variables for base and size. It
relies on the linker to complain if any of the assumptions are broken.
This also allows romstage to use linker symbols for
_early_reserved_dram and _eearly_reserved_dram to store information in
CBMEM about the early DRAM usage by coreboot before ramstage starts
execution. This allows ramstage to reserve this memory region in BIOS
tables so that S3 resume can reuse the same space without corrupting
OS memory.
BUG=b:155322763
TEST=Verified memory reported by coreboot:
Writing coreboot table at 0xcc656000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000001ffffff: RAM
4. 0000000002000000-000000000223ffff: RESERVED
5. 0000000002240000-00000000cc512fff: RAM
6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES
7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE
8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES
9. 00000000cd800000-00000000cfffffff: RESERVED
10. 00000000f8000000-00000000fbffffff: RESERVED
11. 0000000100000000-000000042f33ffff: RAM
12. 000000042f340000-000000042fffffff: RESERVED
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change copies src/arch/x86/memlayout.ld file to
src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to
point to this newly added file. Unused elements from the memlayout.ld
file are dropped and path to early_dram.ld is updated to include the
one from src/arch/x86.
BUG=b:155322763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change reconfigures SPI speeds after FSP-S has run since
FSP-S is currently configuring the SPI frequency when it should
not. Until FSP-S behavior is fixed, this workaround needs to be
applied.
BUG=b:153506142
TEST=Verified that em100 works fine.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor
structs isn't needed, since this code is picasso-specific, so drop it.
Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Combine the Ucode binaries for 3 revisions of CPU into one
CBFS module.
This should be moved to the AMD common code later.
BUG=b:153580119
TEST=mandolin
Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso doesn't really make use of the common mrc_cache driver because
of the PSP/ABL requirements for APOB NV data. The APOB NV data
gets consumed by PSP/ABLs before x86 comes out of reset. Hence, we cannot
really add any metadata to this saved data or use multiple slots as
done by the default MRC cache driver
(CACHE_MRC_SETTINGS). Additionally, FSP-M requires access to this APOB
NV data which coreboot needs to pass in from different locations
depending upon boot mode:
1. Non-S3 boot: PSP/ABLs store APOB NV data in DRAM at predetermined
location which is present in BIOS directory table.
2. S3 boot: PSP/ABLs do not store APOB NV data in DRAM.
Thus, coreboot needs to set FSP-M UPD NvsBufferPtr as the DRAM
location in non-S3 boot and the address of RW_MRC_CACHE on SPI flash
in case of S3 resume.
This change enables MRC cache support in Picasso in order to meet the
above requirements.
1. NvsBufferPtr is set based on boot mode.
2. APOB NV data is not stashed to CBMEM. Instead it is written right
away to SPI flash in romstage.
BUG=b:155990176
Change-Id: I8661a4cf2d34502967e936bf22a13f6f1b88e544
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The ACP device sits behind a bridge. Despite the logs indicating
the bridge is likely hooked up, there's some unusual behavior of
writes not sticking. Aside from the speculation of what's causing
the issues the initialization of the device should occur at init()
because of these potential dependencies.
BUG=b:155882600
Change-Id: I8fa83d7d1d4f356c56971d4175a2ae6497a92fb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42231
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting preferred_pm_profile under sb/ or soc/ overrides the
default determined from SYSTEM_TYPE_xx (or possibly
SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable.
With the overrides removed, AMD platforms will switch from
PM_UNSPECIFIED to PM_DESKTOP as their preferred profile.
Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide
board-specific mainboard_fill_fadt() should they need to change this.
As they already select SYSTEM_TYPE_LAPTOP, following boards
will change to PM_MOBILE:
google/kahlee
hp/pavilion_m6_1035dx
lenovo/g505s
Change-Id: I45c4a495a4bf3422adae9e22a6e436adef252e77
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Use a local variable for the ResourceTemplate in the _CRS methods
instead of the RBUF object. When using RBUF, iasl complained that the
_CRS methods need to be serialized, since objects were created in there.
Since those are only used as local variables, just use local variables
for this.
TEST=iasl stops complaining about those methods not being serialized and
Linux still boots and there aren't any related ACPI errors or warnings.
Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use x86_setup_mtrrs_with_detect_no_above_4gb() to only
solve the MTRR solution for memory up to 4GiB. This assumes
4GiB to TOM2 is marked as writeback in sys_cfg MSR.
BUG=b:155426691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41898
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AGESA FSP-M implementation is now not updating MTRRs out from
under the caller. As such, remove the save/restore of MTRRs
from the FSP-M call.
BUG=b:155426691
Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The PSP does the memory training and setting up of MSRs for
TOP_MEM and TOM2. Set caching up for all the DRAM areas:
Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2.
Enable WC caching fro 0->1MiB except 0xa0000->0xc0000.
BUG=b:155426691
Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
While working on psp_verstage, I noticed that this file had a number of
unnecessary includes. Remove them.
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I32188e2dda39ece9dc98d0344824d997a2e80303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change adds device_operations for UART MMIO devices that provides
following operations:
1. uart_acpi_name: Returns ACPI name of UART device. Generation of
UART device node is not yet moved to SSDT, but will be done in
follow-up CLs.
2. scan_bus: Uses scan_static_bus to scan devices added under the UART
devices. This allows mainboard to add devices under the UART MMIO
device.
Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is a standard MSR. No reason for picasso to define its own.
BUG=b:147042464
TEST=Boot to OS on trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We don't use amd_setup_mtrrs, bsp_topmem or bsp_topmem2 in picasso.
BUG=b:147042464
TEST=Boot to OS on trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1941934975dfea4f189347811b003a33996c887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Advertising SMI triggers in FADT is only valid if we exit with
SMI installed. There has been some experiments to delay SMM
installation to OS, yet there are new platforms that allow some
configuration access only to be done inside SMM.
Splitting static HAVE_SMI_HANDLER variable helps to manage cases
where SMM might be both installed and cleared prior to entering
payload.
Change-Id: Iad92c4a180524e15199633693446a087787ad3a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but
turned out to be correct.
Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
