Commit graph

1971 commits

Author SHA1 Message Date
Lean Sheng Tan
e9ee4390a5 soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipset
Further add initial silicon UPD settings for:
- graphics & display
- chipset lockdown
- PAVP
- legacy timer
- PCH master gating control
- HECI

This CL also enables HECI 1 in devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-06-04 03:45:43 +00:00
Bernardo Perez Priego
ea8a6a2ba2 mb/intel/adlrvp_m: Enable LTR for PCIE
BUG=none
TEST=Use command $ lspci -vv
     LTR+ is listed on DevCtl2

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492
Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01 23:03:35 +00:00
Tan, Lean Sheng
09133c78dd soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
Add Silicon upd settings for LPSS (GSPI/UART/I2C).

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-06-01 05:58:39 +00:00
Bora Guvendik
3585dc5be4 mb/intel/adlrvp_m: add ec device entry to devicetree
TEST=Boot to OS and verify acpi tables.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-30 20:18:42 +00:00
Tan, Lean Sheng
33f8fc698c soc/intel/elkhartlake: Update FSP-M UPD related configs
Upload the FSP-M UPD configs. This CL also updated the chip.h and
devicetree.cb with the relevant variables and configs.
This CL also updated the GPIO related settings (PMC & SD card) in
devicetree.cb.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-30 20:15:42 +00:00
Bernardo Perez Priego
e3a079cff8 mb/intel/adlrvp_m: Disable unused TBT ports from device tree
These PCIe and DMA ports are not available for adlrvp_m.

BUG=none
TEST=Boot device

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-28 04:53:50 +00:00
Tan, Lean Sheng
6948df1f4f mb/intel/ehlcrb: Upload EHL CRB GPIO configs
Initial upload of the GPIO configs for EHL CRB.
This CL also includes the UART GPIO configs in early GPIO table.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-05-28 04:44:06 +00:00
John Zhao
7e982b1dd9 mb/intel/shadowmountain: Update mainboard properties
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.

BUG=b:186521258
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 21:59:33 +00:00
John Zhao
a7f8fb59e5 mb/intel/shadowmountain: Remove power_gpio from baseboard
Along with upstream kernel for Retimer firmware update, coreboot defines
power control for each DFP respectively under host router. This change
removes the power_gpio from the baseboard. Individual DFPx power_gpio
will be added once the dependent definition is complete.

BUG=b:186521258
TEST=Build image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 21:58:36 +00:00
Angel Pons
c56c723deb mainboard: Use decimal for device lapic 0x0 on
Most boards use `device lapic 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.

Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18 11:42:48 +00:00
Angel Pons
bceea67461 mainboard: Use decimal for device domain 0x0 on
Most boards use `device domain 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.

Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18 11:42:36 +00:00
Angel Pons
d2489ee712 mainboard: Use decimal for device cpu_cluster 0x0 on
Most boards use `device cpu_cluster 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.

Change-Id: I083c8f8e9b38ddcc217dc8bf17ae3c9473ba77e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-18 11:42:21 +00:00
Deepti Deshatty
8e7facf343 soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during
silicon init.
Type-c aux lines DC bias changes are propagated from tigerlake
platform.

TEST=Verified superspeed pendrive detection on coldboot.

Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18 10:09:04 +00:00
Maulik V Vaghela
2b97ea153a mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ec
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps
rebooting with hash error.

Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-18 10:00:35 +00:00
Bora Guvendik
39736253d5 mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12 08:01:19 +00:00
Maulik V Vaghela
01ecb77ef6 mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.

BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board

Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-12 00:51:11 +00:00
Angel Pons
a5c829d4e1 mb/intel/dg41wv/devicetree.cb: Fix up whitespace
Remove a blank line and correct the indentation of another line.

Change-Id: Id66f0a847720713c1d3445ac70a9e075228dfe88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54017
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11 12:52:41 +00:00
Angel Pons
94bbf0efc8 skylake DT/HALO mainboards: Drop SaGv setting
SaGv is only supported on ULT/ULX hardware.

Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-07 20:59:26 +00:00
Maulik V Vaghela
ce6fdd458b mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.

Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07 09:32:26 +00:00
Bernardo Perez Priego
e73e1ce9de mb/intel/adlrvp_m: Disable Type-C xDCI
Disabling this pci 0d.1 device since it is not required.

TEST= Boot to OS.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52744
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 14:36:01 +00:00
Anil Kumar
88dd4f705a mb/intel/adlrvp: Enable support for Chrome OS mode switches
Branch=none
Test=build and boot ADL-M RVP. Test recovery mode using servo command
dut-control power_state:rec

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I771f0ef14b1c273f9d1af22c96de0eabd08e9a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52614
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 20:27:13 +00:00
Arthur Heymans
c8116f6ea0 nb/intel: Don't select VBOOT_SEPARATE_VERSTAGE
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.

Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-05 11:47:15 +00:00
Usha P
24f7d2e80f mb/intel/shadowmountain: Enable early EC Software Sync
BUG=None
TEST=Build and boot to OS on shadowmountain. Ensure that the
EC Software Sync is complete.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-05-05 11:44:44 +00:00
Maulik V Vaghela
e46e740f91 mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd
While building adlrvp board with chromeos.fmd and adding all chromeos
related artifacts, RO region is running out of space. Also, we need
to increase RW region size to accommodate all binaries and artifacts.
Aligning chromeos.fmd with Brya will help in solving this issue, thus
aligning chromeos.fmd with Brya.

BUG=b:184997582
BRANCH=NONE
TEST=Code compiles fine and able to boot adlrvp platform

Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 07:42:51 +00:00
Francois Toguo
7da1c1732a mb/intel/adlrvp: Configure TCSS, BT and WiFi related GPIOs
This CL configures TCSS, BT and WiFi related GPIOs based on schematics.

BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-29 20:19:18 +00:00
Anil Kumar
b46ec389bd mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP
This patch adds UART0 config in early GPIO table

Branch=None
Test=Build coreboot and boot on ADLRVP-M board. Check UART logs

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:24:41 +00:00
Sridhar Siricilla
d742d02fe2 mb/intel/shadowmountain: Enable HECI1 interface
The patch enables HECI1 interface

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia2638559bcaac78d024e35abd09534b61eacb843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-04-23 14:49:31 +00:00
Rizwan Qureshi
9452aab4d3 mb/intel/shadowmountain: Enable RTD3 for SD card
Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and specify the srcclk pin and reset GPIO.

TEST=Tested on shadowmountain platform to ensure the system can enter the
S0ix state and suspend/resume is stable

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23 14:49:09 +00:00
Sumeet R Pawnikar
eb2a784b8b mb/intel/adlrvp: Enable DPTF functionality for adlrvp board
Enable DPTF functionality for Alder Lake based adlrvp board

BRANCH=None
BUG=None
TEST=Built and tested on adlrvp board

Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-23 14:47:32 +00:00
Bora Guvendik
17160ffdb4 mb/intel/adlrvp_m: Enable bluetooth
Enable bluetooth on ADL-M RVPi. Remove 10.2 pci entry
since it is not used anymore.

BUG=none
TEST=Check lsusb to see if BT enumerated.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I39e77dbb619235129ed894d20f24956242de3aa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23 14:07:02 +00:00
Sugnan Prabhu S
50f8b4ebdd soc/intel/alderlake: Add enum for HDA audio configuration
This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.

TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.

Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22 15:59:25 +00:00
Furquan Shaikh
c1c1ba5582 soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.h
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.

This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.

BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.

Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22 15:59:16 +00:00
Angel Pons
5d13e7fdcd soc/intel/alderlake: Drop unused PrmrrSize from devicetree
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.

Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 14:21:56 +00:00
Sridhar Siricilla
72e736d8e8 mb/intel/shadowmountain: Disable GSPI1 interface connected to FPS
The patch disables GSPI1 interface connected to fingerprint scanner since
no plans to enable FPS on Shadowmountain.

TEST=Verified on Shadowmountain

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic693a8c9699d7d1cceef9ca26305cc34498022d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-21 09:11:07 +00:00
Sridhar Siricilla
ba0ab9f1f5 mb/intel/adlrvp: Enable ALC711 over SNDW0
The patch enables ALC711 over SNDW0.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43891b94728c8f2d644e14da11946fea3e4515aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-16 06:43:04 +00:00
Tim Wawrzynczak
7f7c3882a6 dptf: Move platform-specific information to struct dptf_platform_info
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.

Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13 08:22:49 +00:00
Michael Niewöhner
c5f1dc96bf mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.

Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-12 16:52:19 +00:00
Sridhar Siricilla
fce0954f45 mb/intel/shadowmountain: Enable Bluetooth config in the devicetree
The patch enables Bluetooth config in the devicetree and removes
non-existent Bluetooth PCI interface.

TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in
the lsusb ouput.

Output of lsusb:

Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive
Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard
Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub
Bus 003 Device 005: ID 8087:0033 Intel Corp.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 20:23:07 +00:00
Sridhar Siricilla
edc6da2de9 mb/intel/adlrvp: Enable HECI1 communication
The patch enables HECI1 interface to allow OS applications to communicate
with CSE.

BUG=None
TEST=Build and boot ADLRVP. Run lspci and check pcie device (00:16.0)

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-09 06:27:00 +00:00
Arthur Heymans
5fa07217a4 mb/{google/jecht,intel/wtm2}: Remove NOOP APM finalize call
The intel/soc/broadwell smihandler has no handler for this APM call.

Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-09 06:11:19 +00:00
Francois Toguo
a0ca786a6e mb/intel/adlrvp: Update iDisp Link UPD settings
This changes updates the iDisp-Link T-mode to 8T required for ADL-M.
The update is made because the HW on ADL now supports 8T mode.

BUG=None
TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 07:48:10 +00:00
Varshit Pandya
5f74818d39 mb/intel/adlrvp: Enable Camera in ADL-M RVP
1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP

Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC

TEST=Build, Boot and Verify streaming in both Camera

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 07:47:43 +00:00
Aamir Bohra
c63a9fb757 mb/intel/shadowmountain: Add Cr50 support
This patch includes changes to add Cr50 support over GSPI0.

BUG=b:175579964
TEST=Verify TPM init is done and boots to kernel

Change-Id: I33f7427d1675190f65acf14679be93546e6db69a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51086
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 06:53:10 +00:00
Tim Wawrzynczak
a10cc8a98b mb/intel/adlrvp: Update VBT filenames
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.

Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-02 20:47:28 +00:00
Maulik V Vaghela
2d22f82a0c mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5

BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP

Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28 16:01:15 +00:00
Maulik V Vaghela
fb670fee3c mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration
List of changes:
1. Add board Ids for ADL-M LP4 configuration
2. Add spd hex files for LP4 configuration
3. Update memory.c file with correct Dq-dqs and byte mapping for LP4

BUG=None
BRANCH=None
TEST=Build and boot is successful for ADL M LP4 RVP

Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:01:04 +00:00
Varshit Pandya
af53ab38ad mb/intel/adlrvp: Configure GPIOs for ADLRVP-M
List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP

TEST=Able to build ADL-M

Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2021-03-28 16:00:53 +00:00
Sridhar Siricilla
1ea938ca5e mb/intel/shadowwmountain: Enable CSE Lite SKU for shadowmountain
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.

TEST=Verified build for Shadowmountain

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:00:38 +00:00
Sridhar Siricilla
d1150fd6d7 mb/intel/adlrvp: Enable CSE Lite SKU
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.

TEST= Built and booted on ADL-P LP4 RVP

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:00:32 +00:00
Angel Pons
84ec70312e mb/intel/dcp847ske: Drop useless MCHBAR writes
There's no need to write the GDCRTRAININGRESULT registers after raminit.

Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27 18:36:05 +00:00
Subrata Banik
f9650771d3 mb/intel/adlrvp: Allow GPIO PM override to disable dynamic GPIO PM
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.

TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.

Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:23:31 +00:00
V Sowmya
a889e2a337 mb/intel/shadowmountain: Disable the unused CPU PCIe RP
This patch disables the unsued CPU PCIe RP for shadowmountain.

TEST= Boot shadowmountain and verify the device is disabled.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-26 06:27:10 +00:00
Maulik V Vaghela
5504cdb511 mb/intel/adlrvp: Remove static VBT stitching
Currently, we used to stitch extra VBT files to ADLRVP build using
Makefile. With enablement of emerge build, we should be able to
integrate more than 1 VBT binaries using ebuild.

This removing these lines to avoid compilation issues in emerge builds

BUG=None
BRANCH=None
TEST=Check if compilation passes on emerge build. Stitched additional
VBT files using emerge and checked that coreboot picks up correct VBT.

Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-26 06:18:31 +00:00
Subrata Banik
efe858b170 soc/intel/alderlake: Add provision to override Rcomp settings
Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.

Mainboard users can pass required rcomp from memory.c file.

Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.

BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.

Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26 04:53:18 +00:00
Subrata Banik
c8ac8f5ce9 soc/intel/alderlake: Align RcompResistor definition as per MRC
List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.

Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.

2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.

3. Also, update RcompResistor value for ADLRVP.

BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.

Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26 04:52:57 +00:00
Angel Pons
d0f971fe9a nb/intel/haswell: Decouple mainboard USB config from MRC
With this change, only raminit.c uses pei_data.h definitions. With MRC
cornered, making it optional is just a matter of writing a replacement.
USB config definitions will be moved to Lynx Point code in a follow-up.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-25 07:51:38 +00:00
Usha P
f02fa4a1a8 mb/intel/adlrvp: Enable CnviBtAudioOffload
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.

BUG=None
TEST=Verified BT offload working on ADL RVP

Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com>
Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-24 07:52:48 +00:00
Angel Pons
c4ee714881 nb/intel/haswell: Use unshifted SPD addresses in mainboards
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 10:59:26 +00:00
Angel Pons
88f94a9635 lynxpoint/broadwell: Rename LP GPIO config global
Do not use the same name as the non-LP GPIO config. This allows checking
at build-time that a mainboard uses the correct GPIO config format.

Without this commit, there are no build-time errors when using the wrong
format of GPIO config, but there would be undefined behavior at runtime.

Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after
toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the
USB config arrays for asrock/b85m_pro4). In both cases, building failed
because the necessary GPIO config global is not defined, as expected.

Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:26:22 +00:00
Marc Jones
f332e47f56 mainboard/: Register chipset_lockdown on xeon_sp mainboards
Set chipset_lockdown in devicetree for recommended security settings.

Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 16:00:54 +00:00
Angel Pons
90ae08922d nb/intel/haswell: Consolidate memory-down SPD handling
Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.

Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:20:06 +00:00
Julius Werner
a9b44f4c79 spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()
In pursuit of the goal of eliminating the proliferation of raw region
devices to represent CBFS files outside of the CBFS core code, this
patch removes the get_spd_cbfs_rdev() API and instead replaces it with
spd_cbfs_map() which will find and map the SPD file in one go and return
a pointer to the relevant section. (This makes it impossible to unmap
the mapping again, which all but one of the users didn't bother to do
anyway since the API is only used on platforms with memory-mapped
flash. Presumably this will stay that way in the future so this is not
something worth worrying about.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17 08:10:35 +00:00
Sugnan Prabhu S
efe873e633 mb/intel/shadowmountain: Update HDMI audio mode to 8T
This patch sets the HDMI audio mode to 8T as required by the latest FSP
version v2081_02

TEST: HDMI audio codecs detection is failing without this change.

Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17 07:58:38 +00:00
Sugnan Prabhu S
565359fee0 mb/intel/shadowmountain: Disable xDCI
This patch disables the xDCI which is causing PC8 to PC10 state
transitions during sleep.

TEST: Confirmed that the transition is happening with this change.

Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-17 07:58:28 +00:00
Bora Guvendik
9d4d2d014c mb/intel/tglrvp: Enable RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.

BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.

Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15 06:29:56 +00:00
Cliff Huang
3663fb36ec mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.

Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:26:37 +00:00
Cliff Huang
b1a128fc88 mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:24:56 +00:00
Meera Ravindranath
8dffc38f6e mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
Add support to pick the right vbt from cbfs according to
SKU-ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:16:50 +00:00
Aamir Bohra
7f61e5703b mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15 06:09:27 +00:00
Tim Wawrzynczak
8996b277ab mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCES
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:03:55 +00:00
Angel Pons
18edd0008c soc/intel/braswell: Factor out common acpi_fill_madt
Function is identical for all mainboards, so factor it out.

Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 15:41:35 +00:00
Michael Niewöhner
2b5892256c mb/intel/adlrvp: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12 08:47:53 +00:00
V Sowmya
8cb7af8e7c mb/intel/shadowmountain: Enable Type-C subsystem
This patch adds the changes to enable the TCSS.

BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 04:26:39 +00:00
Arthur Heymans
bab7f18a43 mb/*/*: Don't select PCIEXP_HOTPLUG
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.

Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:01:04 +00:00
Arthur Heymans
8eb3a342d1 mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device
Pineview does not support PEG.

Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:00:08 +00:00
Arthur Heymans
0ba27fbc44 mb/intel/d510mo/devicetree.cb: Indent with tabs
This is a cosmetic change.
Make the formatting consistent with the rest of the tree.

Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 08:59:53 +00:00
Angel Pons
6bd99f9ada soc/intel/skylake: Clean up SD GPIO handling
This is to align with newer platforms.

Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:37:36 +00:00
V Sowmya
cfb1bf2275 mb/intel/shadowmountain: Add the ASL code
This reverts commit d510b60f5b.

This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27 09:40:57 +00:00
V Sowmya
ae930d85c2 mb/intel/shadowmountain: Add the ramstage code
This patch includes the ramstage changes for the
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27 09:40:47 +00:00
Joel Kitching
a904fd6173 vboot: update GBB flags to use altfw terminology
As per CL:2641346, update GBB flag names:
  GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW
  GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW

BUG=b:179458327
TEST=make clean && make test-abuild
BRANCH=none

Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27 09:37:49 +00:00
Varshit Pandya
4084702567 mb/intel/adlrvp_m: Add initial code for adl-m variant board
List of changes:
1. Add mainboard Kconfig to Kconfig.name files
2. Handle mainboard names in Kconfig file for adlrvp
3. Created a new devicetree.cb for Adlrvp-m.
3. Add override devicetree for ADL-M RVP.
4. Configure proper PCI and USB ports as per schematics for ADL-M

BUG=None
BRANCH=None
TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec.

Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:30:11 +00:00
Subrata Banik
40f53f4b87 mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-22 07:26:14 +00:00
Angel Pons
2a58e187af mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWN
Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n.

Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-22 07:23:36 +00:00
V Sowmya
738aaa24d3 mb/intel/shadowmountain: Add the romstage code
This patch includes the romstage changes for the
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 05:46:58 +00:00
Patrick Georgi
71555955e9 mb: guard irq_tables for clang-format
Some (notably older Intel) boards use a tabular description of irq
routing that we want to keep pristine no matter what clang-format
considers correct (as that's ugly).

Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-17 11:34:27 +00:00
Subrata Banik
d93a5bc115 mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5
Assign 7-bit address of the targeted slave SPD.

TEST=Able to read correct SPD data from SMBUS.

Change-Id: If24e61b583638be7c055541c6eb126da28b542f6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17 06:04:11 +00:00
Subrata Banik
486eabce80 mb/intel/adlrvp: Early program SMBUS CLOCK and DATA
TEST=Ensure SMBUS CLK/DATA GPIO is in NF1.

Change-Id: Id615462cc21fc24e7ec6ef16274d784d41bd9bd4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-17 06:03:28 +00:00
Elyes HAOUAS
0c510a2ac3 mb/{intel,prodrive,protectli}: Remove unused <string.h>
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'

Change-Id: Id2aa085a4762355d9fb1628df40f7b43fbc81fc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-16 17:12:49 +00:00
Kyösti Mälkki
7fb69b01c3 soc/inteL/broadwell: Move select CHROMEOS_RAMOOPS_DYNAMIC
With this selected, chromeos_reserve_ram_oops() is a no-op.

Change-Id: I2f3b7b3c4a9549a14f2ba039c769546f9698409a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-16 09:37:07 +00:00
Elyes HAOUAS
39239e6fff src/mb: Remove unused <console/console.h>
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:48:53 +00:00
Angel Pons
52e48b56e2 broadwell boards: Switch to Lynxpoint GPIO headers
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:53:49 +00:00
Angel Pons
2d11f71220 mb/intel/wtm2: Switch to Lynxpoint GPIO macros
Prepare to unify Lynxpoint LP and Broadwell GPIO code.

Tested with BUILD_TIMELESS=1, Intel WTM2 remains identical.

Change-Id: I422421cc3c336a7a1aceaff7b37ab7c82f64a03f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50067
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:48:46 +00:00
Angel Pons
f76822a75c soc/intel/broadwell/pch: Rename GPIO identifiers
Rename structs, types and functions to match Lynx Point's names.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I11ea27b00b5820eb5553712e0420836470ec0d27
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50064
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 08:19:03 +00:00
Kyösti Mälkki
d591a5a328 ACPI: Move common _PIC method
Change-Id: I659835354570fb1d4860fcbddf2a51831170a374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14 21:35:47 +00:00
Angel Pons
a3c6ed0dff haswell boards: Correct USB config indentation
Change-Id: I72b717a41c5611cf578ce178722029b8646cbb35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50539
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:34 +00:00
Angel Pons
33b59c9170 haswell: Drop mainboard_fill_pei_data
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.

To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.

Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 19:48:26 +00:00
Angel Pons
b27e7db0dc mainboard: Drop unneeded default_brightness_levels.asl
Desktop boards do not have any backlight control.

Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-12 07:58:43 +00:00
Angel Pons
ea573b04d8 sandybridge MRC boards: Drop channel disable masks
Platform code will overwrite these values anyway, so do not program them
in mainboards.

Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12 07:52:01 +00:00
Angel Pons
00f11c0290 sb/intel/i82801jx: Drop Global NVS support
Was copy-pasted from i82801ix and no mainboard actually needs it.

Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:38:15 +00:00
Kyösti Mälkki
aa969e887a ACPI: Move PICM declaration
Variable PICM was not inside GNVS region and can use a static
initialisation value.

For most AMD platforms PICM default changes from 1 to 0.

Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.

Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:37:28 +00:00