We should not need that.
Change-Id: Ic0181a300670ed7ee999dafedac79f3f89bfbee9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner
This change splits lpc_set_spibase() into two separate functions:
lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI
controller (if supported by platforms)
lpc_enable_spi_rom() - Enables SPI ROM
This split is done to allow setting of MMIO base independent of ROM
enable bits. On platforms like Picasso, eSPI base is determined by the
same register and hence eSPI can set the BAR without having to touch
the enable bits.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change adds support for struct soc_amd_common_config that allows
multiple AMD SoCs to share common configuration. This can then be used
by common/block drivers to get the required configuration from device
tree. It also provides function declaration for
soc_get_common_config() that needs to be provided by SoCs making use
of the common configuration structure.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idb0d797525414c99894a8e4ede65469381db7794
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41246
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to configure the Silver and L3 PLLs and switch the APSS
GFMUX to use the PLL to speed up the boot cores.
Tested: CPU speed frequency validated for speed bump
Change-Id: Iafd3b618fb72e0e8cc8dd297e4a3e16b83550883
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Update memory regions, etc.
Change-Id: If852fe4465fb431809570be6cdccff3ad9d9f4f0
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39362
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Transfer sequence used by SPI-Flash application present in CB/DC.
1. Assert CS through GPIO
2. Data transfer through QSPI (involves construction of command
descriptor for multiple read/write transfers)
3. De-assert CS through GPIO.
With above sequence, in DMA mode we dont have the support for read
transfers that are not preceded by write transfer in QSPI controller.
Ex: "write read read read" sequence results in hang during DMA transfer,
where as "write read write read" sequence has no issue.
As we have application controlling CS through GPIO, we are making
fragment bit "set" for all transfers, which keeps CS in asserted
state although the ideal way to operate CS is through QSPI controller.
Change-Id: Ia45ab793ad05861b88e99a320b1ee9f10707def7
Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39807
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all the logic for setting up decode windows for LPC
under configure_child_lpc_windows() which is called from
lpc_enable_children_resources(). This is in preparation to configure
decode windows for eSPI differently if mainboard decides to use eSPI
instead of LPC.
Side-effect of this change is that the IO decode registers are written
after each child device resources are considered.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
eSPI on Picasso is configured using the LPC bridge configuration
registers. This change enables config options to allow SoC to select
if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to
select if it wants to use eSPI instead of LPC for talking to legacy
devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI).
BUG=b:154445472
Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41069
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copyright notices are best stored in AUTHORS
Change-Id: Ib9025c58987ee2f7db600e038f5d3e4edc69aacc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41203
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add setting of the MaxPayload for each root port from the device tree.
By default MaxPayload is set to 128 bytes. This change allows changing
to 256 bytes.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I61e1d619588a7084d52bbe101acd757cc7293cac
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This is used for 'KHz' (line #19)
Change-Id: I4d610607b50d2fac1150deaaf94f3cb331540fbc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
C-State latency table was exposed by both intel-idle driver and
BIOS/coreboot. And table in Kernel was used before.
After kernel patch (https://patchwork.kernel.org/patch/11290319/),
only BIOS/coreboot exposes C-State latency table through _CST.
As current C-State latency table info is not correct for Tigerlake,
update proper info according to BWG and reference code.
- Update latency: CpuPowerMgmt.h
Use BIOS reference code as values in BWG is not up-to-dated
- Remove MSR program for latency: BWG 4.6.4.3.4
Reference:
- TGL BWG #611569 Rev 0.7.6
- https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/
ClientOneSiliconPkg/Cpu/Include/CpuPowerMgmt.h
BUG=b:155223704
BRANCH=None
TEST=Boot to OS and check C-State latency
expected result
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048
For detail, refer Bug info.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8bf2976ad35b4cf6f637a99c26b4f98f9f6ee563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
CB:41106 revealed that mb/intel/cedarisland already sets FSP-S UPD (see
CB:40735) while the required includes are still missing in CPX. Buildbot
did not fail because `ramstage.c` never was (implicitly) included.
Fix this problem by making SKX/CPX share a common ramstage header for
now by moving the one from SKX.
Test: Build cedarisland_crb
Change-Id: I9cd25edd167ec71ee98c7ffa4fa6f95ca73a75e9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This enables adding ACPI objects at run-time for SD Card and EMMC
devices.
BUG=b:150872580
TEST=Build and boot the mainboard. Observe ACPI objects like card detect
gpio are added to the SSDT.
Change-Id: I754aee3b0fd343994bd06d9c28e038f651009d6d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.
Change-Id: Ie21dcfc84d331f036090d01ea3e3925b81eea902
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
vboot_recovery_mode_enabled() was recently changed to assert() when it
is called before vboot logic has run, because we cannot determine
whether we're going to be in recovery mode at that point and we wanted
to flush out existing uses that pretended that we could. Turns out there
are a bunch of uses like that, and there is some code that is shared
across configurations that can and those that can't.
This patch cleans them up to either remove checks that cannot return
true, or add explicit Kconfig guards to clarify that the code is shared.
This means that using a separate recovery MRC cache is no longer
supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already
been broken with CB:38780, but with this patch those boards will boot
again using their normal MRC caches rather than just die). Skipping the
MRC cache and always regenerating from scratch in recovery mode is
likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE.
For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and
that is unlikely to change in the future so we will just hardcode that
fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed
to work around this issue).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Literally nobody else uses it and it does nothing.
Change-Id: I7e6466137b5069a7f785972205bd43f3cb25d378
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41112
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC device name string "PMC" is added to platform soc_acpi_name()
for pmc driver.
BUG=b:151646486
TEST=Built and booted to kernel successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ida7fc7e2340f2a809464ca66fd1922f3229e2e18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
AMD common block LPC driver does not really need a custom ops_pci
structure. This change drops the lops_pci and instead set .ops_pci to
the default pci_dev_ops_pci.
BUG=b:154445472
Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Also split "this is part of" line from copyright notices.
Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kernel pinctrl driver changed for Tiger Lake and went to old scheme.
Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/
third_party/kernel/+/2116670
BUG=b:151683980
BRANCH=none
TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl
verify INTC34C5:00 listing all the pins.
Cq-Depend:chromium:2116670
Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value
of HPR_CAUSE0.
Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card
power enable pin. Setting it 1 will set polarity of this pin as Active
high. This patch will allow to control it from devicetree so that it
can be set as per each board's requirement.
BUG=b:155595624
BRANCH=None
TEST=Build, boot JSLRVP, Verified UPD value from FSP log
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: Id777a262651689952a217875e6606f67855fc2f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC supports messages that can be used for configuring the USB
Type-C Multiplexer/Demultiplexer.
BUG=b:151646486
TEST=Booted to kernel on volteer board and verified PMC and Mux
agent devices identification.
Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add a knob for mainboards to request disablement of the SPI
flash ROM sharing in the chipset. The chipset allows the board
to share the SPI flash bus and needs a pin to perform the request.
If the board design does not employ SPI flash ROM sharing then it's
imperative to ensure this option is selected, especially if the
pin is being utilized by something else in the board design.
BUG=b:153502861
Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If a Picasso platform wants to use GPIO 67 it must disable ROM sharing.
Otherwise ROM access is incredibly slow.
BUG=b:153502861
TEST=Build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update interrupt setting based on latest FSP(3163.01)
Reference:
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/
ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/
PeiItssPolicyLibVer2.c
BUG=b:155315876
BRANCH=none
TEST=Build with new FSP(3163.01) and boot OS and login OS console
in ripto/volteer. Without this change, we can't login due to mismatch
interrupt setting between asl and fsp setting.
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to refactoring of Serial IO code in FSP v3163 onwards we need to
set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart
initialization is skipped in FSP. This makes sure that SerialIo
initialization in coreboot is not changed by FSP.
BUG=b:155315876
BRANCH=none
TEST=build and boot tglrvp/ripto/volteer and check UART debug logs
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization
Registers) when SataPwrOptEnable=0, which currently is the default in
coreboot and FSP. Even if FSP's default was 1, coreboot would reset it.
This can lead to all sorts of problems and errors, for example:
- links get lost
- only 1.5 or 3 Gbps instead of 6 Gbps
- "unaligned write" errors in Linux
- ...
At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and
purism/librem13v2) SATA is not working correctly and showing such
symptoms.
To let FSP correctly initialize the SATA controller, enable the option
SataPwrOptEnable statically. There is no valid reason to disable it,
which might break SATA, anyway.
Currently, there are no reported issues on CML and CNL, so a change
there could not be tested reliably. SKL/KBL was tested successfully
without any noticable downsides. Thus, only SKL gets changed for now.
Change-Id: I8531ba9743453a3118b389565517eb769b5e7929
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DisableHeciRetry to the chip config and parse it in romstage.
Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In CSE Firmware Custom SKU, CSE region is logically divided into
2 boot partitions. These boot partitions are represented by BP1(RO),
BP2(RW). With CSE Firmware Custom SKU, CSE can boot from either
RO(BP1) or RW(BP2).
The CSE Firmware Custom SKU layout appears as below:
------------- -------------------- ---------------------
|CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA |
------------- -------------------- ---------------------
In order to support CSE FW update to RW region, below APIs help coreboot
to get info about the boot partitions, and allows coreboot to set CSE
to boot from required boot partition (either RO(BP1) or RW(BP2)).
GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE
region. The API provides info on boot partitions like start/end offsets
of a partition within CSE region, and their version and partition status.
SET_BOOT_PARTITION_INFO - Sets CSE's next boot partition to boot from.
With the HECI API, firmware can notify CSE to boot from RO(BP1) or RW(BP2)
on next boot.
As system having CSE Firmware Custom SKU, boots from RO(BP1) after G3,
so coreboot sets CSE to boot from RW(BP2) in normal mode and further,
coreboot ensure CSE to boot from whichever is selected boot partition
if system is in recovery mode.
BUG=b:145809764
TEST=Verified on hatch
Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments. Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.
AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.
* Add fsp_memory_init() to romstage.c. Although Picasso comes out
of reset with DRAM alive, this call is added to maximize
compatibility and facilitate internal development. Future work
may look at removing it. AGESA reports the memory map to coreboot
via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
passed from AGESA. Note that relying on the TOM register happens
to be misleading when UMA is below 4GB.
BUG=b:147042464
TEST=Boot trembyle to payload
Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform the P2SB hide/unhide trick. This is needed so that BAR0
(0xfd000000) is not reclaimed by resource allocator, since it can
not deal with a device that does not exist (hidden).
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I5db0ae4e31d72ba86efba5728b2afc68d3180d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Use common P2SB driver. This is needed to address a problem when
enumerator does not see p2sb device (since it is hidden) but it
is active and BAR is decoded.
Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:152019429
BRANCH=None
TEST=1. provision dram_part_num field of CBI
2. modify mainboard - dedede to report DRAM part number from CBI
3. check DRAM part number is correct in SMBIOS for memory device
Change-Id: I509d06a81bd005c5afe6e74a2da2ca408dee7b29
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.
Tested on Intel CFL, the new code allows to boot using FSP-T.
Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM
setup code to properly enable MTRRs. Add that capability to the
bootblock_c_entry() function. In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.
BUG=b:147042464
TEST=Boot trembyle to payload and make sure bootblock isn't abnormally
slow.
Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.
BUG=None
BRANCH=None
TEST=Build and boot tglrvp.
Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree.
Filling this UPD will allow FSP to enable proper clksrc gpio
configuration.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Iad0b394fea019223a5b98fff0cb4a2bd1d2a7bd7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Add support to generate ACPI operations to get/set/clear RX/TX GPIOs.
BUG=b:152936541
TEST=Build and boot the mainboard. Ensure that there are no errors in
the coreboot logs regarding unsupported ACPI GPIO operations.
Change-Id: Ibc4846fbd9baf4f22c48c82acefed960669ed7d4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change enables support for em100 for Picasso platform. Since
em100 requires lower SPI speed, this change configures speed in all
modes as 16MHz.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that em100 works fine on trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds options to allow mainboard to configure SPI speed for
different modes as well as the SPI read mode.
BUG=b:153675510,b:147758054
BRANCH=trembyle-bringup
TEST=Verified that SPI settings are configured correctly for trembyle.
Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a helper sb_spi_init() that makes all the required
calls for configuring SPI to ROM.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic5b395a8d3bdab449c24b05d1b6b8777e128b5e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40824
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
southbridge.h does not really need chip.h. So, this change removes the
inclusion of chip.h from it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I09c87b975ecd5f7798da8dd858be0c729aef42de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 285975dbba.
Reason for revert: VB2_RECOVERY_TRAIN_AND_REBOOT was never meant to have
any special effect on memory training behavior. It was just supposed to
be a "reboot automatically after reaching kernel verification" recovery
reason. On x86 devices this was used to prime the separate recovery
MRC cache in the factory (make sure it is initialized before shipping).
This isn't used on Kukui anyway, but in order to make sure nobody copies
this code and keep the behavior consistent between platforms, let's
remove it.
Change-Id: I5df5e00526e90cb573131de3c8bac9f85f4e3a5f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40623
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that all SC7180 boards we have can well handle 37.5MHz of SPI
flash speed, so bump that up from the current 25MHz so that we don't
leave boot speed on the table. (The next step would be 50MHz which
currently doesn't work on all boards so we're not going there yet.)
BUG=b:117440651
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id6e98fcbc89f5f3bfa408c7e8bbc90b4c92ceeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Check SPD is not NULL before print. This can prevent the system
from hanging up.
BUG=b:154445630
TEST=Check NULL SPD is not print.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which
when enabled includes secure debug unlock blobs and sets the required
softfuses and options for amdfwtool. By default this is set to 'N'.
BUG=b:154880818
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change updates Makefile.inc to use a helper function set-bit to
set a bit for the soft fuses. It gets rid of the different checks that
were done to set soft fuses to magic values in different places.
This is still not the best way to handle the fuses and instead this
logic should be embedded within the amdfwtool by making it aware of
specific platforms. But until that happens, we want to avoid having to
add PSP_SOFTFUSE setting in various places with different values.
BUG=b:154880818
TEST=Verified that the softfuse values are same with and without this
change.
Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the PSP Kconfig options that are prompted to the user should
really be selected by mainboard. This change updates such options to
not make them user-visible any more.
BUG=b:154880818
Change-Id: Iaff02fb1e720e0562b740799593322e59b022212
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PSPTRUSTLETS_FILE was including a binary for fTPM which according to
BIOS architecture design guide is the firmware enabled TPM. Chrome OS
does not really use firmware enabled TPM. Also, this is an option
which is mainboard dependent.
This change drops the addition of PSPTRUSTLETS_FILE to PSP
directory. If this is something that is required by any mainboard,
there should be a separate Kconfig to include the required files.
BUG=b:154880818
TEST=Verified that trembyle still boots
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change drops the addition of PUBSIGNEDKEY_FILE to PSP
directory. This file is used to add OEM key for BIOS, however this is
currently unused for upcoming zork board. In the future, if any
mainboard needs this, it can be added based on some Kconfig selection.
BUG=b:154880818
TEST=Verified that trembyle still boots up fine.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icd97856a94a100898678702d99bbe29b82956004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Inclusion of MP2 firmware is optional and dependent on mainboard. Set
default option for including MP2 firmware in PSP directory to 'n'.
BUG=b:154880818
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1ff7527a409d8ac7f4d30e69eafc53975b63e49b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change adds support in common block HDA driver to add a PCI
device for HDA in SSDT and removes the HDA device from DSDT for
Stoneyridge and Picasso.
_INI method is still retained in stoneyridge since I am unsure why it
was added. In order to support the _INI method, HDA driver makes a
callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks
required for the HDA device. This callback is implemented by
Stoneyridge to provide the _INI method which retains the same
functionality for HDA device.
This makes it easier to ensure that we don't accidentally
make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and
scope.
BUG=b:153858769,b:155132752
TEST=Verified that audio still works fine on Trembyle.
Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40785
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_INI method for AZHD device for Picasso family was just copied from
Stoneyridge as part of initial change. There is no evidence that this
is required for Picasso. Also, removing the _INI method works
perfectly fine. Thus, this change drops the _INI method for AZHD
device on Picasso.
Since the _INI method was the only entity using the OperationRegion
fields, this change also drops the operation region.
BUG=b:155132752
TEST=Verified that audio still works on Trembyle
Change-Id: If42abf91ee5cd47a881b0a3b4ca1916ea5169261
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40782
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds .acpi_name() callback to HDA driver that returns
"AZHD" as the ACPI device name for HDA controller. Since this is now
done by the common HDA driver, this change also removes the HDA device
name returned by stoneyridge in chip.c.
BUG=b:153858769
Change-Id: I89eaa799518572f3c46c7ce9ef8dd3f85daa12bb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a cosmetic change to use tabs to align hda_audio_ops and
hdaaudio_driver entries.
Change-Id: I8e398706cbe7087d0178b2433606f8984651c0d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change sets ops_pci for hda_audio_ops to default pci_dev_ops_pci
and removes the custom lops_pci since the driver does not really need
a custom ops_pci.
BUG=b:153858769
Change-Id: I4b46e22ef556c0f49152c41a07f3c54c513ae37a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40779
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCI device PCI_DEVICE_ID_AMD_FAM17H_HDA0 does not really use the same
vendor ID as PCI_VENDOR_ID_AMD. Thus, drop this device from the list
of pci_device_ids[] that are supported by the common hda driver.
BUG=b:153858769
Change-Id: If41dc7179e1e5b476878ee24c8a355b1cde762eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40778
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The original plan for Picasso was to combine the features of bootblock
with romstage due to its unique way of coming out of reset. Early in
development, all bootblock support was removed from the directory.
All Picasso designs will now use a bootblock as their first stage. The
reason being that it requires less invasive changes than using a hybrid
romstage.
Add a basic bootblock back to the directory, and compatible with the
design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM
and add appropriate settings in Kconfig. Make Makefile.inc calculates
the size and base of bootblock from known parameters.
* Future work may attempt to streamline this further, in conjunction
with changes in amdfwtool. See b/154957411.
BUG=b:147042464, b:153675909
Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds GPID, a helper method to look up GPIO community ID for
an index.
This patch also includes Intel's common GPIO ASL code. CGPM method in
the common code uses the GPID method introduced in this patch.
BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds CGPM, a helper method to configure GPIO power management
bits that are part of miscellaneous config. This is needed for
configuration of these bits on S0ix entry and exit.
BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change sets .ops_pci for sata device_operations to default
pci_dev_ops_pci. It is required to set the subsystem IDs making the
behavior consistent with default_pci_ops_dev.
BUG=b:153858769
Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40777
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables the use of AMD common block SATA driver for
Picasso. Since the common driver provides ACPI device name and PCI
device for SATA in SSDT, these are removed from picasso chip.c and
sb_pci0_fch.asl.
BUG=b:153858769
TEST=Verified that "STCR" device is correctly reported on trembyle in
SSDT.
Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support in common block SATA driver to add a PCI
device for SATA in SSDT and removes the SATA device from DSDT.
This makes it easier to ensure that we don't accidentally
make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and
scope.
BUG=b:153858769
Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds .acpi_name() callback to SATA driver that returns
"STCR" as the ACPI device name for SATA. Since this is now done by the
common SATA driver, this change also removes the SATA device name
returned by stoneyridge in chip.c.
BUG=b:153858769
Change-Id: I5e0998be3016febbb3b0e91940750a38edb6a9e7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40768
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a cosmetic change to use tabs to align sata_ops and
sata0_driver entries.
Change-Id: Ia9eabd0cd64ecc9cbff0d4c3e3c6b71bbf29e3a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40767
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sata.c was being added to ramstage based on the selection of
CONFIG_SOC_AMD_COMMON_BLOCK_HDA which is not correct. This change
fixes the error by including sata.c based on selection of
CONFIG_SOC_AMD_COMMON_BLOCK_SATA.
BUG=b:153858769
Change-Id: I5d23e5817872ddbb3d8d4f7dcabbaafcee4d51f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40766
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pointer passed to print_spd_info() from meminit.c needs to be
dereferenced first, so this change dereferences it.
BUG=b:154352883
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, login to kernel and execute the following cbmem command:
localhost ~ # cbmem -c | grep LPDDR4X
and verify it returns "SPD: module type is LPDDR4X"
Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
.acpi_inject_dsdt() does not need to modify the device
structure. Hence, this change makes the struct device * parameter to
acpi_inject_dsdt as const.
Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
intel_igd_get_controller_info() does not need to modify the device
structure. Hence, this change makes the struct device * parameter to
intel_igd_get_controller_info() as const.
Change-Id: Ic044a80e3e2c45af6824a23f3cd0b08b94c0f279
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
sd_fill_soc_gpio_info() does not need to modify device
structure. Hence, this change makes the struct device * parameter to
this function as const.
Change-Id: I237ee9640ec64061aa9ed7c65ea21740c40b6ae2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
dw_i2c_soc_dev_to_bus() does not need to modify the device
structure. Thus, this change makes the struct device * parameter to
dw_i2c_soc_dev_to_bus as const.
Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.
Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change:
1. Adds PCI device for graphics controller in ACPI SSDT tables using
acpi_device_write_pci_dev().
2. Gets rid of IGFX device from picasso acpi/northbridge.asl.
This makes it easier to ensure that we don't accidentally
make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and
scope.
BUG=b:153858769
Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change selects common block graphics driver for Picasso and also
adds PCI ID for Family 17h graphics controller to the graphics
driver.
Since the common driver provides .acpi_name() callback for graphics
device, soc_acpi_name() no longer needs to provide the ACPI name for
graphics device.
BUG=b:153858769
Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds a common graphics block device driver for AMD
SoCs. In follow-up CLs, this driver will be utilized for Picasso.
This driver is added to enable ACPI name and SSDT generation for
graphics controller.
BUG=b:153858769
Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change adds all the missing PCI device IDs for AMD Family
17h. IDs that were already present are updated to include _FAM17H_ in
the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs
match the family and models as per the PPR. In cases where the
controller is present only on certain models, _MODEL##H_ is also
included in the name.
BUG=b:153858769
BRANCH=None
TEST=Verified that trembyle and dalboz still build.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID
0x15D1. This change updates the name to indicate that the PCI device
ID is supported for FP5(Model 18h) and FT5(Model 20h).
BUG=b:153858769
BRANCH=None
TEST=Trembyle and dalboz still build.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Set SPD array NULL if no DIMM present. do_smbus_read_byte returns
negative value if SMBus transaction fails.
BUG=b:154445630,b:151702387
TEST=Check SPD is NULL if no DIMM in the slot.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie81adbfab5bb1d5c557fe549a158cb68e26b1162
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to doc 621880, it suggests setting 40 ohm in byte 185 in extCSD.
This commit provides _DSM method for driver to query driving strength.
TEST=mmc extcsd read |grep HS_TIMING and found bit[7:4] is set to 4
BUG=b:154159888
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I1b4df8b0d1d2cad3a7f521ad47ee5a4b3320c767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Populate SMBIOS type 17 tables using data from SPD and read via IOSF.
Refactor print_dram_info() to pass thru SPD data and channel/speed info.
Move call to print_dram_info() after cbmem initialization so the SMBIOS
data has somewhere to go.
Test: build/boot google/swanky, verify via dmidecode.
Change-Id: I1c12b539c78d095713421b93115a4095f3d4278d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1
to set SPD for index 4. This change adds a helper macro to translate
DDR4 channel # to the index # that the FSP expects.
BUG=b:154445630
TEST=Verified that memory initialization for DDR4 is successful.
Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Assuming given system is populated with multiple CPUs of same SKUs,
calculate number of threads based on MAX_SOCKET.
This is a stop gap solution until proper way of identifying total
number of sockets is determined.
Change-Id: I7ebad3d57c47b9eeb7d727ffb21bc0a1a84734fd
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Currently FSP-M does not implement the spec completely, e.g it is unable
to use user-provided heap location in CAR. While this is being resolved,
this workaround is a stop-gap solution that allows multi-socket usage.
TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB
Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to allow motherboards to configure certain parameters that
are specific to it. Hence, invoke this function. Also, provide a
weak motherboard implementation that does nothing.
Change-Id: Ifa2824811273236a66e742404856fbe17d4cf496
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40552
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C0&1 are either not available or not functional. Add place holders
instead, so that the array index matches the I2C controller number. I2C4
is slave device only, so do not initialize it as I2C host controller.
Also do some slight refactoring.
BUG=b:153152871
BUG=b:153675916
Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1897071
Reviewed-on: https://chromium-review.googlesource.com/2057468
Reviewed-on: https://chromium-review.googlesource.com/2094855
Reviewed-on: https://chromium-review.googlesource.com/2149870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the
appropriate calling stage (bootblock or romstage). This means that
ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE
are 1. This keeps tripping up people who are just trying to write a
simple "are we in verstage (i.e. wherever the vboot init logic runs)"
check, e.g. for TPM init functions which may run in "verstage" or
ramstage depending on whether vboot is enabled. Those checks will not
work as intended for CONFIG_SEPARATE_VERSTAGE=n.
This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to
clarify that this macro can really only be used to check whether code is
running in a *separate* verstage, and clue people in that they may need
to cover the linked-in verstage case as well.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Type-C subsystem power management support for RTD3.
BUG=b:140290596
TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build
with the firmware CM. Added acpi debug and booted to kernel. Probed
devices PM_STATE transition from D0 to D3 entry/exit while system at S0.
TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT.
xhci:00:0d.0, offset:0x74, PM_STATE:D0D3.
dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST.
Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended
time tick through /sys/bus/pci/devices/bus:device:func/power.
Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This implements the SPI driver for the QUP core.
Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36517
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This implements the UART driver in SoC
Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/25373/78
Change-Id: I6494daa108197c030577ac86dab71f9ca6c21bdb
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35500
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The frequency to be used by UART client is 7.3728MHz, thus define it in
the clock header to be used by the driver.
Tested: UART frequency request by client driver.
Change-Id: I1ced350fe9826ea05b03ffc11aced2c21fe85c9e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Remove explicit setting of iDisp Link parameters. These settings are
related to configuration for the link between HD-Audio controller and
Display unit for purposes of HDMI/DP Audio playback. During PO,
observed that without setting these params display part was not
binding. With the latest code verified that we dont need to explicitly
set these parameters anymore. HDMI/DP audio playback works fine with
default settings.
BUG=b:151451125
BRANCH:none
TEST= build and boot volteer/ripto and verify HDMI/DP audio playback
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jairaj Arava <jairaj.arava@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changing the local pointer "start" has no effect.
Changing the value it points to has.
Change-Id: I1b689896fcf255b795b27d7a7163849d6dfdb00e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch adds _DSM Method in LPIT table for entering and exiting
S0ix. This method get injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
BUG=b:148892882
BRANCH=none
TEST="BUILD"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib58f2e33a33bac9cc5f6aca28e85a8066413a5cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
The error message has been copy-pasted across various functions, so it
is nearly impossible to know which function printed it. So, use __func__
to print that information.
Change-Id: I55438c2b36cc3b21f3f168bf98b0aca5fd50bbbc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40446
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocate storage for the BERT reserved memory in cbmem, and add it in
response to a romstage hook. Add a Kconfig option for adjusting the
size reserved. This is different from the Stoney Ridge implementation
where it was intentionally oversized to ease MTRR use and to keep TSEG
aligned.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tigerlake platform does not have built in eMMC/SD support so all
this code is unused and can be removed.
Change-Id: I70ff983d175375171d5a649378f32f1062c0876d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The eMMC/SD interface is not present in all Intel platforms so this
change removes the default enable for the storage controller and
instead enables it in the specific SoCs that do provide it.
Currently this includes all platforms except Tigerlake.
Change-Id: I8b6cab41dbd5080f4a7801f01279f47e80ceaefd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
