https://github.com/thesofproject/linux/pull/3271
Felwinter will use the OEM string for SOF tplg loading. Update the name
that match to the kernel driver.
BUG=b:210061842
TEST=dmidecode can show AUDIO_AMP-MAX98360_ALC5682VS_I2S_2WAY.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib6114d047762ba26071c9cdc6c43d80f933c1eb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61070
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference
Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband
RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and
ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables
CNVI DDR RFIM feature for brya0 variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:201724512
BRANCH=None
TEST=Build and boot with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: I6ad826d0039e400f219c2d407c51762c1751a909
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem
and prefetch mem.
BUG=b:206739931
TEST=build PASS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses
some of the registers directly.
BUG=b:183149183
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make use of the helper introduced in the parent change to deduplicate
the PCIe root port table.
Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add TGL-H support for the recently introduced code for differentiating
CPU and PCH root ports by adding the missing TGL-H port map.
Change-Id: Id2911cddeb97d6c164662e2bef4fdeece10332a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The patch adjusts CSE region's internal partitions' (CSE RO and Data
partition) sizes to match with sizes of MFIT generated CSE Region's
internal partitions.
BUG=b:213993778
TEST=Generate coreboot for Brya and verify with MFIT generated
coreboot.
Cq-Depend: chrome-internal:4452789
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5418c02f83134814e3f9959ee8c8da32ce8c7bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60951
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures all brya variants with Alder Lake ESx SoC
are using NEM by default for CAR set up.
Default CAR configuration for QS SoC is eNEM.
BUG=b:168820083
TEST=Able to build and boot brya0 variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib04bec188bdfde67c408fcd6b0603a5c2fb0fc97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Since we need the GPIO defines in the devicetree settings, include
gpio.h in each SoC's chip.h file which will indirectly include the
soc-specific soc/gpio.h header instead of having it indirectly included
via soc/i2c.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
in fsp_params.c
BUG=b:213959910
BRANCH=None
TEST=Build and boot brya
Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Per customer spec, change ELAN touch HID from ELAN9050 to ELAN9008.
BUG=b:214010928
TEST=touch screen is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia95fdb378aaf241e38c0beb8ec392d57d77dc4db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61027
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the name of the include guard for
soc/mediatek/common/include/soc/emi.h.
BUG=none
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
This function actually dumps cbmem to the UART. This change renames the
function to make that clear.
BUG=b:213828947
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icc314c530125e5303a06b92aab48c1e1122fd18c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In order to avoid having the FSP fail to detect the SSD device
downstream of the RP, its PERST# must be deasserted earlier in
the boot flow, therefore move PERST# deassertion to a romstage
GPIO table.
BUG=b:213828931
TEST=Build FW and run stress exceed 1000 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4e5eed7db16e1420ccbc22a5c30b00bedd190a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove vbp & hbp as the names are misleading and use edid variables
to simplify the video mode active and total calculations.
Change-Id: I9ccafabe226fa53c6f82e32413d4c00a0b4531be
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
During certain kind of test scenario, observed that CPU temperature
spikes till 98C and based on current thermal critical policy
temperature threshold of CPU set to 98C, it initiates the system wide
abrupt shutdown.
To avoid this kind of abrupt system shutdown, update cpu critical
temperature threshold from 98C to 105C.
BUG=b:213476881
BRANCH=glados
TEST=Built and booted on glados
Change-Id: I56df9285b3c247866a5bfa6dc59d1856544de41c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some SOC add PCI root busses structs at runtime without adding a
device struct to the bus because pci_scan_bus does it. An example
would be xeon_sp which has multiple root busses.
TEST: ocp/deltalake boots again.
Change-Id: I81d9c94652e34dbf9e8cec64fc34ef0042563037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This is a initial mainboard code cloned from adlrvp aimed to serve as
base for further mainboard check-ins. This commit copies the mainboard
directory and adjusts the naming to match the new board's name.
Besides, This commit also trims down major parts of adlrvp code except
some of ADL-P DDR5 RVP as Atlas is using it as main reference.
Follow-up commits will introduce the needed changes for the new
mainboard.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia3129f68c73969604edcd290c3e50ad219cf88d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60899
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<rules.h> and <commonlib/bsd/compiler.h> are always automatically
included in all compilation units by the build system
Change-Id: I9528c47f4b7cd22c5a56d6a59b3bfe53197cc4d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.
This change clones the implementation on Alder Lake which converts
the phyiscal port mapping to EC's abstract port mapping.
BUG=b:207057940
BRANCH=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TGL-LP only has 12 root ports, not 20. Correct the port map.
Change-Id: I3f5c69a2e7e3a2b8292c81beeac4ea6c7279d4b4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The factory versions (minor version 22) of cr50 FW have an issue with
producing short interrupt pulses, which can be missed by the ADL PCH
if autonomous GPIO power management is enabled, therefore instead of
continually adding the setting to all the variants, move it to the
baseboard instead.
Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The existing common AMD SoC code supports some of AMD Family 17h Model
A0h SoC's PCI devices that however have different PCI IDs. Add the new
PCI ID defines to the PCI ID lists of the common PCI drivers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The PCI IDs of the ACP (audio co-processor), the non-GPU HDA audio, the
SMBus and the LPC devices haven't changed from the previous generations
of Zen-based APUs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I41e0a57671b9ef2938b7798d5826de43bea8fe12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add an elog type 0xb6 for Chrome OS diagnostics related events and
log the message while booting the diagnostic tool:
__func__: Logged diagnostic boot
BRANCH=none
BUG=b:185551931, b:177196147
TEST=emerge-volteer coreboot vboot_reference
Change-Id: Icb675fc431d4c45e4f432b2d12cac6dcfb2d5e3a
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
uintptr_t is defined in stdint.h which gets included by types.h. I use
types.h instead of stdint.h, since that's also what the Picasso code
does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3d0811d831b5acc9343398f4d28c73467c0a429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch makes DISABLE_HECI1_AT_PRE_BOOT=y default for Apollo Lake
and ensures disable_heci1() is guarded against this config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7ac0cad97fcd42b2c6386693319d863352356864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the `configure_pmc_descriptor()` function to SoC scope instead of
having two identical copies in mainboard scope. Add a Kconfig option to
allow mainboards to decide whether to implement this workaround.
Change-Id: Ib99073d8da91a93fae9c0cebdfd73e39456cdaa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Copy the `is_descriptor_writeable()` function from the `intel/adlrvp`
mainboard and use it in the `configure_pmc_descriptor()` function. With
this change, this function is now identical for both mainboards.
Change-Id: I2ff39682ed98c6b8bc60cc2218f36f4934b9903c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Adjust the cosmetics of the `configure_pmc_descriptor()` function to
match the code for the `intel/adlrvp` mainboard. The only difference
is that adlrvp checks if the descriptor is writable.
Tested with BUILD_TIMELESS=1, Google Brya0 remains identical.
Change-Id: I9c524d5c422c765db200a15f484c2b8827ebd40b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Restructure the code in the `configure_pmc_descriptor()` so that it
matches the code for the `intel/adlrvp` mainboard. This change does
not reindent the contents of the original if-block intentionally as
this will be taken care of in a reproducible follow-up.
Change-Id: I8c9d9087cb2d0668f6a4afbb566d830bb9febd89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
More Brya variants like Brya0 and Taeko have migrated to use
Alder Lake QS SoC which enables eNEM feature by default. Hence,
select eNEM for CAR by default for these variants.
BUG=b:168820083
TEST=Able to build and boot brya0 variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63be166c8e428f052999fe29c8ebe1238e1a12ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch migrates common code API into SoC specific implementation
to drop CPU privilege level as the MSR is not consistent across
platforms.
For example: On APL/GLK, it's MSR 0x120 and CNL onwards it's MSR 0x151.
Also, include `soc/msr.h` in cpu.h to fix the compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0b6f39509cc5457089cc15f28956833c36b567ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60898
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_64 the struct isn't packed, causing the fw_cfg parser to return
invalid memory entries (possible others as well) through fw_cfg.
Fix that by packing all structs.
Change-Id: Id1bab99f06be99674efe219dda443fb7d44be560
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds a config to let mainboard users choose the correct
state of HECI1(CSE) device prior to handing off to payload.
`DISABLE_HECI1_AT_PRE_BOOT` config to make HECI1 function disable
at pre-boot.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e127816c506df3ac0cf973b69021d02d05bef4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the missing VBT for Mushu, which is simply a copy of the one for the
hatch variant.
Change-Id: I3918ce9e7cfa6a7dafaa228a13d0f0a5b8913c66
Signed-off-by: Dominik Behr <dbehr@chromium.org>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Update all the ADL-P 15W/28W/45W SKU's PL and PsysPL. These config
values are generated iPDG application with ADL-P platform package
tool. RDC Kit ID for the iPDG tools:
* Intel(R) Platform Design Studio Installer: 610905.
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345.
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261.
BUG=b:211365920
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I4a827ae40e26294db20d5d1b2121dcce5118e290
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We support all the ADL-P 15W/28W/45W SKU's and map them with the
latest VR configurations. These config values are generated by iPDG
application with ADL-P platform package tool.
RDC Kit ID for the iPDG tools
* Intel(R) Platform Design Studio Installer: 610905
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Create the volmar variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:213127419
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_VOLMAR
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5ebf62b7a17b075c0e28fb4e8b7c501fc8db3ea3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Update the DPTF parameters received from the thermal team. Refer to
https://partnerissuetracker.corp.google.com/issues/195602767#comment6.
BUG=b:195602767
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I93fe388ff1862d0a96b11ce68a5d28664f11996a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable Elan touchscreen support for chronicler.
BUG=b:213537197
TEST=emerge-volteer coreboot chromeos-bootimage
verified touchscreen works
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ic56092972eb9555b097b21ff5828573926610f31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable CPPC entries generation, needed for Intel SpeedShift.
This can be tested by checking sysfs in Linux:
$ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf
The output should look like this, while the values may differ:
/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5
/sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1
/sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24
/sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28
/sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5
...
Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
FSP reserved memory is allocated inside cbmem which already gets
marked as a reserved memory region, so there is no need to do this
explicitly.
Change-Id: I39ec70bd9404d7bc2a4228c4364e4cc86f95d7c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
In order to make SC7180 boards compatbile with some optional Kconfigs,
increase the bootblock size a bit and add room for a TCPA log buffer to
memlayout. The large pre-RAM CBFS cache wasn't really needed anymore
anyway since we switched QcLib to use LZ4 compression.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7321cca9d7b79368115c57f156b8e71657802a41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Add GPIO configuration for target specific i2s ports.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Boot on herobrine board (no speakers to test yet)
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Change-Id: I2ce95332f892d5d4acb2755307df84d37feb8002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Initialize EC and H1/TPM instances on herobrine devices.
BUG=b:182963902
BRANCH=None
TEST=Validated on qualcomm sc7280 development board
and verified booting on herobrine.
Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add OVTI8856 information for vell:
BUG=b:210801553
TEST=Build and boot on vell
Change-Id: I43de859cd0cdd9fe21c16cabfad511ed0b368ee3
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
According to the latest schematic for the next build phase, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3
BUG=b:210572663
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: If72717a2c073f5b871c3109399f466a04a9d2484
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The PMC IPC method that is used for RTD3 support expects to be provided
the virtual wire index instead of the LCAP PN for CPU PCIe RPs.
Therefore, use the prior patches to update pcie_rp for CPU RPs.
Note that an unused argument to pcie_rtd3_acpi_method_status() was also
dropped.
BUG=b:197983574
TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and
inspect the SSDT to see the PMC IPC parameters are as expected for the
CPU RP, and the ModPhy power gating code is not found in the AML for the
PEG port.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When using a mixed memory topology with DDR4, it's not possible to boot
when no DIMMs are installed, even though memory-down is available. This
happens because the DIMM SPD length defaults to 256 when no DIMM SPD is
available. Relax the length check when no DIMMs are present to overcome
this problem.
Tested on system76/lemp10. Unit boots with and without DIMM installed.
Change-Id: I1cabf64fade1c06a44b6c3892659d54febc7a79a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
We need to protect debugsys for firmware image without serial console.
Original settings for protecting debugsys is wrong which will cause some
hardware modules to fail to set their registers correctly.
We move the setting from MM_AO_APC to INFRA_AO_APC because the setting
of debugsys is defined in INFRA_AO_APC and set the debugsys index to
correct value of 94.
BUG=b:213125558
TEST=all modules work normally using image without serial console.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60833
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DFD (Design for Debug) is a debugging tool, which scans flip-flops
and dumps to internal RAM on the WDT reset. After system reboots,
those values can be shown for debugging using MTK internal parsing
tools.
BUG=b:202871018
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7b711755022b5d9767019611151fea65e71edc66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kingler board has an SD card reader connected via USB and can be
enabled by setting GPIO EN_PP3300_SDBRDG_X to output mode and activated.
BUG=b:211385131
TEST=boot kernel using SD card.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I903731ea4906328b2f0f5a7c6c06bd9c964d24ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60780
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The variable `custom_count` is the number of custom fields, so only
holds non-negative values, so change the struct member type from int to
size_t.
Change-Id: Ic35aafefc870092298523ba2e10adf4fcb687a01
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60790
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Building an image for OCP DeltaLake with `x86_64-linux-gnu-gcc-11` fails
with the format warning below as the size of char * differs between
32-bit and 64-bit.
CC ramstage/drivers/ipmi/ipmi_fru.o
src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_chassis_info_area':
src/drivers/ipmi/ipmi_fru.c:192:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=]
192 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for "
| ~~^
| |
| long int
| %d
193 | "chassis custom data array.\n", __func__,
194 | info->custom_count * sizeof(char *));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| unsigned int
src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_board_info_area':
src/drivers/ipmi/ipmi_fru.c:291:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=]
291 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for "
| ~~^
| |
| long int
| %d
292 | "board custom data array.\n", __func__,
293 | info->custom_count * sizeof(char *));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| unsigned int
src/drivers/ipmi/ipmi_fru.c: In function 'read_fru_product_info_area':
src/drivers/ipmi/ipmi_fru.c:398:57: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'unsigned int' [-Werror=format=]
398 | printk(BIOS_ERR, "%s failed to malloc %ld bytes for "
| ~~^
| |
| long int
| %d
399 | "product custom data array.\n", __func__,
400 | info->custom_count * sizeof(char *));
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| |
| unsigned int
Fix the mismatches in `read_fru_chassis_info_area()` by using the length
modifier `z` for size_t as that is what `size_of` yields to.
Change-Id: If0c4266b19d56fa88abc397f305154d473ae1a93
Found-by: gcc (Debian 11.2.0-10) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message
TEST=On brya, assigned one clkreq to 2 devices and found the warning
message
Change-Id: I2f701a19118f4702c227b17e43b6551591d9b344
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
End all CMOS variable with a C and EC variables with an E.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie0fab6b9dcd805f7b8c9bf8f14b0a799d8f396c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Define the register offsets and bits in a separate header file instead
of in the middle of the .c file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In espi_wait_channel_ready the return value of espi_get_configuration
didn't get checked before. In the case of the espi_send_command call in
espi_get_configuration returning CB_ERR, espi_get_configuration didn't
write to the local config variable, so if this happens in the first pass
of the do-while loop, the following espi_slave_is_channel_ready call
would use the uninitialized local config variable as parameter. Fix this
by checking the return value of espi_get_configuration.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The latest schematics changes the TPM I2C from I2C3 to I2C1. This patch
moves the TPM I2C setting from the board layer to the baseboard and
fixes the TPM I2C bus assignment.
BUG=b:211886429
TEST=build pass
Change-Id: I70d5a8fde1866c5dd4587ab5af2d41724c60ee0c
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60439
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board id assignment CL (CB:56642) landed after
BOARD_GOOGLE_HEROBRINE has been deprecated to
BOARD_GOOGLE_HEROBRINE_REV0 (CB:60284). Fix it to accomodate for the
GOOGLE_HEROBRINE_REV0 board updates.
BUG=b:211644878
BRANCH=None
TEST=built all variants of herobrine to make sure it compiles.
For reference:
=============
CB:56642:
commit 8b63dac061
Author: Ravi Kumar Bokka <rbokka@codeaurora.org>
Date: Tue Jul 27 19:29:18 2021 +0530
google/herobrine: configure gpio to detect board ID
=============
CB:60284:
commit 8bdbe23a93
Author: Shelley Chen <shchen@google.com>
Date: Tue Dec 21 13:17:33 2021 -0800
mb/google/herobrine: Transition BOARD_HEROBRINE to BOARD_HEROBRINE_REV0
=============
Change-Id: I6dab994e65eadff303eb88a63b8dd81e19694678
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Similar to commit 0167f5adb (mb/google/redrix: Add _HID for privacy
screen device), add the same _HID to the privacy screen device.
Change-Id: I58ad538dfaf602e3f4afb98d1a25d52753a15d93
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Add minimal Device entries with just an _ADR for each of the PEG ports
for P and M chipsets (N does not have any PEG ports).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id1009004969729eddf7005fa190f5e1ca2d7b468
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The PMC IPC method used to enable/disable PCIe clk sources uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7aa14a634dcd90c4817009db970fb209ae02c63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Due to the CL was merged: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3354766.
Update to matched id for audio work normal.
1019 id changed to 10EC1019:0/10EC1019:1 from 10EC1019:1/10EC1019:2.
BUG=b:210542422
TEST=emerge-guybrush coreboot chromeos-bootimage; Download image 14425 and tested audio function.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I542f886fe63205777837d7146169177b043cc5f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Create the agah variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:210970640
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_AGAH
Change-Id: I6adcf4e8010969cf185513d68bb1b76ea08194c7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Don't perform GPP lock configuration if
SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS config is not selected.
This patch fixes a compilation issue when APL/GLK boards are
failing while gpio_lock_pads() function is getting called from
IA common gpio block.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I392dc2007dba8169e480f82b58b7f0a1578bb09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch modifies struct pad_config.pad type from `int` to 'gpio_t'
as pad offset inside GPIO community is unsigned type and also to
maintain parity with `struct gpio_lock_config.pad` type.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I15da8a1aff2d81805ba6584f5cc7e569faf456e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch renames struct gpio_lock_config variable `gpio` to `pad`,
to represent the pad offset within the GPIO community.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bed99c401435c96c9543f99406a934d7141c575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO
reset types in Alder Lake as below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- RSMRST for GPD/Reserved for GPP - (Value 11)
Hence, created two different reset types for `GPP` and `GPD`.
Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET().
BUG=b:213293047
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186,
so we need to increase it by 1KiB (and decrease the stack by 1KiB).
Error logs:
CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size!
CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes
BUG=b:202871018
TEST=no cbfs error logs.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60529
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According schematics, we configure audio by turning on setting of
audio power and selecting I2S pin-mux.
Schematics references:
kingler: schematic_kingler_proto0_gerber_20211115.pdf
krabby: crab_proto 0_20211112_final.pdf
BUG=b:204164695
TEST=Verified by CLI command(badusbbeep/devbeep) on kingler and krabby
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: Ia6374d0e5535b7cff4df8759312786fef8b94b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Since fw config fields for DB_SD can share the same driver, we will
remove the duplicate fields DB_SD_GL9750 and DB_SD_RTS5232S.
BUG=b:212240358
TEST=emerge-brya coreboot and can boot to OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: If7814c35f63fd6fa27195d448c4d51fc980aaa9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The VBT is extracted from Chromium OS in developer mode with the device
running firwmare .
$ sudo dmesg | grep ' DMI:'
[ 0.000000] DMI: Dell Inc. Sarien/Sarien, BIOS Google_Sarien.12200.99.0 07/29/2020
$ sudo cbmem -1
coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 bootblock starting (log level: 8)...
[…]
coreboot-v1.9308_26_0.0.22-8761-gdba94f429a Wed Jul 29 16:09:30 UTC 2020 ramstage starting (log level: 8)...
[…]
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 614c0 size 4a0
Found a VBT of 4608 bytes after decompression
[…]
$ sudo cp /sys/kernel/debug/dri/0/i915_vbt vbt.bin
Using the Chrome OS recovery image, Matt DeVillier verified, that the
Sarien VBT is identical to Arcada, so add the VBT for all variants.
Change-Id: Ibab8a7b0b3f721ca434ac38b51528b81e66f3bb7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove display from devicetree as Intel's brightness
controls are not used on this platform.
This solves the below errors appearing in dmesg:
No Local Variables are initialized for Method [_BCL]
No Arguments are initialized for method [_BCL]
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icf2f2fa33abd11952c888c9502d1d5ef1ad6544f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
After checking them against schematics, a few unused GPIOs that were inherited
from the baseboard were missed, so this CL programs them as PAD_NC.
GPP_B2 => non-use
GPP_B15 => non-use (for FPR)
GPP_D3 => non-use (Test point)
GPP_E21 => non-use (for LCLW Detect)
BUG=b:211721639
TEST= USE="project_primus" emerge-brya coreboot
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I4e269bc6fb6eda7b2de57e1a9c900864d3e86e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Touch screen IC couldn't wake up after rebind with current 120 ms delay
after reset since the HID would be activated after 200 ms from reset.
This change increases the reset_delay_ms for touch device to 200 ms to
wait for the touch HID to be ready.
BUG=b:204950000
BRANCH=dedede
TEST=Verified that TSP IC could wake up after rebind
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I34cbc82e2d691266389d498e77d8389cdee23efe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
More Brya variants like Anahera and Primus have migrated to use
Alder Lake QS SoC which enables eNEM feature by default. Hence,
select eNEM for CAR by default for these variants.
BUG=b:168820083
TEST=Able to build and boot primus variant using eNEM mode.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I65d12de08adf85140976e1a7659ad7b684aa75c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AA-MGCR.
BUG=b:211950312
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ic436db8fe3ef6fb8379ec629b128c05c691ea6fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Deprecating Herobrine Rev0 board. The next board is very different
from the Rev0 board (ie: Most GPIOs have been remapped). Deprecating
and reusing the GOOGLE_BOARD_HEROBRINE Kconfig for next board and
reslotting the old GOOGLE_BOARD_HEROBRINE source under
GOOGLE_BOARD_HEROBRINE_REV0 config. Want to keep the code around in
case somebody needs it but we can remove this code in future after we
recall all the Rev0 devices. Also updating the remapped GPIOs to
match those of the current herobrine board.
BUG=b:211644878
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I67a0b282710031b927ce9022c7c535bd8d4ca1aa
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Kano has non-stylus sku. Add a FW_CONFIG field to indicate
stylus presence and add a probe statement to the devicetree for the
corresponding device.
BUG=b:208179467
TEST=non-stylus doesn't register garage driver.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I24839c39280185a6d649a82dd9f025ee305c2eed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add a new baseboard for nissa, an Intel ADL-N based reference design.
Also, add variants for the two reference boards, nivviks and nereid.
This commit is a stub which only adds the minimum code needed for a
successful build.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: I2a3975fb7a45577fec8ea7c6c9f6ea042ab8cba5
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Taeko will use two PCIE port signals with one slot, one CLK and one
CLKREQ at next build. In order to accommodate this, probe statements
are added to the devicetree. This only affects NVME SSD and EMMC.
BUG=b:211914322
TEST=Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC
and BOOT_NVME.
Cq-Depend: chromium:3358662
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below as the size of size_t differs
between 32-bit and 64-bit.
CC ramstage/soc/intel/common/block/acpi/pep.o
src/soc/intel/common/block/acpi/pep.c: In function 'read_pmc_lpm_requirements':
src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~
| |
| size_t {aka unsigned int}
src/soc/intel/common/block/acpi/pep.c:58:62: note: format string is defined here
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~~^
| |
| long unsigned int
| %u
src/soc/intel/common/block/acpi/pep.c:57:50: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
57 | printk(BIOS_ERR, "Failed to retrieve LPM substate registers"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~
| |
| size_t {aka unsigned int}
src/soc/intel/common/block/acpi/pep.c:58:71: note: format string is defined here
58 | "from LPM, substate %lu, reg %lu\n", i, j);
| ~~^
| |
| long unsigned int
| %u
The variables `i` and `j` are of type size_t, so use the corresponding
length modifier `z`.
Fixes: 2eb100dd ("soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM")
Change-Id: I27bce0a6c62b1c1ebbca732761de2f59b042a5d4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Building an image for the Purism Mini v2 with `x86_64-linux-gnu-gcc-11`
fails with the format warning below as the size of size_t differs
between 32-bit and 64-bit.
CC ramstage/soc/intel/common/block/irq/irq.o
src/soc/intel/common/block/irq/irq.c: In function 'assign_fixed_pirqs':
src/soc/intel/common/block/irq/irq.c:186:90: error: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
186 | printk(BIOS_ERR, "ERROR: Slot %u, pirq %u, no pin for function %lu\n",
| ~~^
| |
| long unsigned int
| %u
187 | constraints->slot, fixed_pirq, i);
| ~
| |
| size_t {aka unsigned int}
CC ramstage/soc/intel/common/block/gspi/gspi.o
CC ramstage/soc/intel/common/block/graphics/graphics.o
CC ramstage/soc/intel/common/block/gpio/gpio.o
CC ramstage/soc/intel/common/block/gpio/gpio_dev.o
The variable `i` is of type size_t, so use the corresponding length
modifier `z`.
Fixes: b59980b54e ("soc/intel/common: Add new IRQ module")
Change-Id: I09f4a8d22a2964471344f5dcf971dfa801555f4a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The new settings from the thermal team improve performance mainly with
respect to fan control settings.
BRANCH=None
BUG=b:212210824
TEST=Built and tested on taeko board
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I2d5c9b6dff87a2e8897d74f3be89c965db22fe16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Taeko is going to exchange i2c port for touchscreen and cr50.
BUG=b:211911780
TEST=build pass
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ib7273ba107c58e4cd90db00e301a399d7a7df76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207527331
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3df66eea13a3284d1453d7db6f7845e42a1dcb7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable unused I2C4 PCI device (00:19.0) so that UART2 (00:19.2) can be
enumerated properly, using `PchSerialIoSkipInit` to prevent FSP-S from
configuring anything regarding I2C4 (e.g. GPIOs).
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c2c4f67672ba5667ebdae9ecc01054449dd3dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Convert EC_GPI_SCI to Kconfig option with default value of
0x50 that is used by most boards.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8d47ebe76394fe1bcb217e0c6211db1566f82189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
"integrated_graphics" is already used as a "bool" at line #2128.
So set it as "bool".
Change-Id: Ic5286e691c312e8e44bbbd8e782fdfd4a13cb60f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
macOS has never defined the usual endian(3)/byteorder(9) byte-swapping
functions. This change implements these byte-swapping functions using
the OSSwap functions, which provide identical functionality. This was
tested on macOS 10.15.7.
Change-Id: I44d59869a4420030f3ce26118175304c680d57a1
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GPP_CLK1 is used for SD and GPP_CLK2 is for WWAN on guybrush.
Disable unused PCIe GPP_CLK1 and GPP_CLK2 for dewatt.
BUG=b:211566312
TEST=emerge-guybrush coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: If449453bc60ed41e104346429babc06a73acef64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Super I/O resources were unused and not listed, causing warnings
during resource allocation. Suppress these warnings by setting them to
zero.
Change-Id: I28e37c3a58f3a6b5a613733f26ac18d6a7b3be2e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41459
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bugzzy uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.
On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes under 30 ms delay on booting time.
BUG=b:205496327
BRANCH=dedede
TEST=Verified touch screen worked with test coreboot
and test touch screen 028D firmware
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Iaa4d16deb932f43ae1ab33ff5b4e74120ab670db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The latest schematics changes the EN_PP3300_SSD from GPP_D11 to GPP_F14,
I2C/DDC signals from GPP_E22/E23 to GPP_D11/D12.
BUG=b:206602609
TEST=build pass
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: I1e4aa6c540806c34b4a642f7813de0a64c6ea2b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Typically, FSP-M aka MRC debug log level defaults to `3`
meaning prints all `Load, Error, Warnings & Info` messages.
Sometimes it's too much information to parse even when users
aren't required to have such detailed information hence,
implement `fsp_map_console_log_level()` that maps coreboot console
log level to FSP-M debug log level and suppress verbose MRC debug
messages unless caller selects `HAVE_DEBUG_RAM_SETUP` config and
then the user can enable `DEBUG_RAM_SETUP`.
TEST=FSP-M debug log suggested default `SerialDebugMrcLevel`
UPD value is `2`. While this patch selects `HAVE_DEBUG_RAM_SETUP`
and user to select `DEBUG_RAM_SETUP` config to override
`SerialDebugMrcLevel` UPD value to '5' aka verbose.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea3b32feca0893a83fdf700798b0883d26ccc718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Other drivers may need to know the coreboot log level hence,
export this function rather than marking it static.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I56349f22c71c9db757b2be8eeb2dbfe959f80397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1e36c29e82af631cd650d46b67f031d275c97711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Group all data specific to each notify phase in a struct to avoid
redundant code.
Change-Id: Ib4ab3d87edfcd5426ce35c168cbb780ade87290e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Sort includes alphabetically, drop spaces after type casts and unbreak
some long lines that are less than 96 characters long.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I2dafd677abbdd892745fea1bf4414f6e0d5549bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When coreboot goes to die because FSP returned an error, log the return
value in the message printed by `die()` or `die_with_post_code()`.
Change-Id: I6b9ea60534a20429f15132007c1f5770760481af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since TGL `spi_protection_mode` bit replaces the previous
`manufacturing mode` without changing the offset and purpose
of this bit.
This patch renames to `manufacturing mode` aka `mfg_mode` to
maintain the parity with other PCHs as part of IA-common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6d00f72ce7b3951120778733066c351986ccf343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The `pci_dev_disable_bus_master()` function doesn't need to be guarded
with `CONFIG(PC80_SYSTEM)`, so move it out of the guard.
Change-Id: I813e0f72c3c624c73ab9ecbe7512359608ace927
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I20d79d4b42908314dbf7021a67b92e5fd2b79556
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I72c0e0c3968cb2e92b35381691762148f4c270e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I71f22100fe56a8b88321d220f98ac03887ce6bd7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I9b523ebee2d2af8585736588306ca687dfe16003
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ifcdfd9fff197391ca0da083e7f6151c2dffe3374
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I5c437ee2d62415f9048a24ad4a517fc33eec3cf1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Eric Lai