Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: Ib7396189f4bee0fdd6a8ce5c9ab1277806cb5dcc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ca9efe59a7fcb99412410d509a7f9a91b6ef3ec
Original-Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214600
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9047
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e
Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216927
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the formal devicetree way for bringing up each of
the cpus. This includes providing a cpu_driver as well
as calling arch_initialize_cpus() with the proper
operations to start the cores.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP on ryu.
Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a
Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216926
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9043
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be
SMP aware but the ARMv4 part does not.
Until we need real SMP on ARMv4, work around that situation
with stub defines.
Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9046
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds SMP bring up support for arm64 cpus. It's
reliant on DEVICE_PATH_CPU devices in the devicetree.
Then for each enabled device it attempts to start then
initialize each CPU. Additionally, there is a cpu_action
construct which allows for running actions on an individual
cpu.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted both cores on ryu into linux.
Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e
Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216925
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a simple spinlock implentation for arm64. A value
of 0 is unlocked and a value of 1 is locked.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup on ryu.
Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c
Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9040
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The spinlock header file was not residing in the correct place.
It needs to live under 'arch/smp'.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with SMP. spinlock.h found.
Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0
Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9039
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The load-acquire/store-release operations (including exclusive
variants) form a basis for atomic operations. Also remove
the dmb, dsb, and isb functions from lib_helpers as barrier.h
already included these. Lastly, utilize barrier.h.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup using barriers.
Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118
Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216921
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9038
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0
Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216920
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9037
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I4bf5d98e409840cf07a7759e9273d770f3bbf8bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ec672e52eda69f2b5abb747807a496bb973088f
Original-Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216429
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9036
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f
Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216426
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9034
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of directly using the clk_src_id based on enum for clock source, every
device needs to have its own set of clk source ids defined. This prevents
accidentally selecting a wrong clk source if the ids are different from host1x's.
Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id
represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for
handling the common clock sources based on id to get the proper frequency in
software.
[pg: integrated a later commit to fix the build]
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5d40fb49b81e8838b2be071d32c466213215e0d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27d5d6a34d1c826c6095c18368efb78c228d4ca8
Original-Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216761
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 13c30c50a9e8a7f3c48673a2f6c144ba546129b6
Original-Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217342
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9033
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide access to the MIDR_EL1 register to obtain the
main id for determining CPU implementer and part/revision
information.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and printed the output of this function on ryu.
Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c
Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216423
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9032
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9
Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216421
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9031
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: Id046592415574badb97026224e1e525c174eece4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7
Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/215863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9030
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Expanded sdram.c to add support for LPDDR3 init. This code can
be used with matching BCT .inc files to have LPDDR3 SDRAM
initialized by coreboot instead of the T132 BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I53801d9399dbf67fd86d0a2521174f0668567620
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 60e130c47c1894925a12f251af5b83a1fa144d57
Original-Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214753
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149
Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9028
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of calling out the gpio index and port numbers use
real names. It's semantically clearer and there's only one
place to adjust the hardware values.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted.
Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c
Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215542
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9027
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
more plld errors observed from the kernel.
Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b
Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Depending on the requested frequency the plld cannot
necessarily obtain the exact clock. Therefore provide the
closest configured frequency as a return value. This is
equivalent to the t124 patch.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Built and noted plld actual value close to requested.
Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863
Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214843
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/9025
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With the latest changes to include stack storage within ramstage, we no longer
need to define Kconfig options for ramstage/exception stacks in arm64.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel on ryu
Change-Id: I7361d8f567453e775240151fd1180c49025141b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9aaa89115a67606fcb66eb354741043f7f2094bf
Original-Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214607
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9023
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These symbols should have been removed with the stack
refactoring. I'm not sure how it was missed.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel with both cpus.
Change-Id: Ia6c2103d7b5e2c9d74cdc5d1b5f42f8954812231
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d9432b5cf0cce3bfdbfd5371fb3280e3cc746a42
Original-Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215541
Reviewed-on: http://review.coreboot.org/9024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instruct the SoC to bring up the 2nd core.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Brought up 2nd core in Linux.
Change-Id: I4b31ea5f1466c43abce273b2bfb6a4d06b7faa63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74c62e62a6790de65e303123abee2be1dfffbee3
Original-Change-Id: I5f5febc4719951188106041f73625231eafe1b08
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214778
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9022
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Until PSCI is functional the other core still needs to be
brought up in the kernel. The kernel boots these cpus with
the spin table which is just an address in memory to monitor
a jump location.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up secondary core in linux.
Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca
Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214777
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Optionally bring up secondary cpu according to devicetree.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and enabled bringing up second core on ryu.
Change-Id: I5ede8b2f1b30a6170520cc11c18e263793cea301
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7da2dcce9be653a3c551c33bbefb3810a6949e9
Original-Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214776
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9020
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provides a minimal API for coordinating with the SoC for
bringing up the secondary CPUs. There's no eventloop or
dispatcher currently nor does it do anything proper when
one of the secondary CPUs are brought up. Those decisions
are deferred to the SoC.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu using this API.
Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376
Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214775
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For the secondary CPUs the set of banked registers needs to be
initialized. In the boot CPU path all both the CPU's banked
registers and the global register set is initialized.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu in kernel.
Change-Id: I3a7bc708f726c4435afca817a251790f536844d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 813b0a8b3faacf2342164d385e5837ebede29b18
Original-Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214774
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9018
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
exception_hwinit() provides a path for just setting the hardware
state. This allows for other CPUs but the boot CPU for setting up
the appropriate vector table.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel.
Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1
Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214773
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No need to pass in the same value for the ttb after just
calling mmu_init(). All current users are setting this once
and forgetting it.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8
Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214772
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To allow setting the entry point for the secondary CPUs
provide a pointer, c_entry, which contains the location
to branch to after setting up the stack.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel on ryu.
Change-Id: I03e54b081aa5ff70b90fbd7f1b243fdb4f42c5a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f692c5814ea5c7ff4895576e1db8361ff3b7d9fb
Original-Change-Id: Ic2f6c79cde708b24c379345aed1e2cc0760ccad8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214771
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9015
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move the stack seeding out of assembly and into C so the
code in stage_entry.S can more easily be used. The seeding
of the stack doesn't touch at least 256 bytes to account
for current usage at time fo the call.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel on ryu.
Change-Id: Ib9659ec4265652461bde746140567f21533cc265
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f478cfe175aa674cdfdbbd890663eeaad9d82b1f
Original-Change-Id: I44004220a02b1ff06d27a0555eb4e96d9e213544
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214770
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9014
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of defining the stacks by Kconfig options include
the stack sizes for all the CPUs including each of their
exception stacks. This allows for providing each CPU
on startup a stack to work with.
Note: this currently inherits CONFIG_STACK_SIZE from x86 because
of the Kconfig mess of options not being guarded.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into the kernel on ryu.
Change-Id: Ie5fa1a8b78ed808a14efeb1717b98d6b0dd85eef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6524993f016aac2ac8cd9dba9fbdd9a59260a2b6
Original-Change-Id: Ica09dc256e6ce1dd032433d071894af5f445acdb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214669
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9013
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a common entry point arm64 cores coming out of reset. Also,
take into account CONFIG_ARM64_CPUS_START_IN_ELx to set the
correct SCTLR_ELx register. The SCR_EL3 initialization was removed
as that can be done in policy code in C later. Part of this refactor
allows for greater code reuse for the secure monitor.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=built and booted to linux on ryu
Change-Id: I429f8fd0cdae78318ac171722fa1377924665401
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f92a5a01f07bc370735d75d695aedd8e2ab25608
Original-Change-Id: If16b3f979923ec8add59854db6bad4aaed35e3aa
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214668
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9012
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Depending on the armv8 implementation the cpus could start in
EL1, EL2, or EL3. Therefore allow the SoC to select the appropriate
mode.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I8787fd1bc4e14f03d829e6a5e5af915e29314770
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb6b092a43e34fbc64d941bb62f19a6b8ac2c5de
Original-Change-Id: Id063681ef7691097e528c105fffac5d467585e4e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214666
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9010
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are 2 things wrong with the current implementation:
1. the stack isn't guaranteed to be aligned to CONFIG_STACK_SIZE.
2. the stack isn't necessarily CONFIG_STACK_SIZE bytes.
Utilize the smp_processor_id() function to obtain the correct
cpu_info structure to obtain the correct index.
BUG=chrome-os-partner:31545
BRANC=None
TEST=Built and booted.
Change-Id: I43d4a2baa26e48147bc0dbdb3e9e13ad023f0690
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e2c32b1a46ac8dc1364ed03c195322c0bf28dd7f
Original-Change-Id: I2825118e2313dbbf13712a4afdfa05a2e38ee3a4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214665
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9009
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to accomodate MP on arm64 one needs to be able to determine
the current logical processor id. Because it depends on the SoC
implementation the SoC needs to provide this implementation.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I2f09df9bf7d4f829d8f45471bf7281a4ddba2fc8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6033e73d70c3b8296b36ff36b4b848b176917e12
Original-Change-Id: I9511b54b5a1ab340b0f1309b0d9976be68b50903
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214663
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are 2 cores visible to the OS and both need to be
brought up. Therefore, provide the proper number of cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted CONFIG_MAX_CPUS=2.
Change-Id: I8a99891506af0fb3aa0284475c3c4be8bb69268b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efa6c0343521dd98b86eacc94737f3497b721f95
Original-Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214661
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This just removes some unneeded symbols and comments. Additionally,
moved most of the absolute symbols into the individual sections.
Also, aligned data sections to 64 bytes (typical cache line size).
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted through coreboot normally on ryu.
Change-Id: I8ceed5a48078f70911122d304f2953795af0b421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0524d4769613dc4a762e0a8e1bc1d2549d2df743
Original-Change-Id: I304e3702247a06507f5f4e23f8776331a3562c68
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214662
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the
trust zone. Rest of the TZ memory can be used by el3 monitor.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and boots to kernel
Change-Id: I448574860186815992c15a358a1481faecf224bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de0f3f8016a4e566a2bacb967ef92213648d8257
Original-Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214370
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:30748
TEST=Verify that LTE modem appears on USB during kernel boots on Ryu.
Change-Id: I5b73a632ab827abe9c064a097e04d2c9030f9b46
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 070538e60b384d17e17ba3544881ef642c3f33ba
Original-Change-Id: I8ec1f94c9aec5b4895a01cdfd3b86f88cd6bb877
Original-Signed-off-by: Ben Chan <benchan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9002
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to more easily bring up the 2nd core refactor
the cpu startup logic. A common 32bit_entry.S is compiled
both for romstage and ramstage to provide the common 32-bit
entry point.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted ryu to the kernel. Also, can get the 2nd
core up out of reset.
Change-Id: I0c2c9f637189009767e8d5510732678c64e62a2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7394b271bf67dfad8a601f41faaac8f07ae6d4a5
Original-Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213850
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31515
BRANCH=None
TEST=test_exception generates a page fault which is handled by the exception
handler and execution continues after eret from the exception
Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e
Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213661
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the bus number enumerations from funit to make the
pad names and bus numbers consistent and clearer.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: If84ed825537f598c033dcacbcba759e0fe4e90ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4375a8e47f572d618044f65603fb9288832f936
Original-Change-Id: I817a56e879ecc96474128d624dc46c12ebc5c7a8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213492
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8997
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of requiring the mainboards to know the magic
literals for the bus numbers provide an easier name to
number to handle all the weird ordering.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I4a90f5f5f3ed1d936e2eee23f4726069adc49cc7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b028e90650384c947a3d0ee84c6d1346a22b22b9
Original-Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213491
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8996
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df
Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212795
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to access secure device register space the cpu
needs to have the page tables marked as secure memory. In
addition the page tables need to live within secure memory
otherwise the accesses default to non-secure.
Therefore move the page tables to the trustzone region. Remove
the TTB_* config options as well as removing the TTB reservations
from coreboot's resource list.
BUG=chrome-os-partner:31355
BUG=chrome-os-partner:31356
BRANCH=None
CQ-DEPEND=CL:213140
TEST=Built and booted into kernel.
Change-Id: I1fc8dda932c36935f8523792bc1147f6b0743d11
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1522a83bb57e33749843d5b3ea5545ded97a3953
Original-Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213141
Reviewed-on: http://review.coreboot.org/8994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=none
BRANCH=none
TEST=built ryu, booted to recovery mode OK
Ran TegraShell and could r/w I2C6 regs OK
Change-Id: I7dca131ab5bd4dac50891937f792ac70b1bb532f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 29591a97fbb8fc42143ff6c7838c9935834ca516
Original-Change-Id: Ic74e3518ab69ec7b1bc3bc4f637b7b38b85734c9
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212926
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8993
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I2C6 has a special mux in the SOR/DC domain, so there's a ton
of devices that need to be clocked, SOR unpowergated, and then
the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register.
BUG=none
BRANCH=none
TEST=none, built rush/ryu AOK
Change-Id: Ibeeda763b7fb30fabaee85d03fbf7d5efb42a30a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b4da98e20a89b045f2d5b5033a27cd7ab855f35
Original-Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212887
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Added distinct functions for clock_enable and clock_clear_reset,
and rewrote clock_enable_clear_reset() to use them. Useful when
unpowergating SOR partition, for instance, where we need to
enable a bunch of periph clocks, unclamp SOR, then take all of
those periphs out of reset.
BUG=none
BRANCH=none
TEST=none, built rush/ryu OK.
Change-Id: I92edf3104adc8eb7637c47a5e000788fd55f1452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd76a6d0d0fb7922c6beacbc1cfcb365b6537b2
Original-Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212916
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tegra132 has 2 different paths for booting and resuming from
sleep. The boot path uses the typical bootblock, romstage,
and ramstage. However, the resume path is completely orthogonal.
cbmem_initialize() attempts to recover the cbmem area, but
that functionality should not be used from romstage because
tegra132 is by definition in a fresh boot if it is executing
romstage. Therefore, use cbmem_initialize_empty() so that cbmem
is always initialized from scratch on each boot.
BUG=chrome-os-partner:31239
BRANCH=None
TEST=Built and ran on ryu. Was able to enter recovery and stay in
recovery without entering a reboot loop.
Change-Id: I0453c15e57a873a7ce7a63190dceafb75e4c9342
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 28ebc092e6721552c18db03e7578424c23a64b64
Original-Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211424
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8990
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6
Reviewed-on: http://review.coreboot.org/8972
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
1. Fixed some errors in selftest compare to reference.
2. Some WA steps for xhci in sleep trap is only for lpt.
BUG=chrome-os-partner:28234
TEST=compile ok, run selftest on auron to verify
boot to OS
BRANCH=None
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131
Original-Reviewed-on: https://chromium-review.googlesource.com/215646
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf
Reviewed-on: http://review.coreboot.org/8971
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Samus has a PD MCU, and should handle PD MCU host events.
BUG=chrome-os-partner:31361
TEST=Manual on Samus. Verify that ACPI Notify routine is called when
host event is sent from EC.
BRANCH=None.
Original-Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214860
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Alec Berg <alecaberg@chromium.org>
(cherry picked from commit d0752be013f66313d4218338e62372d0f5975097)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I08eb51eceeb7d2835d55e7e861126b137de72bf6
Reviewed-on: http://review.coreboot.org/8969
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
some clock gating and pcie settings are missed in original code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Original-Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214568
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 57e42c781d435092a08238461f0605dbf092e576)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia62a50f28a411bbd2ba51b94de17ca70051ea093
Reviewed-on: http://review.coreboot.org/8967
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This can be used to know if HSIO registers need updating in ramstage
but it is not possible to query the ME for HSIO version after sending
the DRAM-init-done message.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=build and boot on samus, check for HSIO version messages in log
Original-Change-Id: Id6beeaf57287e8826b9f142f768636a9c055d7eb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 637cbf5c1a1d922dab3f8a5cd4b3cd05617d1b92)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29ce907804e892afde5f91e0b21688a50217cf13
Reviewed-on: http://review.coreboot.org/8966
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This macro is incorrect and should be counting by dword instead of byte.
The effects of this were subtle: incorrect events in ELOG and hanging when
waking from USB input because PME_B0 was not disabled properly.
BUG=chrome-os-partner:31611
BRANCH=none
TEST=test wake from suspend with USB keyboard
Original-Change-Id: I7caf1d46283071787550a9765703897181774957
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214258
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b
Reviewed-on: http://review.coreboot.org/8965
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU
BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus
Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/214024
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1
Reviewed-on: http://review.coreboot.org/8964
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This can be shared between mainboards, they are still free
to override if needed.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus
Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3e40cb804e7a95ce2183ebb3ef5d86820aef61b5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8961
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The original code won't set power gating for disabled port correctly,
due to it must be set before Lock
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify bit 24, 26 is set in RCBA(0x3a84) for samus
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab
Original-Reviewed-on: https://chromium-review.googlesource.com/213561
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 066c8c81df8be9ae9ab7b33342a93b0b3ea7b240)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic7c87b04863f93de5665d72e0f95b4105b1d4d3b
Reviewed-on: http://review.coreboot.org/8960
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
fixed a coding error and sync sata configuration with ref code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Original-Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213137
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 0fbb59e3c5117a513ef19117560bb41dfe8c0d71)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I99a389b06f4ec077c298100ca878c68ef69debfa
Reviewed-on: http://review.coreboot.org/8959
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This was a merge error when I was pulling in some of the
code into this file I put it after the read of CAP2 but
before it is modified and written back. In the end the
DEVSLP bits are getting set/cleared that need to but the
other bits in the register may be wrong. Also when enabling
devslp set the devslp-present bit in each enabled port.
Also remove much of the 0:1f.2@0x98 setup and the attempt
to write (the write once) CAP register that is already
being written in the reference code.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212308
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9110a42982183b2954c865abbf18e008a39c997c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7db5c7ccf619aa28856388dd40f59495ef6d7e77
Reviewed-on: http://review.coreboot.org/8958
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
In order to prevent possible TPM lockout due to PLTRST assertion
shortly after powering up add a small delay before the reset.
This will affect cold power up only, reboot/resume/warmboot will
all have the flex ratio locked already so this reset is unneeded.
BUG=chrome-os-partner:29859
BRANCH=None
TEST=build and boot on samus. I tried unsuccessfully to trigger the
TPM lockout, but I was not able to do that consistently without this
patch so it is unknown yet whether this is 100% effective.
Original-Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 20413f2eafa144f5f381eb6f92d8b959415ca049)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I665e9ed1faa65e88d988660a24bdad40a4c5ab7e
Reviewed-on: http://review.coreboot.org/8957
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
TCO registers are 16bit not 32bit. Also do not log the
TCO reset event in S3 resume path to avoid it being logged
when TCO is not actually tripping.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=manual:
1) build and boot on samus
2) modify kernel command line with nmi_watchdog=0
3) while sleep 1 ; do echo -n V ; done > /dev/watchdog &
4) fg 1
5) ctrl-Z
6) wait for reboot
7) check event log for TCO event
8) check suspend/resume path to ensure no TCO event logged
Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211840
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6
Reviewed-on: http://review.coreboot.org/8954
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211611
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99
Reviewed-on: http://review.coreboot.org/8952
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
I was using the wrong datasheet for these parts. Revert
to the previous geometry settings so they work again.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211610
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f8591e1579d205609a959082d8047d407b4f6a5a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I52ed3609c9686fef13711578597065ca4e907df4
Reviewed-on: http://review.coreboot.org/8951
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot
BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f
Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Original-Reviewed-on: https://chromium-review.googlesource.com/210870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a
Reviewed-on: http://review.coreboot.org/8950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
- geometry was incorrect for 8GB modules, should be x32,
so refactor the rest of the geometry to match
- some of the timing values were off, calcualte new values
from the datasheet
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210660
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 8b2ce5c58442e039f5f6e0e053c0072fdec76e9c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29daa9e0ad1bf32be914c0d998f188b9827344a1
Reviewed-on: http://review.coreboot.org/8948
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=None, but similar usage tested on tegra132.
Change-Id: I91ef59212a2dd1b48640b1aaaab6acacf4e9b3e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b1dd8380f04641f4f73caa3441f349d9eca6be05
Original-Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219713
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Coreboot generic CBFS media API does not support
multiple media access instances, but it should.
With this fix the CBFS context (memory cache for
SPI accesses) is shared among all open media access
streams. A better memory management scheme might be
required, but for now this fix allows to support
booting deptcharge and accessing VPD through two
independent CBFS media streams.
BUG=chrome-os-partner:32152
TEST=no exception is thrown when the second stream
is opened
Change-Id: I62889089b4832c9e9760ef24ecc517220d8f3ec4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 691f9794805d04beff349f1bc60ac9d7530d7cbf
Original-Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219441
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We don't set these by default in upstream.
Change-Id: Ida7aa498e0fe291c6cf3cf31d6516530a9d136d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/8988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Includes moved into $(CPPFLAGS_*), so add that to VBOOT_CFLAGS.
Shift vboot build parameters from the environment to be make parameters,
and use $(MAKE) instead of make to fix non-Linux build systems.
Change-Id: I5aee9935ab36ad571fbcf9f6fa8d8ace2bac16b3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8703
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.
Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9
Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212161
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=None
BRANCH=None
TEST=Built rush and ryu, ran on rush into recovery mode.
I2C6 is in the SOR domain, so a lot of further init is
needed before it can be used. A follow-on patch will do this.
Change-Id: I5701bfcf1d0bb8c6edd3d885b1b7dd14e67ba73a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69908f2489d1a918bb109d43e713932214741b46
Original-Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212671
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8940
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Able to get sporadic USB communication in depthcharge on ryu.
Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8
Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212333
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Continuing down the path of easing mainboard maintenance
provide a way to bring up the USB 2.0 ports through funit.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=With ryu patch was able to get same sporadic USB communication.
Change-Id: Ic75821acf1d48a9f1659849fa007251c61658640
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5183c5081a95219f84c4d6dfca70926b383abc1a
Original-Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212332
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I218c751f41fb881af4fed0bcccc378dde1fd07b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a26e07b58f454c598bf5b7a4940c238135548bbd
Original-Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211039
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The clk_rst.h file wasn't including files that had
functionality it was using resulting in broken builds
if just this file was included.
BUG=None
BRANCH=None
TEST=Built with just this file included -> no more errors.
Change-Id: I229cb3890f1320edc3bc3e82469b301cbaff0f72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03b455aa9da64d6e110690206db65939ca023c27
Original-Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212331
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8936
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make sure the array size matches the number of supported
FUNITs. Also remove the FUNIT_NONE enumeration so that
there isn't an empty slot in the array at index 0.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built when array wasn't large enough. Compiler threw an error.
Change-Id: I1b83ddff799a56ea39efa23a91dca1a9e0f10862
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4cbe74905bbeb815e9f20bcc0fad3751a3133b04
Original-Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212330
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8935
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To provide easier access to the base addresses of the controllers
by funit identifier add the base addresses to the data structure.
BUG=chrome-os-partner:31251
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built.
Change-Id: I427d432beef36e6342c188d607c0e33b3845c0e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8f09e61e3dbfbc96980b98ad25e09554fd49a8d
Original-Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212169
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8934
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide consistently named base address enumerations as well
as provide some that were missing.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built.
Change-Id: I2551bbaa83d1d2c158b87d239098c22fba4d3961
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07954a231f3c11c4102f9db0a2d35654abda208f
Original-Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212168
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to prepare for USB initialization move the clock
configuration into a separate routine in the funit library.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted into recovery mode.
Change-Id: I090b5d12c5805f0179c29cfc62499fad2f245c01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7adaf969762b8296034f4373f550a902d1ed06b
Original-Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212167
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8932
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Just use direct pointers to the registers in the pre-filled
data structures. In 64-bit the sizes increase, but it's small.
The fields now directly point to the correct register so no
need to do any arithmetic to identify the correct register.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted on ryu into recovery.
Change-Id: I0de85c486c005aed23b6118ec91b45dd39acdfb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 358b78c1c4cb72e0166f91b36011676e65576666
Original-Change-Id: I186bf5d145437472126067960e62d7ed6a25f295
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212166
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8931
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the new funit API to do all the dirty work.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through depthcharge and into recovery just like
before.
Change-Id: I8625a06dd847bd3dcfc3ce5a50a31d6aff0b860f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebc04a174269ae072eda804e172fd24362f417d2
Original-Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212152
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently rush needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With the changes for adding non-cacheable memory range and adding DMA
region, booting from USB reaches same point as MMC.
Change-Id: I82d97840fad8cc96bf958c6efa13d2fdc1233d79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b182651a1b6db1a7adbf315b6865467590a0785c
Original-Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/212193
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfully for nyan, big and blaze
Change-Id: Idddd40e409b56875436db6918d05f2889d83870b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1
Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211200
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8927
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently ryu needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With usb added am able to talk to a USB mass storage device
albeit inconsistently.
Change-Id: I7efaf2ba44cc94dc64af3f1cd916bdc5c7ff0795
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e93389479518ee28dc3477da0c6e6e33fa8a47d1
Original-Change-Id: I6b5c052ccaafce30705349e07639dffbb994901f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212162
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8926
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Non-cacheable normal memory is needed when one wants an easy way
to have a DMA region. That way all the reads and writes will be
picked up by the CPU and the device without any cache management
operations.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With a bevy of other patches can use a carved out DMA region
for talking to USB.
Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6
Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212160
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The high address field was being shifted in the wrong direction
resulting in the lower 12 bits of the upper address being dropped.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Was able to run on ryu and not hang while wiping memory.
Change-Id: If1d7ef1c63ce79c143af3c5012b206ee297cd889
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b0da6fa391db2ec2bc1e0bec9325f4e74b5286c
Original-Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211941
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8923
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use funitcfg api for bootblock, romstage as well as ramstage
initialization in rush.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully and boots till last known good point.
Change-Id: I243597de9ec13904a2bb58a04b402f9545424760
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0618ea6828bae3e700b85b79b185aec28568b8ae
Original-Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211766
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8922
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.
Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3
Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211765
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Two changes: 1. A44 ID straps use different gpio pins than nyan.
2. A44 uses tristate values instead two state values.
BUG=none
BRANCH=none
TEST=Built and tested on A44 board.
Change-Id: I6a36f6da0c9f6168780606ba76595c7a0af8e8bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2eb0cae0e3396da1eaeaa72411c4b74300138a7b
Original-Change-Id: Ia2a4309d3b63b0a94d79465dd727b01fae01e1b9
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211753
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
nyan blaze fails to boot because tristates of the board id are interpreted in
the reverse order. this change fixes it.
BUG=none
TEST=Booted Blaze to Linux. Built firmware for Storm.
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4ff8a15cf62869cea22931b5255c3a408a778ed2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3f59b13d615a8985edf2029d89af05e95aefad33
Original-Change-Id: I6d81092becb60d12e1cd2a92fc2c261da42c60f5
Original-Reviewed-on: https://chromium-review.googlesource.com/211700
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/8980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The name was changed due to review comments misunderstanding, it
should be restored to properly convey what the function does.
BUG=chrome-os-partner:30489
TEST=verified that Storm still properly reports board ID
Change-Id: Iba33cf837e137424bfac970b0c9764d26786be9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c0fff28c6ebf255cb9cf9dfe4c961d7a25bb13ff
Original-Change-Id: I4bd63f29afbfaf9f3e3e78602564eb52f63cc487
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211413
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8979
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current 2 boards were setting up clocks and enabling
peripherals that apply to the SoC generically. Therefore,
move the common pieces into the SoC code.
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and booted through depthcharge on ryu.
Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809
Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211191
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8917
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The I2C pads connected to the EC are pulled to 3.3V. Therefore
the pads need to be configured as open drain.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and booted through depthcharge on ryu
Change-Id: Ie5eadfe6aca78eb31fbca4e8d8117d1061acbbec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1530e7e7f500be47355eada56591ac2dbf1e9326
Original-Change-Id: Ia4ad2377d01296235fc7efbba72fa790016c04af
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211135
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8916
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Ryu's EC talks proto v3 over i2c. Select the correct protocol.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built and ran on ryu. Coreboot can speak to the EC now.
Change-Id: Iaed0d2db3c3c93667d65beea98b9719bdbbbfe41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b71cad3bb1e9b64c48b6f2eeb7573c408a508fb3
Original-Change-Id: I50e192cd58f7a29103ab94afc002da18822d4080
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211240
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8915
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the supporting Kconfig options and infrastructure for
performing vboot firmware verification.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Built and ran on ryu into depthcharge noting vboot paths
being taken.
Change-Id: I1d803208cd5789bd73244b91beac6a5a4598ea70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2e7d84725739843a1ed1868fcadebb60477a6dc
Original-Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211134
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8914
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The original intent was to set the equivalent flags by default
for the PAD_CFG_* macros so as not to make the usage too chatty.
The GPIO_INPUT variant didn't have the PINMUX_INPUT_ENABLE field
set. Therefore, automaticaly set it for PAD_CFG_GPIO_INPUT().
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on ryu.
Change-Id: Iab058874314430de08010912c3fc758a98b73eb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 535cdb354efc067caf32d32641846f11fb0cd2ee
Original-Change-Id: Ifb630601cf04d2984542933382aace16540863ad
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211133
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The tegra132 SoC provides the monotonic timer API. Therefore,
ensure the reset of the coreboot infrastructure is aware.
BUG=None
BRANCH=None
TEST=Built and ran on Ryu. Noted that ramsgage is showing timings
for each bootstate.
Change-Id: Ifc2d5b7eb318ffac0ad79bfbc3d1b61a7ba4b10c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b691572c63a43a01a290f1c00f71097028d1415e
Original-Change-Id: I9b8fcf38cba9bdaaf0455701df1d6328bf1927c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211132
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8912
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().
For the existing tegra132 boards remove the unnecessary files
from the build.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.
Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c
Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211131
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that there's a working udelay() in tegra132, upclock
CAM_I2C and SPI1 to the same speeds as used on Nyan.
BUG=chrome-os-partner:30998
BRANCH=rush_ryu
TEST=Built Rush and tested, no nack errors seen.
Change-Id: If1ee6d5c711252e294818d6263732bb34b2fe6f0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 859c0d4fde2cf098cb829e96a5d6dec394bea600
Original-Change-Id: I58fd03ed3512c2498c793cfe30b0c302e4b0e3d4
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The gpio_index_to_port() incorrectly was dividing by
GPIO_PORTS_PER_BANK on a value including the bit number. After
masking off the BANK offset just divide by the number of gpios
in a port to get the port offset.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge. Printed bank, port, and
bit numbers for validation.
Change-Id: I3fbbb90f369bace90e787148a58795b7b1b40c1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97e1f830b4a8e948673433bfa6d81586204b6ee2
Original-Change-Id: I8bb50e922c9fd7c0a1c247ba95394f6deb9f1533
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210909
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8908
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I erroneously added GPIO_NONE_INDEX at the beginning of the
enum block effectively putting every GPIO index off by 1.
Instead, move it to the end.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge on rush. Also
printed out banks, port, and bit offsets to validate.
Change-Id: I4f6510c1b6fcdddddbe36ff738299b4439ffc597
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c020c2125b9a2378a7faa17209d1b78e019c7df
Original-Change-Id: I0471480e8658de9e534beb859a1f5027a961d73e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210908
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8907
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's helpful to be able to track this information. Therefore
dump it in to the console log.
BRANCH=None
BUG=chrome-os-partner:31126
TEST=Built and ran on rush. Revision information is put out on the
console.
Change-Id: I22e7d222259c1179b90edda6d7807559357f6725
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18d318331b696a6a32e0a45b8f903eb740896b02
Original-Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210903
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8905
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are used by the LPDDR3 code in sdram.c.
Based on the schematic and email, I've filled in 4 slots
in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits
1:0) for Samsung SDRAM. I haven't tested the other 2 types of
RAM (Hynix and Micron). The 4th slot is a fallback slow Micron
config.
Previously existing configurations were dropped.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I55a737db269fe5fac1565d58bd8f8afcbc5beecb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a431466171a85a5c8151e7466eb5f77862e7b44
Original-Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: a45e7788dd78697ac5f48b6cc64108ca0e4912dd
Original-Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216000
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of calling out with function names all the possible
combinations of interface and device provide one call to the
mainboard to configure all the necessary bits.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and ran on rush.
Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d
Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210838
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8901
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Rush has its EC on SPI, and Ryu has it on I2C, so need both
mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds,
due to romstage.c being in the common tegra132 subdir.
BUG=none
BRANCH=rush_ryu
TEST=Built both rush and rush_ryu images OK. Will try to
boot on Ryu later.
Change-Id: Iddbf9e9f6de7ba7244f9dd2e810fb6178937c85a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d8b81717c366d19b43964bed3c4047598db4495
Original-Change-Id: I48d9530697d5669177ecd9ba3c34360197002003
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210595
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This resolves an issue where large sections of the cbmem logs
were being dropped on AMD Fam10h boards.
Change-Id: I0e4e86e169aa4f20f06472f1a6e3136705ae4f9d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8851
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The cbmem console output retains usage of the CRLF line ending.
Converting line endings to the standard UNIX LF avoids the
need to use dos2unix before running analysis on log files.
Change-Id: I74a04ee69836d82640c94f250465acb4d1ee1071
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8857
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
I broke cbfs loading with commit 358901. As multiple
functions are being reused one needs to ensure there is
always a cbfs media object allocated on the stack and
initialized. Ya for no common writable globals.
TEST=Ran qemu-armv7. CBFS loading works again.
Change-Id: Ibd047af7dcd8575e6203651471079fc2042da282
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8973
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built for ryu.
Change-Id: Iff981509f258c8fe7bbc2e24ce87bad0c43a55b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8a7ee469124eeb6d05b978b5e68a2fc03b102f47
Original-Change-Id: I2d32d702da38bc0d87a1c159113bba32f4c03407
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210837
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8879
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on rush. Observed consistent results.
Change-Id: Ibfa6fc188a7c503cfad41420ed50c7a88fdec579
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2245478f8e21167e93a6e97b12730788a7f927ae
Original-Change-Id: I1d5d38322bda6740a0ea50b89f88b722febdee22
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210836
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of hard coding certain pieces of a board in the common
chipset code provide a way to initialize things early in the
bootblock path. Add a bootblock_mainboard_early_init() function
before console init to performany necessary mainboard initialization
early in the bootblock.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:29981
BRANCH=None
TEST=built both on rush and ryu. rush still behaves the same.
Change-Id: Idcf081eeffd189a4e2cbfeb8a4ac5dd0a3d1f838
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a523add6de03bea0d88e95b9dbb5e283c629400
Original-Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210835
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8877
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Start using the soc_configure_pads() API. This allows for
bulk processing of pads.
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and can get console messages on rush.
Change-Id: Id2c8a685a4566bda8fc260f74f5dffdd0da03056
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbd7c81bc0777b38bb641b9fcf89425bfd93566d
Original-Change-Id: Iaa6a6ff4d559aedb98b078e87b0ecddefd3402d6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210834
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of sprinkling the pad configuration and pinmux
selection throughout the code allow for a data-driven
initialization sequence. Most of the calls in the
original pinmux functions require 12 bytes per pad
plus the support code. This implementation allows for
4 bytes per pad in addition to the support code.
BUG=chrome-os-partner:29981
TEST=Built and booted into depthcharge on rush.
Change-Id: I22c243a5f9891a97e14b78d8c8064e36adaf50b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9329c17bbadcaab803b38842e38e1704d262817d
Original-Change-Id: I3a119b4068e880b74a0a1597f143d7c4e108a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210833
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8875
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change syncs the i2c driver with the one in depthcharge.
BUG=None
TEST=Booted Veyron Pinky
BRANCH=None
Change-Id: Ic9c7006770bba50fd412e0bcefc52f879b7195ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Id: 95ca6c88061062c0de95a8dd3567a71a372771b0
Original-Change-Id: I0d0fdefa58c5b4cc5c991be40796a800ccf074a5
Original-Reviewed-on: https://chromium-review.googlesource.com/218873
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8872
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The Rk808 PMIC is a part that will probably be used by most Rk3288
boards, so it makes sense to keep it as common code in the the SoC
directory. This patch puts LDO control functions into rk3288/rk808.c, so
that the mainboard only has to call a simple interface to set up the
specific LDOs it requires.
BUG=chrome-os-partner:30167
TEST=Booted both this and the old version with a stubbed-out
i2c_writeb(), ensured that the final values are the same.
Change-Id: I7efa60f8a357ce6be7490e64d2e0e3f72ad16f1c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4df22cd78ee04fefc6f7fa0e5c3d903eb1794422
Original-Change-Id: Ic172f9c402e829995f049726d3cb6dbd637039d1
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217598
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8871
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds code to read the board ID from Pinky and put it into the
coreboot table.
(Note: This implementation differs slightly from Tegra since it pinmuxes
the GPIOs inside board_id(). That means the pinmuxing might be set more
than once if called in multiple stages, which is perfectly harmless and
in my opinion cleaner than having to (remember to) do it manually in one
of the per-stage files.)
BUG=chrome-os-partner:30167
TEST=With depthcharge patch, select -rev1 device tree for board ID 0.
Change-Id: I265fafcb176a31a46f7792ecf352f1671be7dd41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9da10ce8b62ec98243fc7c82544b3004316799a8
Original-Change-Id: I5b5689373e1e47b1e0944b5fe5f2e70a285b931f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217675
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8870
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I88bf5cc2da7c2f969ea184b5f12affaa94045a06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa8ec24b63d11798fec1993091b113a0c0938c7a
Original-Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217674
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some files for the veyron project were checked in with execute
permissions where it doesn't make sense. Fix.
BUG=chrome-os-partner:30167
TEST=None
Change-Id: I2a96816d4fd0af3949b0adaf5208fd2862835b5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7a408ff273d848b60aaad4f8b27103318e56111
Original-Change-Id: Ia3788abf3755baf028518efb975701cf6cb37e46
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217673
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8868
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321
Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209465
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8865
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I23af280764eb28d3f6b215ab32553fe42ee73272
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: abf5c14c8b32573107d2a1c73a752e740264db7e
Original-Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209462
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8863
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I74b30ecfe40c039855b835db0dfd0cd25adf960e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a30378a3152c930029a5b170cc6bf46180b5c7b8
Original-Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209468
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
In order to display a "update in progress" screen on devices with
a slow EC or PD chip it may be necessary to also load the VGA
Option ROM when doing EC software sync.
This adds config options for VBOOT_EC_SLOW_UPDATE which simply sets
a flag in the input parameters that is already handled by vboot.
It also adds a config option for VBOOT_OPROM_MATTERS which is a bit
more tricky in that it sets a flag in input parameters, but also
needs to keep track of the option rom being loaded and pass that
flag into VbInit as well.
Since VbInit will clear the NV bit for option rom loaded the check
that is done in vboot_wants_oprom() needs to first compare against
the vboot handoff copy of the input flags.
BUG=chrome-os-partner:32379
BRANCH=samus
TEST=manual testing:
1) in normal mode, with EC/PD in RW, ensure that they are rebooted
to RO and the VGA Option ROM is loaded and the wait screen is
displayed, and then the system is rebooted at the end and the
VGA Option ROM is not loaded.
2) same as #1 with EC/PD in RO already, same result
3) same as #1 with system in developer mode, same result except
there is no reboot at the end of software sync
4) same as #1 with system in developer mode and EC/PD in RO,
ensure that there is no extra reboot at the beginning or end of
software sync.
Original-Change-Id: Ic2b34bf9e7c6cc5498413fa1b8dff6e6207c9d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223831
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 7d7aa89238efb5081885f9386c8e872fc96f573f)
Change-Id: Ib7fb24e6e80e1f7e836bc62246ab9b3e056fd73d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
this change makes coreboot initialize kernel space and backup space in the tpm
when no firmware space is found in the tpm.
BUG=chrome-os-partner:32410
TEST=Forced factory initialization and verified it went through without errors.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I777e3cb7004870c769163827543c83665d3732b9
Original-Reviewed-on: https://chromium-review.googlesource.com/220412
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit d8c0c407bf0fed60d76441ada7bedd36f6fc3a38)
Change-Id: Icc3779125262b4499e47781991ebbf584abf074a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change makes prevent execution from falling through to unverified
code when hard_reset is not implemented. it also includes a few touch-ups.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Original-Change-Id: I9b02ab766172a62c98b434c29f310bc4a44f342d
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219625
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit d1f5207d83d2247b55f2bb9d02ac843305fc3ded)
Change-Id: I99dd5a2ca3a5369accb14408ea9d266bf60e7132
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.
With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.
BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Original-Reviewed-on: https://chromium-review.googlesource.com/212365
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Note: This purposefully is probably broken in vendorcode/google/chromeos
as I'm just trying to set a base for dropping more patches in. The vboot
paths will have to change from how they are currently constructed.
(cherry picked from commit 4fa17395113d86445660091413ecb005485f8014)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9
Reviewed-on: http://review.coreboot.org/8881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change reduces the code duplication of the bootblock and the romstages for
Nyans.
BUG=none
TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri)
Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a
Original-Reviewed-on: https://chromium-review.googlesource.com/214050
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef
Reviewed-on: http://review.coreboot.org/8880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This introduces a new kconfig variable to select the VBNV backing
store explicitly instead of inferring it from CPU/SoC architecture.
x86 platforms have historically relied only on CMOS to store VBNV
variables, while ARM-based platforms have traditionally relied on
the EC. Neither of those solutions are going to scale well into
the future if/when CMOS disappears and we make ARM-based systems
without an EC.
BUG=chrome-os-partner:29546
BRANCH=none
TEST=compiled for nyan_blaze and samus
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I4a8dadfb6bb666baf1ed4bec98b29c145dc4a1e7
Original-Reviewed-on: https://chromium-review.googlesource.com/213877
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit d088fc71b2e2b45e826d3dedb8e536ad58b8d296)
Change-Id: Iea325a8c4d07055143e993d89b827f86b8312330
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8777
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
rmodules ccopts contain information about specific arch like armv4,v7. Hence, it
is important to include them in VBOOT_CFLAGS
BUG=None
BRANCH=None
TEST=Compiles correctly for armv4 in rush
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id:
Original-Change-Id: I8f5509f753e28046678c3782d6f0b6210559f798
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209979
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit ca9f2f86ff1bc445abf5f97f61c04b6eccbd3e25)
Change-Id: I6cd7c47f33cf897d8ee96e7154222b3bfbe5221f
Reviewed-on: http://review.coreboot.org/8775
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to more cleanly apply upcoming changes some files
will need to do a dance.
Change-Id: Ib50670743c10221785447490190ecdbff8c764fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8654
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This code ports antirollback module and tpm library from platform/vboot_reference.
names are modified to conform to coreboot's style.
The rollback_index module is split in a bottom half and top half. The top half
contains generic code which hides the underlying storage implementation.
The bottom half implements the storage abstraction.
With this change, the bottom half is moved to coreboot, while the top half stays
in vboot_reference.
TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link.
BUG=none
Branch=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e
Original-Reviewed-on: https://chromium-review.googlesource.com/206065
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
(cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0)
Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8615
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
These boards are supposed to be able to determine the board ID at run
time based on GPIO settings.
BUG=chrome-os-partner:30489
TEST=verified that all boards build. Checked that storm proto0 reports
board ID of 0 on the console
Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210119
(cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733
Reviewed-on: http://review.coreboot.org/8722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
storm uses three GPIOs in tertiary mode, such that proto0 returns
value of 8 when the GPIOs are interpreted as a single tertiary number.
Adjust the calculated value to return board ID of 0 on proto0, and
monotonously incrementing values on newer boards.
BUG=chrome-os-partner:30489
TEST=when enabled, the board ID value of zero is reported on the console.
Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210118
(cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24
Reviewed-on: http://review.coreboot.org/8721
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For the majority of Chrome OS boards there is no need to include board
ID calculation in any stage but ramstage, where the ID should be
available for inclusion into the coreboot table.
BUG=chrome-os-partner:30489
TEST=build only, no other tests yet
Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b
Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210117
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Board ID value is usually of interest to bootloaders. Instead of
duplicating the board ID discovery code in different bootloaders let's
determine it in coreboot and publish it through coreboot table, when
configured.
BUG=chrome-os-partner:30489
TEST=none yet
Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb
Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210116
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8719
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add implementation of the GPIO API defined in src/include/gpiolib.h.
Also, clean up the GPIO driver, make it use pointers instead of
integers for register address.
This requires a touch in the SPI driver, where the CS GPIO is toggled
and in the board function where it enables USB interface.
BUG=chrome-os-partner:30489
TEST=tested with the following patches, observed proto0 properly read
the board ID.
Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210115
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2
Reviewed-on: http://review.coreboot.org/8718
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some platforms use tertiary interpretation of GPIO input state to
increase number of distinct values represented by a limited number of
GPIOs. The three states are
- external pull down (interpreted as 0)
- external pull up (1)
- not connected (2)
This has been required by Nvidia devices so far, but Exynos and
Ipq8086 platforms need this too.
This patch moves the function reading the tertiary state into the
library and exposes the necessary GPIO API functions in a new include
file. The functions are still supposed to be provided by platform
specific modules.
The function interpreting the GPIO states has been modified to allow
to interpret the state either as a true tertiary number or as a set
two bit fields.
Since linker garbage collection is not happening when building x86
targets, a new configuration option is being added to include the new
module only when needed.
BUG=chrome-os-partner:30489
TEST=verified that nyan_big still reports proper revision ID.
Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d
Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209673
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8717
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bootblock stack on Danube should be SRAM and defined separately from
the rest of the coreboot stack. The actual coreboot stack will be
defined later.
The top of the stack should be above the bottom, as the stack grows
towards lower addresses.
BUG=chrome-os-partner:31438
TEST=ran bootblock on simulator under codescape, observed stack
properly initialized.
Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437
Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218732
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add basic board support for the ImgTec Danube Virtual Platform, which
emulates a system built around the Danube SoC.
Run this by loading coreboot.bimg into a flash device connected to SPFI1
chip select 0 & then executing the Danube boot ROM.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: Ia62af62804bab261f3cabf7c2e62f5bb08a4a1a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6cb1017f5e2fec85f7f5c60cd2cfec63cc886b49
Original-Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207976
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8766
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Actual timer support is not yet available for Danube, it will be added
soon. For now, just to make the target build, modify it to use
GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option.
BUG=none
TEST=the target builds again
Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750
Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220395
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Romstage initialization code does not need to be board specific, keep
it in the SOC directory. Should there be a need for the board specific
code, it can be added later.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3
Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215992
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Iniitialize I2C bus required for TPM operation. Problem observed was that if
frequency is raised above 20KHz, TPM starts responding with NAKs either for
address or for data. Need to look into that.
BUG=None
BRANCH=None
TEST=Compiles successfully and TPM success messages seen while booting.
Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210001
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2
Reviewed-on: http://review.coreboot.org/8715
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable L1 Sub-State when both root port and endpoint support it.
[pg: keyed the feature to MMCONF_SUPPORT, otherwise boards
without that capability fail to build.]
Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092
Original-BUG=chrome-os-partner:31424
Original-TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boards and
need someone having EVT boards to confirm the settings.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Original-Reviewed-on: https://chromium-review.googlesource.com/221436
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There was an empty udelay() implementation result in 0 waits.
Provide an actual implementation.
BUG=None
BRANCH=None
TEST=Built and ran through to depthcharge on rush.
Change-Id: Ia7060566a71c36bb7e4543c2fe4ee49d168518c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8832e73de238358ea801ccd7c2330de35a7b40e
Original-Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210827
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=Built, but similar usage tested on tegra132.
Change-Id: I1147f2bed84b93d1b776205df9ae04d1db9c98a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c38e054dd166d5eb53f692833b5ce88a230816e3
Original-Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219712
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8819
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of open coding the monotonic timers use the stopwatch
abstraction.
BUG=None
BRANCH=None
TEST=Booted and noted timings work as expected. Built with software_i2c
and no compilation failures.
Change-Id: Ie5ecdd5bc764c1ab8ba4a923e65a1666aacd22f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7bffb5aeb41e9b88cd2c99edd6abc38f1dc90af
Original-Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219495
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8817
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Simplify the SPI timeout by using the stopwatch.
BUG=None
BRANCH=None
TEST=Built nyan. Confirmed stopwatch works independently.
Change-Id: Ida26a0748d4b5a6a28aa8f6e2b92fe2ee4cbe17f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 900d7ac826b76d49290033c87849bf776684f2c1
Original-Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219493
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There's a lot of places where expiration and running time are
open coded. Allow for those places to be simplified by adding
a stopwatch construct. The stopwatch can have an expiration or
just be used to accumulate time.
BUG=None
TEST=Built and verified API works as expected by using implementation.
Change-Id: Ibd636542b16d8554f1ff4512319a53dce81c97e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc623a1b36eb08c5877591c4509cd61131c62617
Original-Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/219492
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8815
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These modules are necessary to resolve external names when building
the board image. These are just skeletons for now which will be filled
later.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I0fcb5d33187172ecac77041425402b33e89e8944
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94ec79b0ab872f5c5fe7db5bef5fdabf77d6b3b6
Original-Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215678
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add build infrastructure and basic support code for the ImgTec Danube
SoC. This support is sufficient to run on a simulator.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401
Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8762
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the proper configuration flags enabled, do_printk is available
from src/console, no need to define it elsewhere.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: I82071b4ca1686639c0bd39c63a06b61cb5bf5571
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69c655537c50274a61cf123b7fc387ec60dd29c7
Original-Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215862
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the build infrastructure and basic architectural support required
to build for targets using the MIPS architecture. This is sufficient
to run on a simulator, but will require the addition of some cache
maintenance and timer setup in order to run on real hardware.
BUG=chrome-os-partner:31438, chromium:409082
TEST=none yet
Change-Id: I027902d8408e419b626d0aab7768bc564bd49047
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21
Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207972
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8760
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As MIPS toolchain does not provide adequate support for 64 bit
division and shift operations, the missing functions are required to
be provided by the user.
This patch brings in the Linux implementation of the 64 bit arithmetic
shift borrowed from arch/mips/lib/ashldi3.c (eg. Linux v3.14).
BUG=chromium:406038
TEST=With the upcoming patches coreboot successfully builds for MIPS
targets in chroot (coming later).
Change-Id: I2168f69352a9b9e3c5d197489f701a442e65703c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ec616161be8ad3aeb6494e7121615e3329b414d
Original-Change-Id: Ia1ccb29d4c9f3c95e04e06f6af7ce8a00e2e7455
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8759
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Certain boards need to speak proto v3 over i2c. Leverage the
transport agnostic API to share the logic with other proto v3
impelementations.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built and ran on ryu. Can talk to the EC successfully.
Change-Id: I1d0cd6907057af4ded3c4460193bbe1d897a1db7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb9ac965ad04c9491f40fd9aa595176a28a467b3
Original-Change-Id: Ib699120fd232392e8caa0889c2bf40f4587a8a35
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211139
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Depending on the transport mechanism for proto v3 different bytes
need to be send and/or read before the request and response. Depending
on the software and/or controller interface that requirement leads to
needing to copy data into temporary buffers. Avoid this by allowing
the transport mechanism to provide the request and response
buffers.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built for rush and ryu. Ran on ryu with i2c implementation.
Also built for rambi to check x86 systems.
Change-Id: I35d4d69bd1fa900fc0cfe3822496f381405bdcb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7224426e1d0bcf06ed010131a2462a6ca201d8b
Original-Change-Id: Iad6cce566a253ca72e6f5009a97235ece0a6c1b5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211138
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8827
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC doesn't return any data when one performs a write to
VBNV context. Therefore there is a mismatch of expectations.
Correct this by properly setting the expected response length.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=No longer hanging while writing to VBNV on ryu.
Change-Id: I7077a507c3280358dac1f88ece62cacee9b71bea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c1735c3377163aeb9e90155cb9f081a1eea919c9
Original-Change-Id: I455724f20f5442bd62a792f09273227417475f07
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/211137
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8826
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It's helpful to view program size by inspecting the symbols.
_start and _end exist on romstage and ramstage. In order to
be consistent add _end for bootblock too.
BUG=None
BRANCH=None
TEST=Built and noted bootblock has _end symbol.
Change-Id: I06634b317e957e8271bf32530a56b5541c79b9ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4ac926b30749d22e90a6f12ebac52107e241526
Original-Change-Id: I7f0b4dd4078c7d23c70949563b4c3f4df9e66142
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210832
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In some cases, we need to use 1 common VGA device ID to share
among different VGA devices.
But it will show error when it can't find a specific pci rom
by PCI DID.
in fact, it will find the pci rom with common vga ID.
Without this commit, you may need to skip error check during
suspend_stress_test
BUG=none
BRANCH=none
TEST=build OK, and check no error on Auron and Samus
Change-Id: I2b18347e46c831038f048cfd0b065430c72c6f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c32ee21b4c942182e5ffb21b58b93fa7c082223
Original-Change-Id: Ib743e960f772b7e2e73a1feb80790a13bd8c06c7
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217415
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/8821
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It causes fan top speed due to this bug + our board-specific workaround,
and causes invalid temperature sensor readings.
Therefore, re-configure the register "External Temperature Sensor Host
Control Register" to terminate processes when this issue happens.
BUG=chromium:402204
TEST=ran suspend_stress_test 500 times
Change-Id: I439d5de798fbe999e4eec5497e6969b7b453121b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b82f2922c7fce3ca6b2797a8d9775e9db2817fe9
Original-Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219445
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/8820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When adding gargabe collection to x86 the --gc-sections
flags was inadvertently missed when linking romstage_null.debug.
Fix this omission.
Change-Id: I7d2700755afa78459c6f8707303a0e64936a1a9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8850
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Instead of sprinkling the cbfs calls around (as well as getting
return values incorrect) use the common run_romstage() to perform
the necessary work to load and run romstage.
Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of sprinkling the cbfs calls around (as well as getting
return values incorrect) use the common run_ramstage() to perform
the necessary work to load and run ramstage.
Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8710
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a common run_romstage() function to be used by
bootblocks to load and run romstage. This is similar to
run_ramstage() in that it provides a single entry point
for doing the necessary work of loading and running romstage.
Change-Id: Ia9643cc091f97a836cf5caefdff8df4a3443df4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8709
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Miraculously a console is being compiled in for romstage.
However, as no calls were potentially printing to the preram
console this was being ignored. Instead provide the symbol
required so as not to fail the build.
Change-Id: Id8f0b6e6d15b41fa7fe1b63bf2d91f15baa0edda
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of two headers for payload and ramstage loading
combine the 2 files into one. This also allows for easier
refactoring by keeping header files consistent.
Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8708
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Vboot2 targets so far did not have COMMON_CBFS_SPI_WRAPPER
configuration option enabled, so the verstage is missing the relevant
files in some Makefiles. This patch fixes the problem.
BRANCH=none
BUG=none
TEST=with the rest of the patches applied cosmos target builds fine
with COMMON_CBFS_SPI_WRAPPER enabled
Change-Id: I3ce78c8afc5f7d8ce822bbf8dd789c0c2ba4b99c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b72693c96f7d8ce94ce6fe12b316d5b88fded579
Original-Change-Id: Iab813b9f5b0156c45b007fe175500ef0de50e65c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223751
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8772
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
GD25LQ64C and GD25LB64C have the same ID and settings.
BUG=chrome-os-partner:25907
BRANCH=baytrail
TEST=Boot with GD25LQ64 and check MRC data save/restore works.
Change-Id: I8a4aa7cabd9a7657c2f0bae255a87341db3f1061
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20b5896adbbbdedcb1b7de435466dcc6bfa703cb
Original-Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193238
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8770
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This allows us to use the driver before ramstage.
BRANCH=none
BUG=none
TEST=built and booted on Pinky
Change-Id: I0700388b0e4e0562e3c0a52863c8357097bfd8d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cd57587dab74de509d5c50cfc1ad337d765af6c8
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I0ce901331e401274254b8889484ffb41359119fa
Original-Reviewed-on: https://chromium-review.googlesource.com/235864
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8774
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When the driver is included in bootblock, malloc() is not available.
Come to think of it, it is perfectly fine to use a statically
allocated structure for the SPI device descriptor - coreboot is
unlikely to require concurrent support of multiple SPI devices of the
same kind.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=bootblock on the FPGA board recognizes the installed Winbond
device:
coreboot-4.0 bootblock Tue Nov 11 07:27:24 PST 2014 starting...
SF: Detected W25Q16 with page size 1000, total 200000
Change-Id: Iea1936a219d38848580a10f75eb8bbcab17e6507
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0b4082442aa526d387a80cb5872d78670e6b468b
Original-Change-Id: Iaa69d610ef18e69b1ae5ade2d958f9fe1595a723
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228959
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8771
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
S25FL116K family uses the first 3 bytes in response to a legacy identification
command (9f) while previously supported models use the last 4 bytes. This change
defines identify functions to allow both types to be handled correctly.
BUG=none
BRANCH=tot
TEST=verified romstage is loaded on cosmos development board.
Change-Id: I1970a9af17e81299fada5029724d405de4022156
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 65ff436db2355cb68a766a3dedbcd7e2f765e6db
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Icdd2645e356652672c4482e7b805da1bc0f21e71
Original-Reviewed-on: https://chromium-review.googlesource.com/234431
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a macro to check if a value is aligned.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio.
Change-Id: I0680954eb1b1964a631527f96aa0570a32944fa1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f1717648e0a4b54217d71f8d0a15d496737d156
Original-Change-Id: Ie0bc1374918a7ffaaec5fea62c1193a42edd416c
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246692
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8757
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
mainboards/amd/fam10: Initialize cbmem area after raminit
When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
When GFXUMA is disabled, CBMEM is placed at TOM
This matches the behaviour present before conversion to early
CBMEM.
The CBMEM location code implicitly assumes TOM does not change
between romstage and ramstage. TOM is set by romstage raminit,
and is never changed by romstage or ramstage afterward. As
the CBMEM location is positioned at a specific offset from TOM
that is known to both romstage and ramstage early CBMEM is safe
on Fam10h systems.
TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
tables from romstage and cbmem log tables from ramstage.
Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8489
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.
Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA
is enabled, however when GFXUMA is disabled an attempt was made to locate
the CBMEM memory segment above the I/O hole in certain rare cases.
Removing this special case does not impact functionality, and paves
the way for early CBMEM support.
Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.
Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.
In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.
Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses.
This fixes a KCONFIG unmet dependency warning on ARM mainboards with
chromeec.
Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8665
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add license header with copyright of the original authors.
Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8691
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.
Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The current spi_xfer() function sets the count in hardware and then
loops while waiting for the requested number of bytes to be sent or
received. However, the number of bytes to be transferred may exceed
the maximum count that can be programmed into the controller.
This patch re-factors spi_xfer() to split the low-level FIFO handling
portions for transmit/receive into their own functions to be called
by loops in spi_xfer() which will break large transfers into smaller
ones.
BUG=chrome-os-partner:30904
BRANCH=storm
TEST=built and booted with a >64KB payload on Storm
Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209838
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108
Reviewed-on: http://review.coreboot.org/8676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible
from AVP, the first place that can change CPU clock is after CPU
has been brought up, ie, ramstage in this case.
CPU initial clock source is set to PLLP by MTS.
BUG=None
TEST=Norrin64 and A44
Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209698
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89
Reviewed-on: http://review.coreboot.org/8677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently, the rmodules inclusion for vboot is dependent on ramstage_arch.
This change adds dependency on romstage_arch, since vboot is associated with
romstage. Inclusion based on ramstage_arch is left as is in case someone needs
it in ramstage.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for link, rush and nyan
Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209568
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc
Reviewed-on: http://review.coreboot.org/8673
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide functionality to create dynamic classes based on program name and the
architecture for which the program needs to be compiled/linked. define_class
takes program_name and arch as its arguments and adds the program_name to
classes-y to create dynamic class and compiler toolset is created for the
specified arch. All the files for this program can then be added to
program_name-y += .. Ensure that define_class is called before any files are
added to the class. Check subdirs-y for order of directory inclusion.
One such example of dynamic class is rmodules. Multiple rmodules can be used
which need to be compiled for different architectures. With dynamic classes,
this is possible.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for nyan, rush and link.
Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209379
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295)
Some of this cherry-pick had already been committed here:
commit 133096b6dc
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c
Reviewed-on: http://review.coreboot.org/8672
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In some previous attempt to enable monotonic timers on all platforms,
the LAPIC monotonic timer was selected for Haswell devices, despite
the fact that LAPIC timers are not used in coreboot on Haswell
(See haswell Kconfig) and there already was a monotonic timer
implementation enabled that just needed to be added for SMM as well.
Change-Id: I6beb2977864e507956636860ed463e1991cea1ed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8702
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
When the Intel SPI drivers were refactored, compilation for Chrome OS
devices broke, because ELOG uses the SPI driver in SMM.
Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8701
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
On ChromeOS devices the ELOG section size and offset are
provided by the FMAP, rather than KConfig. Some upstream
refactoring broke compilation in that case.
Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Under certain conditions, e.g. automated testing, it is useful
to have the payload (e.g. Linux) reset the reboot_bits CMOS
value. This allows automated recovery in the case of coreboot
starting properly but the payload failing to start due to bad
configuration data provided by the coreboot image under test.
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd
Reviewed-on: http://review.coreboot.org/8698
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
From GCC's documentation:
Optimize debugging experience. -Og enables optimizations that do not interfere
with debugging. It should be the optimization level of choice for the standard
edit-compile-debug cycle, offering a reasonable level of optimization while
maintaining fast compilation and a good debugging experience.
Change-Id: I9a3dadbf8e894cb28e29d7b2f4e9add252e7bbb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This removes the mainboard agesawrapper.c file from binarypi
based boards and creates a common one.
Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This makes the change to the cpu/amd/pi/00730F01 that was
made for the cpu/amd/agesa based boards in:
commit 48518f0d
AGESA: Add amd_initcpuio() and amd_initmmio()
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().
The equivalent change has already been made for cpu/amd/pi/00630F01.
Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8670
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested on an X60, Native graphics init still works perfectly.
Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8696
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Most things still needs to be filled in, but this will allow us to build boards which use this SOC.
BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot
Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I thought this wasn't going to work, and observing the timC detection
failure of early tests, I was getting somewhat discouraged; however,
this works. I've tried it with all possible permutations of the
following memory modules:
* 2 GiB single-rank DDR3-1600
* 4 GiB single-rank DDR3-1600
* 4 GiB dual-rank DDR3-1600
I did notice a limited number of memtest errors during one of the
runs, but they were in an address range that is otherwise marked as
reserved. I wrote that off as "maybe something was doing MMIO there
just when memtest was poking the address range". I was not able to
reproduce that error.
Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This brings the KFSN4-DRE in line with other boards in the tree.
Change-Id: I9216130f51ed0576871fd27ca6ae4610c5f5810e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This was missed in commit bde6d309 as the driver is not enabled
in any configuration by default.
Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8660
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There is no point in duplicating boardid.h per board - they are all
the same. Let's keep a single instance in the common include directory
and let the linker report a problem if one tries using this function
on a board where it is not supported.
BUG=chrome-os-partner:30489
TEST=verified that coreboot builds fine for nyan_big and nyan_blaze.
Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209699
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962
Reviewed-on: http://review.coreboot.org/8666
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is useful when the PCB layout of a mainboard does not allow
stable operation at the increased HyperTransport speeds of newer
processors.
Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8464
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This patch removes a chunk of romstage code from Tegra and all Nyan
boards that was supposed to enable some LCD power rails early, but never
really worked. The dev_find_slot() function can only find PCI devices,
which the CPU cluster is not. Since we're done with Nyan-RO and the
ramstage display code is fine as it is, there is no point in trying to
fix this... but we should remove it from ToT lest someone uses it as a
blueprint to add more dead code to future boards.
BRANCH=None
BUG=None
TEST=None
Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207720
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8deedea5e9787848aae3064509c611bc349313cc
Reviewed-on: http://review.coreboot.org/8638
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This capability means:
FERR messages are sent out on system detected an
unmasked floating point x87 FPU error.
Even though this capability is supported on nehalem it doesn't
make sense to set it in early stage. This MSR
has a core scope which results in an unsync MSR because
it's not set on other cores than the BSP.
Found-by: BITS
Tested-on: lenovo thinkpad x201t
Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BIOS Writer's Guide, rev 1.6.0, June 2012:
This MSR controls whether and FERR message is sent over the system bus
when unmasked x87 exceptions are generated.
This feature is not supported from Sandy Bridge processor onwards.
Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8658
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Stop running AVP at the end of romstage until event conditions are met (JTAG,
GIC_IRQ or LIC_IRQ).
BUG=chrome-os-partner:30831
BRANCH=None
TEST=Compiles successfully and boots till last known good checkpoint.
Original-Change-Id: Ia221f08b27ac0c60a66d588e351677144cc6a322
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209424
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit df4e8b4c8a1002443a936bd0563fbc9e0710f489)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I59f7702bd50a1039b8723e9cb12b8d714e353d37
Reviewed-on: http://review.coreboot.org/8651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The SPI controller operates on packets which can be variable
length up to 32-bit packets. It also has the ability to be
put in packed or unpacked mode w.r.t each packet. i.e. does
a single fifo register hold >= 1 packet. The current programming
uses 8-bit packets in unpacked mode which means 4 fifo slots
are used for a 32-bit DMA transfter. As the AHB can only operate
on a minimum of 32-bit bursts the triggers need to be programmed
correctly so that there is room for a full 32-bit DMA transaction.
Previously faster SPI clocks just made things magically work.
BUG=chrome-os-partner:30779
BRANCH=None
TEST=Built and booted through coreboot with 20MHz SPI clock.
Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208862
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196
Reviewed-on: http://review.coreboot.org/8649
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Trust Zone carveout registers are only accessible using
a secure access mode. The AVP runs as non-secure all the time.
In EL3 the CPU is in secure mode, but when the MMU is enabled
the page tables dictate if accesses to certain regions are
secure or not. However, ramstage is currently being loaded
into non-secure memory and the page tables will live in
non-secure memory as well. Therefore, handle all these
cases by providing global state which mirrors the TZ
register.
BUG=chrome-os-partner:30782
BRANCH=None
TEST=Built and ran through ramstage with the MMU enabled
Resources are read and set accordingly.
Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209061
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b
Reviewed-on: http://review.coreboot.org/8648
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for mmu initialization and enabling caches. mmu_operations provides
functions to add mmap_regions using memrange library and then calls mmu_init for
armv8.
BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until depthcharge load. Goes past
all the earlier alignment errors.
Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208762
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b
Reviewed-on: http://review.coreboot.org/8647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for initializing and enabling mmu for armv8. Using 64KiB granule and
33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes
use of memrange library to get a list of all the mmap regions from the SoC to
initialize XLAT table.
Currently, all calculations in mmu.h are based on the assumptions that max 33
bits are used in VA and granule size is 64KiB. Changes in these assumptions will
have to reflect in the dependent calculations as well.
BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until "payload not found". Goes past
all the earlier alignment errors.
Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208761
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285
Reviewed-on: http://review.coreboot.org/8646
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Other default slams should be added later to the init table
once we know what the kernel touches. But for now, only VDD_CPU
is needed.
Also slipped in a minor name change in mainboard.c
BRANCH=none
BUG=none
TEST=none, no HW here for me to test on yet
Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/208385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With this memory resource, the payload loading code should be
able to create a bounce buffer and load the payload successfully.
Adapted from tegra124 soc.c
BUG=None
BRANCH=None
TEST=Built and booted to ramstage on rush.
Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208121
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f
Reviewed-on: http://review.coreboot.org/8644
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Once LPDDR3 init is supported in the ryu romstage, this can
be reverted. Note that this 528MHz BCT has been pre-qualed
by NVIDIA AE's, but will be updated as more tuning is done.
BUG=none
BRANCH=none
TEST=Builds, BCT is in binary, but I have no HW here to test on
Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208384
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe
Reviewed-on: http://review.coreboot.org/8643
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The CCSIDR_EL1 register has cache attribute information
for a given cache selection in CSSELR_EL1. However, the
cache isn't being selected before reading CCSIDR_EL1.
Instead use CTR_EL0 which better fits with the semantics
of dcache_line_bytes(). CTR_EL0 has the minimum data cache
line size of all caches in the system encoded in 19:16 encoded
as lg(line size in words).
BUG=None
TEST=Built.
Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208720
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0
Reviewed-on: http://review.coreboot.org/8642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The address map code was originally assuming all carveouts would
be packed together in the upper end of the physical memory
address space. However, the trust zone carveout is always in the
32-bit address space. Therefore, one needs to query memory ranges
by above and below 4GiB with the assumption of carveouts being
packed at the top of *each* resulting range.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran through coreboot on rush.
Original-Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208101
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 8d5795fbff36e91906384e10774a32541d358324)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If15ff48d5a4c81731eb364980b30c8086deb1cca
Reviewed-on: http://review.coreboot.org/8641
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The default CBFS size configuration setting is incorrect in case of
Qualcomm SOC targets, as the coreboot blob is much smaller than the
actual bootprom. Note that this size also must match the board fmap
defined in the appropriate depthcharge board directory.
BUG=chromium:394068
TEST=manual
. previously failing to boot coreboot image does not fail to load
depthcharge anymore.
Original-Change-Id: I1b178970b1deee05705490542e4a0c57500379dd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208146
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 01f3561fdee7b5547534e20d423fbbb1b490532c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If573bbc6254cf6786e75970eae3ad2b327a7ecfe
Reviewed-on: http://review.coreboot.org/8640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Provide a default Trust Zone region size of 1MiB, and
correctly account for it in the AVP and the arm64 cores.
The different path between the arm64 cores and the AVP
is because the AVP cannot access the Trust Zone region
registers. Therefore the AVP needs to account for the
Trust Zone region.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran. Noted Trust Zone region being accounted for.
Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208062
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44
Reviewed-on: http://review.coreboot.org/8639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio.
Verified with schematics.
Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8358
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Currently on AMD boards no romstage messages can be saved in CBMEM, so
only messages from ramstage on will be stored in CBMEM. Other than
that nothing changes.
Enabling CBMEM console by default does not noticeably decrease boot
time as the messages are directly written to CAR or RAM.
The board status script under `util/board_status/` reads the coreboot
messages from CBMEM, which are then uploaded to the board status
repository. With CBMEM console disabled by default, currently no
coreboot console messages are uploaded to the board status repository,
although it is important to have those.
Enabling CBMEM console by default improves this situation, so that for
all boards at least ramstage messages are stored in the board status
repository.
Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5350
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.
Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This was added to handle cases of Intel FSP platforms that had
EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM.
These boards were recently fixed.
To support combination of EARLY_CBMEM_INIT without CAR migration was
added maintenance effort with little benefits. You had no CBMEM
console for romstage and the few timestamps you could store were
circulated via PCI scratchpads or CMOS nvram.
Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8636
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
If it's not supported on a particular board, either the build will fail or
checks within the cbmem console itself should detect the problem. There
shouldn't be random memory corruption any more.
BUG=None
TEST=Built with CONSOLE_CBMEM enabled on nyan and saw that it was actually
enabled.
BRANCH=None
Original-Change-Id: Id6c8c7675daafe07aa4878cfcf13faefe576e520
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193167
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 20b486443bfc2d93d72bbc9e496023a00ab9ab30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I39fbcdff61f6d8f520f2e9d7612dee78e97898b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7748
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commit 2e0cf14 corrected this for pi/00730F01/northbridge.c.
This commit fixes it for pi/00630F01/northbridge.c.
Found-by: Clang
Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8289
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Also fix a typo in a config option for SteppeEagle.
Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7247
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The CAR macros and the associated functions are only employed
under the following conditions:
- chipsets which have CAR
- compilation during romstage
Therefore clean up the build-time conditionals to use those 2
constructs.
Change-Id: I2b923feeb68f2b964c5ac57e11391313d9c8ffc5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8634
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Starting with version 2.1 qemu provides a full set of smbios tables
for the virtual hardware emulated, except type 0 (bios information).
This patch adds support for loading those tables to coreboot.
The code is used by both i440fx and q35.
Change-Id: Id034f0c214e8890194145a92f06354201dee7963
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/8608
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
x86 systems run their romstage as execute-in-place from flash, which
prevents them from having writable data segments. In several code pieces
that get linked into both romstage and ramstage, this has been worked
around by using a local variable and having the 'static' storage class
guarded by #ifndef __PRE_RAM__.
However, x86 is the only architecture using execute-in-place (for now),
so it does not make sense to impose the restriction globally. Rather
than fixing the #ifdef at every occurrence, this should really be
wrapped in a way that makes it easier to modify in a single place. The
chromeos/cros_vpd.c file already had a nice approach for a wrapper
macro, but unfortunately restricted it to one file... this patch moves
it to stddef.h and employs it consistently throughout coreboot.
BRANCH=nyan
BUG=None
TEST=Measured boot time on Nyan_Big before and after, confirmed that it
gained 6ms from caching the FMAP in vboot_loader.c.
Original-Change-Id: Ia53b94ab9c6a303b979db7ff20b79e14bc51f9f8
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203033
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit c8127e4ac9811517f6147cf019ba6a948cdaa4a5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I44dacc10214351992b775aca52d6b776a74ee922
Reviewed-on: http://review.coreboot.org/8055
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Make compilation fail if this is included in non-romcc compiles.
I am a bit surprised that this ever compiled.
Change-Id: I8dfc1229681819d2381821a0195a89b44dd76b6a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8420
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All boards in tree use 0. Looks like this is all work that was
never completed and tested.
We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.
Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.
Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
They don't contain any useful information and
also block us from having reproducible builds.
Change-Id: Ib03887f6a548230de9f75fb308c73a800e180c48
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8616
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Also drop some more #if UNUSED_CODE.
Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8551
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There is no requirement that in dev->link_list the last element
would have the highest link->link_num.
Also fix off-by-one error when allocating for more links.
Change-Id: Id8a7db3ffb4111eb31e70ea14fd522b70368dd8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8550
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Since commit ee894357 (cpu/intel (non-FSP): Use microcode from
blobs repository), selecting the option to generate the
microcode from tree fails without allowing to use the BLOBs/
3rdparty repository, which is the default setting.
Therefore, only show the option, if the user has selected the
option to allow the use of the BLOBs repository.
Change-Id: Ide20da0f946aae43dc2c8cdce54941c704d3d288
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31424
BRANCH=none
TEST=build only, due to I don't have broadwell system with wifi to test
need somebody help me to verify
Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8448
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Set PCIe "Enable Clock Power Management", if endpoint supports it.
BUG=chrome-os-partner:31424
BRANCH=none
TEST=build and boot on rambi, check Enable Clock Power Management
in link control register is set properly
Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220742
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
[Edit commit message.]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8447
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
At some point the license text for a file was incorrectly
changed. That license was then copied and pasted. I'm sure it
was myself. Anyhow, fix the bustedness.
Change-Id: I276083d40ea03782e11da7b7518eb708a08ff7cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8620
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
src/include/device/ is the place for include files of the resource
allocator. Hence, drop the i915 include file copies and use the ones
supplied with the i915 driver instead. The only remaining user of this
was the Intel Whitetip Mountain 2 reference board, all other occurences
have been previously fixed already.
Change-Id: Ib9f72df4e8f847597508971e9dbf671f49019767
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8140
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The BKDG for K10 revision D and later processors recommends a smaller
MCT burst write queue depth when using unganged memory.
TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431
processors.
Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This change brings all agesawrappers in a single file to make it
easier to understand the actual execution flow.
Change-Id: Ifbb2b16e4cccfaa17aaf10887a856797be9b6877
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8605
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We do not allow platforms to mess around with memory layout.
Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to make sharing of the location of MTS microcode easier
provide a Kconfig option that is the path to the files.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built rush coreboot.
Original-Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207839
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6f1de0e7fd312c1d6798e65d4b43d586f0994337)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I660cb9d8bd13c765c89b54b0807b5b3ee836e807
Reviewed-on: http://review.coreboot.org/8614
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The preboot MTS microcode needs to be supplied within the
bct so the BootROM can load it. The size of the bootblock
space in SPI needed to be extended to accomodate the extra
length.
BUG=chrome-os-partner:29059
BUG=chrome-os-partner:29060
BRANCH=None
TEST=Built rush with updated cbootimage with t132 support.
Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204940
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11
Reviewed-on: http://review.coreboot.org/8466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The former pstates_algorithm() function has two early exit
points now, and so it might never get around to writing
pstates data.
Change-Id: I19ca937375c6d33b78bd5b1859fa5c25473be9b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8610
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
If a certain register returns crap values, we
determine core_power using an uninitialized variable.
That doesn't sound healthy.
Change-Id: I1e890b78bfcc3bf0255a3d4f6561a783134b1719
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8508
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
With BOARD_VARIANT_AP148 configuration option enabled the image will
be built for 512MB DRAM instead of 1024MB and the
mainboard_part_number field in the lb_mainboard entry will be set to
"AP148" instead of "Storm".
BUG=chrome-os-partner:30440
TEST=manual
. built and booted both AP148 and proto0 all the way to reading the
kernel
. verified that the config file includes correct part number and
memory size
. verified proper machine IDs reportted when starting the kernel
Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207427
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a
Reviewed-on: http://review.coreboot.org/8590
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Some of the SoC's need an early hook to configure
certain registers. One example of this is on t132
where ramstage is the first thing being ran on the
arm64 core and it is the only entity that can configure
certain registers required for the rest of ramstage.
Therefore, provide the opportunity for the SoC to
implement such requirements.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran through coreboot.
Original-Change-Id: Ib352f3788872f888581b398c9b394b7c4e54b02a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208061
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2c50e2b39e75d1383e8e573c576630a5b7313349)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I38df63e46c5c21b2d319fc9eb42053c3a0d61bc8
Reviewed-on: http://review.coreboot.org/8595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is a clone of rush for the time being. All the incompatible
bits can be moved later. Additional patches to follow.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built coreboot for rush_ryu board
Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207838
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab
Reviewed-on: http://review.coreboot.org/8594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The TrustZone carve-out needs to be taken into account when
determining the memory layout. However, things are complicated
by the fact that TZ carve-out registers are not accessible by
the AVP.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and booted to end of ramstage. Noted that denver cores
can read TZ registers while AVP doesn't bother.
Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207835
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494
Reviewed-on: http://review.coreboot.org/8593
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.
BUG=None
BRANCH=None
TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.
Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207815
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9
Reviewed-on: http://review.coreboot.org/8592
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
The carve-out regions need to be taken into account when
calculating addressable memory because those regions aren't
accessible from the main cpu. The additional exposed functions
are to accommodate adding resources during ramstage resource
reading. The TZ (trust zone) region is empty for now until
more documentation is provided on determining its location.
BUG=None
TEST=Built and booted through attempting payload loading.
MTS carve-out is taken into account programmatically.
Original-Change-Id: I3301b2a12680ad79047198ada41f32eb1b7fa68b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207585
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 15b9c74dd1ef5bfb1fd7c6dab50624f815658e14)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I46d54dbbb8e102fc70ab34bc4bbd2361ef1ea504
Reviewed-on: http://review.coreboot.org/8591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enabled CBMEM support for t132 platforms. Some of the existing
code is moved around to avoid dependencies in the other stages
that need it.
BUG=None
BRANCH=None
TEST=Built and booted a rush with cbmem support.
Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207163
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b
Reviewed-on: http://review.coreboot.org/8589
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The startup sequence for cpu0 is implemented while also
providing a trampoline for transitioning to 64-bit mode because
the denver cores on t132 come out of cold reset in 32-bit mode.
Mainboard callbacks are provided for providing the board-specific
bits of the bringup sequence.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through ramstage.
Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207263
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97
Reviewed-on: http://review.coreboot.org/8586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This mainboard is based on Intel's Bayleybay
board which uses Bay Trail CPU with Intel FSP.
It has one USB3.0 interface, 4 USB2.0 interfaces,
up to two Ethernet ports and a LVDS connection
for LCD panels. The board is equipped with 512 MB
of DDR3 in a memory down configuration.
This board boots into Ubuntu/Lubuntu 14.10 using SeaBIOS,
but other OSes should work as well (but are not tested).
It has a version.hex file which is needed for
our OS and has no hardware functionality.
Change-Id: I94401bbd1d61ec69703de38ae1bc97969c5d979e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8430
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a driver wich can handle the internal I2C controllers
of Baytrail SoC. This driver is not suitable for the
SMBus controller.
Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8401
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a new microcode for Bay Trail M D0 stepping used
in cpu N2807 silicon.
In addition, a selection of the used CPU type has
been added (I or M/D) which allows to use only the
really needed microcode for a given CPU type.
Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To align with arm use the RAMSTAGE_BASE Kconfig option
for start of ramstage. Also, use 16-byte alignment for the
start and end of the sections. 4 bytes were previously used, but
it definitely seems more appropriate to at least have the heap
handing out 16-byte aligned pointers.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through attempting to load payload
Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207432
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550
Reviewed-on: http://review.coreboot.org/8588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Inconsistent progress was observed running ramstage.
It was determined that the hand-coded assembly functions
were causing issues. Some of the comments seems suspect about
the hardware taking care of alignment. The prudent thing to do
is to use the C ones. Optimization can come later after maturity.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted to attempting to payload
Original-Change-Id: I4137adf9b36b638ed207e4efd57adaac64c6a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207431
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2762e478c6b59dd30c59aa87a922d0f78c00c0c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id3196b0c2bf41a21db31f999ba437d118875a236
Reviewed-on: http://review.coreboot.org/8587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Ramstage needs an assembly entry point for setting up
the initial state of the CPU. Therefore, a function is
provided, arm64_el3_startup(), that bootstraps the state
of the processor, initializes the stack pointer, and
branches to a defined entry symbol. To make this work
without adding too much preprocessor macro conditions
provide _stack and _estack for all the stages.
Currently the entry point after initialization is 'main',
however it can be changed/extended to do more work such
as seeding the stack contents with tombstones, etc.
It should be noted that romstage and bootblock weren't
tested. Only ramstage is known to work.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Brought up 64-bit ramstage on rush.
Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207262
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949
Reviewed-on: http://review.coreboot.org/8585
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The driver structures live in special sections which have no
direct reference to the symbols. Therefore, when garbage
collecting sections in the linker the drivers are tossed out
resulting in no drivers being linked into ramstage. Fix this
by adding the KEEP() directive to those special sections.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and noted console starts working in ramstage.
Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207261
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4
Reviewed-on: http://review.coreboot.org/8584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
1) In order to avoid stack from overflowing during ramstage decompression,
initialize stack right at the beginning of romstage.
2) Declare different Kconfig options for stack at each stage.
3) Provide a macro that does stack seeding if required and calls appropriate
function.
BUG=None
BRANCH=None
TEST=Compiles and runs successfully on rush.
Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206880
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd
Reviewed-on: http://review.coreboot.org/8583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Still waiting on VDD_CPU value, etc. from board guys, but this is a start.
BUG=None
BRANCH=None
TEST=Built and flashed rush, saw 'PMIC init done' string OK.
Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206412
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2
Reviewed-on: http://review.coreboot.org/8582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Once the MTS microcode is loaded the core complex can be
directed to decode the MTS and start running. The cores,
however, won't start executing until instructed to do so.
BUG=chrome-os-partner:29222
BRANCH=None
TEST=Built, booted, ran. Noted it took about 920ms for the
core complex to decode and handshake back.
Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206075
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e
Reviewed-on: http://review.coreboot.org/8581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The armv8 cores need to have microcode loaded before they can
be taken out of reset. Locate and load the MTS microcode at the
fixed address of 0x82000000. The ccplex, once enabled, will
decode and transfer the microcode to the carveout region.
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and ran. Confirmed dump of MTS region after loading code.
Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df
Reviewed-on: http://review.coreboot.org/8580
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As a convenience, print the actual stage name when entering a stage.
Also unify the banner between bootblock / romstage and ramstage. No
reason for two different occurences.
Instead of this:
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...
you will see this:
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting...
Roughly based on: https://chromium-review.googlesource.com/199671
Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8578
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The recommended settings for the size of the MTS region is 128MiB.
Therefore, provide this region 128MiB below the top of DRAM for
each configuration.
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and noted MTS carveout region at expected location.
Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206291
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I369a3897e31f3126d031d3582f52f9892350f658
Reviewed-on: http://review.coreboot.org/8579
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Use the Kconfig value to load the name of the stage instead of the
hard-coded fallback stage.
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b
Reviewed-on: http://review.coreboot.org/8576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.
BUG=None
BRANCH=None
TEST=Built and booted to same place as before.
Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.
BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5
Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Add basic romstage support for rush. Since, dram init needs to be done before we
can jump to armv8 core, romstage will run on armv4 core as well. Thus,
correcting the compiler selection options.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Prints romstage banner and initial printk
Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205763
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a
Reviewed-on: http://review.coreboot.org/8573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source
for the CPU cluster). So, remove the init call for pllx. This needs to be added
later when required. Also, add a few more printks to display the progress.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Print messages seen on serial console.
Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205680
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81
Reviewed-on: http://review.coreboot.org/8571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Pull in mainboard specific bootblock_init function from nyan into
rush. Additionally, pull in all files required for proper compilation of rush
after adding the bootblock_init function
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205583
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795
Reviewed-on: http://review.coreboot.org/8570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.
Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
BUG=None
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203143
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3)
This cherry-pick was modified to match the tegra124 uart.c, which
uses the idx and base address calculations instead of Kconfig settings.
This driver could use the 8250MEM driver when the ARM vs x86 IO
calling convention is worked out.
Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8517
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
This is just dead code.
Should we decide that we want some of these calls made, they would
be implemented in the mainboard context.
Change-Id: I1f097c8da722f3afab9aa1c80b96590c7ca457d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8532
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Vadim Bendebury