- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)
After this commit, there is no way to build an image that is not using
CBFS anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
per discussion on the mailing list.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for years.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
it is a P4 and it needs SSE for romcc not to go into infinite loop.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some of this trickery was determined with serialice.
There are several lovely undocumented features to the chipset.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fam10 and h8dmr k8 targets.
Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with
this, and to Arne for doing the s2912 fam10 port.
Build and boot tested. Abuild tested.
There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, simplify the M2V-MX SE Kconfig file a bit while I'm at it.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
kconfig development.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
the socket it has, and the CPUs are pulled in automatically. There is
some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
- intel/eagleheights
- intel/jarrell
- intel/mtarvon
- intel/truxton
- intel/xe7501devkit
- sunw/ultra40
- supermicro/h8dme
- tyan/s2850
- tyan/s2875
- via/epia
- via/epia-cn
- via/epia-m
- via/epia-m700
- via/epia-n
- via/pc2500e
(PPC not considered, probably overlooked something)
All of them only _build_, but some options are probably completely
wrong. To be fixed later
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also enable building individual boards with kbuildall for
debugging.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's only three files. Also fix up all the paths (Gotta love included C files)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig_bools.diff: Change some more ints to bools, change some default values.
xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB.
smp.diff: set CONFIG_SMP based on MAX_CPUS.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
copy any comment lines before the start of the device tree.
Fix up amd/pistachio and technexion/tim8960.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This allows us to change
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x64);
to the much more readable
dword = pci_read_config32(sm_dev, 0x64);
Clean up all PCI operations in mainboards based on AMD 690:
amd/pistachio
amd/dbm690t
technexion/tim8690
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
out of the way of the serial port. Tested extensively in user mode.
Works and gets the BMC out of my way, which is good, because there
are few more useless things than IPMI and the BMC.
The BMC, all by itself, is the cause of most of our problems in booting
and talking to these nodes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I don't know what else to do for files generated by programs ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
let it build.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tested. I also addressed questions raised by Uwe:
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
UDELAY_TSC
Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in
the mainboard Kconfig. The remaining question of Uwe's is a deeper
problem:
---
We'll have to check if this works. From a quick glance
the Rumba does not have the mmx related lines (which _are_ in
Makefile.romccboard.inc, though):
crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
crt0-y += auto.inc
crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
---
We're going to need a whole variant of this standard mainboard OR
we're going to have to make (some) of the unconditional includes above
conditional.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
remove Config variables now defined elsewhere.
add rumba Kconfig and Makefile.inc
rumba won't build until my earlier patches are acked.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch tries to improve the pcie portA configuration.
The Matrox G550e PCIe gfx card shipped along with the dev board is supported.
Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
copy any comment lines before the start of the device tree.
Copy over the comments for amd/dbm690t.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a
boolean value, so make it so.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This includes:
soyo/sy-6ba-plus-iii
a-trend/atc-6240
a-trend/atc-6220
gigabyte/ga-6bxc
biostar/m6tba
azza/pt-6ibd
tyan/s1846
abit/be6-ii_v2_0
compaq/deskpro_en_sff_p600msi/ms6119
msi/ms6147
asus/p2b
asus/p2b-d
asus/p2b-ds
asus/p3b-f
The Makefile.inc for all of them are _exactly_ the same, so I made a common
src/mainboard/Makefile.romccboard.inc (maybe needs a nicer name). I also suspect
that many other romcc-based boards will be able to re-use this Makefile.inc.
Apart from the board name, most boards only differ in the Super I/O that's
being used and the IRQ_SLOT_COUNT value. The Tyan S1846 is a bit different
as it doesn't have an irq_tables.c.
I also dropped the broken MS-6178 kconfig stuff for now, I'll submit a
proper config in another patch.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Any whitespace or dashes are replaced with underscores.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is the correct choice. Avoids type problems in kconfig
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only build-tested so far, not tested on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Whitespace fixes, remove trailing whitespace, use TABs for identation
(except in Kconfig "help" lines, which start with one TAB and two spaces
as per Linux kernel style)
- Kconfig: Standardize on 'bool' (not 'boolean').
- s/lar/cbfs/ in one Kconfig help string.
- Reword various Kconfig menu entries for a more usable and consistent menu.
- Fix incorrect comment of NO_RUN in devices/Kconfig.
- superio/serverengines/Kconfig: Incorrect config name.
- superio/Makefile.inc: s/serverengine/serverengines/.
- superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
- mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
- mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
- console/Kconfig: Don't mention defaults in the menu string, kconfig
already displays them anyway.
- Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
important corrections to the Kconfig and Makefile.inc that were there. I
would like to go ahead and get this in, because I don't want anyone to
continue using what is in the upstream tree as it now exists.
I also tested old-style build with this and it did not break anything.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CBFS uses sprintf, which requires vtxprintf, which requires (in the
current design) a nested function. That works on x86, but on PPC this
requires a trampoline. In the ROM stage, this is not available, so
remove the single use of sprintf and replace it with a direct string
handler - it's only used to fill in fixed-length hex values.
20090819-3-more-noreturns-in-romcc:
Mark two more functions in romcc as noreturn. Helps clang's scan-build a
bit
20090819-4-cbfsify-ppc:
Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and
not complete yet.
20090819-5-fix-ppc-build:
The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat
plausible value.
With fixes to tohex* functions as discussed on the list, and correct
function names.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This eliminates 56kb of padding in the bootblock.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
kernel) from SATA HDD.
ACPI is working for PCI interrupt routing, some memory stuff and
Soft-Off.
USB/SATA Working
VGA Console Working
X Working via Onboard AGP
Removed dsdt.c, fixed some whitespace.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Remove the normal/* files from the image. they're just
copies of fallback/* anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Keeping identical files around will only bite us eventually, when they
get out of sync. See coreboot-v2 history for examples.
Trivial and build tested.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
when Patrick's tree and mine got out of sync.
Link stage still fails.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and we will fix issues as they appear.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
certain configuration options are disabled. The strings were just
at the wrong place.
Two boards fix up some variables for romstream. This isn't necessary (or
possible) when CBFS is active, as there is no romstream. It would be
nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any
invariant that forces that to be inactive if CBFS is active, and this
patch is supposed to be small, esp. as the stream loaders are on the way
out.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
and through the general vga infrastructure i committed a month or two ago.
Add videoram_size option for k8m890 and the Asus M2V-MX SE.
Now the Asus M2V-MX SE will magically come up with a working standard VGA
80x25 textmode.
Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
of its components; this vga bringup was a breeze thanks to your hard work
for this excellently supported board. And separate thanks to Rudolf Marek
for spurring me on and for providing a register dump.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
linux out of the box. There were two problems. First was that the
mmconfig ACPI structure was empty because of cut and paste (PCI ID of
K8M890 is different).
Second problem is now nicely solvable by add_region. Linux expects that
the mmconfig region is found as reserved memory. Otherwise it does not
trust it.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* acpi_add_table requires a pointer to the RSDP, not the RSDT anymore, in order
to properly support XSDT generation.
* fix compilation the DSDT on gigabyte/m57sli
* drop a remaining, forgotten HPET_NAME for "HPET"
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Move interrupt routing to mainboard specific code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
soon as there's an ACPI 2.0 or later table)
* add XSDT support
* add more table types
This patch will break at least the kontron (and possibly some new boards I
missed)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add the respective Super I/O config in Config.lb (Winbond W83697HG),
enable COM1 on the board, fix irq_table.c, as well as the PCI
devices listed in Config.lb (based on lspci output).
This has been tested by Jakob Bornecrantz <wallbraker@gmail.com>
on hardware, i.e. there is serial output. It does not yet boot
to a Linux console successfully, more fixing will be needed.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on hardware, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Change the parallel port from polling to interrupt-driven.
This was tested by Andreas Mundt with a parallel port printer.
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt@web.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.
Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.
Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on hardware with the patch from r4398 and works fine as soon
as Linux boots (no VGA in FILO for some reason, will investigate).
In order to make the 'i810.vga' VGA blob from the vendor BIOS work
you have to make the check for PCI device ID mismatches non-fatal
(for now) in the src/devices/pci_rom.c file like this:
Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c (Revision 4393)
+++ src/devices/pci_rom.c (Arbeitskopie)
@@ -87,7 +87,7 @@
if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
rom_data->vendor, rom_data->device);
- return NULL;
+ // return NULL;
}
printk_spew("PCI ROM Image, Class Code %04x%02x, Code Type %02x\n",
The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
whereas it really is 0x7121 on hardware. There are multiple ways to work
around this (there have been many discussions in the past), we'll see which
method will be used in future...
Note: This has been tested against r4393 only for now to make sure there
are no problems because of the recent resource allocator changes, see
http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
Tests with trunk will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Turn on Parallel Port and Floppy in Config.lb
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt@web.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.
Importantly, this also sets
default CONFIG_AP_CODE_IN_CAR=0
in
src/mainboard/supermicro/h8dmr/Options.lb
which is required to make this box boot since the changes that went in in
r4315.
At Myles' suggestion, this patch also sets
default CONFIG_USE_FAILOVER_IMAGE=0
default CONFIG_USE_FALLBACK_IMAGE=0
default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
in src/mainboard/supermicro/h8dmr/Options.lb to simplify
targets/supermicro/h8dmr/Config.lb a bit further.
Build tested with abuild, boot tested on physical hardware.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
didn't build before, and it still doesn't)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.
Patch should work against r4381 (or later ?)
This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)
The coreboot_table issue seems to have been automagically resolved by
the latest core files.
It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on hardware by Andrew Morgan <ziltro@ziltro.com>, boots
Linux fine. Detailed status at:
http://www.coreboot.org/Soyo_SY-6BA_Plus_III
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Andrew Morgan <ziltro@ziltro.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, enable HIGH_TABLES support for this board.
The HIGH_TABLES failed with:
No matching ram area found for range:
[0x00000000000f0000, 0x0000000000100000)
Ram areas
[0x0000000000000000, 0x0000000000001000) Reserved
[0x0000000000001000, 0x00000000000a0000) RAM
[0x0000000000100000, 0x000000000fff0000) RAM
[0x000000000fff0000, 0x0000000010000000) Reserved
SELFBOOT RETURNED!
Boot failed.
The fix was to change northbridge.c as follows:
- ram_resource(dev, idx++, 1024, tolmk - 1024);
+ ram_resource(dev, idx++, 768, tolmk - 768);
This is build-tested and tested on hardware by me. It boots fine,
for instace with SeaBIOS and the standard GRUB1 from my disk.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add initial ACPI support for M57SLI.
Activates/Enables:
* native Coreboot ACPI for M57SLI
* Soft-Power-Off
* PowerNow!
* High Precision Event Timer
* Windows booting with ACPI support
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ways superior to v3, while lacking its completeness. But, one nice
thing: no more included .S or .c files. It's all separate compilation.
That should allow our Makefiles to work much better.
Note that the current non-CAR implementation is the default and
continues to work (tested FILO boot to Linux on both CAR and non-CAR).
Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
depend on this variable are grouped in one if, and the other parts
(romcc etc.) are in the else. This change is a model of how we should be
able to do other motherboards.
Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options.
Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file.
Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3.
Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem.
Index: src/pc80/serial.c
make uart_init non-static.
Index: src/pc80/Config.lb
add initobject
Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.
Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init.
Index: src/arch/i386/init/car.S
generic i386 car code from v3.
Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section.
Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well
get all the debugging we can.
Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds.
Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Abuild tested and boot tested on s2895 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
gets us through config, but it fails during build because the original patch
duplicated some files for VIA systems.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Make get_dsdt script executable.
- Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.
- Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
is correct.
- Fix broken or incorrect #include names to increase likelyhood of a
successful compile.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
files for targets without failover:
src/config/nofailovercalculation.lb (64 kB XIP)
src/config/nofailovercalculation128.lb (128 kB XIP)
Targets with other XIP sizes were ignored.
This patch moves XIP size back into mainboard code.
Benefits from this patch:
- src/config/nofailovercalculation128.lb is no longer needed
- Targets with XIP sizes besides 64k and 128k benefit from refactoring
- Conceptually, this makes the include files pure calculation files
without settings.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same. The errata need some extra room in failover.
Trivial and abuild tested
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.
This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.
Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
as it's done everywhere else
- change the default config of abuild to not
provide ROM_IMAGE_SIZE values for the images
in a CBFS configuration
- change abuild's crosscompile autodetection to
not try to use "i386-elf-i386-elf-gcc" (which
is bogus)
Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS
The changes in util/abuild/abuild are trivial and
abuild tested.
As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The patch has been submitted by bari <bari@onelabs.com> and written
by OLPC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code, specifically the difference between pre_f and f code.
The only functional changes are in printk statements. The rest is white space.
1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks. All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code
There is much more that could be done, but it's a start.
Abuild tested and boot tested on s2892 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec.
Stepan pointed out that 's' means string, and that therefor strings do exist.
Marking this as reserved breaks some payloads.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices".
The changes to the cmos code no longer allow usage of values larger than
32bits. Since this option was completely unused, mark it as reserved.
Fixes build after the get_option change (r4332)..
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.
get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.
The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.
build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
directory just with one common file.
Changes to FADT: move to rev4, fix the generic register descriptors, detect additional VT8237S features.
Change the compiler to CORE , its revision to 42.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why
the Solaris version behaves differently, but CURDIR is a safe
choice on gnu make (and we require gnu make already)
- Use tail -1 instead of tail -n1 in a file that already relies on
tail -1 support in another place
- Use tail -1 as alternative to tail -n1 in another place
- Use #define for ulong_t in romcc, as that name is used on Solaris
- Avoid fprinting a null pointer. The standard doesn't mandate that
this is a special case, and Solaris doesn't implement it that way.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
out in the mainboard config file. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tree it was copied from.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Vincent Lim (vincent.lim@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I would like to remind you that this firmware enables the hardware
virtualization on the AMD cpu's on the machine. That feature was
explicitly disabled by the factory BIOS.
Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS)
than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read
config space of a device that is actually not present.
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
./cbfstool coreboot.rom add-payload filo.elf img/FILO
Signed-off-by: Samuel Verstraete <samuel.verstraete@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c
It also adds a driver for the ISA device that is found when using
0.9.1 If you look in a log without this patch you won't find the RTC
init lines.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
because it was not working anyway (it was hardcoded) and because it allows me to
fix the XIP base to something sane (and use generic computation and approach)
This board is bit tricky because until now it required the VGA BIOS on the flash
start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
aligned too to 64KB.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.
For shadowed variable declarations I renamed the inner-most variable.
The one in src/pc80/keyboard.c might need help. I didn't change the
functionality but it looks like a bug.
I boot tested it on s2892 and abuild tested it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
3 (with one of them way too much assembler code).
On the way, I had to make some changes to the way the code is built,
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects
lots of post-raminit code (memcpy doesn't really make sense before
raminit, or at least CAR)
The coreboot_apc code (AMD boards) gained some .c includes because I
don't know that part of the code enough to really rework it and only
have limited possibilities to test it. The includes should give an
identical situation for this part of the code.
This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
support for it.
The related mainboards don't need to activate it
themselves anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this generic code could be added to the caller of
add_mainboard_resources (wrapped in HAVE_HIGH_TABLES, of course).
That way, boards that really need it (for other things) can use this
function, while others don't have to do anything to use
HAVE_HIGH_TABLES.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tested, incl. optionrom-in-cbfs for kontron, and compressed payloads
for both.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
