Enable "CnviBtCore" and "CnviBtAudioOffload" to increase
bluetooth performance.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibafabfaa39ba46620a2e06b288c457267f041ab0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
If the version of the EC firmware in coreboot doesn't match
the firmware that the EC is running, print the versions.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I55c09b8d5ffe8ca9135384c823d005b55cfd83d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76380
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the TGL variant to use the "merlin" EC variant, and delete the
no longer needed "TGL" EC variant.
This is not a functional change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the ADL variant to use the "merlin" EC variant, and delete the
no longer needed "ADL" EC variant.
This is not a functional change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The UCSI mailbox isn't used, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03587a2322b1f34fa26a5c2ba7906a4e1ae82ae0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Merlin was the name for the open-source variant of the EC. It
ended up getting entirely rewritten to work with SDCC, and is
currently being used on starbook/adl. The source code isn't
available at the time of this commit due to some old ITE XLT
code being used.
Add the latest version of the code, replacing the old code, so
the boards can be migrated over.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib8384fc9322058297e8219ac8e483ac37a70bd33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Recent ChromeOS devices use Ti50 instead of Cr50. Therefore, some
strings or comments are not accurate anymore. When applicable, rename
Cr50 to GSC (Google security chip).
BUG=b:275544927
TEST=./util/abuild/abuild -x -t GOOGLE_TOMATO -a
BRANCH=none
Cq-Depend: chromium:4756700
Change-Id: Ie5b9267191a5588830ed99a8382ba1a01933028f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Width of registers are always dwords on pl011, not bytes.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I955319d31bba5c0cd4d50f2b34111d51fea653ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The use of a separate _PRW is not necessary when the _CRS interrupt
already has the Wake flag set (as these all do). Additionally, Windows
does not allow the use of a gpioint for the _PRW source, which results
in an ACPI_BIOS_ERROR BSOD.
Since ChromeOS builds for CYAN devices use an older kernel and may not
make use of _CRS interrupt Wake flag, keep the _PRW around when
CONFIG_CHROMEOS is selected.
TEST=build/boot Win11 on google/{cyan,edgar}
Change-Id: I7d0883e4de9572a14c8bad0ac086370bd00eeb1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76798
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Specify the size of the ME region so that it matches the IFD.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I51ba0a7646ab72d4dd22b99519708649c78b25b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch creates a new variant karis4es.
The new variant will support only ESx samples. The existing karis
variant will support the QS samples.
BUG=b:293326312
TEST=Image built properly
Change-Id: I854fee7206528a235f027ff8ec98593a02be4806
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76761
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Add configs for USB 3.1 Gen2 electrical validation (EV) settings
so that people can set the EV settings per board in device tree.
BUG=b:285811345
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to taranza and checked the log.
All usb configs were set correctly.
Change-Id: Iecd12d3db76b63ad99887dee5991d94d47f138fd
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76246
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This is unused - other references were removed long ago.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia7a65f54c736db20a5440795fdfaa8be31ef971f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
´config´ is removed from measure list (CB:74750)
Add 'config' to ram_stage_additional_list[] to have it measured and
verified.
BUG=NA
TEST=boot and verify coreboot logs on facebook FBG1701
Change-Id: Id4119bc3a01e11f14a091facf81964d1a71092c1
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie54fd6c5a82f368018d0b5fb811a6c9220c2c70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77079
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0fe478a710ecc1f2c8b36347aaf2d1634ebba9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77078
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibabe8faa79e3dcd02f4c885d29b9634645947b98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77077
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
PPR #56569 Rev 3.04 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfac7d996c6de9ea7c6adf2760de0ad97ffb9ec0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
PPR #55570 Rev 3.18 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide492f4479b85cd885044bbf74d8bf18c12e552b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
device/device.h provides struct device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie03f6d15d94f2858e293b9f57505034263c03bbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77074
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Prior to commit d1c0f958d1 ("acpi: Call acpi_fill_ssdt() only for
enabled devices"), uart_inject_ssdt() was used to set the ACPI status
(_STA) for both enabled and disabled devices. The aforementioned commit
limited it to being called only on enabled devices, which left disabled
devices without any _STA method at all -- which the OS assumes means
that the device is present and enabled.
To fix this, create the _STA method in the UART asl code for each port,
and set the return value to a name variable (STAT) which defaults to
0 (not present/disabled). Then, have uart_inject_ssdt() set STAT to
present and enabled (0xF) for UARTs actually present on the board.
TEST=build/boot google/skyrim (frostflow), dump ACPI tables, and verify
that _STA returns 0xF only for UARTs enabled in devicetree.
Change-Id: Id89e74c3ea7f53280935898ee35311b7cf3b152a
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console,
so enable uart_0 in the devicetree to make sure that the UART will be
marked as enabled in the SSDT that will be generated with the next patch
applied. This also matches the other AMD SoC based Chromebooks.
Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI
_STA in asl since now handled by common SSDT generator. Implement
wait_for_aoac_enabled() since required by SoC common code, and ensure
compiled during all stages necessary.
TEST=build/boot google/liara, verify console UART still functional.
Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 5dfec71829.
Reason for revert: This change made it impossible to disable ASPM by
FSP parameter. ASPM_DISABLE would result in the FSP parameter not
being programmed, causing it to be the FSP default value instead.
This additionally fixes MTL to match ADL.
Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75280
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I56ee0d4a26931fe05d2d35046325901930086e35
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76344
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TESTED=On Intel AC, after seleting DISPLAY_UPD_IIO_DATA to compare
IIO UPD data are expected. lspci -vvv result is also normal.
Change-Id: Icfc2a22cb2e1f95be6bfc1d712e620e19a23ce27
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
To deduplicate mainboard mainboard_config_iio since there are a few
SPR-SP mainboards now.
The flow would be soc function initialize_iio_upd initializes the table
with the default values which are mostly zero, then mainboard can
overwrite it by soc_config_iio.
Change-Id: I72d74241fcad4c85a95f6d14587418f544caadd9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76185
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Generate RAM ID for CXMT CXDB4ABAM-ML
DRAM Part Name ID to assign
CXDB4ABAM-ML 1 (0001)
BUG=b:290154780
BRANCH=dedede
TEST=FW_NAME=boxy emerge-dedede coreboot chromeos-bootimage
Change-Id: Ide44acf6bb8e5d5023c76d9e5e48ef113f7c6ec6
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76825
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This has two noticeable effects:
1. Devices populate the list much quicker while scanning.
2. Devices do not disappear and reappear from the list while scanning.
Tested on system76/lemp10.
Change-Id: I598c53805785914b4e9ae7f620e724eadbe643d4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Daniel Sutton <daniel@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77047
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NVM has 8KB to store camera module related settings and
parameters. According to NVM hardware spec, the NVM size should be
0x400 and the width size should be 0x08.
Re-set the right NVM format and ensure camera related configs can
get the correct module information.
BUG=b:294155898
TEST=none
Change-Id: I58932bc0f3dd935aa0ea8e68b2a4b0ae4907b316
Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76893
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
TEST=build/boot Windows/linux on redrix?, verify touchscreen functional
in OS, dump ACPI and verify only i2c devices actually present on the
board have entries in the SSDT.
Change-Id: I0273014b2d164f67f503da7b968a09256bffb43c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74929
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For brya variants with a touchscreen, drive the enable GPIO high
starting in romstage while holding in reset, then disable the reset
GPIO in ramstage (done in the baseboard). This will allow coreboot
to detect the presence of i2c touchscreens during ACPI SSDT generation
(implemented in a subsequent commit).
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
TEST=APU2 still boots and doesn't show any new errors in dmesg.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia9f0eb3df8fd2dfe395f616da981cc3a0cd3b29d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Before add_io_regions only reported one fixed IO range to the resource
allocator that covered the whole IO range from 0x0000 to 0xffff. Instead
read the data fabric IO space decode base and limit address register
pairs to get the actual IO port decoding from the data fabric registers.
This will also help with adding support for multiple PCI root domains to
the common data fabric domain code so that Genoa can use it. In that
case each PCI root domain will only decode a part of the whole IO port
range.
Beware that the data fabric IO base and limit fields can contain values
that correspond to IO port addresses far outside of the addressable IO
port range. In case of Picasso, the IO limit read from the only enabled
DF IO range register would be 0x1ffffff after converting the raw data to
an IO port address. To not give the resource allocator wrong constraints
make sure that the IO limit we report will be at maximum 0xffff.
TEST=On Mandolin (Picasso) and Birman (Phoenix) the full range of IO
port addresses still gets reported as a domain IO resource producer like
before the patch:
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I087d96f7bdaae0d7b53089f6abaf0500a4b064e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
PPRs #57254 Rev 1.52 and #57255 Rev 0.33 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58e26caa1ba910b41911991b176a1ac8c4e0065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
PPRs #57019 Rev 3.05 and #57396 Rev 3.06 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I769dc317115981391cf0f4e0b743c600407a6eb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76958
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PPRs #57243 Rev 3.02 and #56558 Rev 3.04 were used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic68e73e28362abc5d812839b40282114c7ba25ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
PPR #56569 Rev 3.04 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifcae9c9ad664d50100cd40692fd9631845f76671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
PPR #55570 Rev 3.18 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I61d4fca48d71010bbc4bd94a2fb8889bad08f1cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Rename add_io_regions to add_data_fabric_io_regions to be consistent
with add_data_fabric_mmio_regions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia990cc14dd6dc162ad614a6e9e0b36426cb04670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
As a preparation to read the IO decode ranges from the data fabric
registers instead of having it hard-coded, factor out the
report_data_fabric_io function to report one IO producer region from
add_io_regions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51c3f8cd6749623f1a4bad14873d53b8a52be737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76933
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the fabric_id struct field in the df_mmio_control union to
dst_fabric_id to both better match the register definitions and also be
a bit clearer about what this is doing. Also use tabs for indentation in
the struct inside the df_mmio_control union.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0a17d82a5d7b66a8f84854f21fbbb319da81ac43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Order the data fabric register definitions by function number and
register offset.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia3066ad0f564520cb322a3e41a413eb3bf51260d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Now that the data fabric PCI device functions are included in the
register definitions, the remaining data fabric device function numbers
can be dropped from the define names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76889
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the data fabric PCI device functions are included in the
register definitions, the remaining data fabric device function numbers
can be dropped from the define names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0355838ac1d513ba562fd6fb4672342dd383498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76888
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Instead of open coding the broadcast data fabric PCI register access in
the functions for indirect non-broadcast data fabric register access,
just use the existing data_fabric_broadcast_[read,write]32 functions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I174c1e6ee4856d97c5ec6d07bb8c217d6df9425f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
To have both the PCI function number and the register offset into the
config space of that function of the data fabric device in the data
fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN
and DF_REG_REG macros. The DF_REG_ID macro is used for register
definitions where both the function number and the register offset are
specified, and the DF_REG_FN and DF_REG_REG macros are used to extract
the function number and the register offset from the register defines.
This will allow having one define for accessing an indexed group of
registers that are on different functions of the data fabric device.
TEST=MMIO resources read from the data fabric's MMIO decode registers
don't change on Mandolin and the ACPI CRAT table is also identical.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63a284b26081c170a217b082b100c482f6158e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Debug messages shown during IDE initialization are streamlined as
follows:
"Primary IDE interface" (and similar) are shortened to
"Primary interface".
We don't need to see "IDE" twice as messages are already prefixed.
Refactor "IDE: (Primary) IDE interface: (on)" into
"IDE: (Primary interface): (on)" to allow compiler to deduplicate
component strings, also used later in messages re UDMA/33.
This reduces uncompressed string size by 32 bytes and allows ramstage
to compress a wee bit better.
Change-Id: I16f5c2b3775c5a73b83d83817d7075e944089a12
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73331
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since it was the only super I/O in the serverengines folder, also drop
the parent folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I610c94bc100c9d5558da442b2847d8f26de07820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77064
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix ethernet MAC address configuration. Currently, coreboot would
use ethernet_mac0 for both ports when setting the system's MAC
address. Instead, set the right device_index for the second controller
to pick up ethernet_mac1.
BUG=b:294856127
TEST=boot device and observe two different MAC addresses on the ethernet
ports.
Change-Id: I5ff6d62d2f837a120f7095f9b9aed487e6c5aee4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77044
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the RPL CPU power limits and system power limits based on
the suggestion of the thermal team for RPL SKUs.
The PL4 value suggested by the thermal team which is different from the reference document 686872.
BUG=b:292471206
BRANCH=firmware-brya-14505.B
TEST=built and booted into OS.
Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Without setting these GPIO bits, you /can/ power on your board after
powering it down again. This includes after cutting the power.
The only way to recover from this is to pull the CMOS battery and cut
the power for 15mins. Then make sure you don't do this GPIO trickery or
you end up with the same state of basically an unresponsive "dead"
mainboard. So flash the chip before you pull the battery.
One small workaround I found when you like to flash from the system, is
to press the power button with 1 second after you enable power to the
board. In this small timeframe, apparently the superio chip didn't
intialise/restore/gets set with the settings that make it never want to
power on again. The other workaround is to connect the appriopriate
pins on the ATX power connector to force power to the mainboard.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I4c9df200ba3ec5f315ad3d184588551d29fa68ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I19c029968584fedbb6749e66c7ea2f74a7d580f4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Copy jack detect GPIO config of NAMI variant, which uses the same
codec for the external jack/mic. The internal pull-up isn't needed,
and fixes issue of high CPU usage under Windows.
TEST=build/boot google/rammus, verify jack detect functional under
both Win11 and Linux 6.x, no high CPU usage from excessive interrupts.
Change-Id: Ifbe23a6b33343e54b43879a8971c7cb6475cf1f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76947
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Once platform code has filled in the (legacy) ACPI PM register
map, added function will fill in the extended entries in FADT.
TEST=samsung/lumpy and amd/mandolin FADT stays unchanged.
Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The first platform samples came with IT8786E. The production units
switched to IT8784E in the final design.
Change the code to use IT8784E and reflect the proprietary firmware
configuration of the SIO chip.
TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
IT8784E is basically a IT8786E stripped from serial ports 3-6.
The patch creates a chip directory for IT8784E used by
protectli/vault_cml platforms.
TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add ramstage.c in Makefile.inc and update boxy power limits in
Boxy ramstage.c.
BUG=b:290293153
TEST=emerge-dedede coreboot and check psys and PLx value on boxy
Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ARM architectual timer by initializing frequency to 13 MHz. Since
system timer is the source of the architectual timer, we also call
`timer_prepare` in `init_timer`.
BUG=b:229800119
TEST=run `suite:faft_bios` to verify the firmware stability.
check timestamps by cbmem.
Cq-Depend: chromium:4747539
Change-Id: I8b1348044e4c92984510604b7f61611e13284d86
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All boards based on brya will have GFX devices to represent DRM
connectors in the kernel's /sys/class/drm/.
There should be no functional impact with or without this patch.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the device and soc directories that don't already have an
SPDX license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the drivers directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8442bc18ce228eca88a084660be84bcd1c5de928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68980
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the cpu directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3033f2a9eebc75220f7666325857b3ddd60c8f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68979
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.
TEST=build/boot google/banshee, verify able to boot from all USB ports
using edk2 payload.
Change-Id: I998cc4a40950f43b4c511ead93ccc02c56c8367c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76945
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.
TEST=build/boot google/drobit, verify able to boot from USB ports using
edk2 payload.
Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Inspect all type-C USB ports, check if there is a USB device attached,
and if so, send the connection request to the PMC. This allows for any
attached USB2/USB3 devices to be used for booting by the payload.
Since this functionality is only needed by ChromeOS devices with TCSS
running upstream coreboot, introduce a new Kconfig to guard its use.
Boards needing it will select it in subsequent commits.
TEST=tested with rest of patch train
Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable 'i' is unsigned, so use %zu vs %zd.
Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similarly to te_relocate(), on success pe_relocate() should return 0.
It has never been an issue so far as pe_relocate() return value is not
tested.
Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to
detect if PECI can be used.
Change-Id: I301361f35caee8ba1c3fd9227219603897add92b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When lemp9 was converted to a variant in CB:64528, the Makefile was not
updated to handle the variant-specific `romstage.c`. This, as would be
expected, caused memory init errors and broke boot on CML-U boards.
Tested lemp9 boots to payload again.
Fixes: 5b7b04c938 ("mb/system76/cml-u: Convert lemp9 to a variant")
Change-Id: Ibc11d69a1662df653e6553421d67a9cd1b1d03e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
BUG=b:279097356
TEST=On dibbi:
- flash OS 15449.0.0 (where suspend is broken due to b:274531972)
- run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28`
- check the AP wakes up immediately when the EC detects a sleep hang
Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add PLx from JSL PDG(ID: 613095) in boxy devicetree.
BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
CPU TDP = 6 Watts, CPU PL4 = 60 Watts
Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
_DSD "StorageD3Enable" property is needs to be set under the root
port in the DSDT or SSDT. The ACPI _DSD method is the preferred way
to opt D3hot support for storage devices.
This also bypasses the low LTR from SSD that blocking S0i2.2
LTR/latency SoC requirement.
Name (_DSD, Package () {
ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
Package () {
Package (2) {"StorageD3Enable", 1},
// 1 - Enable; 0 - Disable
}
}
)
BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.
Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:290165011
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were verified by the thermal team.
Based on thermal table in 290705146#comment11.
Set "tcc_offset" = "8"
BUG=b:290705146
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
To be consistent with other boards setting the keyboard backlight at
boot.
Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature was originally present and then dropped, but turns out
that users prefer it. Set the backlight to 50% in romstage, back to
zero in ramstage; skip enabling on the S3 resume path.
TEST=build/boot google/eve, verify keyboard backlight turns on/off
as expected.
Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the jack detect GpioInt resources under the codec (where they
belong), but also leave a copy under LPEA for since the Linux drivers
(incorrectly) require them there. Add pin list for Windows' SST driver.
Adapted from the Intel ValleyView edk2 ACPI reference code.
TEST=build/boot Win11, Linux on google/swanky; verify audio functional
OOTB under Linux, under Windows with coolstar's drivers.
Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
- add HRV and GpioIO for coolstar's windows drivers
- fix interrupt type for TI jack detect switch
TEST=build/boot Win11, Linux on google/cyan; verify audio working
OOTB under Linux, under Windows with coolstar's audio drivers.
Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Most of the components of this laptop are tested to work,
which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The JPEG decoder, that was added many years ago to display a boot-
splash in coreboot, has a few quirks. People used to do some voodoo
with GIMP to convert images to the right format, but we can also
achieve the same with ImageMagick's `convert`. The currently known
constraints are:
* The framebuffer's color format is ignored,
* only YCC 4:2:0 color sampling is supported, and
* width and height have to be a multiple of 16 pixels.
Beside that, we can only display the bootsplash if it completely
fits into the framebuffer. As the latter's size is often decided
at runtime, we can't do much more than offering an option to set
a specific size.
Change-Id: I564e0d89fb46503ff4c11e095726616700009968
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Include multiple hash tables into relevant CBFS.
BUG=b:277292697
TEST=Ensure that all multiple hash tables are part of Myst BIOS image
with PSP verstage enabled.
Change-Id: I1601f4a01db5b2bbf8b5636ef9e69e41c1d9a980
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76589
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mainboards using Phoenix SoC with PSP verstage enabled, to
accommodate growing number of PSP binaries, multiple smaller hash tables
are introduced. Also some hash tables are in V2 format identifying the
concerned PSP binaries using UUID. Add SVC calls to support multiple
hash tables with different versions.
BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that
all the hash tables are injected successfully. Ensure that PSP validated
all the signed PSP binaries using the injected hash tables successfully.
Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently PSP verstage updates PSP bootloader with one unified hash
table containing hashes for all the signed PSP binaries to be validated.
With growing number of PSP binaries to validate and memory constraints
in PSP, there is a requirement to split and update the hash table into
multiple smaller chunks. Hence change the update_psp_fw_hash_table()
signature such that the hash tables are updated in a chipset specific
way.
BUG=b:277292697
TEST=Build and boot to OS in Myst with PSP verstage enabled. Build the
Skyrim BIOS image and confirm that the hash table is identical before
and after this change.
Change-Id: I75aac5bc5e7f61069be25d801d0838fdf565d3d1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76587
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby.
The wake issue either needs to be fixed, or S1 should not be advertised
as a capability in the ACPI table.
Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not
supported on Skyrim devices. This results in 'standby' being removed
from /sys/power/state.
BUG=b:263981434
TEST=suspend_stress_test
TEST=frostflow-rev2 ~ # cat /sys/power/state
freeze mem
Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
C1-state auto demotion feature allows hardware to determine C1-state
as per platform policy. Since platform sets performance policy to
balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter PC2 and lower
state in camera preview case and save platform power.
Note: C1 demotion heuristics used EPB parameter to balance between power
and performance, i.e. low threshold when EPB is low in-order to get C1
demotion faster and vice-versa. ChromeOS operates at default EPB=0x7
(low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits
than expected (similar to AC mode) and losing power respectively.
BUG=b:286328295
TEST=Code compiles and correct value of c1-state auto demotion is
passed to FSP. Also verified PC residency improvement ~10% in
camera preview case.
Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since all indirect data fabric register accesses will be non-broadcast
accesses that target a specific data fabric instance, the
cfg_inst_acc_en bit in the DF_FICAA_BIOS register will always be set
since that makes the indirect access target only a specific data fabric
instance.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9aff01750c2c1e3506141b3ed293a980a64f8fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
FSP has a parameter to enable/disable c1-state autodemotion feature.
Boards/Baseboard can choose to use this feature as per requirement.
This patch hooks up this parameter to devicetree.
BUG=b:286328295
TEST=Check code compiles & boot google/rex, and correct value has been
passed to FSP.
Change-Id: I2cc60bd297271fcb3000c0298af71208e3be60fc
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76826
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
USB DBC is very helpful for SoC debug. TraceHub needs to be enabled in
coreboot if debug consent == 2 or 4. Debug consent == 6 enables USB DBC without TraceHub enabled.
This patch updates the Kconfig help text to meet PlatformDebugOption in
MTL and changes debug consent to 6 in default to provide basic SoC
debug capability.
TEST=Boot to OS on screebo and DBC connection is OK.
Change-Id: Ic12528bdd8b1feda7f1b65045c863341f932d3a2
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76880
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 9a7a677 from opensbi project moved the fu540 platform to generic
code and commit 26998f3 from opensbi removed the old non generic
platform. Therefore opensbi platform needs to change to generic.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I76aa3d386936b331785a23edb8deb0d73609be47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tablet motion control is a function of the EC, and under Windows, the
TBMC device needs to be initialized after CREC, or driver init will
fail. The only way to ensure this happens is for TBMC to be a child
device under CREC.
TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers
loaded and orientation switching functional under both OSes.
Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
cse_prep_for_rw_update() should return CB_ERR when
cse_data_clear_request fails. It was modified to CB_SUCCESS in this
commit ad6d3128f8 ("soc/intel/common: Use enum cb_err values")
BRANCH=None
BUG=None
TEST=Verify the system goes to recovery during downgrade when
cse_data_clear_request() fails.
Change-Id: Ibbccb827765afa54e5ab1b386fa46093b803977a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Enable config TME_KEY_REGENERATION_ON_WARM_BOOT for Intel Meteor
Lake SOCs. This config allows Intel FSP to programs TME engine to
generate a new key for each warm boot and exclude CBMEM region
from being encrypted by TME.
Bug=b:276120526
TEST= Boot up the system, generate kernel crash using following
commands:
$ echo 1 > /proc/sys/kernel/sysrq
$ echo "c" > /proc/sysrq-trigger
System performs warm boot automatically. Once it is booted,
execute following commands in linux console of the DUT and confirm
ramoops can be read.
$ cat /sys/fs/pstore/console-ramoops-0
S0ix also tested and found working.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set UPD params GenerateNewTmeKey, TmeExcludeBase, and TmeExcludeSize
when TME_KEY_REGENERATION_ON_WARM_BOOT config is enabled. These UPDs
are programmed only when INTEL_TME is enabled.
Bug=b:276120526
TEST=Able to build REX platform.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75626
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Merge TME_KEY_REGENERATION_ON_WARM_BOOT and
TME_EXCLUDE_CBMEM_ENCRYPTION config options under new config option
named TME_KEY_REGENERATION_ON_WARM_BOOT.
Program Intel TME to generate a new key for each warm boot. TME always
generates a new key on each cold boot. With this option enabled TME
generates a new key even in warm boot. Without this option TME reuses
the key for warm boot.
If a new key is generated on warm boot, DRAM contents from previous
warm boot will not get decrypted. This creates issue in accessing
CBMEM region from previous warm boot. To mitigate the issue coreboot
also programs exclusion range. Intel TME does not encrypt physical
memory range set in exclusion range. Current coreboot implementation
programs TME to exclude CBMEM region. When this config option is
enabled, coreboot instructs Intel FSP to program TME to generate
a new key on every warm boot and also exclude CBMEM region from being
encrypted by TME.
BUG=b:276120526
TEST=Able to build rex.
Change-Id: I19d9504229adb1abff2ef394c4ca113c335099c2
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76879
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add more details to instruct future boards/models implementers regarding
how GFX devices should be added.
If HDMI and DP connectors are enumerated by the kernel in
/sys/class/drm/ then corresponding GFX device should be added to ACPI.
It is possible that some connectors do not have dedicated ports, but
still enumerated.
The order of GFX devices is DDIA -> DDIB -> TCPX.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Build issue introduced by patch CB:76418 (commit hash
01025d3ae7) for Google boards.
Patch has not been rebased to latest master and tested before
submission causing the Jenkins jobs to fail.
Change-Id: I95bd2485b98be4ab3a39eaaebb9efb34db93bbe8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce new symbol SOC_INTEL_RAPTORLAKE_PCH_S that can be selected
by board with RPL-S PCH.
For now only the IoT variant of RPL-S FSP is available for use with
700 series chipsets. Boards with 600 series chipsets can still use
RPL CPUs with the ADL-S C.0.75.10, which contains minimal RPL-S CPU
support.
Change-Id: I303fac78dac1ed7ccc9d531a6c3c10262f7273ee
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Only the headers on Intel FSP repository have the CnviWifiCore
present. Options guarded for RPL like: DisableDynamicTccoldHandshake
or EnableFastVmode and IccLimit is also supported by all public FSPs
(except ADL-N for the handshake).
Options like LowerBasicMemTestSize and DisableSagvReorder have to be
guarded when FSP_USE_REPO is not selected, as publci FSPs do not have
these options.
Use FSP_USE_REPO instead of/in addition to SOC_INTEL_RAPTORLAKE
as dependency on the guarded UPDs to make them available for FSPs
that support them as well. Also prioritize the headers from FSP repo
over vendorcode headers if FSP_USE_REPO is selected.
Change-Id: Id5a2da463a74f4ac80dcb407a39fc45b0b6a10a8
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
If ACPI is above 4G it's not possible to have a valid RSDT pointer in
RSDP, therefore swap RSDT and XSDT. Both are always generated on x86.
On other architectures RSDT is often skipped, e.g. aarch64. On top of
that the OS looks at XSDT first. So unconditionally using XSDT and not
RSDT is fine.
This also deal with the ACPI pointer being above 4G. This currently
never happens with x86 platforms.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6588676186faa896b6076f871d7f8f633db21e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This makes sure google/ovis don't get a random mac address on boot.
Additionally, program the LAN WAKE GPIO properly as per the Ovis
schematics dated July'23.
BUG=b:293905992
TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles.
Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
TESTED acpixtract -a is able to extract all the dumped tables including
FACS and DSDT.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7fad86ead3b43b6819a2da030a72322b7e259376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Arm needs very little of FADT. Just a HW reduced model bit and low power
idle bit set.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76180
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for Samsung K4U6E3S4AB-MGCL.
BUG=b:293240969
TEST=emerge-dedede coreboot
Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Configure GPIOs based on schematics and confirm with EE.
BUG=b:290248526
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
It's not expected that non-x86 arch implement x86 style sleep states and
resume.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76178
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select this Kconfig to ensure the PSP_ADD_MSR is properly programmed
across all cores.
This resolves a Windows BSOD "CRYPTO_LIBRARY_INTERNAL_ERROR."
BUG=b:293571109
BRANCH=skyrim
TEST=build/boot google/skyrim, use rdmsr to verify MSR value identical
across all cores.
Change-Id: I67391b49496d767912f5d81c1758a52a70fca6f6
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76809
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ideed4b333632df5068b88dde6f89d3831e3046d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
In the datasheet of ILI9882T [1] section 3.11 Power On/Off Sequence,
the TReset-CMD (Reset to First Command in Display Sleep In Mode) should
be larger than 10ms, but it's 1.1ms now. This may cause abnormal
display as some commands may be lost during power on. Fix this and
leave some margins by increasing TReset-CMD to 20ms. Also, to align
with the kernel driver structure starry_ili9882t_init_cmd, add 20ms
delay at the end of command.
[1] ILI9882T_Datasheet_20220428.pdf
BUG=b:293380212
TEST=Boot and display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ifdcaf0e34753fc906817c763f1c8e7389448d1dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76766
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iad9cbe16a2d1881d74edcc702be843168df8a4ff
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I16ac584781214350355e0625f8a2eca39a37cf85
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3d5838b825c6ac2a2959388381004993024081c3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76813
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I2d65e9dbefc8fa5d8288151995a587f76049c65a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Id19193b960935eeffca8e8db60073321592368fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76836
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iab55c57ee5cac60911c9fe4cee8d86a252bde372
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76839
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3ab3538b276fee5ed135bb4e88d9ef2cd6a00bb9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76843
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I79e4b34fe682f5f21415cb93cf65394881173b34
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76842
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ibd1e4bc96a2f5eea746328a09d123629c20b272c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The EFS_OFFSET is the relative address to flash base. We can not
assume the flash size is 16M.
The change will affect only Gardenia and Pademelon whose flash size
are 8M.
Change-Id: Ia68032db05264c55d333deec588ad9690a4ed2c1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76764
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H54G56CYRBX247
2. H9HCNNNCPMMLXR-NEE
3. MT53E1G32D2NP-046 WT:B
4. K4UBE3D4AB-MGCL
5. K4UBE3D4AA-MGCR
BUG=b:290811418
BRANCH=dedede
TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage
Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The PSP_ADDR_MSR is programmed into the BSP by FSP, but not always
propagated to the other cores/APs. Add a hook to run a function
which will read the MSR value from the BSP, and program it into the
APs, guarded by a Kconfig. SoCs which wish to utilize this feature
can select the Kconfig.
BUG=b:293571109
BRANCH=skyrim
TEST=tested with rest of patch train
Change-Id: I14af1a092965254979df404d8d7d9a28a15b44b8
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch chooses to show the early splash screen which is an
OEM feature. The current implementation is relying on the Intel
FSP GFX PEIM to perform the display initialization.
Having this feature allows the platform to show the user notification
with 500ms since boot compared to traditional scenarios where first
user notification is coming from kernel (typically ~3sec+ after cpu
reset). Eventually this feature will help to improve the user
experience while booting Intel SoC platform based chromeos devices.
BUG=b:284799726
TEST=Able to see the early splash screen on google/rex.
Change-Id: I399ddb6618e774302200e8a87629647ba070d080
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These devices are not present/used on CYAN boards.
Change-Id: I012b49562c2b932822823537032e2265901ddc81
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Set the ACPI status (_STA) for the PD device enabled+visible, to allow
coolstar's Windows drivers for USB4/Thunderbolt to attach.
TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify
USB4/TB ports are functional for PD and data at USB4 speeds.
Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow
coolstar's Windows drivers for the EC and keyboard backlight to attach.
TEST=build/boot Win11 on google/samus, install EC/kblight drivers,
verify keyboard backlight control functional.
Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
No drivers are needed/available, so hide the device to prevent
an unknown device from showing under Device Manager.
Linux does not use the ACPI _STA so no effect there.
Change-Id: I02efb64a845edc6e4fc559e7e99a7825abf4c2aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
While FSP programs the VmxEnable UPD per CONFIG_ENABLE_VMX, it doesn't
set the lock bit, which prevents Windows from enabling virtualization
on devices which support it. Call set_vmx_and_lock() to ensure the
lock bit is properly set.
TEST=build/boot Win11 on google/ampton,reef; verify virtualization
enabled.
Change-Id: I54ea0adb0a6d10f2df18f604b1f1e5a7a145dfb3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76804
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Typically we set SaOcSupport to allow overclocking RAM, but addw2 saw a
high rate of errors when using the provided 3200 MHz DIMMs. Disable OC
so modules run at the standard 2933 MHz.
Change-Id: I469b9c73d2e6bfa0b3c9175bcc87584aeaa95f75
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform a codec reset to match all other System76 boards.
This applies commit 705ebbea04 ("mb/system76: Reset Realtek codec
before configuring") to boards that were added later.
Change-Id: I618cc042f1803d07bfc067d1999e1c44ab4a1fa9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Users report having the touchscreen as a wake device causes many
spurious wakeups due to proximity to the keyboard when the lid is
closed, so remove it as a wake source.
TEST=build/boot google/glimmer, observe no unintended wakeups when
the lid is closed.
Change-Id: Id16cabcd21afa0b373ecddd9eb3b0b8befb71576
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This matches the change done for DDR4 in commit 8509c25eec
("soc/intel/alderlake: Allow channel 0 for memory-down").
Fixes detection of the on-board RAM (Samsung M425R1GB4BB0-CQKOD) on the
System76 Lemur Pro 12 (Clevo L140AU). The Clevo L140*U are the only
boards in the tree using mixed memory topology.
Change-Id: I395f898472a9a8f857fd6b0564b95c787b96080b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Set the ACPI SSID using Google's project campfire ID for EVE, to allow
coolstar's Windows drivers to identify the device (since it uses a
generic ACPI _HID). Custom drivers are necessary under Windows since
the touchpad firmware is not fully I2C-HID compliant.
TEST=build/boot Win11 on google/eve, verify touchpad fully functional.
Change-Id: I3b8d56ff01d4cca7ba5c02f1aaab1a7049607dbc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
CB:73353 switched ADL boards from using S0ix to S3. DevSlp can be
reenabled now as it no longer breaks suspend.
Change-Id: I618696833b7ed02e49c35d06021b730be91d879e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
System76 EC since system76/ec@99dfbeaec3 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 value from
coreboot since it won't be used.
Change-Id: I2bc37f12aab11910b4fe029efcee891a93257529
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Do not reconfigured LSX0 so that the FSP values are used.
Change-Id: I76e2ab01a5e853e3c1ac78b471ea0aa87d703d52
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76751
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EAPD pin needs to be enabled and set in order for the headphone
jack to work properly. It's already done for the speaker in the
beep verbs, but needs to be done for the HP jack as well in order
for output to work properly under Windows.
TEST=build/boot Win11 on LINK, verify headphone output functional
when headphones plugged in.
Change-Id: I411d7317aefc1154635c4c17ca0dc1e37c9f40f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76746
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the pirrha variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:292134655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PIRRHA
Change-Id: Idc0a4dbb467cbdb91a5ed55c5e0a9e898e775b11
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76768
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC serial port on these devices is not accessible to the end user
and exposing it to the OS via ACPI serves no purpose. Debugging over
the EC serial port (via the servo interface) does not require the
ACPI exist. Drop it since it's not needed and serves no purpose.
TEST=build/boot Win11 on auron/link/slippy, verify Windows Device
Manager no longer shows an unusable COM port.
Change-Id: If453bfca8e094aa06043293bdf91a40c38cc7866
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76793
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Id0baf970dbe94a8ebf75f8dbabc6abe345d1c454
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I03c21e180e9e399e5cb451bf3b9cfb6484cab68b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I00807a435a21e078c89f797cfd0b00d03604ea0e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76786
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The non-PCI resources added to the domain device are resource consumers,
so they mustn't be reported as resource producers. To make sure that
this is the case, skip all resources that have the IORESOURCE_RESERVE
flag set in amd_pci_domain_fill_ssdt.
Commit 7a5dd781d1 ("soc/amd/common/data_fabric/domain: provide
amd_pci_domain_fill_ssdt") that introduced amd_pci_domain_fill_ssdt
already contained the bug, but since no MMIO range consumers were added
back then, the bug only became visible when commit 32169720bb
("soc/amd/common/data_fabric/domain: report non-PCI MMIO resources")
added the reserved non-PCI MMIO resources to the domain device's
resources resulting in MMIO producer objects being generated for MMIO
consumers. Those producers that should have been consumers then
overlapped with the actual MMIO resource producers which caused Windows
to BSOD with an ACPI_BIOS_ERROR.
TEST=The non-PCI MMIO resources are no longer added as resource
producers and Windows boots again on google/frostflow.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ib099675bc5bea93bf7c2a80f741bef067fd37a58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
When iterating over the resource list in amd_pci_domain_fill_ssdt, don't
return when a resource is unassigned, but just continue to the next loop
iteration so the resulting SSDT will be complete and not broken due to
a missing resource template footer and the scope not being closed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I39fe516f27a6d971fb9c57a1e64ead79d23aff08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I80b4b2df4a38dcbb28d928018446e91acae90ee6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I3d716b29d8e28584a0c9e4056d4c93dca2873114
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76780
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: If31cbc5ae184c4eb66011666c1bb655fa16afba0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Ia1d597c0e3e86db8c13829e58a8a27d9de1480b4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76788
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I52b5a83e7e484889bfef5a4e45a0279fadd58890
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I495605190b2c6cd11c7f78727ab4611e10b4d9d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I53ffa4b35d35d4f8b0170377041b258d4bd2eeeb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: Iea63e7ce165b1c8129725136e39bff45765023e6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I688bef264ff41b2a9755133698880fa397f652d4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76755
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 49d8aa7043 ("soc/amd/common/block/psp: Unmap EFS region after
use") removed the 'efs_is_valid' function but left the function
signature in the header file.
TEST=stoney/picasso/cezanne/mendocino/phoenix builds
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib596946679b50be63868af57e3428b4d65845419
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76750
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Introduce new parsing rules for ux_locales.c:ux_locales_get_text():
* Add a version byte: PRERAM_LOCALES_VERSION_BYTE in the beginning. This
provides more flexibility if we want to change the format of
preram_locales region.
* Add a new delimiter 0x01 between two string_names. This could fix the
issue that 'string_name' and 'localized_string' might be the same.
Also fix two bugs:
1. We would search for the language ID exceeding the range of current
string_name.
2. In 'move_next()', we would exceed the 'size' due to the unconditional
increase of offset.
Finally, make some minor improvements to some existing comments.
BUG=b:264666392, b:289995591
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ic0916a0badd7071fa2c43ee9cfc76ca5e79dbf8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Lower the TCC Offset by 10 degress.
Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the SSID to allow the correct Creative Labs Windows audio drivers
to attach (vs generic HDA audio ones) and provide full functionality.
Linux doesn't care about the SSID, so changing it has no effect there.
TEST=build/boot Windows, Linux on google/link, verify the correct
audio drivers attach under Windows, no regressions under Linux.
Change-Id: Ib5e523b07583289b0222ef156245fb0771ad1f1c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76745
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e75f29a52179b72b25092f0ffdfd91a182d6648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This address is more certain to not collide with other symbols.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I02eddf43a00c443a1193d6db77d6fad3715216f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Without FSP we assume TSEG is right above CBMEM.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8700803617c3fe4890e497c6d7b94f1d36e21cb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76472
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Factor out the common FSP-specific code to get the location and size of
the SMM region from the HOB that FSP has put into memory. This moves
FSP-specific code out of the common AMD SoC code into the FSP-specific
common AMD SoC code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie137bb0f4e7438a1694810ae71592a34f9d8c86e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76760
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Factor out the common FSP-specific code to report the usable and
reserved memory resources read from the HOBs that FSP has put into
memory. This both reduces code duplication and also moves FSP-specific
code out of the SoC code into the FSP-specific common AMD SoC code
folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib373c52030209235559c9cd383f48ee1b3f8f79b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76759
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Set GPP_C6(TCHSCR_REPORT_EN) and GPP_C7(TCHSCR_INT_ODL) to NC for
non-touchscreen sku.
BUG=b:283199751
BRANCH=firmware-nissa-15217.B
TEST=build and boot to ChromeOS
Change-Id: Ie062eef24f640c3d6c4a0b4c77792e57ac3a722c
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Uldren will support internal fivr in next phase and using fw_config to
decide the board with internal or external fivr.
BUG=b:287379760
BRANCH=firmware-nissa-15217.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.
Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B
2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E
3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP
4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 1 (0001)
H9JCNNNCP3MLYR-N6E 2 (0010)
BUG=b:292461498
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
The patch disables PCH USB2 Phy power gating to fix display flicker
BUG=b:292403156
TEST=Verified on the defeat board
Change-Id: If0c0e655c5d32f39b90635bb3c1d13d8b6993b59
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Update Touchscreen GPIO to use the correct GPIO 90. GPIO 32 was a
copy/paste from dalboz and corresponds to the FP PWR EN on trembyle
platforms.
BUG=b:292656388
TEST=build/boot morphius
Change-Id: Ia6cdbe9195535093e68dbafedaddb70aaf73da88
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76747
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Set the cs_pi_start_high_in_ect if the DUT is using one of the two
following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to
set cs_pi_start_high_in_ect when using these parts will result in an
MRC cache failure and DUT will fail to boot.
BUG=b:292153199
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya
variant to kernel.
Change-Id: I36040139b959c85c3ac220a34574caa12ca6c5fe
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
With currently set default PSP_SOFTFUSE_BITS for phoenix SoC,
the non-serial build does not boot on Myst.
Override PSP_SOFTFUSE_BITS by disabling SPIConfig to also get
the non-serial build booting.
The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA).
BUG=b:292489356
TEST=Flash image-myst.bin, verify that it's able to boot on Myst
proto0.
Change-Id: Id4472fd85fdefcafb8378199dbaa054fab8b3274
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76713
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: Ica3756e117fc58166958f37e7b007abb79d9d350
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76744
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: Ie1d882cac90211541a636d2dab297c343a12d66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76743
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: I61912fd6db9eb4b8d202ab633b8c7ca5913e759f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for redrix board. Please refer Intel doc#723158 for
more information.
BUG=b:292435264
TEST=build and boot redrix
Change-Id: I34d10c763f4710d2c5678704320fd1cc8d8b6287
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76670
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Camera LED will blink several times as sensor is being probed during
kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:292173903
TEST=Build and boot on Yavilly EVT unit. Verify & observe Camera LED
blinking behavior.
Change-Id: Ic3e3439dc9313325189761b277e1a3bd1c1d9418
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the mobile SoCs, SMN_IOHC_MISC_BASE_13B1 is the only IOHC misc base
address, but on for example Genoa it's the address of the IOHC misc base
of the second IOHC. Due to it not being the first one on Genoa, use 13B1
as part of the name instead of using an index of 0 which would look odd
in the Genoa case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1db28ec03a3ba1c2040d8a1500ae17aa9705f6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76756
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
These boards do not actually support RTD3. The power GPIOs for
components are connected to 3.3V and the reset GPIO is connected to
`PLT_RST#`.
Change-Id: Id5e318c388f669d6b2935dc98ae29485955e6e72
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
After switching to S3, it was found that drives on the SATA port do not
exit D3cold on S3 exit. Disable RTD3 on the port until the issue can be
resolved.
Avoids the following error in Linux:
pcieport 0000:00:1d.0: Unable to change power state from D3cold to D0, device inaccessible
Tested on darp8 with a Samsung 970 EVO or Crucial P5 in J_SSD1.
Change-Id: Ib26f59db61acfbf9248cea379c197765d3d9c470
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76593
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the per PCI root IOAPIC is now reported as domain MMIO resource
and the IVRS code now again probes for the IOAPIC resource on the domain
device, the IOAPIC resource doesn't need to be reported as resource of
the northbridge PCI device any more.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8604bd321ec4239076b1be99dca095e47f8b75a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76600
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This reverts commit e33d253793 ("soc/amd/common/block/acpi/ivrs: fix
missing IOAPIC[1] error").
Now that the per PCI root domain IOAPIC MMIO resource is reported on the
domain device, we can again probe the resource on the domain device
instead of the northbridge PCI device in that domain. This will make the
IVRS code compatible again with the work in progress Genoa SoC support.
TEST=Linux doesn't complain about the IOAPIC[1] missing in the IVRS on
Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib861b19d798fc8ee6603e8803d8d1939be08d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76659
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Call read_non_pci_resources from amd_pci_domain_read_resources to tell
the resource allocator about the non-PCI MMIO regions within the data
fabric MMIO regions so that the allocator won't place any PCI MMIO in
the same areas.
TEST=On Mandolin 3 new non-PCI resources get reported to the allocator:
avoid_fixed_resources: DOMAIN: 0000 04 base fd100000 limit fd1fffff mem (fixed)
avoid_fixed_resources: DOMAIN: 0000 05 base fd000000 limit fd0fffff mem (fixed)
avoid_fixed_resources: DOMAIN: 0000 20000120 base fec01000 limit fec01fff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7f69b86e376e3368d4f156ccf93791cc00886489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add the SoC-specific non-PCI MMIO register list. PPR #57254 Rev 1.52 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I29b4ef947776ab8a6c215c1a5204769a9f61e6fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the SoC-specific non-PCI MMIO register list. PPR #57019 Rev 3.05 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f57df6ca09f1583409f6c4e68177b05b9f31def
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76597
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the SoC-specific non-PCI MMIO register list. PPR #57243 Rev 3.02 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c5173e596f3f3f1c63165871178dbbd0e9641be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76596
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the SoC-specific non-PCI MMIO register list. PPR #56569 Rev 3.04 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id99c64c172481984306814980a1ddf0b2d535413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the SoC-specific non-PCI MMIO register list. PPR #55570 Rev 3.18 was
used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7bfcdd9b70b71fe6aedcab3694698967d48e18e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Introduce the common read_non_pci_resources function to read the base
address of the non-PCI resources within the MMIO regions configured in
the data fabric registers and pass that info to the resource allocator.
Each SoC will need to provide implementations for get_iohc_misc_smn_base
and get_iohc_non_pci_mmio_regs in order for read_non_pci_resources to
know the SoC-specific base addresses, register offsets and MMIO region
sizes. In case of SoCs with only one PCI root domain, the domain
parameter of get_iohc_misc_smn_base will be unused, but in the case of
SoCs with more than one PCI root domains, this parameter will be used by
the SoC-specific code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If9aca67fa0f5a0d504371367aaae5908bcb17dd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add bank locator and slot existance to the mainboard code.
TEST: Verified on Linux that all slots show in dmidecode -t 17.
Change-Id: I4ced36e26368d3f99a7341cb55a8deb118b2d1a4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set AllowedSocketsInParallel to 1 for RMT builds.
This help in associating any failures encountered during RMT run
with the corresponding Socket/MC/DIMM.
Intel recommended setting EnforcePopulationPor to 1 for RMT runs
for debugging failures if any.
Change-Id: Ie2301368e9470cc23171c3c4eca9fe978e1513d4
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76679
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.
Add the virtual UART on 0x3f8 as ACPI device.
TEST: Verified on SBP1 that serial still works.
Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add pujjo new supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Hynix H58G56BK7BX068
2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
3. Micron MT62F1G32D2DS-026 WT:B
BUG=b:292452868
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a new variant screebo4es.
The new variant will support only ESx samples. The existing rex
variant will support the QS samples.
BUG=b:292280656
TEST=Able to build google/screebo4es board and boot on target
hardware.
Change-Id: If77b4a773bee3633008d39c1886b61869c9618de
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Do not add type 0x63 entry to amdfw.rom when APOB_NV cache is disabled.
BUG=b:290763369
TEST=boot birman multiple times with/without APOB_NV cache enabled
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iefe6f56d7dbedd289680f25a5f372eaa12e967b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76568
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable the APOB cache for only Myst, and re-enable APOB for other
Phoenix SOC mainboards.
BUG=b:290763369
TEST=verify APOB cache is disabled
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add Kconfig option to disable the non-volatile APOB cache for a
mainboard using an SOC that supports APOB.
BUG=b:290763369
TEST=verify APOB cache is disabled when selected
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I0170355bbf29ea6386fa69a318e61f057b9a9a3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76566
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Mapping to the fw_config of AUDIO_AMP in dedede,
and set new AUDIO_AMP configuration of ALC5650 as value 4.
BUG=b:284060672
BRANCH=dedede
TEST=build pass
Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.
On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.
The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).
However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).
Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.
BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.
Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.
BUG=b:268546941
TEST=Verified the settings on google/brya using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:290985698
BRANCH=firmware-volteer-13672.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value
for variants created using google/rex model.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples.
BUG=b:290732344
TEST=Able to build google/rex4es board and boot on target hardware.
Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch creates a rex model so that other variants developed using
`rex` baseboard are easy to land without duplicating the config
selection.
So far, `rex0` and `rex_ec_ish` are developed using the `rex` model.
The plan is to extend the support for `rex4es` and `rex4es_ec_ish`
variants.
TEST=Able to build and boot google/rex.
Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
acpi.c contains architectural specific things like IOAPIC, legacy IRQ,
DMAR, HPET, ... all which require the presence of architectural headers.
Instead of littering the code with #if ENV_X86 move the functions to
different compilation units.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
With arm64 -Wstack-usage= is enabled which is triggered on any use of
alloca(). Since this function basically works on x86 without wrecking
things and causing massive stack consumption it's unlikely to cause
problems on arm64.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76007
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
SoC family is able to provide SoC-specific information
via amd/fsp/<soc_family>/soc_dmi_info.h.
Use common amd/fsp/common/dmi_info.h for all AMD platforms.
This way, duplicated dmi_info.h files in
vendorcode/amd/fsp/<soc_family>/ can be removed.
BUG=b:288520486
TEST=Dump `dmidecode -t 17`.
Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76107
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AGESA S3 restore needs to occur before SMM finalization/locking,
but it's a crapshoot as to which runs first since both use the same
BS_OS_RESUME/BS_ON_ENTRY boot state callback, and there's no way
to prioritize/force ordering.
To work around this, move the AGESA S3 resume call to the preceding
boot state (BS_OS_RESUME_CHECK) to ensure it runs first, and guard it
to ensure it only runs on the S3 resume path.
BUG=none
TEST=build/boot google/liara, verify S3 resume successful.
Change-Id: I765db140c6708a0b129f79fb7d3dc8a4ab3095bd
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76592
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Follow baseboard Rex to make GPIO changes
BUG=b:286187821
TEST=Ability to enable and disable WIFI function in OS.
Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Add smn_read64 which calls smn_read32 twice to read two adjacent 32 bit
SMN registers and merges the results into a 64 bit value which it then
returns.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2d58ec9818559cbefd7b819ae311ad02fafa18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This supports a brand new I2C driver that is designed specifically
for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU
is an i2c-compatible interface, but AFAIK only Link has touch devices
attached in this way.
On Windows, the PCIe device for the IGP is owned by the Intel
proprietary driver, hence a separate ACPI device has to be added for
the I2C driver arbitrator to attach to. The MMIO method is used instead
of _CRS so that Windows does not try to assign ownership of the
resource to our device (even though we're using the MMIO registers at
the same time as the IGP driver).
Even though in theory 2 drivers accessing the same MMIO may cause
problems, in testing, there has been no issues with
sleep/wake/hibernate, updating/installing/uninstalling the IGP driver,
or changing display resolutions with the i2c driver attached.
The arbitrator is necessary as well, since even though there are
multiple i2c buses, the MMIO registers are shared. Hence a shared lock
is required for i2c access across the buses.
The original Sleep Button devices are preserved for Linux due to the
completely custom and non-standard implementation of the Windows driver
in order to work around the non-standard nature of Link's hardware.
Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Now that we have x86 architecture specific VGA_MMIO_* defines in
arch/vga.h, use those instead of having SoC-specific defines for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77b914d563bdc83e7fad7d7fccd5cf7777cb4918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.
As no AMD platform has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table in such a way that it prevents Linux from using PCIe ECAM. This
change fixes that problem.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to reduce S0ix resume time, decrease stop_delay_ms from
300ms to 200ms for Goodix GT7996F. The value source is from
https://partnerissuetracker.corp.google.com/issues/285999032#comment16.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
There is a problem of screen shake on the old panel[1]. So increase the
panel GOP component pull-down circuit size in hardware, and update the
initialization code at the same time. The new initialization code is
mainly adjusted for GOP timing. When Display sleep in, raise all GOP
signals to VGHO and then drop to GND. In order to be consistent with
the current panel model, let's rename this file.
[1]: INX old panel product number is HJ110IZ-01A-B1, and the new
panel product number is HJ110IZ-01A-B2. We have recalled the shipment
old panel.
BUG=b:270276344
BRANCH=trogdor
TEST= test firmware display pass
Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch updates the Type-C USB2/3 port mapping to reflect the mux
connection change as mentioned in previous patch
commit ee3f796200 (mb/google/rex/var/ovis: Fix mux
change as per schematics).
Here is the correct port mapping after considering the mux swap:
+--------------------------------+-------------+---------------+
| TCSS-USB Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
+------------------+-------------+-------------+---------------+
BUG=b:289300284
TEST=Able to build and boot google/ovis to get display over Type-C1
and Type-C2 port.
Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Patch to increase CONSOLE_CBMEM_BUFFER_SIZE to contain FSP debug serial log.
The existing implementation uses larger cbmem size irrespective of FSP debug is enabled or
not. Ideally. larger cbmem size is required only if FSP debug is enabled.
Bug=b:284124701
TEST=Able to build and boot google/marasov.
Change-Id: I9a9e660f2738813808e0dd65d2783424b49f9a5e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reduces the CAR (Cache-as-RAM) variable usage while using FSP debug binaries, which can prevent the CAR from becoming too full and unable
to integrate other CAR global variables.
This change has the following downsides:
- FSP debug output into the cbmem buffer will be partial.
To test this change, you can:
Build and boot google/rex without any function impact with non-serial
and serial FSP debug image (unless what has been documented here).
Bug=b:284124701
TEST=Able to build and boot google/rex.
Change-Id: I16a1aa25fd32327d03a37381a696c86c95014ba0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add and use a define for the total number of P-state MSRs to avoid magic
constants in the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I37a89faa0f216790b3404fc03edc62408684cc24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
There are 8 P-state MSRs and not only 7.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic2899b6e454233c6cbb8fc1e439ff069c4d3d3a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.
BUG=b:284192689
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.
Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.
BUG=b:281643325
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.
Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit provides option for board to set CsPiStartHighinEct
FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field.
BUG=b:279835630
BRANCH=none
TEST=CsPiStartHighinEct UPD is set properly
Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Intel SPR supports up to 64 DIMMs on a 4 socket board.
Bump DIMM_INFO struct to 64 slots to properly present all
of them to the OS.
Change-Id: I52d77c4e9bff96adba6d265a272e0e425dbdb791
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73367
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Disable the CSME by default now that S3 is used instead of S0ix.
The CSME will not go into a low power state during S0ix when it is
disabled. This prevents the CPU from reaching C10 and so increases the
power usage during suspend compared to leaving CSME enabled. (This was
measured to be a ~2W different on TGL-U.) In S3, the state of the CSME
doesn't matter because the CPU will be off.
Change-Id: I88c0aebdcc977f3ba9dd8f46a6abfaa7a4ae8eb6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73354
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
System76 EC since system76/ec@9ac513128a detects if the keyboard is
white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for
the selection and update the ACPI methods for the new functionality.
Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After fixing TPM logs clobbering other regions in CB:73297, S3 no longer
causes cache issues resulting in power off after multiple suspends.
This is required for disabling Intel CSME by default.
Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
The preram TPM log was being copied to the end of the CBMEM TPM log no
matter what the size of the CBMEM TPM log was. Eventually, it would
overwrite anything else in CBMEM beyond the TPM log.
This can currently be reproduced by enabling TPM_MEASURED_BOOT and
performing multiple S3 suspends, as coreboot is incorrectly performing
TPM measurements on S3 resume.
Change-Id: If76299e68eb5ed2ed20c947be35cea46c51fcdec
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73297
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current Sapphire Rapids code assumes that all sockets have working
CPUs. On multi-socket platforms a CPU might be missing or was disabled
due to an error. The variable PlatformData.numofIIO and the variable
SystemStatus.numCpus reflect the working CPUs, but not the actual
socket count.
Update the code to iterate over sockets until PlatformData.numofIIO
IIOs have been found. This is required as FSP doesn't sort IIOs by
working/non working status.
This resolves invalid ACPI table generation and it fixes a crash
as commands were sent to a disabled CPU.
TEST: Disabled Socket1 on IBM/SBP1.
Change-Id: I237b6392764bbdb3b96013f577a10a4394ba9c6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76559
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:290876132
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Change-Id: Id5e0ba7a4ca57e311465ba8e74105f5ee7b8ee8a
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76435
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the actual SocketID instead of the running index.
Change-Id: I9128909756d0dbb0c4dabc52acdc98cb2a4f7baa
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The comment is only true if all sockets have working CPUs installed.
Change-Id: I8c3376c9233c33fb770082573e07e9d96abb7855
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76557
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a function to check if the CPU placed at the specified socket was
found usable during QPI init. This is useful for multi-socket
platforms were a CPU is missing or has been disabled due to an error.
Change-Id: I135968fcc905928b9bc6511e3ddbd7d12bad0096
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use the FSP define to iterate over all sockets as the runtime value of
numofIIO is the detected number of sockets, not the highest working
socket.
This fixes printing the HOB on multi-socket platforms where a CPU has
been removed or has been disabled (4S system running as 3S).
Change-Id: Ieed67cd48d26c7634636c0aae6a56f3b6fbdf640
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76492
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by
P2SB on IOE/SOC die.
So this patch does:
1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB
2. Include pcie_clk.asl
3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H.
BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled.
Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it
needs PMC IPC cmd to turn on/off the corresponding clock.
Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on
IOE or SoC die.
BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard pcie port doesn't block S0ix with RTD3 cold enabled.
Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes the ioe_pcr.asl file as Intel Meteor Lake has
support for IOE die.
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: Ia534dbc0db5e54e173da9cdf475a7eb2bfda9e2f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76410
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
