Commit Graph

1779 Commits

Author SHA1 Message Date
Kyösti Mälkki 82fbda76c9 AGESA: Use same HeapManager for all BiosCallOuts
We do not allow platforms to mess around with memory layout.

Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:22:44 +01:00
Kyösti Mälkki 0127c6c808 AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
Make the build tolerate re-definitions.

Change-Id: Ia7505837c70b1f749262508b26576e95c7865576
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8609
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:22:20 +01:00
Patrick Georgi a425b96091 AMD Fam10h: Only create _PR scope if it is filled in
The former pstates_algorithm() function has two early exit
points now, and so it might never get around to writing
pstates data.

Change-Id: I19ca937375c6d33b78bd5b1859fa5c25473be9b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8610
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-06 22:30:13 +01:00
Patrick Georgi aab66b1dc7 AMD Fam10h: sanity check some CPU data
If a certain register returns crap values, we
determine core_power using an uninitialized variable.
That doesn't sound healthy.

Change-Id: I1e890b78bfcc3bf0255a3d4f6561a783134b1719
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8508
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-05 20:57:33 +01:00
Timothy Pearson a89accd74f cpu/amd/model_10xxx: Documentation update
Change-Id: Ic29009be42ef77261a3b535327cf5c12761023c1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:16:22 +01:00
Timothy Pearson ead8751367 cpu/amd/model_10xxx: Refactor model detection to reduce code duplication
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.

Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:15:55 +01:00
Alexandru Gagniuc 5818da262d cpu/intel: (non-FSP) Remove microcode updates from tree
Now that we use the microcode updates in the blobs repository, remove
them from the main repo. Since the microcode updates are blobs, it
makes more sense to ship them in the blobs repo rather than the main
one.

The update-microcodes.sh script is also deleted, as a more current
version resides in 3rdparty.

Change-Id: Iee74a3ede3b5eb684ef0386d270120e70173c1b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4531
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28 08:21:15 +01:00
Alexandru Gagniuc ee89435798 cpu/intel (non-FSP): Use microcode from blobs repository
Now that microcode has been added to blobs, use that one instead of
the one included in the tree. Microcode from the tree will be
removed in a subsequent patch. Since the microcode updates are blobs,
they belong in the blobs repository.

This change may introduce a build failure if the "Generate from tree"
microcode option is selected, but the blobs repository is not
enabled. We have to live with this for now, until microcode is moved
to blobs for all CPUs, at which point we may adjust Kconfig
accordingly.

Leave the FSP  cpu alone for now, as that will need approval from
SAGE.

Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28 00:14:49 +01:00
Patrick Georgi 477b4c539a AMD Fam10h: Don't write uninitialized data into ACPI
The goto statement skipped all the code that is necessary
to fill in the data structures that are read right after
the jump.

Since there doesn't seem to be useful data, why write these
ACPI objects in the first place?

Change-Id: I1d06c11a7a31517b81e54159355d5c27e3cc3735
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 20:33:45 +01:00
Dave Frodin b85656f285 cpu/amd/agesa: Use alloc_cbmem() only in ramstage
This copies a change made in commit 1cc3338 that allows alloc_cbmem()
to be called only in ramstage. This will allow the */cpu/amd/agesa/*
field to be removed from the list of illegal_globals EXCLUDE_FILEs.

TEST: Booted the amd/parmer board.

Change-Id: I2d4b5352815aae090ffce7b83e487f7c0a4d0c88
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-23 10:39:39 +01:00
Dave Frodin 1cc3338c1d cpu/amd/pi: Use alloc_cbmem() only in ramstage
Without this change the builder would fail with the complaint
that there was a global static variable in romstage. alloc_cbmem()
is only called in ramstage. The alternative was to add
*/cpu/amd/pi/*.romstage.o to the list of illegal_globals
EXCLUDE_FILEs in arch/x86/init/romstage.ld.

TEST: Booted the amd/lamar board.

Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21 00:27:17 +01:00
Bruce Griffith fa0ab8cfc2 AMD Bald Eagle: Add CPU subdirectory files for new AMD processor
This adds the AMD Family 15h model 30 CPU.
S3 suspend/resume currently is not supported.

Tested on the amd/lamar platform.

Change-Id: Ifef55747a5d715b17937fc75ab9d35945b59f0e6
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21 00:24:44 +01:00
Alexandru Gagniuc e5ccbfd290 cpu/allwinner/a10/twi.c: Refactor I²C handler to use i2c_seg API
The coreboot I²C API was completely reworked in commit
* cdb61a6 i2c: Replace the i2c API.

For the allwinner I²C driver, wrappers to the old API were provided
on a "best guess" basis. Replace these wrappers with proper
transaction handling based on the i2c_seg API.

Change-Id: Ibdda3b022ce4876deb2906e17a5a0ca9e939aada
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8431
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-20 23:24:17 +01:00
Kyösti Mälkki f5e7fa22e7 AMD amdfam10: Always have HT3_SUPPORT
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:43 +01:00
Dave Frodin 891f71a541 amd/00730F01: Move SteppeEagle specific settings to northbridge
These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.

Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-18 18:55:56 +01:00
Alexander Couzens 452efc23b9 cpu/intel/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1
They seem to have been copy-pasted during the backport from sandybridge.

Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8295
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-18 12:40:31 +01:00
Timothy Pearson a2f79d5971 cpu/amd/model_10xxx: Add monotonic timer support
Change-Id: Idf37d51c6b53ae85dc96fb609531ceda06ec948c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8470
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-18 01:26:51 +01:00
Timothy Pearson 033bb4bc8d acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9.  The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.

The modified code will function with up to 99 cores.

Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16 21:02:30 +01:00
Alexandru Gagniuc 4b10dec1a6 cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM
The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions

However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.

Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.

Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 22:54:01 +01:00
Nicolas Reinecke 0908839323 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id
Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8355
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:44 +01:00
Timothy Pearson 6fdb4d5d3c amd/amdfam10: Fix incorrect core count identification
The core count identification code in the PowerNow! _PSS
ACPI object generation code was incorrectly copied from the
model_fxx code.  This code has been rewritten to properly
return the number of cores installed in the system.

Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8421
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:10 +01:00
Nicolas Reinecke fa0b3c8cdd cpu/amd/model_10xxx: update microcode
microcode updates are extracted from: www.amd64.org/microcode.html
Mircocode versions of 1020h and 1022h are more recent in coreboot
than inside the AMD archive.

Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8354
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:41:33 +01:00
Alexander Couzens f251a6d7d4 cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.

Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:58:06 +01:00
Timothy Pearson c1f47c1460 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
Fix a mistake that led to an invalid 0ms latency in the automatically
generated PowerNow! ACPI _PSS objects.

TEST: Booted FreeBSD and Linux and verified correct latency values.

Found-by: Coverity Scan
Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8376
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-10 07:26:32 +01:00
Martin Roth 582b2aee0f FSP & CBMEM: Fix broken cbmem CAR transition.
1) Save the pointer to the FSP HOB list to low memory at address 0x614.

This is the same location as CBMEM_RESUME_BACKUP - the two aren't used
in the same platform, so overlapping should be OK.  I didn't see any
documentation that actually said that this location was free to use, and
didn't need to be restored after use in S3 resume, but it looks like
the DOS boot vector gets loaded juat above this location, so it SHOULD
be ok.  The alternative is to copy the memory out and store it in cbmem
until we're ready to restore it.

2) When a request for the pointer to a CAR variable comes in, pass back
the location inside the FSP hob structure.

3) Skip the memcopy of the CAR Data.   The CAR variables do not
get transitioned back into cbmem, but used out of the HOB structure.

4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.

Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8196
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 00:53:13 +01:00
Kyösti Mälkki 08e39c572f AMD K8: Remove some excessive preprocessor use
Tests on CPUID are valid regardless of revision.

Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:20:42 +01:00
Kyösti Mälkki 1608f3651f cpu/amd (non-AGESA): Remove terminator from microcode blob
Change-Id: I6370e971922dee5e8d476a883c5f0f32fbbc8911
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:52:12 +01:00
Kyösti Mälkki d15cb519ad amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selection
Include microcode updates in CBFS for every CPU revision the platform
can support, as changing to different CPU revision should not require
a coreboot rebuild.

This increases CBFS usage from 2 kB to 14 kB.

Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4521
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-02-03 04:52:00 +01:00
Kyösti Mälkki 5fe1fb7a5f cpu/amd (non-AGESA): Load microcode updates from CBFS
Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4502
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:52 +01:00
Alexandru Gagniuc 893b81f79f cpu/amd/model_10xxx: Remove UPDATE_CPU_MICROCODE option
This option is now deperecated by loading microcode updates from cbfs.
Remove this option in anticipation of implementing CBFS loading for
AMD cpus. Removing it beforehand results in less patch overhead.

Change-Id: Ibdef7843db686734e2b6b1568692720fb543b240
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:43 +01:00
Timothy Pearson 9c8106696e cpu/amd (non-AGESA): Fix AP crash during microcode version lookup
Move mapping tables to struct and prevent OOB array
access that was crashing the APs during CAR initialization.

Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-31 21:33:10 +01:00
Timothy Pearson 0d7f8d0b79 amd/amdfam10: Update name table with Opteron 2400/8400 series codes
Change-Id: I52587c0c0dffd814d39087475b8f14c500a68933
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8309
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-31 21:32:25 +01:00
Nicolas Reinecke 5e03170541 intel/model_2065x: update microcode
Change-Id: I6c13518d2217bc823d409ab800bca011e76e9f25
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8277
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:21:15 +01:00
Timothy Pearson 6300b03414 amd/amdfam10: Add runtime ACPI _PSS generation
Skeleton and ACPI generator interface taken from
model_fxx powernow_acpi.c
Small portions of FIDVID MSR code taken from
model_10xxx fidvid.c

Nearly completely rewritten for the P-state-based K10 CPU

TEST: KFSN4-DRE with dual Opteron 8356 CPUs
Verified CPU per-core dynamic state change with system load
Verified reported P-state count and frequencies
Stress-tested each CPU (all cores simultaneously) to verify
proper P0 transition and configuration.

Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8284
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:58:36 +01:00
Kyösti Mälkki ae98e83eb2 CBMEM: Always use DYNAMIC_CBMEM
Drop the implementation of statically allocated high memory
region for CBMEM. There is no longer the need to explicitly
select DYNAMIC_CBMEM, it is the only remaining choice.

Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:54:32 +01:00
Kyösti Mälkki f1e3c763b3 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.

TODO: Check TSEG alignment, it used for MTRR programming.

Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:48:06 +01:00
Kyösti Mälkki 91fac61240 CBMEM: Tidy up CAR migration
Move the  CAR migration call to arch -specific part of CBMEM init,
it is truly a x86 specific thing.

Change-Id: I715417e54f197b8745e0670d6b900a5660178141
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7860
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:47:35 +01:00
Kyösti Mälkki e45542580c CBMEM console: Fix CAR migration step
With the change it becomes irrelevant if memcpy() car.global_data or
cbmemc_reinit() is done first.

Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8032
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:42:10 +01:00
Stefan Reinauer 77b1655d9b vboot2: add verstage
This reverts the revert commit 5780d6f387
and fixes the build issue that cuased it to be reverted.

Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains,
compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the
boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with
verstage_.

TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none

Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>

(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf
Reviewed-on: http://review.coreboot.org/8224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27 01:41:40 +01:00
Kyösti Mälkki 78c5d584a0 ACPI: Add acpi_is_wakeup_s3() for romstage
This replaces acpi_is_wakeup_early().

Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8187
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10 13:53:51 +01:00
Kyösti Mälkki dc357566ea cpu/amd/pi: Use acpi_is_wakeup()
Propagate commit 9107e53 from amd/agesa and fix some
related #includes under cpu/amd/pi.

Change test to return true on S2 wakeup too. In S2 CPU would
have been powered down so MTRR recovery is required.

Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8171
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09 11:01:19 +01:00
David Hendricks bb0d5ef97a x86: Initialize drivers in SMM context if needed
This adds a block in the SMI handler to call init functions for
drivers which may be used in SMM. A static variable is used to
ensure the init functions are only called once.

BUG=chrome-os-partner:29580
BRANCH=mccloud
TEST=Built and booted on mccloud, system no longer hangs when
pressing power button at the dev mode screen. Also tested on parrot.

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee
Original-Reviewed-on: https://chromium-review.googlesource.com/204764
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861
Reviewed-on: http://review.coreboot.org/8134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:44:57 +01:00
Stefan Reinauer 5491ca23fc cpu: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the cpu code to use printk() on all non-ROMCC
boards.

Change-Id: I233c53300f9a74bce4b828fc4074501a77f7b593
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8114
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:16:20 +01:00
Martin Roth 32bc6b6b84 doxygen fixes: fix parameter names to match the functions
The doxygen parameter names in the comments no longer matched the
functions they were attached to.  Doxygen complains about extra
parameter comments and uncommented parameters in the functions.

Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8101
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:32:37 +01:00
Nicolas Reinecke dafa12adfc intel/model_206ax: update microcode
tested on ivy and sandy (t520/t420s & t530)

Change-Id: Ie527e8c4804821764ecc42f7495573eff67828f7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7976
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03 20:11:32 +01:00
Kyösti Mälkki a38d1b2795 ARMv7: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:07:22 +01:00
Kyösti Mälkki 22261c387e allwinner/a10: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: Iadaab225fea04b455c559c25b918a2a842b9faca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8029
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-02 21:52:15 +01:00
Kyösti Mälkki bae775a4f4 arch/x86: Declare GDT symbols and move_gdt()
We relocate GDT to CBMEM, this can be done late in ramstage.
Note: We currently do this for BSP CPU only.

Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 09:51:50 +01:00
Julius Werner 37d7ac8b5b i2c: Add software_i2c driver for I2C debugging and emulation
This patch adds I2C emulation in software through raw toggling of the
SDA/SCL lines. Platforms need to provide bindings to toggle their
respective I2C busses for this to work (e.g. by pinmuxing them as GPIOs,
currently only enabled for Tegra).

This is mostly useful as a debugging feature, to drive unusual states on
a bus and closely monitor the device output without the need of a bus
analyzer. It provides a few functions to "wedge" an I2C bus by aborting
a transaction at certain points, which can be used to test if a system
can correctly recover from an ill-timed reboot. However, it can also
dynamically replace the existing I2C transfer functions and drive
some/all I2C transfers on the system, which might be useful if a driver
for the actual I2C controller hardware is not (yet) available.

Based on original code by Doug Anderson <dianders@chromium.org> and
Hung-ying Tyan <tyanh@chromium.org> for the ChromeOS embedded
controller project.

BRANCH=None
BUG=chrome-os-partner:28323
TEST=Spread tegra_software_i2c_init()/tegra_software_i2c_disable()
through the code and see that everything still works.

Original-Change-Id: I9ee7ccbd1efb38206669a35d0c3318af16f8be63
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/198791
Original-Reviewed-by: Doug Anderson <dianders@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 8f71503dbbd74c5298e90e2163b67d4efe3e89db)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id6c5f75bb5baaabd62b6b1fc26c2c71d9f1ce682
Reviewed-on: http://review.coreboot.org/7947
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-30 22:07:42 +01:00
Vadim Bendebury 0b341b341d ipq/arm: Redesign hooks for bootblock
The following patches had to be squashed
to properly build all the different ARM boards.

ipq8064: storm: re-arrange bootblock initialization

The recent addition of the storm bootblock initialization broke
compilation of Exynos platforms. The SOC specific code needs to be
kept in the respective source files, not in the common CPU code.

As of now coreboot does not provide a separate SOC initialization API.
In general it makes sense to invoke SOC initialization from the board
initialization code, as the board knows what SOC it is running on.

Presently all what's need initialization on 8064 is the timer. This
patch adds the SOC initialization framework for 8064 and moves there
the related code.

BUG=chrome-os-partner:27784
TEST=manual
  . nyan_big, peach_pit, and storm targets build fine now.

Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197835
(cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

arm: Redesign mainboard and SoC hooks for bootblock

This patch makes some slight changes to the way bootblock_cpu_init() and
bootblock_mainboard_init() are used on ARM. Experience has shown that
nearly every board needs either one or both of these hooks, so having
explicit Kconfigs for them has become unwieldy. Instead, this patch
implements them as a weak symbol that can be overridden by mainboard/SoC
code, as the more recent arm64_soc_init() is also doing.

Since the whole concept of a single "CPU" on ARM systems has kinda died
out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had
already been done on Storm/ipq806x, which is now adjusted to directly
use the generic hook.) Also add a proper license header to
bootblock_common.h that was somehow missing.

Leaving non-ARM32 architectures out for now, since they are still using
the really old and weird x86 model of directly including a file. These
architectures should also eventually be aligned with the cleaner ARM32
model as they mature.

BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Storm and confirmed in the
disassembly that bootblock_soc_init() is still compiled in and called
right before the (now no-op) bootblock_mainboard_init().

Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57
Reviewed-on: http://review.coreboot.org/7879
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 20:05:04 +01:00
Kyösti Mälkki 87accccdc2 CBMEM: Always build for x86 romstage
Always build CBMEM for romstage, even for boards that will not use it.
We further restrict car_migrate_variables() runs to non-ROMCC boards without
BROKEN_CAR_MIGRATE.

This fixes regression of commit 71b21455 that broke CBMEM console support
for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME.

Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7877
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 17:47:22 +01:00
Kyösti Mälkki 773485b892 intel CAR: Fix DCACHE_RAM_BASE for old sockets
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.

The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.

Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 10:21:43 +01:00
Kyösti Mälkki 78c622443e intel: Fix microcode alignment
CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable
CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS.

Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only
used with PLATFORM_FSP.

CPU_MICROCODE_CBFS_LEN was no longer used at all.

Change-Id: I0454397924d2526d97b1f095cc371ba962873c99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7957
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-28 19:57:37 +01:00
Kyösti Mälkki 94e796aae6 AGESA fam15: Unify agesawrapper
Disable TSC output for now.

Change-Id: I078b4f0170aaf0ada58e464cf609c234204f8196
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7822
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:24:41 +01:00
Kyösti Mälkki 4a08e15086 AGESA fam14: Add amd_initenv()
Not part of wrapper to AGESA, but workaround for enable_resources().
Also remove remains of comments in non-fam14 wrappers.

Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7816
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:18:35 +01:00
Kyösti Mälkki 48518f0d60 AGESA: Add amd_initcpuio() and amd_initmmio()
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().

Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:18:00 +01:00
Edward O'Callaghan 569bd3ff60 cpu/armltd/cortex-a9: Remove stub func dead code
Change-Id: Ia8246e2bdf346883072a924d8808f14f48d44bb3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7351
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-19 22:32:13 +01:00
Kyösti Mälkki 3165c46f45 intel/truxton: Add dummy cache-as-ram region
Board has no chance of working without a cache_as_ram.inc, but without
a specified CAR region we also break builds.

Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7863
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-19 19:48:40 +01:00
Alexander Couzens 8c53b751f5 arm/ti/am335x: use new arm bootblock infrastructure
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
changes config flags for cpu and mainboard bootblock initialization.
Tested on beaglebone black.

Change-Id: I70cbe3abad8443c5dc71c8ba76a35973a5284477
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7189
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-12-19 19:37:14 +01:00
Kyösti Mälkki 450335918c AMD amdfam10: Drop EXT_CONF_SUPPORT
Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690.

Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7809
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 19:28:11 +01:00
Kyösti Mälkki ac7402dc11 AGESA fam12 fam14: Drop EXT_CONF_SUPPORT
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped
from other AGESA families.

Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 19:28:00 +01:00
Kyösti Mälkki 2fa088be40 AMD binaryPI: Drop EXT_CONF_SUPPORT
Change-Id: I2ec08df2eb8e65bc759de9917894df9d0c8b1995
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7807
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 19:27:50 +01:00
Stefan Reinauer 46c85d7dfb Drop SC520 and related boards
There is no Cache As Ram for these boards, let's get rid of them.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Ia70befc59708c360ad02ed7e3a49d3b0f95dc707
Reviewed-on: http://review.coreboot.org/7119
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-16 21:18:43 +01:00
Stefan Reinauer b59c5de056 Drop GX1, CS5330 and related boards
There is no Cache As Ram for these boards, let's get rid of them.

Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7117
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-16 21:17:36 +01:00
Kyösti Mälkki 13a845acb3 Intel FSP: Move to DYNAMIC_CBMEM
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT
is not enough to disable CBMEM console for romstage on these platforms.

To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy.

Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16 20:40:41 +01:00
Gabe Black cdb61a6f5d i2c: Replace the i2c API.
The new API is in use in depthcharge and is based around the "i2c_transfer"
function instead of i2c_read and i2c_write. The new function takes an array of
i2c_seg structures which represent each portion of the transfer after a start
bit and before the stop bit. If there's more than one segment, they're
seperated by repeated starts.

Some wrapper functions have also been added which make certain common
operations easy. These include reading or writing a byte from a register or
reading or writing a blob of raw data. The i2c device drivers generally use
these wrappers but can call the i2c_transfer function directly if the need
something different.

The tegra i2c driver was very similar to the one in depthcharge and was simple
to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and
replace the ones in coreboot. The Exynos 5420 driver was ported from the high
speed portion of the one in coreboot and was straightforward to port back. The
low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot
and were replaced with the depthcharge implementation.

BUG=None
TEST=Built and booted on nyan with and without EFS. Built and booted on, pit
and daisy.
BRANCH=None

Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193561
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe)

This cherry-pick required additional changes to the following:
src/cpu/allwinner/a10/twi.c
src/drivers/xpowers/axp209/axp209.c

Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7
Reviewed-on: http://review.coreboot.org/7751
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-16 00:02:43 +01:00
David Hendricks be6f8cb0f0 x86: Set BOOT_MEDIA_SPI_BUS
BOOT_MEDIA_SPI_BUS is a Kconfig variable used on some ARM-based
platforms to set up CBFS media. It turns out it can also be helpful
for setting up the eventlog which is intended to reside on the same
SPI flash as CBFS. Setting it for x86 will allow us to remove an
assumption about which SPI bus is used for this flash device.

Long term this can go away as we come up with a better abstraction
for the eventlog's backing store. This is only intended to help us
get from here to there.

BUG=none
BRANCH=none
TEST=built and booted on Link
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I1d84dc28592fbece33a70167be59e83bca9cd7bc
Original-Reviewed-on: https://chromium-review.googlesource.com/191202
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 200aa7c5b1b1f4c74412893cf7231a12e2702463)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If988bcff5244ec6a82580203471b25fac49c45ef
Reviewed-on: http://review.coreboot.org/7752
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-12-15 23:59:00 +01:00
Scott Duplichan f454ac82e6 AMD model fxx powernow_acpi.c: Fix incorrect loop count
powernow_acpi.c array TDP has 20 entries, yet the loop that reads it
processes 21 entries. This causes a gcc 4.9.2 build failure. Limit
processing to 20 entries.

Change-Id: Ice173b276293184386cd8943a3213f3154f86458
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/7791
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-13 18:48:39 +01:00
Edward O'Callaghan 5d0601767f vendorcode/amd/agesa/fam10: Build as a static library
Following the same reasoning as commit
 ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

Change-Id: I8fbb318daacf64a14a71022705eb040a01c34fa8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7699
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-08 06:24:18 +01:00
Alexandru Gagniuc 45b64fbf9d vendorcode/amd/agesa: Remove unused helper.c file
The contents of these files were guarded by a check for the _MSC_VER
macro, which we don't use.

Change-Id: Ic595c8e6284c54e1449cf21e0cebee8c9ce7c682
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7670
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-06 17:09:06 +01:00
Martin Roth e10108a669 FSP platform microcode: Update to remove Kconfig variable
Move the Kconfig variable into a .h file - this does not need to be
in Kconfig.

Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05 21:40:12 +01:00
Vladimir Serbinenko 24813c1490 i945: Consolidate acpi/platform.asl
Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03 21:02:50 +01:00
Kyösti Mälkki 1aa35c6f6c AGESA: Trace execution with AGESA_EVENTLOG()
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:11:03 +01:00
Kyösti Mälkki b139b5efcc AGESA: Common agesawrapper for S3 resume
Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:10:36 +01:00
Kyösti Mälkki 4ee82c69a2 AGESA fam16kb: Move clearing of NoSnoopEnable bit
Originally from commit 4ca72139 move this code now from
cpu/ to northbridge/.

Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7603
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:09:32 +01:00
Kyösti Mälkki f21c2ac055 AGESA: Use common header for agesawrapper
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7153
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:04:34 +01:00
Alexander Couzens 9b79731dd4 arm/allwinner/a10: use new arm bootblock infrastructure
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
changes config flags for cpu and mainboard bootblock initialization.
Tested on a20/cubieboard2.

Change-Id: I753aa60ff66de9a3352a3a0759e4d0be9d8ae1c7
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7187
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-02 14:18:34 +01:00
Patrick Georgi 546953c0c5 Replace hlt with halt()
There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.

All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).

Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02 10:25:55 +01:00
Patrick Georgi 4f75af9fe2 Unify remaining binutils invocations
No need to pass calls through gcc in one case and
directly to binutils in another. Just always call
binutils.

Change-Id: Icf9660ce40d3c23f96dfab6a73c169ff07d3e42b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7610
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-30 12:20:15 +01:00
Patrick Georgi bd79c5eaf1 Replace hlt() loops with halt()
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:07 +01:00
Edward O'Callaghan eaab6305be cpu/amd/agesa/family15rl: Provide Richland CPU support
Richland -
 Microarchitecture: Piledriver
 Core stepping:     RL-A1
 CPUID:             610F31

Change-Id: I790085fbf36d836c903dcce77d794abb8578712b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7537
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27 11:27:51 +01:00
Patrick Georgi bd79296d34 amd/fam10: Fix pstate configuration
Testing for msr.hi | PS_EN_MASK doesn't make sense.

Change-Id: If3305e4255f227be4bb7a5496a625ef2a50a5808
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7578
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-25 13:04:38 +01:00
Patrick Georgi 95948934e7 build system: unify linker use across gcc and clang
Let's just call ld directly for gcc, too.

Change-Id: I305eb92ed0d21b098134a7eb5a9f9fe3b126aeea
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7553
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-25 08:47:41 +01:00
Patrick Georgi 3ce96bd49c build system: use a single variable name for compiler runtimes
We build with either gcc or clang, no need to keep both around

Change-Id: I9af2cc7636bdc791a68ba8ed6e7c5a81973c5dfd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7552
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-25 08:47:38 +01:00
Patrick Georgi c637a887dd allwinner/a10: fix raminit
gcc 4.8.3 broke on it, and the u-boot code that this was
derived from contains the same change.

Change-Id: I3936567a1bee3eceb469373a81e464b1238fdf9c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7538
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-22 21:04:43 +01:00
Vladimir Serbinenko f8457985d8 amdk8: Move to implicit length patching
Change-Id: I8b4c36adaa7ea791ae1a8f7c0d059b9201b08f94
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7332
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-22 16:58:29 +01:00
Vladimir Serbinenko 2a19fb1d76 amdfam10: Move to per-device ACPI
Change-Id: I9ce2333e1ea527843f83d411dea2a669263156c2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7027
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-22 16:57:07 +01:00
Edward O'Callaghan 25819d357b cpu/amd/agesa/family1{0,2}: Fix init introduction printf output
Presumably this output made sense when the code was first being
developed.

Change-Id: I3380d6996838a9405b324d57ec449830ed88a99a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-22 15:37:52 +01:00
Edward O'Callaghan d7e5008bdf cpu/amd/agesa/family1{0,2}: Fix indent and sync closer together
Change-Id: If1ca90aa8050fc1b2e1c98e0fb669de1d155a949
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7543
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-22 15:37:28 +01:00
Edward O'Callaghan 3b8bfeba43 cpu/amd/agesa/family1*: Use IS_ENABLED() macro
Change-Id: I54d6871597121392625293027a794d52cf28dd4c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7542
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-21 14:07:53 +01:00
Kyösti Mälkki 023ed1f999 amd/olivehillplus: Share agesawrapper header
This interface is common with AMD PI implementations.

Change-Id: Ifabfce97db749e04aa19e53f62216be78158b282
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7150
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
2014-11-20 19:06:26 +01:00
Kyösti Mälkki e4c17ce803 AMD: Isolate AGESA and PI build environments
To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.

Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.

Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
2014-11-20 19:02:37 +01:00
Vladimir Serbinenko 80fb8edaea acpigen: Add and use acpigen_write_method.
The sequence of bytes to create a method is used several times in codebase.
Put it into a function with logical arguments rather than duplicating magic
bytes everywhere.

Change-Id: I0e55d8dc7d5e8e92a521c7a83117c470d0614008
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7347
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19 19:50:51 +01:00
Edward O'Callaghan d6b452f181 cpu/amd/model_10xxx/processor_name.c: Duplicate 'const' specifier
Remove duplicate 'const' declaration specifier.

Change-Id: I27802ce9a8fe799e9187644ebd1fa5924d5e512b
Found-by: Clang
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7446
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-16 09:42:04 +01:00
Aaron Durbin e742dda985 chromeos: provide stub functions for !CONFIG_VBOOT_VERIFY_FIRMWARE
Instead of checking #if CONFIG_VBOOT_VERIFY_FIRMWARE #else #endif
provide empty stub functions for !CONFIG_VBOOT_VERIFY_FIRMWARE.

BUG=none
BRANCH=baytrail
TEST=Built and booted.

Original-Change-Id: Id9d1843a0ec47c5a186c9a22ea3e4c13c89ec379
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/184841
(cherry picked from commit f6d95cf4ba6ce1bc0e1df4a0e9f655ad9fea9feb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If35ace863243e36399fc40c2802a2f7f2711e83b
Reviewed-on: http://review.coreboot.org/7395
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-15 00:39:39 +01:00
Kyösti Mälkki abc083e06b AMD (K8/fam10): Rewrite CAR migration in post_cache_as_ram
Old routine copied all of CAR region as-is right below CONFIG_RAMTOP.
Most of this region was reserved to interleave AP CPU address spaces
and unused on BSP CPU. The only part of CAR region requiring a copy
in RAM is the sysinfo structure.

Improved routine changes this as follows:

A region of size 'backup_size' below CONFIG_RAMTOP is cleared. In
case of S3 resume, OS context from this region is first copied to
high memory (CBMEM_ID_RESUME).

At stack switch, CAR stack is discarded. Top of the stack for BSP
is located at 'CONFIG_RAMTOP - car_size' for the remaining part
of the romstage. This region is part of 'backup_size' and was zeroed
before the switch took place.

Before CAR is torn down the region of CAR_GLOBALS (and CAR_CBMEM),
including the relevant sysinfo data for AP nodes memory training,
is copied at 'CONFIG_RAMTOP - car_size'.

NOTE: While CAR_GLOBAL variables are recovered, there are currently
no means to calculate their offsets in RAM.

NOTE: Boards with multiple CPU packages are likely already broken since

  bbc880ee amdk8/amdfam10: Use CAR_GLOBAL for sysinfo

This moved the copy of sysinfo in RAM from above the stack to below
the stack, but code for AP CPU's was not adjusted accordingly.

Change-Id: Ie45b576aec6a2e006bfcb26b52fdb77c24f72e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4583
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-14 15:44:56 +01:00
Edward O'Callaghan e90080253b cpu/x86/smm/Makefile.inc: Fix up linkage rules
Broken linkage rule for Clang builds on one side of a
branch. Hence refactor out common rules from branch.

Change-Id: I00e5a2f5f9af1b7882a453caebb378ef74d2d51e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7425
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-11 12:34:27 +01:00
Vladimir Serbinenko be0fd0a44f haswell: Move to implicit length patching
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7327
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09 02:01:26 +01:00
Vladimir Serbinenko 226d784377 ibexpeak, bd82x6x: Move to implicit length patching
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7326
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09 02:01:21 +01:00
Vladimir Serbinenko 689ddf6832 fsp_rangeley: Switch to per-device ACPI
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7046
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-08 20:12:31 +01:00
Edward O'Callaghan e81b1f1699 cpu/intel/fsp_model_406dx: Invaild include path
Found-by: Clang
Change-Id: Iac54755caadc3ffbe8a09d40aed8500c2359e829
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7349
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07 09:30:15 +01:00
Edward O'Callaghan 0625a8bcfb {cpu,soc}: Use DEVICE_NOOP macro over dummy symbol
Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7285
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01 21:14:35 +01:00
Damien Zammit 304089b0b7 cpu/intel: Add configuration for socket LGA1155
This allows mainboards to explicitly select LGA1155.

Change-Id: Id33679b27c89038588347cb4f1a6a0e66aae3e6e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7197
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-10-29 21:11:11 +01:00
Edward O'Callaghan 3e72ecfd35 cpu/x86/smm/Makefile.inc: Correct SMM linkage under clang builds
Ensure that the SMM build stage links properly using the compiler-rt
runtime under a Clang build.

Change-Id: Iead28c46d63f5bbb27757b7dc66fe06b4813d03c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6462
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-28 00:40:51 +01:00
Edward O'Callaghan 2c9d2cf75c {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/7146
Tested-by: build bot (Jenkins)
2014-10-27 23:40:05 +01:00
Kyösti Mälkki 29d9c56758 AMD Trinity and Kabini: fix fan control
The fan can stop but can't run again. "AGESA: Call get_bus_conf() just
once" (commit ef40ca57) results to this problem.
This patch can resolve this problem.

Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6981
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-23 19:18:17 +02:00
Vladimir Serbinenko 4743254424 amd: rename model_fxx_powernow to powernow.
Change-Id: Iee581183f9cd9f5fecd5604536b735f6a04a0f93
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7019
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-10-19 10:55:51 +02:00
Kyösti Mälkki 26f297e981 AGESA: Drop board and chipset -specific callout headers
Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7115
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19 06:20:58 +02:00
Kyösti Mälkki 1729cd8574 x86 romstage: Move stack just below RAMTOP
Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.

Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19 06:14:05 +02:00
Kyösti Mälkki d05d0db0d0 haswell baytrail: Enable RELOCATABLE_RAMSTAGE
Change-Id: I84ee953196ae9bed3392c2b9bab2e8d9f0d27908
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7095
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19 06:13:35 +02:00
Ronald G. Minnich 2adb297cf9 uarts: 32/64 cleanup
We had lots of casts that caused warnings when compiling on RISCV.
Clean them up.

Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7066
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16 17:41:14 +02:00
Vladimir Serbinenko 822bc65b0e ACPI: Remove CONFIG_GENERATE_ACPI_TABLES
As currently many systems would be barely functional without ACPI,
always generate ACPI tables if supported.

Change-Id: I372dbd03101030c904dab153552a1291f3b63518
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4609
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-16 12:01:10 +02:00
Isaac Christensen 81f90c58d2 x86/mtrr: Enable MTRR's before enabling caching
Fix up the following commit by enabling the MTRR's before enabling caching.

7756fe7 x86: Minimize work done with the caches disabled in mtrr functions.

Also fix two typos in comments.

Change-Id: If751b815f9dab781fc38c898cf692f0940c57695
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6969
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-09-25 23:24:03 +02:00
Gabe Black 7756fe70eb x86: Minimize work done with the caches disabled in mtrr functions.
The code in src/cpu/x86/mtrr/mtrr.c disables caching in a few places when
changing mtrr settings. While I can't find anything that says that's actually
required, I can believe it's necessary. With that said, other code around the
wrmsr instructions which actually modify the settings should be able to run
with caching enabled with no ill effects.

This is particularly true for two calls to printk, one in the fixed mtrr code
and one in the variable, which could result in an arbitrary amount of work
being done without caching. When changing the implementation of the cbmem
console, these two printks caused a significant regression in boot performance
on link of about 70ms which is about 10% of total firmware boot time. When the
window where the cache is disabled is minimized, both this and the new
implementation were about 30ms faster than the original boot time.

For the variable MTRRs, we now store what we want to set the MSRs to and then
write them all at once at the end of commit_var_mtrrs(). This way we don't
have some set and some not, but we still minimize the time we spend with the
caches disabled.

Change-Id: I5139b262bd2d13f79afd88e2e2c0f514fb3e27c9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/187811
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 31529d6d965676c6cedeb62137eabc26819956fc)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6952
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-24 22:49:45 +02:00
Julius Werner d84afd3e61 arm: Remove CAR_MIGRATE Kconfig and associated cruft
This is essentially a revert of commit 10bd772d. The CAR_MIGRATE
mechanism is only useful to migrate variables from a special region
(e.g. cache as RAM) into DRAM-backed CBMEM between different parts of
the romstage (it does not persist into ramstage). Since ARM devices use
SRAM for which there is no reason to become inaccessible in later parts
of the romstage, this mechanism isn't useful for them. Removing it makes
the romstage.ld script much simpler, which has the nice side-effect of
putting the BSS at the end of the memory image (so that cbfstool can
actually figure out that it doesn't need to be part of the ROM image).

Old-Change-Id: I50e91d8bd51b5deb19446d9da48699edecbef6ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176761
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ebfd698e57c902e2f39a0cfc1bc2b02665e47ec6)

console: Make cbmem depend on x86.

The cbmem implementation isn't supported on anything other than x86 right now
and actually causes memory corruption on ARM machines. Until that's fixed, this
will prevent people from turning it on and causing hard to track down errors.

Old-Change-Id: I00e8aacf008acfe2f76d4eab82570f7c1cc89cab
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191107
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit e54f16e346a7f2c66d802fb78a6b24e53b732b83)

Squashed two related commits for cbmem support on arm.

Change-Id: I2be48cea348ee5dc8ca3632d743500aa111bab08
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6888
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-09-15 17:38:28 +02:00
Paul Menzel 3f0f300bcf cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct comment
Currently there is no way to enable or disable VMX during runtime using
CMOS/NVRAM. It is only possible to configure it during build time by
setting the Kconfig option `CONFIG_ENABLE_VMX`. So update the comment
accordingly.

Change-Id: I4e3294cb39a40cf30d294fd566bc97420592262f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6228
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-12 21:46:07 +02:00
Gabe Black 51edd54738 ARM: Generalize armv7 as arm.
There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.

Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>

ARM: Split out ARMv7 code and make it possible to have other arch versions.

We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.

The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.

Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)

Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.

Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
2014-09-08 18:59:23 +02:00
Bruce Griffith 230fe0ef2f AMD Steppe Eagle: Disable "No Snoop Enable" to stop HDMI audio stutter
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
resolve this issue.  The posted amd_late_init.c northbridge code
is missing a test for Steppe Eagle northbridges.  See coreboot Gerrit
change 3934, commit ID 4ca721399c (AMD Olive Hill: Disable
NoSnoopEnable to fix HDMI audio corruptions with Ubuntu).

Change-Id: I89894d0ce4ad72ea16d61b445edb9e67920bca24
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6822
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-04 12:28:29 +02:00
Bruce Griffith 5888d86868 AMD Steppe Eagle: CPU files for new SoC
Add the CPU files required to support the Steppe Eagle and Mullins
models of Family 16h SoC processors from AMD.  This CPU is based on
the Jaguar core and is similar to Kabini.

Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6679
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2014-08-30 19:15:18 +02:00
Vladimir Serbinenko 309fc4ce8b sandybridge: Add native sandybridge
Change-Id: I1b51310b4387e588c4828563620b0e2770598503
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6753
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-30 18:59:23 +02:00
Hung-Te Lin 22d0ca0ceb armv7: Move Exynos from 'cpu' to 'soc'.
The Exynos family and most ARM products are SoC, not just CPU.

We used to put ARM code in src/cpu to avoid polluting the code base for what was
essentially an experiment at the time. Now that it's past the experimental phase
and we're going to see more SoCs (including intel/baytrail) in coreboot.

Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c
Reviewed-on: https://chromium-review.googlesource.com/170891
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6739
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-26 17:55:18 +02:00
Ronald G. Minnich 9518b56ab0 intel/gma: Clarify code and use dedicated init for Google Peppy
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.

Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.

The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c.  I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.

The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works.  To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.

Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.

Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.

Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
(cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)

snow: Fix a typo in devicetree.cb that was breaking the snow build.

A typo in a recent change broke the snow build.

Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171014
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 154876c126a6690930141df178485658533096d2)

Squashed a fix into the initial patch and updated nehalem/gma.c
to have a non-static gtt_poll.

Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6657
Tested-by: build bot (Jenkins)
2014-08-25 22:36:03 +02:00
Gabe Black 77ffa0d3ad UART 8250: Unconditionally provide register constants and use UART8250 prefix.
The register indexes and bitfield masks were guarded by the UART8250 config
options, but it might be (is) necessary to use them in a driver that is
UART8250 like without actually using the 8250 driver itself. To avoid any name
collision with other drivers, also change the constant prefix from UART_ to
UART8250_.

Change-Id: Ie606d9e0329132961c3004688176204a829569dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171336
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6715
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-25 19:07:04 +02:00
Gabe Black 8b685398a7 ARM: Overhaul the ARM Makefile.
The ARM Makefile was copied from x86 and then modified, and as a result it
was carrying a lot of baggage. On top of that, the extra complication made it
inflexible, and we need a lot of flexiblity in order to support the fact that
the Tegra124 starts on an ARMv4 coprocessor instead of one of the ARMv7 main
CPUs.

Change-Id: Ia6ddc27619bdb51e152ad0c628ad6f3037c103ce
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171017
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 512d942788336c8d52470135b43ee4e6a1c95f6c)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6709
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-22 22:23:11 +02:00
Gabe Black 4f3873d2ce arm: Get rid of the INTERMEDIATE variable used on exynos.
The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
Exynos SOCs, but we can do that directly without having a special hook.

Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170921
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6714
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-21 18:44:56 +02:00
Gabe Black 8128a56c0e trustzone: Pull trustzone init out of cpu.c and do it in romstage.
Trustzone needs to be initialized/disabled both on boot and on wake, so it
needs to be done before ramstage which doesn't run on wake. cpu.c isn't
compiled into romstage and fixing that causes other problems, so the trustzone
functions were split out.

Change-Id: I8fc630237ebec1f02a91600f8baf3d4e9ea66d0e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/169817
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 055ed0e28476123b0bd666109af90baf40aadcee)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6666
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18 19:25:57 +02:00
Julius Werner f0cd03c142 exynos5420: Don't map low addresses that lead nowhere
I just spent half a day (including the time to implement a stack dumper)
to figure out that I am reading from a NULL pointer. A problem this
simple should be more easy to catch. Let's mark the address range below
SRAM as uncached so that the MMU can yell at you right away for being
the bad programmer you are when you access a NULL pointer.

Change-Id: I4a3a13f75bf21b25732be2ecb69d47503eff1b53
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170112
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 7316732ea0ccdc0d607bde81dbb38ca9abd29fa9)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6650
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18 19:04:08 +02:00
Hung-Te Lin 12b121f3fe arm/exynos: Allow releasing UART retention for resume.
The UART / serial console is put in retention state by kernel during suspend /
resume path, which caused Coreboot not able to print any messages during resume.

Sending values to the padret_uart_opt inside PMU may release UART, but that may
also cause unexpected output when kernel is back. However, it's still very
helpful when we are debugging suspend/resume inside Coreboot.

To get UART message on resume, call wakeup_enable_uart() in boot block or
romstage (before console_init).

Change-Id: Ib5759cb402c6e018d9dba14fad8b61f6a1b1a265
Reviewed-on: https://chromium-review.googlesource.com/170440
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 547fbbfe2eeb6da4e161f36be2caf8099f9eac9b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6649
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18 19:03:39 +02:00
Julius Werner 68aef11692 exynos5: Implement support for USB 3.0 DRD PHYs/controllers
This patch adds support for the DesignWare3 USB 3.0 DRD controller and
PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the
Google Snow and Pit boards to turn these controllers on where
applicable.

Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169452
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6642
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-18 19:02:41 +02:00
Stefan Reinauer 9125d88596 console: conditionally include console in bootblock
Right now some console specific objects are included
in the bootblock even if CONFIG_BOOTBLOCK_CONSOLE is
disabled while others are not. Make all of them conditional
and also fix a preprocessor misuse in bootblock_simple.c
and a stray (useless) die() in the Exynos wakeup code that
made inclusion of those files necessary.

Change-Id: Ia7f9d17654466f199b0e13afbdc9e14c9706530f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168772
Reviewed-by: David Hendrix <dhendrix@chromium.org>
(cherry picked from commit 855da1f07b52898c7edcaffe5baabe9d485bbd83)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6637
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-18 19:02:11 +02:00
Martin Roth 9ff030fb25 cpu/intel/fsp_model_406dx: code cleanup
Code cleanup requested in commit 09670265 -
"cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)"

- add guard statements to chip.h
- remove excessive includes
- whitespace cleanup
- add an IS_ENABLED

Change-Id: Iaa85bd66953df015f083b23f6fd32949bcfd17bc
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6599
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-18 02:22:09 +02:00
Patrick Georgi 905e6f2b56 exynos5xx0: rename local "main" variable
Change-Id: I9a454c88c65e4e70d351f1ec781e75ba400ceb29
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6664
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-16 08:35:08 +02:00
Stefan Reinauer 6ada053709 Exynos: de-duplicate mct timer initialization
timer initialization is the first thing happening in
the Exynos CPU's bootblock code. Hence we don't need
to keep track of it in several places, and we don't
need to do it over and over again (e.g. in each stage)

Change-Id: I7bd9a0b7930fc9c37faabd62e3eecc3e5614a879
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168994
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 5a95bc2bcab5a92c5e6c144005861bf731f59de3)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6638
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14 20:02:36 +02:00
Stefan Reinauer 8f993784ef ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM

Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix@chromium.org>
Tested-by: David Hendrix <dhendrix@chromium.org>
(cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14 01:43:57 +02:00
Julius Werner fa938c7508 exynos5: Refactor crazy old U-Boot base address macros away
All this samsung_get_base_address_of_device_with_a_really_long_name()
boilerplate makes my eyes bleed... I think there are so much cleaner
ways to do this. Unfortunately changing this ends up touching nearly
every Exynos5 file, but I hope you agree that it's worth it (and the
sooner we get it over with, the better... I can't bring myself to make
another device fit into that ugly scheme).

This also removes the redundant EXYNOS5 base address definitions from
the 5420 directory when there are EXYNOS5420 ones, to avoid complete
confusion. The new scheme tries to use EXYNOS5 for base addresses and
exynos5 for types that are common between the two processors, and
EXYNOS5420/exynos5420 for things that have changes (although I probably
didn't catch all differences).

Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167579
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6632
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-14 01:43:11 +02:00
Stefan Reinauer 755615a123 exynos5420: Enable relocatable module support
Since we're now supporting ARMv7 relocations, we can enable
rmodule support on Exynos 5420. This does not automatically
enable relocatable ramstage.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: Ic3af1eabb3b816944587a46409224f778d941b8a
Reviewed-on: https://chromium-review.googlesource.com/167403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 7b5afef4ee87fc3245ec887dfda873c529d8d04d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6629
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-13 22:30:18 +02:00
David Hendricks 5a0fdb4565 exynos5420: minor clean-up memory related stuff
This cleans up a few minor things (mostly #defines) of the memory code
for exynos5420, pit, and kirby. Specifically:

- CONCONTROL.empty is read-only, so don't try to set it and also
  get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define.
- MEMBASECONFIG* overlaps members of the mem_timings struct and
  are mainboard-dependent anyway, so get rid of 'em.
- DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may
  have been deprecated.
- Same with TIMING* #defines.
- Clarify DDR_MODE_* usage and use mem->mem_type when appropriate.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17
Reviewed-on: https://chromium-review.googlesource.com/167500
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12 22:20:23 +02:00
David Hendricks 122b6d6ce6 exynos5420/pit: re-factor membaseconfig0/1 usage
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)

exynos5420: necessary updates for DRAM

This updates DRAM usage for Exynos5420 so that we can actually
use 3.5GB:

- Memory chips used with Exynos5420 may have 16 row address lines.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)

Squashed two related commits.

Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12 22:19:27 +02:00
David Hendricks 72a4288650 exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420
This changes the number of chip selects that we configure from 2 to 1.
On current setups with (x16 memory 4Gbit chips) that means that we're
at 2GByte.

Technically we should add a second setting in the ares_ddr3_timings
and select between the two of the based on board strappings.  That
would make the CONFIG_RUN_TIME_BANK_NUMBER work properly.  I've
changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not
actually doing the board strapping read right now.

This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G
systems will no longer put the system in a messed up state (leading to
a hang).  It also prevents some of the weird boot behavior that we've
seen that comes and goes depending on U-Boot alignment.  See
<http://crosbug.com/p/20577>.

This patch was ported from: https://gerrit.chromium.org/gerrit/66117
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d
Reviewed-on: https://chromium-review.googlesource.com/167210
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6612
Tested-by: build bot (Jenkins)
2014-08-12 22:18:53 +02:00
David Hendricks 42b1b8069c Exynos5420: ddr3: fine tuning the DDR3 timing values
Fine tuning DDR timings value for better stability

* Changed Data Driver Strength from 34 ohms to 30 ohms, expected to
  enhance signal integrity.
* Changed DQ signal from 0xf to 0x1f000f, to keep default value safe.
* Changed mrs[2] and added new mrs direct command for setting WL/RL
  without resetting DLL.
* Added explicit reset value write in phy_con0 instead of just setting
  a bit, to ensure that reset happens.
* Added DREX automatic control for ctrl_pd in none read memory state.

This is ported from: https://gerrit.chromium.org/gerrit/61405
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1
Reviewed-on: https://chromium-review.googlesource.com/66995
Reviewed-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6611
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12 22:07:26 +02:00
David Hendricks 3ffdafdfa4 Exynos5420: Remove code for enabling read leveling
This patch intends to remove all code which enables hardware read
leveling. We need to disable h/w read leveling because new ASV table
is merged in kernel (which is based on the new characterization
condition) and new characterization environment has h/w read leveling
disabled, so we should also disable this. Also, disabling h/w read
leveling improves the MIF LVcc value (LVcc value is the value at which
DDR will fail to work properly), improve LVcc means we have enough
voltage margin for MIF. When h/w leveling is enabled, we have almost
zero volatge margin.

This was ported from: https://gerrit.chromium.org/gerrit/66070
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83
Reviewed-on: https://chromium-review.googlesource.com/66994
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6610
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12 22:06:10 +02:00
Julius Werner 79bff70ac8 exynos5: Refactor board-specific parts out of USB PHY code
This patch moves around some of the existing Exynos5 USB 2.0 PHY code
to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS
GPIOs (which are completely board-specific) into the mainboard code and
makes sure to only initialize PHYs on the boards that actually need
them. It also removes the USB 3.0 PLL hack that was needed on Snow from
the Pit and Kirby boards (which do not have that PLL anymore).

Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66887
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12 22:05:17 +02:00
David Hendricks 0f0c720621 exynos5420: ddr3: Cleanup init to use constants for directcmd
The old ddr3_mem_ctrl_init() for exynos5420 had hardcoded constants
for accessing directcmd registers.  Modify to use #defines where
possible.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/65616
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I01567fc6941608a570832de97259c55e84942d01
Reviewed-on: https://gerrit.chromium.org/gerrit/66789
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit d751e019f450172f060ce255ae53e972bc4a19ea)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12 22:02:56 +02:00
David Hendricks 2f3daddd28 exynos5420: Alter init sequence as per recommendation
As per hardware recommendation, CKE PAD retention release must
happen just before gate leveling enable and only in case of resume.
Hence, this patch moves pad retention release from dmc_common.c to
dmc_init_ddr3_exynos5420.c. In addition to this we are providing
125 (+3 extra being safe) times auto refresh to DRAM by sending
REFA direct command. This is required because when CKE PAD retention
release happens, self refresh mode of DDR3 is disabled.
Hence, auto refresh 125 times.

This is ported from https://gerrit.chromium.org/gerrit/#/c/65573

Note: Since WAKEUP_DIRECT does not go thru memory init, it should be
safe to move CKE PAD retention out of bootblock.c.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866
Reviewed-on: https://gerrit.chromium.org/gerrit/66788
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6604
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-12 22:01:48 +02:00
Julius Werner ad4556f2cb exynos5420: Make USB A-A booting work with early data cache
Apparently the IROM doesn't like data caches... the recently added
dcache-in-bootblock makes A-A booting fail, and flushes/invalidations
alone don't seem to fix it. It's pretty fast anyway, so we just disable
the cache again for the duration of the IROM call.

Also removes a superfluous invalidation line from the bootblock code...
dcache_mmu_enable/disable already take care of that.

Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66602
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f)

exynos5: Implement booting from SDMMC media

This patch augments the alternative CBFS media source implementation for
Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as
an SD or uSD card reader, if available). It also moves MMC
initialization for the Snow, Pit and Kirby boards from romstage to
ramstage (mainboard_init) to prevent it from interfering with the IROM
during SDMMC boot.

Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66154
(cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc)

snow and pit: turn on FET4 (for SD card) at bootup

Explictly enable FET4 on Snow and Pit.

Historically we haven't needed to do this because:
* On snow there's a bypass around FET4 which effectively eliminates
  it.  Even if we don't turn on FET4 the SD card is still powered.
  Turning on FET4 doesn't hurt though and is technically correct.
* On pit the EC turns on FET4 on cold bootup.

On pit we run into a problem if the kernel turns off FET4 like in
<https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a
software reset or warm reset.  In this case the EC won't know to turn
it back on.

This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c
Reviewed-on: https://gerrit.chromium.org/gerrit/66786
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646)

Squashed three commits for alternate cbfs SD support.

Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12 22:01:13 +02:00
Daniele Forsi 21fbc08d4b armv7/Makefile.inc, cpu/Makefile.inc: align output of printf
Fix whitespace.

Change-Id: I9e28b819d685851a84cee6c5a71458e07d0ec808
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6577
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12 09:02:43 +02:00
Martin Roth 9944b28cc4 cpu/intel/XXX/acpi.c: Fix coding style violation
Clean up a coding style violation as requested in the review of
commit 09670265.

Change-Id: I2815635efbb70a1e5841ca79cf2b4845bc6c23f2
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6598
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-12 03:35:10 +02:00
Patrick Georgi 20e2f3c6e4 x86/smm/smihandler.c: break case in switch
The case doesn't look like a deliberate fall-through,
since the next case (SNB/IVB/HSW) is more specific
than the one before it, so break out.

Change-Id: I55497aefe9e835842a82121270f2b2a9952f560d
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6571
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-11 17:03:45 +02:00
Furquan Shaikh 133096b6dc coreboot classes: Add dynamic classes to coreboot
Provide functionality to create dynamic classes based on program name and
architecture for which the program needs to be compiled/linked. define_class
takes program_name and arch as its arguments and adds the program_name to
classes-y to create dynamic class. Also, compiler toolset is created for the
specified arch. All the files for this program can then be added to
program_name-y += .. Ensure that define_class is called before any files are
added to the class. Check subdirs-y for order of directory inclusion.

One such example of dynamic class is rmodules. Multiple rmodules can be used
which need to be compiled for different architectures. With dynamic classes,
this is possible.

Change-Id: Ie143ed6f79ced5f58c200394cff89b006bc9b342
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/6426
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-11 15:42:20 +02:00
Ronald G. Minnich cff6667eba exynos5420: Tighten up displayport timing loops
We were running this loop 100 times with 5 ms delays. Change it
to run 500 times with 1 ms delays, which gives us the same
overall timeout but lets us bail out a bit sooner -- in practice,
at most, 4 ms sooner but every bit counts. Note, however, that
the tighter timing does reduce opportunities for threading. There
is a non-obvious set of tradeoffs on timeouts.

Change-Id: I4af671c2a791aa92e446e66ac2fe5710d1e6aa4c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/167387
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: ron minnich <rminnich@chromium.org>
Tested-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 575e910127dc74416018f182ef27ef223e61daef)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6543
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-10 22:19:16 +02:00