The _OSC method is used to tell the OS what capabilities
it can take control over from the firmware. This method
is described in chapter 6.2.9 of the ACPI spec v3.0.
The method takes 4 inputs (UUID, Rev ID, Input Count,
and Capabilities Buffer) and returns a Capabilites
Buffer the same size as the input Buffer. This Buffer
is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control
Dword. The OS will request control of certain
capabilities and the firmware must grant or deny control
of those features. We do not want to have control over
anything so let the OS control as much as it can.
The _OSC method is required for PCIe devices and dmesg
checks for its existence and issues an error if it is
not found.
Change-Id: I1494285def7440972f0549b7cb73eb94dafc72c2
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the Persimmon DSDT.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`. PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge. However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.
This change will apply to other AMD mainboards and
will be in a different commit.
Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Changes:
- Get rid of the inagua mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2607
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Replace »persimmon« by »board« in comment to keep `diff` output
between boards small.
Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Changes:
- Get rid of the union_station mainboard specific code and
use the platform generic function wrapper that was added
in change http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: I19d6b0d674b67294519383f80928471b37da1e14
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2609
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Changes:
- Get rid of the south_station mainboard specific code and
use the platform generic function wrapper that was added
in change http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2608
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Changes:
- Get rid of the persimmon mainboard specific code which has been
moved into the wrapper as a platform generic function in change
http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2500
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commit f154c018
Author: Marc Jones <marcj303@gmail.com>
Date: Wed Dec 14 11:24:00 2011 -0700
Persimmon audio codec verb patch.
Reviewed-on: http://review.coreboot.org/490
has a typo code*c* in the comments for `AZALIA_OEM_VERB_TABLE`. As
this was copied over to the LiPPERT Fam14 boards, use the following
command to fix the typo.
$ git grep -l cocec | xargs sed -i s,cocec,codec,
Change-Id: I1525b0445edab81ab136b3adece52b78ba7abc71
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2576
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be
disabled.) turned off the device in AGESA. Now remove it from
devicetree.cb, too. This prevents the following boot message:
PCI: Left over static devices:
PCI: 00:01.1
PCI: Check your devicetree.cb.
Also clarify the line's comment a bit for the Fam14 boards which still
retain this device (to counter the loss of information ;-).
Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2537
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Mainly replace spaces by tabs and format comments correctly.
Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was
unfortunately incomplete and also used spaces instead of tabs in
some cases.
Hopefully fix this once and for all to have a template for the
other boards.
[1] http://review.coreboot.org/547
Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2526
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch reduces unnecessary differences between AMD Inagua, Persimmon,
Union Station, South Station and Asrock E350M1. It's only cosmetical, but
makes them a little bit easier to compare.
This is the remainder of the original http://review.coreboot.org/2464,
parts of which somehow got lost in a flurry of refactoring and splitting
patches.
Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2529
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Changes:
- Add #include of delay.h in mainboard.c to pick up declaration of
mdelay function.
Notes:
- This fixes this warning:
mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal
implicit declaration of function 'mdelay' [-Wimplicit-function-declaration]
Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2501
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently on for example on AMD Persimmon and ASRock E350M1 Linux
complains, that the PBLK length is invalid [1].
ACPI: Invalid PBLK length [0]
Consequently, frequency scaling might not work correctly, though for
these two boards it seems to work according to PowerTOP.
Indeed, according to the ACPI specification [2], setting PBlockLength
to 0 is only allowed if there is no PBlockAddress. Otherwise it has to
be set to 6.
18.5.93 Processor (Declare Processor)
[…]
PBlockAddress provides the system I/O address for the processors
register block. Each processor can supply a different such
address. PBlockLength is the length of the processor register
block, in bytes and is either 0 (for no P_BLK) or 6. With one
exception, all processors are required to have the same
PBlockLength. The exception is that the boot processor can have
a non-zero PBlockLength when all other processors have a zero
PBlockLength. It is valid for every processor to have a
PBlockLength of 0.
And that is exactly what Linux is checking in
`drivers/acpi/processor_driver.c` [3].
static int acpi_processor_get_info(struct acpi_device *device)
{
[…]
/*
* On some boxes several processors use the same processor bus id.
* But they are located in different scope. For example:
* \_SB.SCK0.CPU0
* \_SB.SCK1.CPU0
* Rename the processor device bus id. And the new bus id will be
* generated as the following format:
* CPU+CPU ID.
*/
sprintf(acpi_device_bid(device), "CPU%X", pr->id);
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id,
pr->acpi_id));
if (!object.processor.pblk_address)
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n"));
else if (object.processor.pblk_length != 6)
printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n",
object.processor.pblk_length);
else {
pr->throttling.address = object.processor.pblk_address;
pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset;
pr->throttling.duty_width = acpi_gbl_FADT.duty_width;
pr->pblk = object.processor.pblk_address;
/*
* We don't care about error returns - we just try to mark
* these reserved so that nobody else is confused into thinking
* that this region might be unused..
*
* (In particular, allocating the IO range for Cardbus)
*/
request_region(pr->throttling.address, 6, "ACPI CPU throttle");
}
[…]
}
This issue has proliferated to all AMD based boards so fix it for
all of them by setting P_BLK length to 6.
The DSDT of for example AMD Parmer and AMD Thatcher also set it
to 6 everywhere so this solution is taken instead of setting the
P_BLK system I/O base to 0 for all but the first processor which
is how it is done for earlier AMD based boards.
As note having to set this manually should not be needed and
this should be autogenerated as done for most of the Intel boards
and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`).
[1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html
[2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf
[3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/acpi/processor_driver.c;h=e83311bf1ebdaaaea1adbf2de1351cca907d3465;hb=5da1f88b8b727dc3a66c52d4513e871be6d43d19#l351
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
• ASRock E350M1:
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
• AMD Persimmon:
Tested-by: Martin Roth <martin.roth@se-eng.com>
Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2189
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1
simply does not exist, so remove it from devicetree.cb. While at it make the
comment more detailed. Likewise for all USB ports.
USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1. Add it
to devicetree.cb. It's used on Inagua (on), but not on Persimmon (off).
Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
The DSDT header contains the fields OEMID and OEM Table ID. See
for example ACPI specification 4.0a [1]
5.2.11.1 Differentiated System Description Table (DSDT)
on page 135. There Table 5-16 contains the descriptions.
Field Byte Length Byte Offset Description
===================================================
OEMID 6 10 OEM ID
OEM Table ID 8 16 The manufacture model ID.
Currently in coreboot there is no common method what to put in
these fields.
Mostly Intel based boards populate it with "CORE " ore "COREv4"
and AMD based boards populate it with the board vendor and
model number, abbreviated appropriately to fit into these fields.
On most boards the proprietary vendor BIOS seems to leave these
fields – displayed with `sudo dmidecode` under System Information –
blank
To Be Filled By O.E.M.
and fill out the Base Board Information with the board vendor and
model name.
In [2] Jens Rottmann argues that the this is really just the table
ID used for naming it and that »99% of the DSDT code is not board
specific«.
Both approaches seem to have their advantages, but using the
second one, developers often seem to forget to update them (for
example AMD Thather).
The current situation is at least not optimal. and therefore at
least unify the string in the OEM Table ID. If unifying the
OEM ID is also a good idea this should be done too.
If later on it should be decided that the board vendor and model
should be used again, this should be somehow derived from
Kconfig.
The following command was used for the change [3].
$ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/'
This patch is split out from [2].
[1] http://www.acpi.info/spec40a.htm
[2] http://review.coreboot.org/#/c/2464/
[3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-to-double-quotes-when-a-certain-text-appears-i
Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2472
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Fix redefinition warning for SB_GPIO_REG50 introduced in commit
fa8702cf - http://review.coreboot.org/#/c/2446/
Persimmon: adapt PCIe reset code copied from Inagua to actually
match Persimmon
The warning being fixed is:
SB800.h:1491, GNU Compiler 4 (gcc), Priority: Normal
"SB_GPIO_REG50" redefined [enabled by default]
- Enable warnings as errors so no more warnings will be accidentally
committed.
Change-Id: Ib443b2bd2067f0b7d5f93f79170899a0f8f61060
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2494
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To reduce the differences between these file name the enabling
device function in the directory `src/mainboard` uniformly
`mainboard_enable` [1].
Thanks to the awesome help of gnomon and BlastHardcheese in the
IRC channel #sed on <irc.freenode.net>. gnomon came up with the
following command to do the actual work.
$ cd src/mainboard
$ for f in */*/mainboard.c ; \
> do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \
> [[ -z $src ]] && continue ; \
> printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \
> done
`src/mainboard/digitallogic/msm586seg/mainboard.c` and
`src/mainboard/technologic/ts5300/mainboard.c` had to be adapted
manually as no comma was used separating the struct members.
And with the following statement, gnomon is even more likable!
My pleasure entirely. Good luck with coreboot; I'm a big fan of the project.
[1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html
Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2493
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reduce unnecessary differences between AMD based boards only
using the file `platform_cfg.h` for configuration making them
a little bit easier to compare.
Inagua & co. mention the board name in several places which are really not
that board specific. Sometimes people even forget to change it:
Union Station’s platform_cfg.h starts with "#ifndef _PERSIMMON_CFG_H_".
Funny. Change that to "_PLATFORM_CFG_H_" everywhere.
The following command was used.
$ find . -name platform_cfg.h | xargs sed -i '/_CFG_H_/s/_.*_/_PLATFORM_CFG_H_/'
More boards seem to use that kind of naming (`git grep _CFG_H_`)
but it is not certain that this will not break anything as for
example the board AMD Dinar also has header files for
configuration stuff for the north- and southbridge.
$ git grep _CFG_H_
[…]
src/mainboard/amd/dinar/platform_cfg.h:#ifndef _PLATFORM_CFG_H_
src/mainboard/amd/dinar/platform_cfg.h:#define _PLATFORM_CFG_H_
src/mainboard/amd/dinar/platform_cfg.h:#endif //_PLATFORM_CFG_H_
src/mainboard/amd/dinar/rd890_cfg.h:#ifndef _RD890_CFG_H_
src/mainboard/amd/dinar/rd890_cfg.h:#define _RD890_CFG_H_
src/mainboard/amd/dinar/rd890_cfg.h:#endif //_RD890_CFG_H_
src/mainboard/amd/dinar/sb700_cfg.h:#ifndef _SB700_CFG_H_
src/mainboard/amd/dinar/sb700_cfg.h:#define _SB700_CFG_H_
src/mainboard/amd/dinar/sb700_cfg.h:#endif //_SB700_CFG_H
[…]
Change-Id: Ida15fa6a7adfc770240ac30e795946000dae3f16
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2464
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
At the request of Paul Menzel, I reran an
old classic of a coccinelle script:
@@
expression E;
@@
-(E + 7) & -8
+ALIGN(E, 8)
@@
expression E;
@@
-(E + 15) & -16
+ALIGN(E, 16)
Change-Id: I01da31b241585e361380f75aacf3deddb13d11c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There were just whitespace differences and three boards did not
contain
printk(BIOS_DEBUG, "alib\n");
dump_mem(ssdt, ((void *)alib) + alib->length);
which is enclosed `#if DUMP_ACPI_TABLES == 1` to dump the ACPI
tables.
Basically the whitespace in the license header in Inagua’s file
was fixed and then the file copied over to the other directories.
Change-Id: I23f73acad427b5ec14cf51651af67240871f7488
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2470
Tested-by: build bot (Jenkins)
Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The following command was used to correct the typo.
$ git grep -l @breif | xargs sed -i 's/@breif/@brief/'
Change-Id: If0b579279de3c41571b9cda643836f5748a752a2
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2473
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
From ISO C99 standard: »The placement of a storage-class specifier
other than at the beginning of the declaration specifiers in a
declaration is an obsolescent feature.«
Found at <http://www.approxion.com/?p=41>.
Change-Id: Iee7878affb2a5d157a94763083689d75e8218b2f
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2474
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The relational operators in the if-predicate are aligned in all
`dimmSpd.c` files so revert part of the change in
commit 36abff1dc8
Author: Marc Jones <marcj303@gmail.com>
Date: Mon Nov 7 23:26:14 2011 -0700
Cleanup Persimmon mainboard whitespace.
Reviewed-on: http://review.coreboot.org/427
to remove the incorrectly introduced tabs and to unify that. It
might contradict the current coding style but it is even used in
the latest code as seen in the following file.
src/northbridge/amd/agesa/family15tn/dimmSpd.c
Change-Id: Ib611267f99090d0830bdc2319527389f193ea1eb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2471
Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
Tested-by: build bot (Jenkins)
This was overlooked in the following commit.
commit 36abff1dc8
Author: Marc Jones <marcj303@gmail.com>
Date: Mon Nov 7 23:26:14 2011 -0700
Cleanup Persimmon mainboard whitespace.
Reviewed-on: http://review.coreboot.org/427
Change-Id: If6bf4836b46077614a04c1e106c241a4f97da166
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2468
Tested-by: build bot (Jenkins)
Reviewed-by: Alvaro G. <andor@pierdelacabeza.com>
For AMD Inagua, the following two commits
commit 01f7ab9335
Author: Kerry Sheh <shekairui@gmail.com>
Date: Thu Jan 19 13:18:36 2012 +0800
Inagua: Synchronize AMD/inagua mainboard.
Reviewed-on: http://review.coreboot.org/542
and
commit d91c9b7e3c
Author: efdesign98 <efdesign98@gmail.com>
Date: Thu Sep 15 10:59:55 2011 -0600
AMD Inagua platform updates
Reviewed-on: http://review.coreboot.org/136
replaced the constant `iobase` is set to by the define `SMBUS0_BASE_ADDRESS` from `OEM.h`.
Do the same for AMD Persimmon, South Station, Union station and ASRock E350M1.
Change-Id: If095cd9d9b28b118b4072c7c9d345bf620b774c9
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2453
Tested-by: build bot (Jenkins)
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].
$ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'
[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt
Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
The following commit was too eager replacing spaces with tabs.
commit 36abff1dc8
Author: Marc Jones <marcj303@gmail.com>
Date: Mon Nov 7 23:26:14 2011 -0700
Cleanup Persimmon mainboard whitespace.
Reviewed-on: http://review.coreboot.org/427
Fix that with the following command.
$ git grep -l 'Floor, Boston, MA'$'\t''02110-1301 USA' | xargs sed -i 's/Boston, MA[ ]*02110-1301 USA/Boston, MA 02110-1301 USA/'
Change-Id: Ia118a8c19d94ce1f1048280a0f1d49d447cfa2a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2461
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Looking at AssertSlotReset, the comments and all other case's it's
obvious this is a simple copy & paste error where someone just forgot
to change one occurrance of the GPIO nr. Also the AMD Inagua
schematics show that GPIO02 is what they really meant.
Also forward the fix to boards copied from Inagua (AMD South
Station, Union Station, Asrock E350M1).
Change-Id: I6b9a3d473245fa27604b2f148a730290277a88ed
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2445
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Inagua can use GPIOs 178,179 to switch VMEM to 1.5, 1.35 or 1.25 V,
which it does according to data read from the SO-DIMM's SPD EEPROM.
On Persimmon (according to DB-FT1 rev. D schematics) both GPIOs are
unconnected, there is no way to change the 1.5 V DDR3 voltage (save
unsoldering a resistor). The whole code copied over from Inagua is
useless.
Removed the code, instead a comment hints at Inagua, for people who do designs
based on Persimmon but do have a way to change VMEM.
The line ...->DDR3Voltage = VOLT1_5; is supposed to make the AGESA DDR3 code
select the RAM timings for the actually supplied voltage instead of the
hoped-for but unavailable lower voltage. I have no idea how to test this, but
in any case it can't hurt.
Change-Id: Id098e09418b665645814a6ee2d41a3bff72238ba
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2448
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected.
Reflect this fact in the mainboard code.
Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2447
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Comparing Persimmon and Inagua schematics and Coreboot code show the PCIe reset
code has been blindly copied even though it doesn't suit the Persimmon at all.
The Inagua can employ GPIOs 21, 25, 02 to manually reset devices on APU PCIe
lanes 0/1, 2, 3 respectively. (Appearently the motivation for this is to revive
buggy PCIe gen1 devices which got confused by PCIe gen2 signal training.)
However the Persimmon not only doesn't support this, it even needs these 3 pins
for the PCI interface! Instead it uses GPIO50 to reset devices on lanes 0-2 all
at once. Lane 3 is unconnected anyway.
This patch adapts the Persimmon mainboard code according to the DB-FT1 rev. D
schematics.
Change-Id: I05a657d9bf8cc59acc4f5174eb20375165c860c7
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2446
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.
Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The hardware is there, so turn it on.
Change-Id: I40aff1e84a22a05599c62b9f0b20397df0a40b15
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2353
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The following command was used to correct the grammatical mistake.
$ git grep -l 'This is the stub function will call' | xargs sed -i s,This is the stub function will call,This stub function will call, '{}'
sed: -e Ausdruck #1, Zeichen 6: Nicht beendeter `s'-Befehl
As this file seems to have been copied around a lot, it originally
seems to have come with the following commit for AMD Persimmon and
AMD Inagua.
commit 69da1b676c
Author: Frank Vibrans <frank.vibrans@amd.com>
Date: Mon Feb 14 19:04:45 2011 +0000
Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.
Change-Id: I2e6630a5172738b01e6def7062284f167e5508b1
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2268
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The LVDS is on DP0, not DP1.
Change-Id: I724764d0f013e7a10d974a8716e075139982ded2
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2259
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Continuing with the mainboard cleanup for F15tn, move the functions
to read the SPD from the mainboards for Thatcher and Parmer into the
wrapper for the northbridge/amd/agesa/family15tn.
Move the SPD address customization for the mainboard into the
devicetree.cb file.
Unrelated side note - Porting.h has an un-closed #pragma pack(1)
that can cause confusing side-effects. AGESA's structures all
use this, but coreboot's don't. Be sure to include the coreboot
.h files BEFORE Porting.h is included, not after.
This fix has been tested.
Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2190
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
This change is required in order to use a LVDS panel
attached to the LVDS connector.
Change-Id: Id97c233f964151b6515bd46c797425d0e6690cbd
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2188
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
commit 585a400697
Author: zbao <fishbaozi@gmail.com>
Date: Thu Apr 12 11:27:26 2012 +0800
Leverage the Pstate table created by AGESA.
… introduced unneeded whitespace in front of a comma.
Revert that part of the above commit. In the file for AMD Dinar
tabs and spaces are mixed, but leave that alone for the beginning.
Change-Id: I279cd0cb0be8c79258034733773f2ae1c2207cce
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2187
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Enable 'all warnings being treated as errors' in thatcher and parmer.
Fixed the following warnings on parmer / thatcher:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
In function 'GetPstateGatherDataAddressAtPost':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
In function 'MemNInitNBDataTN':
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0:
note: this is the location of the previous definition
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
src/include/cpu/x86/lapic_def.h:9:0: note:
this is the location of the previous definition
In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
from src/mainboard/amd/parmer/mainboard.c:28:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0: note:
this is the location of the previous definition
Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2171
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.
This is just cleanup and should make no functional difference.
Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
There are currently too many things in the mainboard directories that
are really more suited to being in the northbridge / southbridge
wrappers. This is a start at moving some of those functions down
into the wrappers.
Move the bios callback functions into the northbridge/amd/agesa/family15tn
directory from the mainboard directories. These can still be overridden
by any mainboard just by updating the pointer in the callback table to
point to a customized version of the function.
Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Add Kconfig option for Legacy free and hook it into the parmer
AGESA initialization as well as the FADT code. This should really
be done inside the southbridge wrapper and not in the mainboard,
but for now the code to attach it to is inside the mainboard.
Update Kconfig for parmer and thatcher to default to legacy free.
Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2157
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Re-formatting and cleaning up the devicetree.cb files for
parmer and thatcher.
Change-Id: Ic458e59701c1f2593b0a035b96cac60df476ee82
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2164
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
The way that devicetree.cb was configured for the family 15tn boards
was doing... interesting things to the video device initialization.
This was causing S3 resume to fail.
There is a disconnect between how the devicetree should be configured
if there are multiple HT links on the CPU and how it's configured if
there's only one HT link. These platforms were set up as if they
had multiple HT links, which was causing duplicate instances of
devices in the device list.
The scan for the IO Hub was removed from the northbridge code which
isn't a problem for F15tn devices.
Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2160
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Bits were being shifted off the end of the mask accidentally.
This results in all masks being 32 bits wide instead of 48.
Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2146
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these
bits will cause exception. So be carefull when spread this change.
The supermicro/h8scm needs more work. Currently it is set as it was.
We need to check if the F10 and F15 have different value.
Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
ACPI code:
The ACPI code is not currently being compiled in by default, but
assuming that it will be at some point, I'm fixing the loop that
waits for the IMC to respond after sending it a command. The
loop now exits after 500ms, similar to the function in agesa.
Agesa Code:
a 16 bit variable will always be less than 100000. Change to
be a 32 bit variable.
Change-Id: I9430ef900a22d056871b744f3b1511abdfea516e
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2119
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Size of BiosCallouts[] struct can be calculated as:
CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
There is no longer need for REQUIRED_CALLOUTS define.
Originally that change was done for AMD Persimmon in
commit d7a696d0f2
Author: efdesign98 <efdesign98@gmail.com>
Date: Thu Sep 15 15:24:26 2011 -0600
Persimmon updates for AMD F14 rev C0
without deleting the define. This was ported to some of the other
boards and for some the define was not removed.
The AMD Inagua, Parmer and Thatcher boards were already adapted but
the define was left in. So just remove it for those.
Tested on Supermicro H8QGI.
Change-Id: Ia09795579a1170fa20ab94a30feb1af6821153d2
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2049
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.
- Allows user to add the IMC rom to the build and to configure the
location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
platform.
Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Change-Id: I4b735fe4e6441f99236e43b34695fdac95b8888a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1875
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This gets rid of the somewhat unstructured placement of AMD's
sysinfo structure in CAR.
We used to carve out some CAR space using a Kconfig variable,
and then put sysinfo there manually (by "virtue" of pointer magic).
Now it's a variable with the CAR_GLOBAL qualifier, and build
system magic.
For this, the following steps were done (but must happen together
since the intermediates won't build):
- Add new CAR_GLOBAL sysinfo_car
- point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
- remove DCACHE_RAM_GLOBAL_VAR_SIZE
- from CAR setup (no need to reserve the space)
- commented out code (that was commented out for years)
- only copy sizeof(sysinfo) into RAM after ram init, where
before it copied the whole GLOBAL_VAR area.
- from Kconfig
Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
- Optionally override FSB clock detection in generic
LAPIC code with constant value.
- Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz
- compile LAPIC code for romstage, too
- Remove #include ".../apic_timer.c" in AMD based mainboards
- Remove custom udelay implementation from intel northbridges' romstages
Future work:
- remove the compile time special case
(requires some cpuid based switching)
- drop northbridge udelay implementations (i945, i5000) if
not required anymore (eg. can SMM use the LAPIC timer?)
Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1618
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When dropping ramstage.a duplicate symbols in ramstage
will start breaking the build. Hence drop all the duplicate
functions implemented by mainboards that have those functions
in generic or component code already.
Change-Id: I5cf8245c67b6f0f348388db54256d28f47017a61
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1865
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
This will make it easier to switch over to use the config_enabled()
macro later on.
Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
intel_irq_routing_table is a local structure that should not be used
globally, because it might not be there on all mainboards.
Instead, the API has to be corrected to allow passing a PIRQ table in
where needed.
Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1862
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Some boards selected GENERATE_ instead of HAVE_
Change-Id: I450c22d7b044f0c88c21692246d452d516a68a83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1841
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This patch is the beginning of a Kconfig cleanup series
- drop CONFIG_HAVE_BUS_CONFIG and add get_bus_conf.c if it
exists in the mainboard directory
- drop duplicate ACPI_SSDTX_NUM from mainboard Kconfig
if it only defines the defaul value of 0
- Add mptable.c, fadt.c, reset.c and ssdtX.asl when they
exist, not based on some Kconfig magic
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: Ia14a7116dad6a724af7e531920fee9a51fd0b200
Reviewed-on: http://review.coreboot.org/1832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Compose the name from Kconfig strings instead.
As the field is for debug print use only, a minor change in the output
should do no harm. The strings no longer include word "Mainboard".
Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because enable cache is added at the end of disable_cache_as_ram,
( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc )
enable_cache() should be removed. The 3 mainboards are: amd parmer,
amd thatcher and tyan s8226
Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1669
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Enable the PCIE bridge which is connected to the PCIE slot.
Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1098
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Change-Id: I2f10909a626fb64c7f95663ddd79a3b899f73bc4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1606
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
According to file "northbridge.c" in family 15h code
IO-HUB should be placed on link_lsit[0] in devicetree.cb.
This hack in "northbridge.c" was made to satisfy both f10 and f15 cpu's.
Change-Id: I4754235bd38239460347b0dc4a82cd4e58ae7cd0
Signed-off-by: Kostr <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/1540
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Without this change 64 bit versions of Windows will BSOD.
Change-Id: If39627a179c24184b6c956b3a50f692f8a034d2f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1476
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The includes removed here were previously required for
struct lb_memory and lb_add_memory_range().
Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1391
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
These existed to provide a hook to add reserved memory regions
in the coreboot memory table. Reserved memory are now
added as resources.
Change-Id: I9f83df33845cfa6973b018a51cf9444dbf0f8667
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1414
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The function is a noop for all but amd/serengeti_cheetah.
Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1184
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Thatcher features: Family 15 trinity FP2. Hudson.
close to Parmer.
This board and parmer both need to revert the change
http://review.coreboot.org/#/c/1359/, and add thatcher's own
chip.h,otherwise the mainboard_enable can not be called.
Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1382
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
UMA region can be determined at any time after the amount
of RAM is known and before the uma_resource() call.
Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1379
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This reverts commit 78efc4c36c.
The broadcast patch was reverted, so this commit should also
be reverted. The reason for reverting the broadcast patch:
It turned out that sending IPIs via broadcast doesn't work on
Sandybridge. We tried to come up with a solution, but didn't
found any so far. So revert the code for now until we have
a working solution.
Change-Id: I05c27dec55fa681f455215be56dcbc5f22808193
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.
Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.
These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.
Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)
Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Read event routine didn't get the correct BIOS callout. So it could not get
the heap address. Then it would creat many warning in serial port.
Change-Id: Ia35601bda1579c7f726ed767d7be78713ac185d2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is for GfxInitSview(GnbSview.c). It would create warning message if it
could not get VBIOS image.
Change-Id: I3b2726f612b4b7a237644a4b63b56efad52b7ab5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Remove the warning message from linux dmesg,
mtrr: your BIOS has configured as incorrect mask, fixing it.
Change-Id: I355509db12ab10c33b7c1c23e2c7c4783f30e67e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1349
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Use of uma_resource() in AMD northbridge code created a memory
resource marked as reserved. Such resources are removed
from system memory in write_coreboot_table().
Change-Id: Ib5e49e851d6622d8ece9d6d612e245b3962b9167
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1233
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
These boards had identical UMA code:
amd/dbm690t
amd/pistachio
technexion/tim5690
technexion/tim8690
The ones below had whitespace or debug level change
compared to the one above:
kontron/kt690
siemens/sitemp_g1p1
These boards use AMDFAM10 guidelines in code:
asrock/939a785gmh
amd/mahogany
Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following boards had identical code:
advansus/a785e-i
amd/bimini_fam10
amd/mahogany_fam10
asus/m5a88-v
avalue/eax-785e
gigabyte/ma78gm
iei/kino-780am2-fam10
jetway/pa78vm5
Following boards had identical code:
amd/tilapia_fam10
asus/m4a78-em
asus/m4a785-m
gigabyte/ma785gm
gigabyte/ma785gmt
In between the two, only whitespace difference.
Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following boards had identical code:
amd/inagua
amd/persimmon
The following had only whitespace or debug level changes
compared to ones above.
amd/union_station
amd/south_station
asrock/e350m1
Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The new broadcast code doesn't support serial init - if a CPU
needs serial init, this should be handled in the model specific CPU
init code.
Change-Id: I7cafb0af10d712366819ad0849f9b93558e9d46a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1140
Tested-by: build bot (Jenkins)
- Add #define to allow the FADT PM Profile to be overridden.
- Change the location of the PMA_CNT_BLOCK_ADDRESS to match
current documentation.
- cst_cnt should be 0 if smi_cmd == 0
- add a couple of default access sizes.
- Add a couple of #define values for unsupported C2 & C3 entries.
- Add PM Profile override value into amd/persimmon platform.
This does not use the #defines in acpi.h so that the files that
include this don't all need to start including acpi.h.
Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1055
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Stupid typo: APCI instead of ACPI in Persimmon.
Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1054
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.
Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
In the heap function, only check for S3 check when it is built in
with CONFIG_HAVE_ACPI_RESUME.
Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1034
Tested-by: build bot (Jenkins)
Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The South Station recieved updates that fix a number of fadt problems.
South Station now uses the southbridge fadt.
Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The fadt.c is the same across all the platforms using the sb800
cimx southbridge wrapper.
Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1019
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is a model fadt.c that I would like to use for updating
several other AMD platforms with after acceptance.
- Updated to match ACPI 3.0b specification and added comments
to reflect that.
- Since smi_cmd is 0, remove commands that rely on it:
acpi_enable, acpi_disable, & pstate_cnt
Add comments to that effect.
- Changed preferred_pm_profile to SOHO Server (platform
specific)
- The southstation platform is legacy free - Updated
iapc_boot_arch and flags to reflect that.
- Added reset_register flag so that operating systems
will actually use the reset_reg. This is important
on legacy free systems.
- Updated Generic Address Structures to use access_size
name in the updated acpi.h. Added access sizes to
the structures where reasonable.
- Removed 64-bit x_firmware_ctl pointer to facs. This was
causing a fwts failure and windows-64 BSOD.
- Added bit width for pm2_cnt_blk and modified gpe0_blk bit
to match the hardware.
Change-Id: Icf1a982aa122636d1088c8b80f53d04732b54c49
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/942
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
There is no reason for this to be a top level directory.
Some stuff from lib/ should also be moved to drivers/
Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/939
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Hope no more blank issue is got from future copy-paste.
Change-Id: I5eb50e8232e339e7039a15054606aaff6b7ebc52
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/907
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The name of processor created by AGESA is P00n, whose P is
BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
from 0. The dsdt should be aligned with that.
This feature has only been tested on persimmon. The changes on all the
other boards were propagated.
Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/884
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
During normal boot, the cbmem is uninitialized. So it is illegal to find
the heap in cbmem.
Change-Id: I8b5e1dbf1124819ed91693a86a6dbe41aea109e5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/904
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Persimmon is the demo board. Tested by Linux and Windows 7.
Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/624
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
HEST feature starts from ACPI 4.0.
HEST is one of four kinds of tables of ACPI Platform Error
Interfaces (APEI). In Windows world, APEI is called Windows Hardware
Error Architecture (WHEA).
APEI consists of four separate tables:
1. Error Record Serialization Table (ERST)
2. BOOT Error Record Table (BERT)
3. Hardware Error Source Table (HEST)
4. Error Injection Table (EINJ)
All these 4 tables have the same header as FADT, MADT, etc. They are
pointed by RSDP.
For the HEST, it contains the error source. The types of them are
defined as
type description
1. Machine Check Exception (MCE)
2. Corrected Machine Check (CMC)
3. NMI Error
6. PCI Express Root Port AER
7. PCI Express Device AER
8. PCI Express Bridge AER
9. Generic Hardware Error Source
Error source types 3, 4, and 5 are reserved for legacy reasons and
must not be used.
Currently AMD board only provide part of "Machine Check
Exception (MCE)" & Corrected Machine Check (CMC)". we need to provide
the header of each error source. Other types of Error Sources is in
TODO list.
Only persimmon is tested. Linux can add HEST feature. The dmesg says,
ACPI: HEST 0000000066fe5010 00198 (v03 CORE COREBOOT 00000000 CORE 00000000)
......
HEST: Table parsing has been initialized.
No more message is got.
Windows can boot with this patch. Havent found a way to test it.
Change-Id: I447e7f57b8e8f0433a145a43d0710910afabf00f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/888
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
some blank changing is integrated into the previous patches, which hold
the unsplitted diff hunk.
Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove
the explicit selects from the mainboards.
Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/792
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit includes the changes to enable the HDMI on Union
Station. The changes switch the output from the display port
to the HDMI.
Change-Id: I4e15ff6db7d056f156791ff1406d4bae35ff2767
Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com>
Reviewed-on: http://review.coreboot.org/788
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Because the Union Station platform doesn't have an SIO chip,
this commit removes the Fintek SIO support.
Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2
Signed-off-by: Frank Vibrans <frank.vibrans@se-eng.com>
Reviewed-on: http://review.coreboot.org/787
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
We used several names for that same value, and hardcoded the value
at some more places.
They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).
Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
CPP is ran with src/ as part of its search path, so
using <northbridge/...> and the like is safe.
Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/649
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/660
Tested-by: build bot (Jenkins)
The family10 code had a very slow decompress before the cache settings were
fixed. This has been fixed for some time. Remove all the old messages from the
serial stream.
Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/672
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Fixes the warnings generated in the torpedo mainboard build. Most of these
changes are similar to fixes already implemented in the persimmon mainboard.
Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5
Signed-off-by: Martin L Roth <martin@se-eng.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/661
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge. (cimx/sb800 is a "different"
chipset)
Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Fix issues reported by new lint test.
Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree amd8111-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/654
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Dinar mainboard is an AMD evaluation board for
Orochi Platform family15 model 00-0f processor.
The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
16 cores InterLagos Opteron processor are supported.
Windows 7 are verified on this platform.
Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Driver components are conditionally included in the build using the
Kconfig options.
Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Pcie device connected to Hudson/sb800 southbridge GPP training can works,
by applying this mainbaind specific GPIO PCIE De-Assert setting.
Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/543
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.
Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Make changes MPtable to match ACPI tables.
Change-Id: I387f301370582fcb5e0d348d793333a919d2f373
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/575
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup.
Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/574
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.
Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This line was unnecessary and was duplicated on several mainboards.
Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/541
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The #define REQUIRED_CALLOUTS is no longer used on these platforms.
Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.
At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.
Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
call was failing without heap space allocated causing the ASSERT messages in
the output. I think are there may still be other issues in integrating the
SSDT table with the DSDT, but now it is there to debug.
The changes were made in Persimmon and copied to the other Fam14 mainboards.
Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/517
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.
The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.
Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes
Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add interrupt routing for APU GNB internal Graphic and HD audio device, and
other pcie bridge device in GNB.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/452
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Added the default ID to the mainboard Kconfig.
Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.
Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Untested, changes ramstage build for boards:
supermicro/h8qme_fam10
amd/serengeti_cheetah
amd/serengeti_cheetah_fam10
AMD 8132 was not built for any mainboard due to a typo.
AMD Serengeti Cheetah:
Chip 8151 is referenced in devicetree.cb but was not built.
AMD Serengeti Cheetah Family10:
There are indications the board has 8151, but it is not listed
in the devicetree.cb. The 8151 chip is not added in the build.
Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.
Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
AMD unionstation Reference Design Kit is Designed for hd settop box application.
This platform using family14 APU, SB800 southbridge.
Vgabios is required, can download vgabios from AMD NDA website.
Verified Feature:
HDMI, LAN, mini-pcie slots, sata, usb, analog audio and
optical fiber digital audio output.
Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
AMD southstation Reference Design Kit is designed for NAS application.
This platform using family14 RevC0 processor, SB850 southbridge.
Vgabios and Promise RAID Option ROM is required for hardware RAID support,
can retrieve from the AMD NDA website.
Verified feature:
HDMI, LAN, usb and mini-pcie slot.
RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10.
Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
No romstage is supposed to use usbdebug functions/defines
directly, so remove all those includes. The usb code is now
called and setup from console code.
Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/354
Tested-by: build bot (Jenkins)
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.
Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add configure option SB_GPP_UNHIDE_PORTS for mainboard
to hide/unhide the unused sb800 gpp ports.
Certain gpp port should be hidden, if no device was detected and
hotplug feature is disabled for such port.
Hidden unused ports makes lspci -vvv get more accurate information under Linux.
Test on avalue/eax-785e mainboard.
Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.
Coccinelle script:
@@
identifier mc;
@@
(
-mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-return smp_next_mpe_entry(mc);
+return mptable_finalize(mc);
|
-mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-return smp_next_mpe_entry(mc);
+return mptable_finalize(mc);
)
Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
We copied pretty much the same code for generating mptable entries for
local interrupts (with some notable exceptions).
This change moves these lines into a generic function "mptable_lintsrc"
and makes use of it in many places.
The remaining uses of smp_write_lintsrc should be reviewed and replaced
by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.
This patch was generated using Coccinelle:
@@
expression mc;
expression isa_bus;
@@
-smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+mptable_lintsrc(mc, isa_bus);
@@
expression mc;
expression isa_bus;
@@
-smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+mptable_lintsrc(mc, isa_bus);
@m@
identifier mc;
expression BUS;
@@
-#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
...
-IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+mptable_lintsrc(mc, BUS);
Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/244
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
So the missing sb800 USB3 devicees was add to the mainboard devicetree.
Because of no physical usb connector connected to USB3, the USB3 device setting was off.
Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/232
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/230
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.
Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/219
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Tested-by: build bot (Jenkins)
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/220
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
These are the changes for the AMD Persimmon mainboard
required to support the update of the AMD Family 14
cpu to rev C0. There are many warning fixes; the agesa-
wrapper.c file has been changed to fix the amdinitlate
and amdlaterunaptask routines, and more.
Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/137
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
These changes update the Inagua platform. The changes
include modifying the Kconfig to suggest video bios
and ahci rom implementations, changing the dimm spd
code to use the correct bus addresses, cleaning up the
makefile a bit, and fixing a duplicate definition
warning associated with the BIOS_SIZE value.
Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/136
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This update fixes warnings and supports as necessary
the Agesa infrastructure changes required to support
the AMD Family 14 cpu update to rev C0.
Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/138
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.
Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/109
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.
Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.
Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.
Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/54
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.
Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.
Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
So we don't waste time on the first cbfs scan.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2) Correct UMA graphics PCI device ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2) Correct I/O APIC ID reported by mptable
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The patch makes these changes:
1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
romstage.c files where it is used (AMD family 10h projects).
2) Add a prototype to amdfam10.h.
3) Modify the swap list and test in real hardware for mahogany_fam10 and
kino family 10h and confirm HT3 operation for the SB link.
Abuild tested.
Signed-off-by: Scott Duplichan <sc...@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
all boards to the new config scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fixes abuild issues.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
smp_write_config_table will run. Then intr_data will be written
into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We did the same with other chipsets in r6150.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
to HAVE_DEBUG_CAR in r5898.
- Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
- Drop obsolete/unused COMPRESS, see r6145.
- Drop obsolete SET_NB_CFG_54, see r6086.
- Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
- Rename some GENERATE_* options to HAVE_*, see r6027.
- Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
- Drop ACPI_SSDTX_NUM, the global default is 0 already.
- Random whitespace and coding style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
databook. (Part1)
This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot made it kind of complicated to print a character on serial. Not quite
as complicated as UEFI, but too much for a good design. Fix it.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We currently use "COREBOOT" unconditionally as the "OEM ID" in our
mptable.c files, and hardcode the mainboard name in mptable.c like this:
mptable_init(mc, "DK8-HTX ", LAPIC_ADDR);
However, the spec says
"OEM ID: A string that identifies the manufacturer of the system hardware."
(Table 4-2, page 42)
so "COREBOOT" doesn't match the spec, we should use the hardware vendor name.
Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID"
(truncate/fill it to 8 characters as per spec).
Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID",
and truncate/fill it to 12 characters as per spec, if needed.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/arch/x86.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Factor out the ROM decode enable functionality into bootblock.c and
handle it via the usual TINY_BOOTBLOCK mechanism.
Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The files debug.asl, globutil.asl, and statdef.asl are duplicated in
many K8/Fam10h boards. However, they're neither board-specific nor
K8/Fam10h-specific nor AMD-specific, so move them to src/arch/i386/acpi.
debug.asl contains generic chunks for I/O port 0x80 handling, and debug
output over serial port (init COM port, send byte, send string, etc).
globutil.asl contains utility methods for string comparison, string length
and similar stuff.
statdef.asl contains generic ACPI bit definitions / status codes from
the ACPI spec (not board- or chipset-specific).
This patch was mostly generated by:
mkdir src/arch/i386/acpi
svn add src/arch/i386/acpi
svn cp src/mainboard/amd/dbm690t/acpi/debug.asl src/arch/i386/acpi/
svn cp src/mainboard/amd/dbm690t/acpi/globutil.asl src/arch/i386/acpi/
svn cp src/mainboard/amd/dbm690t/acpi/statdef.asl src/arch/i386/acpi/
cd src/mainboard
find . -name debug.asl -exec svn rm {} \;
find . -name globutil.asl -exec svn rm {} \;
find . -name statdef.asl -exec svn rm {} \;
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
into the socket directories, and remove it from the individual boards.
Do the same for Intel CPUs/sockets where all boards use CAR.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only to be used by developers
during bringup (and thus added manually to romstage.c and removed before
the board gets committed). This method seems to be preferred from what I
have heard on IRC / mailing list in the past.
Or, we add the ram_check() somewhere globally and allow the user to enable
it via menuconfig (possibly only if EXPERT is selected).
Either way, the current method of spreading the calls all over the place is
not really the way to go.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6114 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, remove some less useful comments, some dead code / unused functions.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
