CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region
in case of firmware update. Ensure that the size of the regions match
so that we do not have situations where ME_RW_A/B firmware grows
bigger than what CSE_RW can hold.
BUG=b:189177538
Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: I4da677da2e24b0398d04786e71490611db635ead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds support for allowing mainboards to stitch CSE
components during build time instead of adding a pre-built CSE
binary. Several Kconfig options are added to allow mainboard to
provide the file names for different CSE region components. This makes
use of the newly added cse_serger and cse_fpt tools to create
following partitions:
1. BP1 - RO
2. BP2 - RW
3. Layout
In addition to this, it accepts CSE data partition as an input using
Kconfig CSE_DATA_FILE. All these partitions are then assembled
together as per the following mainboard FMAP regions:
1. BP1(RO) : CSE_RO
2. BP2(RW) : CSE_RW
3. Layout : CSE_LAYOUT
4. Data : CSE_DATA
Finally, it generates the target $(OBJ_ME_BIN) which is used to put
together the binary in final coreboot.rom image.
Several helper functions are added to soc/intel/Makefile.inc to allow
SoCs to define which components use:
1. Decomposed files: Files decomposed from Intel release CSE binary in
FPT format.
2. Input files: Mainboard provided input files using corresponding
Kconfigs.
3. Dummy: Components that are required to have dummy entries in
BPDT header.
These helpers are added to soc/intel/Makefile.inc to ensure that the
functions are defined by the time the invocations are encountered in
SoC Makefile.inc.
BUG=b:189177580
Change-Id: I8359cd49ad256703285e55bc4319c6e9c9fccb67
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In the following changes, CSE binary for some platforms will be
stitched at build time instead of adding a pre-built binary. This
change adds a new Kconfig `STITCH_ME_BIN` which allows mainboard to
select if it wants to stitch CSE binary instead of adding a pre-built
one. In this case, ME_BIN_PATH is not visible to user and instead
mainboard and/or SoC code is expected to provide the recipe for
stitching the CSE image.
BUG=b:189177580
Change-Id: I78ab377e110610f9ef4d86a2b6eeb4113897df85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make the `get_cst_entries()` function provide a read-only pointer. Also,
constify the actual data where applicable.
Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Return a read-only pointer from the `soc_get_cstate_map()` function.
Also, constify the actual data where applicable.
Change-Id: I7d46f1e373971c789eaf1eb582e9aa2d3f661785
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry`
functions don't modify the provided C-state information. So, make the
pointer parameters read-only to enforce this. Also constify arguments
where possible.
Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A regular assignment works just as well and also allows type-checking.
Change-Id: Id772771f000ba3bad5d4af05f5651c0f0ee43d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
With the recent addition of SMBIOS table 20, the cbmem area on
google/brya0 overflows and
ERROR: Increase SMBIOS size
SMBIOS tables: 2128 bytes.
is seen in the logs.
Therefore, double the size of the SMBIOS area from 2 KiB to 4 KiB to
accomodate more tables as needed. This happens during ramstage so 2k
is not a big deal at this point.
Change-Id: I43aa6a88d176e783cc9a4441b35b8d608c4101cd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Don't use a typedef for the embedded_firmware struct so that it's
clearer that this is a struct.
TEST=Timeless build for google/guybrush results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The element at offset 0x14 in the embedded_firmware struct is the
pointer to the combo PSP directory header, so rename it from comboable
to combo_psp_directory to clarify that this is not a flag, but a pointer
to a data structure. Also rename psp_entry to psp_directory since it
points to the PSP directory table.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
As long as there is only one PCI segment we do not need
more complicated MCFG generation.
Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The push/pop of %ebx was only added because smm_stub saves the canary
value in it. Now that we no longer use cpu_info in smm, we no longer
need to save the register.
BUG=b:179699789
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I554dbe016db8b1c61246c8ffc7fa252b2542ba92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Now that cpu_info() is no longer used by COOP_MULTITASKING, we no
longer need to set up cpu_info in SMM. When using CPU_INFO_V2, if
something does manage to call cpu_info() while executing in SMM mode,
the %gs segment is disabled, so it will generate an exception.
BUG=b:179699789
TEST=Boot guybrush to OS with threads enabled
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id64f32cc63082880a92dab6deb473431b2238cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Since cpu_info() is no longer required to use threads, we no longer need
to initialize it in romstage or earlier. This code was also incomplete
since it didn't initialize the %gs segment.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I615b718e9f035ca68ecca9f57d7f4121db0c83b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We only ever start and execute threads on the BSP. By explicitly
checking to see if the CPU is the BSP we can remove the dependency on
cpu_info. With this change we can in theory enable threads in all
stages.
BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and verify coop multithreading still works
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iea4622d52c36d529e100b7ea55f32c334acfdf3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58199
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CNVi (14.3) to IRQ Table to stop dmesg error:
iwlwifi 0000:00:14.3: can't derive routing for PCI INT F
iwlwifi 0000:00:14.3: PCI INT F: not connected
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5b793997f9ea954217871eb4656dacf6abe77e74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain
to toggle during a switch from DP Alt to TBT Alt modes.
Contrary to DS specifying it may be left unconfigured, hence floating, there are instances
seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp).
Hence configure it to LOW.
Branch=none
Bug=none
Test=Boot to OS, connect TBT dock which enumerates in DP Alt,
Login, TBT dock enumerates in TBT Alt
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
For older CPU models where CPUID leaf 0xb is not supported, use
initial LAPIC ID from CPUID instead of LAPIC register space to
to detect if logical CPU is a hyperthreading sibling. The one
in LAPIC space is more complex to read, and might not reflect
CPU topology as it can be modified in XAPIC mode.
Change-Id: I8c458824db1ea66948126622a3e0d0604e391e4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It is not a requirement to have X2APIC mode enabled to use
CPUID leaf 0xb EDX to detect logical CPU is a hyperthreading
sibling.
Change-Id: I288f2df5a392c396f92bb6d18908df35de55915d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Remove code, which was only needed for B and C2 stepping
of P54C. The linux kernel source has commentary on X86_BUG_11AP:
* See if we have a good local APIC by checking for buggy Pentia,
* i.e. all B steppings and the C2 stepping of P54C when using their
* integrated APIC (see 11AP erratum in "Pentium Processor
* Specification Update")
Change-Id: Iec10335f603674bcef2e7494831cf11200795d38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All boards with DRIVERS_GENERIC_IOAPIC select it.
Presumably the related configuration of routing IRQ0 when
IOAPIC is enabled should be always done to provide i8259
legacy compatibility for payloads.
Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the common ACPI code to reduce code duplication.
After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state
table generation (as of commit c2540a9) and the number reduces from 10
to 7 entries.
Also, remnants of P_BLK support missed in CB:58096 will vanish.
Tested on google/fizz: no errors in dmesg, ACPI tables remain the same
(except PSS, as mentioned above).
Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Apollo Lake and Gemini Lake do not have a hardware PM ACPI timer but
only uCode PM Timer emulation. Add a Kconfig `NO_PM_ACPI_TIMER` denoting
SoCs without PM Timer and make it mutually exclusive with the Kconfig
`USE_PM_ACPI_TIMER`.
This is partly redundant to `PM_ACPI_TIMER_OPTIONAL`, which will be
dropped in the follow-up change, though.
Change-Id: Ic323bbfb7089c53a6f22724910a0ff3df8904ebd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
uCode PM Timer emulation is only needed when the hardware PM ACPI timer
is disabled. Also, since it redirects any register accesses to uCode,
it overrides the hardware PM Timer. Thus, only enable emulation
when required.
Change-Id: I60a775bd6eb4206750f606ce8a8777d2e2dfb579
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Disable the PM ACPI timer during PMC init, when `USE_PM_ACPI_TIMER` is
disabled. This is done to bring SKL, CNL, DNV in line with the other
platforms, in order to transition handling of the PM timer from FSP to
coreboot in the follow-up changes.
For SKL and CNL, this temporarly redundantly disables the PM Timer,
since FSP does that, too. This redundancy is resolved in the follow-up.
Change-Id: I47280cd670a96c8fa5af107986496234f04e1f77
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since it's just a one-liner, implement disabling of the ACPI timer in
soc code. This reduces complexity.
Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move disabling of PM Timer to SoC PMC code.
The original reason for placing that in `finalize` [1] was FSP hanging
due to use of the PM timer without enabling timer emulation first in
coreboot, which was added later [2].
[1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable
XTAL OSC shutdown)
[2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation
on all CPUs)
Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently, only the PM1_STS mask gets passed to `acpi_fill_soc_wake`. To
be able to override the GPE0_STS mask as well, also pass that one. To
accomplish that, pointers to the variables are passed now.
Change-Id: If9f28cf054ae8b602c0587e4dd4a13a4aba810c7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
`RTC_EN` is in the RTC well* so we can rely on the actual register
content instead of statically overriding it. Drop it from the static
wake bits mask.
* Tested on clevo/l140cu
Change-Id: Ia0ae71f0a472513233bc0fd5625faf15bf86beaf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific
handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in
common code.
Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Switch to common GNVS. No additional fields to those being present in
common GNVS are used by any SKL/KBL device. Thus, they're dropped
completely.
Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Add the SGX fields to the GNVS. This is required for Skylake to use the
common GNVS.
Change-Id: I0077260b7eb1bc2b2fe2af69ac039b38ca0e7423
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ
table. None of these boards do it, so specifying this value achieves
absolutely nothing. Drop it to prevent further useless copy-pasting.
Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
ExtINT is related to external PIC mode i8259 interrupts,
they should be delivered to one CPU (BSP) only.
Change-Id: I78490d2cbe3d9f52e10ef2471508263fd6c146ba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base
addresses of the I2C controllers, so align Stoneyridge with this. The
ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now
since this might change behavior in the OS and would also change the
resulting binary of a timeless build.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ACPI 5.0A it is allowed to disable the ACPI Timer, when the
according FADT flag `ACPI_FADT_PLATFORM_CLOCK` is unset.
Starting with Skylake, most platforms (except Xeon-SP) support PM Timer
emulation, so even legacy OSes and payloads should work fine with the
hardware PM Timer disabled. However, when the `TMR_STS` functionality
is required, some legacy OSes might still not work (properly).
Add a note about this to the Kconfig help.
Change-Id: I53f1814113902124779ed85da030374439570688
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
The FADT contains a flag `ACPI_FADT_PLATFORM_CLOCK` telling the OSPM if
a specification-compliant PM Timer is present. Currently, this flag is
set regardless of the timer being enabled or disabled.
To be specification-compliant, only set that flag, when the hardware PM
Timer is enabled. This changes behaviour of all mainboards defaulting to
USE_PM_ACPI_TIMER=n.
Note: On platforms supporting uCode PM ACPI Timer emulation, this is
required, too, because emulation does not support `TMR_STS`. Any
OS or software checking this flag and thus relying on the overflow
flag would not work (properly).
Change-Id: Id2e5d69b5515c21e6ce922dab2cb88b494c65ebe
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Follow the spec to correct the WWAN poweron and powerdown sequences.
BUG=b:195625346
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I232d283a9d6093f5da64fcdce44e5cb640e3df0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58319
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support GL9763E as a eMMC boot disk
BRANCH=none
BUG=b:202192686
TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taeko.
Cq-Depend: chromium:3153210
Signed-off-by: Kevin.Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I5db2b229ce1bbea54efe15f5288f13f8d4656899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
The definition of those bits changed between Picasso and Renoir/Cezanne
so add a comment where those bit definitions are used as well.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The writes were originally added due to being part of the initialization
sequence in the reference code, but coreboot already has those registers
cleared by the time we reach this part of the code, so we can drop these
redundant writes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I43344460e5355664841d77daf1df3fd386e047e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Move the actual implementation of configure_espi_with_mb_hook out of the
header file and into the espi_util.c file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1106e69a52bf329a41e8e12fd09db846310b102a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
If a system doesn't use eSPI or has the eSPI interface already
configured in verstage on PSP, not calling configure_espi_with_mb_hook
from fch_pre_init makes it a bit more obvious that the eSPI interface
initialization will be skipped.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Rename configure_espi to configure_espi_with_mb_hook to clarify that
this function will call into the mb_set_up_early_espi function in the
mainboard-specific code if it exists.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Now that the I2C[ABCD]_BASE_ADDRESS defines aren't macros that calculate
the MMIO addresses any more, those defines can also be used in the ACPI
code.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7de2f83dc2f8061d8f1735caf10314bcddb2d3fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The I2C_BUS_ADDRESS(x) macro isn't used to iterate over the I2C
controller base addresses, so drop this and use the fixed MMIO address
for the I2C[ABCD]_BASE_ADDRESS defines instead which also allows using
those defines in the ACPI code.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idd7484a0322dc5167cbb7fdcd9a2583f0dbed50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
I2C_BASE_ADDRESS is the beginning of the MMIO space that contains the
I2C controllers MMIO. I2C[ABCD]_BASE_ADDRESS are the base addresses of
the 4 I2C controllers, so use I2CA_BASE_ADDRESS instead here.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie8d6a438f76cd33929f5070f9ec6b2f280f471a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Before this patch the reservation of the MMIO region of the I2C
controllers was done in the LPC controller PCI device despite the I2C
controllers already being devices in the devicetree. This patch
implements this functionality as read_resources function of the I2C
device instead. This will only reserve the memory when the I2C devices
are enabled in devicetree which is a change from the previous behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change splits CSE metadata structure (added to CBFS) into two
separate CBFS files (me_rw.hash and me_rw.version). Since `struct
cse_rw_metadata` is now used, it is dropped completely.
This change is being made in order to prepare for the upcoming changes
to stitch CSE binary at build time. Since the binary might not be
available pre-built, it complicates the order of operations for the
addition of CSE metadata structure and declaring hash and version as
CPPFLAGS_common. Instead rules can be enabled for individual CBFS file
targets for hash and version that ensure proper ordering as well.
BUG=b:184892226
TEST=Ensured that update works correctly on brya by forcing version
mismatch. In case of version match, no update is triggered.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7c9bb165e6a64415affcd0b3331628092195fa0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set POWER_CTL MSR bit 18 to enable Energy/Performance Bias control.
TEST=Boot and verify EPB is enabled in coreboot log:
cpu: energy policy set to 6
Change-Id: Ibd1db77b5b63cb6e2b0ad9d2f79caa2f3b576ead
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The SHRM region needs to be 4 byte aligned, which make enabling
compression slightly more complicated. We need to map it to cached
memory before loading it and flushing to memory (in aligned chunks)
then remapping the address space back to device memory before
beginning execution of the SHRM region.
Also, did some cleanup in this file based on comments in CB:49392.
BUG=b:182963902
BRANCH=None
TEST=Make sure we can still boot to kernel on herobrine
Change-Id: Iaad8a8a02abe40bd01766d94ef0b61aac7671936
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Implement the read_resources function for the UART devices so that the
resource allocator knows about their fixed MMIO resources when enabled.
TEST=UART still works on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ffddee3f5f4281aca98ddfcefa639dfb7a38dae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 6260bf712a.
Reason for revert: This CL did not handle Intel GPIO correctly. We need
to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel
SoC.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure I2C high / low time in the device tree to ensure Touchpad
I2C CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
Touch Pad CLK: 389.2 KHz
BUG=b:202787528
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Change-Id: I0f9d062fc611de0062a39849aee1174268391682
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Since espi_util.c is also built in the case of verstage on PSP, we can
just add it to all stages.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65e07c356aac73c5de2d9ce5582434872a223c19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The bits REMOTE_IRR and SEND_PENDING are documented as read-only,
and reserved bits should not be modified either.
Change-Id: I6bcb9eb990debe169340a0bfe662158b62a8f4dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The bit LAPIC_SPIV_ENABLE returns 0 after reset even though
LAPIC has not been temporarily disabled.
Change-Id: Id261bc68fe9d1b1b0e5a3ef599a8f33a686d283b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Only the enable_lapic() part is required while doing
SMP init. Also disable_lapic() must not be called if
we rely on LAPIC for timer source.
Change-Id: Ib5e37c1a0a91fa4e9542141aa74f1c1876fee94e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:
config VGA_BIOS_FILE
default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200
Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.
Also, update autoport to not generate `VGA_BIOS_FILE` defaults.
Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
If available, use data from MEMINFO CBMEM table and saved handles
from type 17/19 tables to generate type 20 (Memory Device Mapped
Address) SMBIOS table.
Windows 10/11 and some other OSes use this table to report the total
memory available on a given device.
Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58271
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
microcode_file could be NULL and passed to get_microcode_size,
this was detected by klocwork scan.
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no need to mask out bit 11, as it is unconditionally set. For
some reason, this changes the resulting coreboot image. Also simplify
another PCI operation with a redundant AND-mask.
Change-Id: I5492acd5f9c61db83a07ce7c1f6b887768c3eadf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
variant_has_pcie_wwan helper returns true if gpp_bridge_2 PCIe engine is
enabled. On some variants, this engine is used by storage controllers.
Fix it by adding a weak override that returns no PCIe WWAN by default.
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that PCIe WWAN is
enumerated on boards where it is stuffed.
Change-Id: I07b9dd8fc5c8c3e1557f9268c1176d4a3cade1af
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous
I2C configuration copied from Puff.
BUG=b:202195805
TEST=Boot scout, verify no more errors due to missing I2C devices
Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
S3 is not currently functional on Guybrush. Remove support from ACPI.
BUG=b:202401767 b:181766974
TEST=Boot Guybrush
Confirm 'deep' is not in /sys/power/mem_sleep
Confirm S0ix suspend/resume still works
BRANCH=None
Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
`cse_fw_update()` is currently checking whether an update is required
by comparing versions once and then again comparing versions later in
`cse_is_downgrade_instance()` to determine if the update is an upgrade
or downgrade. Additionally, if CSE RW partition is corrupt (determined
based on `cse_is_rw_bp_sign_valid()`), `cse_is_downgrade_instance()`
ends up using the corrupted version information to determine if it is
a downgrade instance.
This change reorganizes the firmware update checks to return different
status values:
1. CSE_UPDATE_NOT_REQUIRED: No update required. Versions match.
2. CSE_UPDATE_UPGRADE: Update required and it is an upgrade.
3. CSE_UPDATE_DOWNGRADE: Update required and it is a
downgrade (requires data clear).
4. CSE_UPDATE_CORRUPTED: `cse_is_rw_bp_sign_valid()` failed and hence
requires data clear.
5. CSE_UPDATE_METADATA_ERROR: Unable to read CSE metadata from CBFS.
This change also prepares the file for follow up changes which
completely drop cse_rw_metadata structure.
BUG=b:184892226
Change-Id: Iabecab8e373e65a11ba7fe1bfc125467571a0588
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58157
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.
Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to handle S0ix entry and exit notifications by adding the
corresponding _DSM functions. The function indices are chosen based on
the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside
the notification functions perform any mainboard specific S0ix entry and
exit actions.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the notification
functions are invoked on S0ix entry and exit. Perform suspend/resume
cycles for multiple iterations.
Change-Id: I3014551f6e281d466628559453a0141a3dd6abad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the PCH serial IO settings, suitable for this mainboard.
Change-Id: I3c9915b2d52fbc6a15ac1e68c77bfb3983f7b1cd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Correct the USB settings, suitable for this mainboard.
Change-Id: I691d91d2a76e27b8efdc18eeae737a78e9ae38fa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard has its own coreboot ready LED. The LED is switched
on via GPIO GPP_F20.
Change-Id: I3570d691e90d2cb6e11b856b876f0327da118522
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enabling clock gating for CGPLL to lower power consumption in S3
and S0i3 states. See also: Cezanne PPR chapter 7, rev 3.03.
BUG=b:185273565
TEST=iotools mmio_read32 0xfed80e2c and 0e30 show clk gating
enabled and suspend_stress_test works.
Change-Id: I33cbdeec62e49db90b680da37e5028df03a9c015
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Init overridetree based on the schematics.
Refer to brya0/overridetree.cb to update the settings of the devices
including DPTF, WIFI, NAU8825 and etc.
Refer to kano/overridetree.cb to update the SSD settings (pcie4_0).
TODO: DPTF and USB positions will be further updated later.
BUG=none
TEST=Build Pass
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
HPD event may not be ready when configuring TCSS mux for DP,
check if any DP device is connected and wait for HPD ready before
TCSS configuration. Remove unnecessary dependency on mainboard
functions, use generic interface which provides USB-C mux
operations.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for
Brya. Build coreboot and update your Brya. Boot Brya with USB-C
display connected, you should find `HPD ready after %lu ms` and
`Port C%zd is configured to DP mode!` in coreboot log. Display
should show screen in developer mode or recovery mode.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently override speed config is applied only for non EM100 cases.
For EM100 case, override speed board version defaults to 0 leading to
"comparison of unsigned expression >= 0 is always true" error. Fix this
error by defining the override speed config for both EM100 and non-EM100
use-cases.
BUG=None
TEST=Build Guybrush for both EM100 and non-EM100 cases.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.
For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.
Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
No need for dynamic config (and the additional RAM training time)
on a Chromebox; always use high power/high performance mode.
Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
No need for dynamic config (and the additional RAM training time)
on a Chromebox; always use high power/high performance mode.
Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support to override SPI fast speeds based on board version from both
bootblock and verstage. Overrides apply for Guybrush only and SPI speed
is overridden from 66 MHz to 100 MHz starting board version 4. This will
help to improve the boot time on board version by ~60 ms and still allow
the old boards to boot with 66 MHz.
BUG=b:199779306
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add support to override SPI ROM fast speed based on board version. This
will allow boards to start at lower speeds during bringup and then
switch to higher speeds after assessing the signal integrity. Also
implement a default no-op override.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently all SPI speed configurations are done through EFS at build
time. There is a need to apply SPI speed overrides at run-time - eg.
based on board version after assessing the signal integrity. This
override configuration can be carried out by PSP verstage and bootblock.
Export the APIs to set and read SPI speeds from both PSP verstage and
bootblock.
BUG=None
TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I281531e506b56173471b918c746f58d1ad97162c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tracker is a debugging tool, include AP/INFRA/PERI tracker.
When bus timeout occurs, the system reboots and latches some
values which could be used for debug.
Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: I82f8e6e5f8ccb7f8246cae45a01a3ddd5f2966f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58244
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tracker is a debugging tool, include AP/INFRA/PERI tracker.
When bus timeout occurs, the system reboots and latches some
values which could be used for debug.
Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is the wrong register offset printed in the debug log when the
data register is written:
'lpc_tpm: Write reg 0x18 with 0xnn' should be
'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access.
This can be confusing when searching for issues with the help of the
TPM debug messages since the code itself is correct. Fix this error.
Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Some poppy variants did not select a system type, which led to the
default desktop type being set. Select the best fit enclosure type
for each variant.
Alphabetize the variant-specific options for improved readability.
Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get partially filled.
Test: dumped SSDT before and after do not differ.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the DRAM population is fixed to both channels on all mc_ehl boards
there is no need to have this 'half_populated' variable at all.
Simply use a fixed 'false' in the call of 'memcfg_init()' and delete
this variable here.
Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The preferred location for the SPD data on mc_ehl based boards is the
HW-Info data structure. Inside this structure there is a field of 128
bytes available for the SPD data. So in order to use it construct a
buffer in memory which is 256 bytes long (as FSP requests minimum 256
bytes for the SPD data) and where the upper 128 bytes are taken from
HW-Info holding the needed timing parameters for LPDDR4.
If there is a case where HW-Info is not accessible or where the
contained SPD data is not valid (by checking the CRC in HW-Info SPD)
fall back to fixed SPD data set in CBFS.
Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=b:202480992
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
For 1 bit long bit fields an unsigned type should be used. In this case
uint32_t is used instead of a generic unsigned int for both consistency
reasons with the rest of the file and to clarify that the bits will be
packed into a 32 bit memory location.
TEST=Resulting image of a timeless build for google/guybrush results in
identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic630d1709174d90336746bc37da504437c12643c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ia196906d3c2636742ae90160a224354e8df7863a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add a space before the `*/` C-style comment ending.
Change-Id: Ic8928286c8237808b9e380e4393078792589615d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A"
BUG=b:198716348
TEST=Build nipperkin, codec is functional with new machine driver.
Cq-Depend: chromium:3195465
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.
BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as
specified in the DXIO descriptors. This change requires FSP version
1.0.4 revision 2 otherwise setting this value does affect any FSP
behavior.
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and
PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will
eventually be factored out and moved to the Cezanne SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can
remove the clearing of that bit. This is split off from the previous
patch to be able to use timeless build to verify that the previous patch
didn't change any behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
It's hard to understand what this code is doing because it uses hard
coded values, so use the register and bit defines instead.
BUG=none
TEST=Timeless build for guybrush results in identical binary.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib109efe679560604ff8209b4177611eb2aa9ebdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The definitions of bit 9 and 10 somehow got swapped between Picasso and
Renoir/Cezanne, so put those in the Cezanne-specific header file. The
reference code writes the same values to the raw bits in both, so we
probably would still get away with putting this into the common header,
but it's better to keep the defines consistent with the documentation in
all cases.
Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03
and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Fizz's USB ACPI code is intended to allow the OS to control port
charging power, but since Fizz's ports are dumb (vs smart), it
controls power to the port itself. The end result is that active
ports become disabled when rebooting from Windows (10/11), and
power is not restored until the device is powered down (a warm
reboot is not sufficient).
Subsequent Chromebox models (eg, Puff-based variants) don't bother
with EC-controlled USB port power, so just drop it since it's
problematic and provides no benefit.
Test: boot Windows 10/11, reboot, observe active USB ports still
functional (eg, USB KB still works)
Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Populate a memory_info struct with PEI and SPD data, in order to inject
the CBMEM_INFO table necessary to populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older Sandy Bridge
MRC binary doesn't populate the pei_data struct with all the info
needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Caroline uses a Wacom digitizer, so adjust the ACPI HID
so that the proper drivers attach under Windows/Linux.
Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Before attempting another commit 6260bf71 (vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs
GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in
verstage.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. Fix PCIe slot capabilities not being really read from an IIO root
port device. The Hot-Plug capability of IIO root port cannot be
enabled due to FSP limitation (v2.1-0.2.2.0), but the code should
reflect the true capabilities by reading the root port device's CSR.
2. Initialize the characteristics flags to 0 in the for-loop to fix the
issue of the flags values persists to the next iterations.
Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results.
For example without the fix it shows 'Hot-plug devices are supported'
but in fact it's not:
System Slot Information
Designation: SSD1_M2_Data_Drive
Type: x4 PCI Express 3 x4
Current Usage: Available
Length: Short
ID: 1
Characteristics:
3.3 V is provided
PME signal is supported
Hot-plug devices are supported
Bus Address: 0000:00:1d.0
With the fix it shows the correct result:
Handle 0x0016, DMI type 9, 19 bytes
System Slot Information
Designation: SSD1_M2_Data_Drive
Type: x4 PCI Express 3 x4
Current Usage: Available
Length: Short
ID: 1
Characteristics:
3.3 V is provided
PME signal is supported
Bus Address: 0000:00:1d.0
Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason, we have to adjust the PIR8
register (0x3150) which is responsible for PCIe device 25h. The bridge
is connected to PCIe root port 7.
The following routing is required:
INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#
TEST:
- Boot into system software
Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In upcoming patches, we need mainboard specific adjustments.
Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enable LPC ComB on this mainboard.
TEST:
- Boot Linux and check with 'dmesg | grep tty'
Change-Id: I7ec58685a723c177df18144011934b206e6425d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard uses an eSPI-to-LPC bridge for console output. For this
reason, the internal LPSS UART must be disabled.
Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Set the GPIOs according to the circuit diagram for this mainboard.
Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard has only SATA Port 1 available with no device sleep
feature.
Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard has SD slot available and therefore it should be enabled.
Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus
as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC
only supports the standard speed.
TEST:
- Console Log shows no errors for RX6110SA during I2C2 init
- Finalize device for I2C 00:32 shows correct date and time
Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since this variant uses different DDR4 devices compared to mc_ehl1 in a
memory down configuration, the SPD data file must be adapted.
In a first configuration we use Micron MT53D512M32D2NP modules.
Following values were adjusted according to this board characteristic
and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4
SDRAM Modules JEDEC Spec and the Specification for this Micron modules
itself:
- SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1
- SPD Byte 5 - different Row and Column Address Bits
- SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab
- SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb
Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Return the package with a value for the dptf user space service.
This is required in write tpch method for pch device under dptf
driver.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I64e1bb04a6115c7f93c84a5d6644101ac1d3d8ba
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology. The OS is informed to reduce latency for upstream
ports while connecting USB4/TBT devices.
BUG=b:199757442
TEST=It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add various methods support for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I2d40fff98cb4eb9144d55fd5383d9946e4cb0558
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add ALC5682-VS codec support in corori.
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of ssfc.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:201372531, b:194436265
TEST=ALC5682-VD/ALC5682-VS audio codec can work.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2f3edb0b594066714b42050a411103a215e68b12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
nipperkin has different H/W topology to guybrush that the eMMC device
is on a different GPP:
guybrush: GPP3
nipperkin: GPP2
Hence we need to enable RTD3 for nipperkin additionally which refers
to this one:
https://review.coreboot.org/c/coreboot/+/54967
BUG=b:200246826
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
run suspend test on eMMC sku
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Drop overrides from `soc_fill_fadt` that do not differ from what common
ACPI code already sets.
Change-Id: I7a5f43f844b12ff0e9bc5c7426170383209c8e0a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Before attempting another commit 6260bf71 ("vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants
all program EC_IN_RW as an input GPIO in bootblock so that it can be read
from in verstage.
Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
These will be used in the follow-up change.
Change-Id: I4723ffaf0adff8cb5b1717600ed4d1634768e2b7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch enables eNEM flow for ADL-M
TEST=Able to build and boot ADL-M RVP using eNEM mode.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD
is still detected correctly by SeaBIOS (version 1.14.1).
Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
BT offload hardware design is using only i2s0 pins. Need to disable
i2s2 pins which are not used. As per the hardware spec there is an OR
operation between vgpio and physical gpio pins related to i2s2. During
BT offload configuring the i2s2 pins to its native function is causing
offload issue on proto 2 boards.
BUG=b:201736222
TEST=Verified BT offload on brya on proto 1 and proto 2.
Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
As we checked the panel doesn't display firmware screen if we hold
GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy
uses the built-in touch screen on the panel, the panel seems like
under reset state by the TOUCHSCREEN_RESET signal.
This change sets default GPP_D5 level to high for bugzzy.
BUG=b:None
BRANCH=dedede
TEST=built and verified bugzzy showed firmware screen
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch adds the setting of PsysPmax to 145W according to
the brya board design.
BUG=b:195615830
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Tested by adding gfx register on system76/gaze16 and booting Windows.
Display settings has a brightness setting, and can change the brightness
level.
Change-Id: Id8b14c0b4a7a681dc6cb95778c12a006a7e31373
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Now that the vb2ex_hwcrypto_* stub functions are included in vboot fwlib
(CL:2353775), we can remove the same stubs from coreboot.
BUG=none
TEST=emerge-brya coreboot
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I62bdc647eb3e34c581cc1b8d15e7f271211e6156
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There are 4 GPE0 STS/EN register pairs, each 32 bit wide. However, SoC
code sets a GPE0 block size of 4 byte length instead of 32 byte.
The resulting value of `x_gpe0_blk.bit_with` is wrong, too (32 bit
instead of 256 bit).
Drop the overrides and let common ACPI code set the correct values based
on `GPE0_REG_MAX`.
Change-Id: I45ee0f6678784c292ee3ed3446bf3c0f2d53b633
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When "SpeedStep" is disabled on an Intel Atom C3538,
the maximum CPU clock speed is always 800 MHz(min CPU clock).
Оperating system cannot change the frequency.
Avoid this issue allow "Intel Speed step" technology
for processors that do not have "Intel Turbo Boost".
Signed-off-by: Dmitry Ponamorev <dponamorev@gmail.com>
Change-Id: Ia922e45c12e4239f1d59617193cdbde2a813e7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
This patch enables bootblock compression on SC7280. In my tests, that
makes it boot roughly 10ms faster (which isn't much, but... might as
well take it).
Ref link: https://review.coreboot.org/c/coreboot/+/45855
BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.
Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
google_chromeec_usb_pd_get_info() is used in ec.c only. Make it
static and drop from ec.h.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I4b3df4223d5c26ea1c1a52b26f7d49fa4c947de8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add API to allow AP to send the command to EC to enter DP ALT mode
and API to wait for DP HPD event.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name. Build
coreboot and update your system. Boot the system you will find below
message in the coreboot log with or without USB-C display connected:
'HPD ready after %lu ms' or 'HPD not ready after %ldms. Abort.'.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Id11510c1ff58579ae2cddfe5a4d69646fd84f5c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Update google_chromeec_pd_get_amode() to return bitmask.
2. Update google_chromeec_wait_for_displayport() to handle the
updated return value of google_chromeec_pd_get_amode().
3. Drop google_chromeec_pd_get_amode() from ec.h and make it static
because it's not used outside of ec.c.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: I6020c4305e30018d4c97d862c16e8d642c951765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add parameter `active_cable` to obtain the cable type
(active or passive) which is needed for USB-C configuration for
some SoCs (at least Intel TGL and ADL), change the function name to
google_chromeec_usb_pd_get_info() for better understanding.
BUG=b:192947843
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ie91a3096d49d5dde75e60ab0f2f38152cef720f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create a generic interface to allow any of the EC or other drivers
to provide set of USB-C mux operations.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ic5435f2054d1c9f114b06c3b4643e34713290e0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch skips setting D0I3 bit for all HECI devices by FSP.
BUG=b:200644229
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.
Change-Id: I86d61c49b8f187611efd495712ad901184665f31
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57815
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`heci_finalize` ensures to put all heci devices to D3 by setting the
D0i3 bit prior to booting to the OS.
BUG=b:200644229
TEST=Verified D0i3 bit is set for all HECI devices prior to booting
to OS.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I86d5959646522f9a2169bf13ae04d88b8f685e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch creates a helper function in cse common code block to check
the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and
CSE_4.
Currently cse common code is only able to read the device state of
`PCH_DEVFN_CSE` CSE device alone.
Additionally, print `slot` and 'func' number of CSE devices in case
the device is either disable or hidden.
BUG=b:200644229
TEST=Able to build and boot ADLRVP-P with this patch where the serial
message listed the CSE devices that are disabled in the device tree
as below:
HECI: CSE device 16.01 is disabled
HECI: CSE device 16.04 is disabled
HECI: CSE device 16.05 is disabled
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch ensures to pass cse device function number as argument for
`set_cse_device_state()` to allow coreboot to perform enable/disable of
D0i3 bit for all CSE devices to put the CSE device to Idle state or
Active state.
BUG=b:200644229
TEST= Able to build and boot ADLRVP where `set_cse_device_state()` is
able to put the CSE device toidle state or active state based on `devfn`
as argument.
Change-Id: Ibe819e690c47453eaee02e435525a25b576232b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CPU_INFO_V2 now encapsulates the cpu_info requirements. They no longer
need to leak through to thread.c. This allows us to remove the alignment
requirement.
BUG=b:179699789
TEST=Reboot stress test guybrush 50 times.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0af91feddcbd93b7f7d0f17009034bd1868d5aef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This reverts commit 5f80e7c764.
The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2
into this patch to satisfy the dependency.
BUG=b:194391185, b:179699789
TEST=reboot stress test guybrush for 50 iterations.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
CPU_INFO_V2 changes the behavior of cpu_info(). There is now only 1
cpu_info struct per cpu. This means that we no longer need to allocate
it at the top of each threads stack.
We can now in theory remove the CONFIG_STACK_SIZE alignment on the
thread stack sizes. We can also in theory use threads in SMM if you are
feeling venturesome.
BUG=b:194391185, b:179699789
TEST=Perform reboot stress test on guybrush with COOP_MULTITASKING
enabled.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5e04d254a00db43714ec60ebed7c4aa90e23190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There is currently a fundamental flaw in the current cpu_info()
implementation. It assumes that current stack is CONFIG_STACK_SIZE
aligned. This assumption breaks down when performing SMM relocation.
The first step in performing SMM relocation is changing the SMBASE. This
is accomplished by installing the smmstub at 0x00038000, which is the
default SMM entry point. The stub is configured to set up a new stack
with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
of smm_do_relocation located in RAMSTAGE RAM.
This means that when smm_do_relocation is executed, it is running in SMM
with a different sized stack. When cpu_info() gets called it will be
using CONFIG_STACK_SIZE to calculate the location of the cpu_info
struct. This results in reading random memory. Since cpu_info() has to
run in multiple environments, we can't use a compile time constant to
locate the cpu_info struct.
This CL introduces a new way of locating cpu_info. It uses a per-cpu
segment descriptor that points to a per-cpu segment that is allocated on
the stack. By using a segment descriptor to point to the per-cpu data,
we no longer need to calculate the location of the cpu_info struct. This
has the following advantages:
* Stacks no longer need to be CONFIG_STACK_SIZE aligned.
* Accessing an unconfigured segment will result in an exception. This
ensures no one can call cpu_info() from an unsupported environment.
* Segment selectors are cleared when entering SMM and restored when
leaving SMM.
* There is a 1:1 mapping between cpu and cpu_info. When using
COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
each thread's stack. This no longer needs to happen.
This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so
reviewers can feel more comfortable knowing most of the CL is a no-op. I
would eventually like to remove most of the guards though.
This CL does not touch the LEGACY_SMP_INIT code path. I don't have any
way of testing it.
The %gs segment was chosen over the %fs segment because it's what the
linux kernel uses for per-cpu data in x86_64 mode.
BUG=b:194391185, b:179699789
TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct
%gs segment. Verify cpu_info looks sane. Verify booting to the OS
works correctly with COOP_MULTITASKING enabled.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Some distributions (e.g. NixOS, Debian) are actively working on getting
rid of EOL Python 2. Since `SplitFspBin.py` supports both Python 2 and
Python 3 as of upstream commit 0bc2b07, use whatever version is present
by utilizing `python`.
Change-Id: I2a657d0d4fc1899266a9574cfdfec1380828d72d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5b8ecdfe75d99028fee820a2034466a8ad1c5e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58080
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds type-c port information for USB type-c ports to cbmem.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage', flash and boot
volteer2 to kernel, log in and check cbmem for type-c info exported to
the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Change-Id: Ic56a1ad1b617e3af000664147d21165e6ea3a742
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO PM was disabled for brask to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.
TEST=Boot brask to OS, ensure no TPM errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.
TEST=Boot adlrvp to OS, ensure no TPM timeout errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.
Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.
Add a new section RW_SPD_CACHE to fmd for caching SPD data.
The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.
BUG=b:194055762
BRANCH=None
TEST=build pass
Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch feeds PsysPmax setting to FSP through UPD and adds a
PsysPmax member in chip information so that we can set PsysPmax
through devicetree. The PsysPmax needs to be set correctly mapping
to maximum system power. Otherwise, system performance would be limited
due to the default PsysPmax setting in FSP is only 21W.
BUG=b:193864533, b:195615830
TEST=Set PsysPmax to an example value eg 145 in devicetree &&
put debug code in FSP to print the PsysPmax value before sending
to Pcode, ensure the setting is correctly programmed.
Change-Id: Ia07aa815f90739240f110cab984068237c02d896
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the locally declared typec_orientation enum from chip.h to
coreboot_tables.h.
Change enum typec_orientation name to type_c_orientation for consistency
with contents of coreboot_tables.h.
Rename TYPEC_ORIENTATION_FOLLOW_CC to TYPEC_ORIENTATION_NONE.
BUG=b:149830546
TEST="emerge-volteer coreboot" and make sure it compiles successfully.
Change-Id: I24c9177be72b0c9831791aa7d1f7b1236309c9cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds type-c port information for USB Type-C ports to the
coreboot table. This allows depthcharge to know the usb2 and usb3
port number assignments for each available port, as well as the SBU
and data line orientation for the board.
BUG=b:149830546
TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds
successfully. Cherry-pick CL to enable this feature for volteer,
flash and boot volteer2 to kernel, log in and check cbmem for type-c
info exported to the payload:
localhost ~ # cbmem -c | grep type-c
added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0
added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A signed bitfield with a length of 1 bit can only have the values 0 and
-1. Assigning a 1 ends up behaving as expected, but it's not the
semantically correct thing to do there. Changing the type of the element
to an unsigned bitfield with a length of 1 would fix that, but since
this is used as a boolean value, just change it to bool type.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I230804335e7a15a8a9489859b20846988ba6c5cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The u8 type is used in the file, but neither stdint.h not types.h was
included in the file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd67aff9eba01f9618004c869f1473217b3aeae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Correct OVTI2740 information for Kano:
MIPI camera CIO port, HID and Link Freq
BUG=b:200974074
TEST=Build and boot on Kano
camera driver is not probed before,
and it can now be probed properly
after this change.
Signed-off-by: Lai, Jim <jim.lai@intel.com>
Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Round the PM Timer emulation frequency multiplier to the closest value
to increase precision.
Test: compared hexdumps of CML binaries for the expected result:
before: 0x262E8B51, after: 0x262E8B52
Change-Id: Iafd645c248fc17943ea4be558ed7d01a301ba809
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57943
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ltiming and clock_div are not support for MT8173, so we separate them
to weak function: mtk_i2c_dump_more_info()
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3228c6953be5fac18a76029702b878a34c7563f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58074
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. The original algorithm for I2C speed cannot always make the
timing meet I2C specification so a new algorithm is introduced
to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
the original implementation was fixed at fast mode (400Khz).
So the mtk_i2c_bus_init is now also taking an extra speed
parameter.
There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1
BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
at 100/300/400/500/800/1000Khz.
Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures all attempts to read CSE BAR is performing PCI config
space read and returning the BAR value rather than using cached value.
This refactoring is useful to read BAR of all CSE devices rather than
just HECI 1 alone.
Additionally, change the return type of get_cse_bar() from `uintptr_t`
to `void *` to avoid typecasting while calling read32/write32 functions.
BUG=b:200644229
TEST=Able to build and boot ADLRVP where CSE is able to perform PCI
enumeration and send the EOP message at post.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
There are two different types of 282 SKU available with TDP
of 15W and 12W for Alder Lake-M SoC. This patch adds support
for these TDP values for 282 SKU as per document 643782.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Set PL4 value dynamically for adlrvp board based on CPU SKUs
which is detectable at runtime. These values are based on
platform design specification.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
On 682:
Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000)
Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move MILLIWATTS_TO_WATTS macro in power_limit header file
so all other files can use the same macro.
BUG=None
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
These values are as per platform design specification.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add TPCH as participant for dptf control functionality.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I17c0c6cfb7804dd2caa188acc93f1a63b47cab36
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add PMC IPC commands information for FIVR control functionality
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I9d08bb71f7ea5da7614c68fc0ce4edf9aef59baa
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There are currently two variants for mc_ehl where different UARTs are
used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the
Kconfig of the variant and select the matching value there.
Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new variant of the mc_ehl board called mc_ehl2. This patch just
copies the files and renames things where needed.
Following patches will adapt the needed features for this new variant.
Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
<clocks.h> and smp_processor_id() aren't used anywhere anymore. Get rid
of them.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1a8c892b066e6ac0e7cec5316633d44165344e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On AArch64 platforms, GIC initialization is generally the job of Trusted
Firmware and shouldn't be necessary in coreboot. Only the ancient T210
platform (which was started before we had decided on using Trusted
Firmware) calls this code, and even there they have a comment wondering
"do we still need this?". I'm just gonna assume (without testing because
that board is ancient and I'm lazy) that they don't, and that the TF GIC
initialization[1] is sufficient here. Remove this obsolete driver.
[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3ff448/plat/nvidia/tegra/soc/t210/plat_setup.c#259
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3e9d90039dd27cb3a13f830ba21fc5cc7a70abe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The value printed is the EPC (Enclave Page Cache) status, but the printk
statement refers to it as `ECP status` instead. Fix the typo.
Change-Id: Iba0a6013f2c537072dd7aa8266f2be3c5b0963ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58038
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to fix SSD detectiong failure in warm boot observed
on ADL-M RVP. This patch implements the coreect power sequence:
SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Append `_MS` for miliseconds and `_US` for microseconds to HECI timeout
macros to improve the code readability.
Change-Id: Ic7f18f07ecaabb3e43356f372d15d18be083464b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across
various warm reboots.
This patch ensures late sending EOP msg when function disabling of CSE
is no longer a requirement.
BUG=b:200644229
TEST=Able to save ~30ms+ of boot time
Without this code change EOP sending timestamp as below:
943:after sending EOP to ME 1,248,328(61,954))
With this code change EOP sending timestamp as below:
943:after sending EOP to ME 1,231,660 (2,754)
Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch ensures soc_finalize() is getting called at the entry of
BS_PAYLOAD_BOOT boot state instead of BS_PAYLOAD_LOAD, BS_ON_EXIT.
The purpose of this change is to accommodate more time to push out
sending CSE EOP messages at post.
BUG=b:200644229
TEST=coreboot serial log suggests soc_finalize() is getting called
as part of the BS_PAYLOAD_BOOT entry.
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
BS: BS_PAYLOAD_BOOT entry times (exec / console): 21 / 15 ms
Change-Id: I8632eca057255d7f4a38b64fd17c1f3d84123051
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Prior to coreboot sending EOP messages during post, it's important to
ensure that CSE is not in Idle state. In case CSE is in Dev Idle
state (which means D0I3 bit is set), reset this bit before sending
EOP command.
This patch ensures coreboot has provision to send CSE EOP messages even
after the FSP Notify phase without any delays waiting for the device
to respond or timeout.
BUG=b:200644229
TEST=Able to send CSE EOP message even after FSP Notify phase.
Attempting CSE EOP msg sending post FSP notify without this code change
causes `timeout` issue as below:
BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
HECI: timed out reading answer!
HECI: Failed to receive!
HECI: receive Failed
HECI: EOP send/receive fail
ERROR: Failed to send EOP to CSE, 2
cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3:
0x20
VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc
Saving nvdata
board_reset() called!
full_reset() called!
Attempting CSE EOP msg sending post FSP notify with this code change
is `successful` as below:
BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch ensures APIs that are responsible for CSE device state
transition between active to idle and vice-versa are available
publically for other modules/boot stages to consume.
BUG=b:200644229
TEST=Able to build and boot ADLRVP-P.
Change-Id: Ia480877822d343f2b4c9bf87b246812186d49ea3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update to recommended Rcomp drive strength value for DDR4 as per
MRC team's input.
Additionally, add space around the `targets` array.
Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:201512872
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These platforms no longer use reg-script. Drop unneeded select.
Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.
Change-Id: I87d1278360a231cbe5b5f825ad9a448e59e63ea2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Using reg-script just to read-modify-write some registers makes no
sense. Replace reg-script usage with regular register operations.
Change-Id: Ib3c83131c30fd02c579b910cfad6843eb28ba8f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The current names of the PMC init/enable callbacks are very confusing.
Rename them.
Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In CB:52662 when MIPI display support was added, we accidentally changed
the code flow for eDP displays such that i2c_init() will no longer be
called when display_init_required() is false. This is a problem because
on this platform, i2c_init() does not just prepare the I2C controller
for firmware use, it also loads firmware to the controller that makes it
behave like an I2C device in the first place -- a step that the kernel
cannot later do on its own if the firmware didn't already do it.
Skipping this initialization means the I2C controller becomes unusable
to the kernel.
This patch fixes the issue by making the i2c_init() unconditional again.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the `ecps` GNVS struct member to `epcs` to match the name in ASL.
Change-Id: I1f6b97309eea75e7dbb4e5e664660df05ec0845e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Initializing SAR sensor (QUP2, address 0x988000)
BUG=b:198456205
BRANCH=None
TEST=Boot into kernel and make sure no i2c errors for 0x988000 in
dmesg
Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For Herobrine variants that include a finger print sensor, we will
need to power sequence it. We are using the same FP sensor as
trogdor, so we will follow the timings used for trogdor from
CL:2695676.
BUG=b:198474942
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B
Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360.
BUG=b:198716348
TEST=Build nipperkin, codec is functional with new machine driver.
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:193694180
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The %fs and %gs segment are typically used to implement thread local
storage or cpu local storage. We don't currently use these in coreboot,
so there is no reason to map them. By setting the segment index to 0,
it disables the segment. If an instruction tries to read from one of
these segments an exception will be raised.
The end goal is to make cpu_info() use the %gs segment. This will remove
the stack alignment requirements and fix smm_do_relocation.
BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaa376e562acc6bd1dfffb7a23bdec82aa474c1d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This CL adds support for new ADL-M graphics Device ID 0x46c3.
TEST=boot to OS
Change-Id: Ib55fb501f96fe9bcc328202511bbfe84a3122285
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add ADLP 242 sku power related settings, which follow the settings of
ADLP 282 sku (both are 15w).
BUG=b:201253904
TEST=Build and check fsp log to confirm the settings are set properly.
Change-Id: I829dd690c22d167a507b1910106da06b275cec09
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The voltage rail discharge times have been measured, so therefore
the boot time on a cold boot when the CSE must go through a global reset
and thus a trip to S5 can be optimized. Select the lowest applicable
value for each PchPmSlp UPD that can be used with these measurements.
This is programmed in the baseboard because the measured discharge times
leave (what should be) plenty of margin for variants to also not violate
any power sequencing guidelines from the PDG.
BUG=b:184799383
TEST=verified time in S5 during a global reset is ~1s instead of 4s
Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The UPDs for PM power cycle duration and SLP_* signal durations are all
identical to Tiger Lake, so add similar support, but use enums instead
of comments to represent the durations symbolically.
BUG=b:184799383
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Furquan Shaikh