few more code comments to src/cpu/x86/*.inc files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All Intel CPU models appear to be identified with the form
INTEL_CPU_MODEL_xxxxx. I haved changed the Atom to fit this normal form.
A side effect is that the CPU doesn't need to be listed on the boards
that support it since the socket identifies the CPUs it supports.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which
is obviously wrong, so drop the #includes. None of their #defines are used
in the Intel code.
Build-tested with two of the affected boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
statement to those files that actually need it. This significantly
reduces the number of dependencies, so it's no longer extremely ugly to
specify them manually (see the src/pc80/Makefile.inc portion)
- Add double include guards around option_table.h defines
- Also, drop the AMD DBM690T work around for the issue
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
newer Phenom II.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code
sets msr c001_102a bit 3 when bit 35 was intended.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to make sure MMCONF is set up before use. Otherwise, PCI config
accesses run before init_cpus() will be lost if MMCONF is enabled
(unless explicitly done as port-based accesses).
This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in
mcp55_early_setup, so reinsert.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Noticed-by: Uwe Hermann
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to using ram, so something like the appended is perhaps more
appropriate. Confirmed to work on hw.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Removing the code preloading reduces the boot time.
Preload code is enabled when doing CARTEST (not exposed
to Kconfig given that it's a pure debugging measure)
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot_ram can be unpacked to 1MB. The value is quickly
replaced with the real value later, thus causing no harm.
Move RAMBASE to the default of 1MB for the affected boards
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
This patch likely breaks the following two boards since it unconditionally
activates CAR code for this socket:
* digitallogic/adl855pc
* intel/mtarvon
stepan suggests moving those two boards over to CAR, too, so we don't have to
worry.
---
src/cpu/intel/socket_mPGA479M/Kconfig | 1 +
src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 ++
2 files changed, 3 insertions(+), 0 deletions(-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
3.74 June 2010 for errata 351 and it agrees with the comment on
setting ForceFullT0= 000b but I believe the code didn't honor the
comment.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
processors (#41322) rev 3.74 June 2010 says to set the register
to 1 before CAR and to 0 after. We were setting it to 0 after CAR,
but not to 1 before.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
While reviewing impact of this change it seems code for erratum 531 was not in
sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
haven't looked up the docs for all of them, at first sight it seems ok
to include all FAM10 revisions in this mask.
Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010. Before it was applied also to
DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Drop lots of dead code from the various cache_as_ram.inc files.
- Use some descriptive macros instead of magic numbers for MTRR MSRs
- drop unused duplicate descriptors from romstage GDT
- slightly reformatting code and comments
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
board porter: printk should always be available in CAR mode.
Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board
but it's not been used there. Very odd.
There is one usage of CONFIG_USE_INIT which was always off in
src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with
those few lines.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix up converted mainboards that still used early_mtrr_init()
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- make SMM relocation debugging Kconfig accessible
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Part of converting GX2 to use CAR.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
there is no free list.
Converting resource arrays to lists reduced the size of each device
struct from 1092 to 228 bytes.
Converting link arrays to lists reduced the size of each device struct
from 228 to 68 bytes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Especially most _smbus functions misuse port 0x80 writes for delays.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
src/northbridge/amd/amdk8/amdk8_acpi.c
src/southbridge/amd/amd8132/amd8132_bridge.c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
http://www.coreboot.org/pipermail/coreboot/2010-June/058668.html
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This still requires someone to adjust the #includes in the
model_XXX_init.c files but with a script we're getting closer
to automate the update of 3rd party files.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
No new microcode files included.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and replace them by their counterparts from Intel's
opensource microcode file.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot is direct. This patch does it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_10xxx/fidvid.c:758:
warning: 'fid_max' may be used uninitialized in this function
Quoting Marc:
It [fid_max] should be initialized to 0. The !nb_cof_vid_update would mean that
the fidmax shouldn't change so the value isn't important, but 0 would be the
safest if there is another hole in the logic and CPUs are not matched.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
also the GCC generated code and it looks all right. Please test on some
multicore CPU.
I added the "memory" clobber to read_cr0 / write_cr0 function as it is in Linux
Kernel. Seems that if this is missing, GCC is too smart and messes the order
of reads/writes to CR0 (not tested if really a problem here, but be safe for
future users of this function ;)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
northbridge/amd/amdht/ht_wrapper.c
northbridge/amd/amdfam10/raminit_amdmct.c
cpu/amd/model_10xxx/fidvid.c
pc80/mc146818rtc_early.c
They are now included by the fam10 chipset code that requires them.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
romstage.c files in mainboards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
geode lx and amd opteron don't use this yet.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(which could at some time hold global post code definitions, too)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the gx2+5536 issue is still open, and it reveils a serious problem with the
code that was hidden under a bunch of warnings until now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
between having VSA functionality in the code, and adding a VSA image to the
ROM.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the rest of the code unreadable.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this patch also slightly changes it so we have a single cache_as_ram.inc which
requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or
worse, a lot of cruft hacked right into romstage.c like on tyan s2735)
Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new
simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mention it explicitly.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
into the cached area. Back to 469ms until coreboot_ram is actually
running on epia-cn
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
currently unused. Just keep it in sync, we might need it some day.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
single several pages long asm statement
Could use some renumbering of post codes, but that's good for another time.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/arch/i386/Makefile.inc to the respective CPU directories.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- set them to span the last 64k, instead of the last 128k
by default
- fixes via CAR for tiny bootblock
- enabled tiny bootblock for via/vt8454c
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
does not work as it is, but it's the only compile test case for i855pm). It's
the only board left using an ICH4 that does not use CAR. Change that.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
later.
Call copy_and_run instead of cbfs_and_run_core because we can choose the
coreboot_ram filename in C instead of Assembler.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of the ugly mixture it was before. It also enables CAR for all C7 boards
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.
The 1000 ways of how the AMD code waits for the cores to be started up
are a real pain for the brain.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
drop some non-car code from amd/dualcore (there is no AMD dualcore without CAR)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson
IP1000
Build and boot tested.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
The change to CAR reveiled a few more warnings in the ICH4 and i830 code,
I fixed them on the fly.
Checking this in because my last two commits broke Joseph's CAR patch. This
version fixes the issues.
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
So move it to src/arch/i386/lib/cbfs_and_run.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
all the others do. Make sure copy_and_run is called with
the right calling convention. Fix up 2 license headers.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Remove some special print statements.
In general, make them easier to compare.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer