Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16
are the industrial standard electrically erasable programmable
read only memory (EEPROM's) and this patch adds ACPI objects
and power resources for NVMEM device.
Update DOVD method to set sensor IO LDO voltage and remove repetitive
code from OVFI, VCMP and NVMP power resources.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Read the NVMEM content via sysfs interface.
Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.
BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.
Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add gpio.c to bootblock so that the variant early_gpio_table can be
used for configuration in bootblock.
BUG=b:64181150,b:62726961
Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.
Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
in Scarlet the Sdcard control gpio differs from other
board variants, So set the GPIO to high on Scarlet.
Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the Google mainboard GPIOs to the ACPI table.
Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC KBC controller was not initialized, so the EC wouldn't put
keys in the output buffer. With nothing in the buffer, vboot didn't
try to boot the USB stick. Add the driver to setup the KBC called by
EC init.
BUG=b:62066405
BRANCH=none
TEST=Boot Kahlee with USB stick and CTRL+U boots the stick.
Change-Id: If9346fda558e802536c7de38da5b21fd25320e40
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20480
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard_ec_init out of mainboard enable to the more
appropriate mainboard init phase.
Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.
Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set DDI port 2 type to Display Port.
Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Inform AGESA to setup an I2S codec instead of an Azalia codec.
This is step one for audio to work. ASL to connect the
driver and the hardware is in a follow-on patch.
Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/19841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add ASL for the Elan touchpad driver connection in ChromeOS.
This is based on the Auron and Rambi ASL. The AMD ACPI code
doesn't have the auto table generation the newer Intel
Chrome SOC use.
Device visible to OS: /sys/bus/acpi/devices/ELAN0000
Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the ASL whitespace and formatting to match the iasl -d
style as other parts of coreboot.
Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD internal A-link (AAHB device) doesn't support an IRQ,
so remove it. This solves a conflict with the GPIO IRQ required
for touchpad operation.
Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.
TEST=Wifi card is detected and connect to an AP.
Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet.
Set continuous mode until the quiet mode feature is available. This
allows keyboard and other EC based interrupts through.
Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19840
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly
report in the FADT.
Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19836
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update GPIO settings based on the schematic.
Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update for a single DIMM with an SPD at address A0.
Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee does not use the AMD IMC. Remove the files and calls.
Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19832
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update for the Stoney Ridge FT4 package and the on chip UART.
Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19831
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable S0ix for poppy and soraka in their device trees respectively.
BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).
Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.
BUG=b:62322846,b:62240755
Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.
BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.
Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the necessary changes to support Scarlet revision 1.
Since the differences to revision 0 are so deep, we have decided not to
continue support for it in the same image. Therefore, this patch will
break Scarlet rev0.
All the deviations from other Gru boards are currently guarded by
CONFIG_BOARD_GOOGLE_SCARLET. This should be changed later if we
introduce more variants based on the newer Scarlet board design.
Change-Id: I7a7cc11d9387ac1d856663326e35cfa5371e0af2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
BRANCH=reef
TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/20633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All other Sandy/IvyBridge google boards have this function,
which is required by nb/sandybridge/raminit_mrc.c. Without it,
compilation fails when using MRC vs native ram init.
Change-Id: I3318700c540e97baf0a75aafb73f160aaae6703f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There will be more follow-up changes.
BUG=b:63537905
BRANCH=None
TEST=emerge-nefario coreboot libpayload
Change-Id: I6bb80723ea2573df617026a4a5740adb89331892
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/20522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
1. Due to reset signal, PMIC loses its internal register state. This
causes PMIC to be in improper state after sleep.
2. The intent of reset signal is to reset internal state of PMIC (which
happens once during power on), hence avoid asserting reset signal
when not needed.
3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode
when not in use to save max possible power.
To fix the same, do not reset PMIC while entering sleep.
By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto
3.63uW (Max). Refs: TPS68470 datasheet.
Measured value: 0.66uW
TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check
whether PMIC internal registers state are preserved.
Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Chell doesn't have a touchscreen, so remove the driver
definition from devicetree. Leave the PCI device function 0
enabled since disabling results in the touchpad (function 1)
being disabled as well.
Change-Id: I32619b7618bc0cdd99fa54fdda9bf2b5c1bb79a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use the new PAD_CFG_GPI_INT macro to specify the headset codec
interrupt as specifically edge triggered (since it is registered
as EDGE_BOTH in the devicetree) in order to prevent the interrupt
from firing unexpectedly when the system is resuming.
Also change the DSP interrupt to edge triggered since the kernel
is registering with IRQF_TRIGGER_RISING in order to prevent an
interrupt storm when it asserts.
BUG=b:35582164
TEST=manual testing on Eve:
1) ensure the headset codec sends interrupt on insert and remove
2) ensure there is only one interrupt counted when DSP asserts irq
Change-Id: I40a8ee667de653e4e70770cd96b6417442c1b0ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make this pin a GPI as it is supposed to be an input from the touch
controller and not driven by the AP.
BUG=b:35581264
TEST=check pin state with a scope
Change-Id: Ife5f84fcc614255b20e44389279d515a12f5751d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Board changes in rev6+ have a fix to VDDQ that should fix the issue
that was being seen with this SKU, so only lower the memory speed on
older boards.
BUG=b:37172778
TEST=memory stress testing on rev6 boards
Change-Id: I6d6fe730cabd74af23eab3f02feef9da01a35fd4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for waking from and logging device events that
originate in the Embedded Controller. As this device uses
Deep S3 it relies on the EC to wake the AP from the trackpad
and DSP wake sources.
BUG=b:30624430
TEST=manual testing on Eve: wake from Deep S3 via trackpad and
DSP and verify the event log contains the expected device event.
Change-Id: I0d6a9c5bfd4cea85e13446ffaa6fe3dab0db96a2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.
Remove this from the boards that were enabling it.
BUG=b:36024430
TEST=build coreboot for affected boards
Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
- Describe RT5663 headphone codec in ACPI so it can
be enumerated by the OS.
- Supply NHLT binaries for RT5663
BUG=b:62872377
TEST=Apply full patch set and UCM, verify basic audio works.
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076
Reviewed-on: https://review.coreboot.org/20305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.
BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.
Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The ChromeEC board directories for auron and rambi have been removed
from the latest version of ChromeEC. Remove them here so the submodule
can be brought forward.
Change-Id: I763d03009f735d3f8aedbeb44788d03714c86102
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Update the world facing camera sensor to OV13858 and also
add delay of 5ms after xshutdown rising which indicates system
ready status.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Add clock frequency property into _DSD ACPI object and set it
to 19.2MHz for camera sensors. Upstream camera kernel has added
a check for clock frequency in sensor probe function and without
this property sensor probe fails.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20294
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable RT8168_GET_MAC_FROM_VPD in fizz Kconfig.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I00f63dcb56a2c9a4600c8461bc94e06ec5ab2d81
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
By default disabled. Will need to add
FIZZ_USE_SPI_TPM config to enable.
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
CQ-DEPEND=CL:530184
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20134
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds mipi_camera.asl,
* Add TPS68470 PMIC related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Use a GNVS variable to store the trackpad interrupt, in order to
support both SNB and IVB variants from a single build.
Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the hardware designed on gru, the AP_I2C_TP_PU_EN (gpio3_b4) controlled
the SCL/SDA status to avoid leakage. And the gpio3_b4 of rk3399 pull
resistor is 26k~71k and 3.3v for supply power, and gpio3_b4 pin connected
2.2k resistor to i2c of TP device.
The default of this gpio status is pulled up during the start to bootup,
it's very weak drive for the TP device that maybe cause to trigger the
recovery process of elan's firmware.
Also, the Elan updated its firmware(102.0.5.0) to delay checking the
i2c of touchpad is greater than 1 second.
So we have to drive the stronger pull-up within 1 second of powering up
the touchpad to prevent its firmware from falling into recovery.
Change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
TEST=Verified that board still boots to OS without any error.
Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.
Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.
TEST=Verified that unused interface does not show up in ACPI tables.
Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20141
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for google/rambi
as to not break compilation.
Change-Id: I4ef978214aa36078dc04ee1c73b3e2b4bb22f692
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20056
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update user facing camera i2c address to 0x36.
BUG=None
TEST=Build & boot on soraka. Make sure user facing camera is detected.
Change-Id: I4645ae5734faef4b6a821c04ab817a7b99da6e4b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user
option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to
use the latter in a choice.
Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
A new variant copied from reef.
Allow override of the SKU.
Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20020
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each rambi variant has a different USB port config.
Port data currently available for only candy and squawks;
other variants to be added once data obtained.
Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each jecht variant has a different USB port config.
Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each auron variant has a different USB port config.
Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
No reason to compile/include chromeos.c for non-ChromeOS builds
Change-Id: Ie8ef1f4c521b2a7308941299f2501073937bdf4a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update camera sensor detail to OV 13858
Also update i2c address of OV5670
BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.
Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is to align with the SD_CD GpioInt setting in acpi
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/20001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove MONOTONIC_TIMER_MSR selection from mainboard
Konfigs, as it only does a reduntant selection of
HAVE_MONOTONIC_TIMER config, already selected under
skylake soc Kconfig.
Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/20002
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
All beltino variants use the exact same USB port layout.
Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of having the SMI handler power off the touchscreen on the
way into suspend add power resource controls to the ACPI device so
the power is managed by the kernel instead of the BIOS.
BUG=b:35581264
TEST=manual testing on Eve to ensure that the touchscreen is still
functional at boot and after suspend/resume, and that it does not
draw power in suspend.
Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
GPP_C2 is being used as strapping option, so
should not be set to NF. Signal was floating
previously, which can lead to an assertion of
smbalert#.
BUG=b:37681121, b:35775024
BRANCH=None
TEST=powerd_dbus_suspend and ensure stays in suspend
Change-Id: I68091206014621419b886b723a5681541be989bc
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19904
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Do not enable touchscreen device by default in gpio configuration.
2. Select use of PowerResource for touchscreen device in devicetree so
that the ACPI subsystem can take care of powering on/off the
device. When system enters suspend, touchscreen device is powered off
and on resume, it is powered back on.
BUG=b:62028489
TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on
poppy.
Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19829
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD),
it displays wrong part number during boot in coreboot logs.
So correct part number info within the SPD.
TEST= Build for Soraka & make sure part number is rightly printed.
Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19692
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC code was never completed. It's just a skeleton that gets
in the way of refactoring other code. Likewise, the mainboard was
never completed either. Just remove them both.
Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19823
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
TEST=Boot from scarlet, and mipi panel works
Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This device is no longer directly connected to the SOC so it
does not need to be enabled in coreboot.
BUG=b:35648259
TEST=build and boot on Eve
Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19728
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The touchpad frequency was still slightly above 400kHz so tweak
the timing values manually to get under the spec limit.
BUG=b:35583133
TEST=verified the bus frequency with a scope to be < 400kHz
Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19727
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19577
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations’ Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
BUG=None
TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/19524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This reverts commit 39b633b26d.
Commit was accidentally pushed too early and broke the tree.
I'll repush the original.
Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
TEST=Boot from scarlet, and mipi panel work
Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on device 1c.0 in order to enable devices
under it.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=Boot from NVMe
Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19533
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Remove the code that was enabling the keyboard backlight at boot
since this is not desired behavior for this device.
BUG=b:35581264
TEST=build and boot on Eve and ensure keyboard backlight does
not turn on when booting but can still be enabled in the OS.
Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Board Scarlet doesn't use usbphy1.
BUG=b:37685249
TEST=boot Scarlet, check the firmware log, and confirm
no errors about USB1
Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.
BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.
Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices'
FADT version were incorrectly set to 3, rather than the correct
ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these
devices reporting compliance to ACPI 2.0, rather than ACPI 3.0.
This mirrors similar recent changes to SKL and APL SoCs.
Test: boot any affected device and check ACPI version reported
vai FADT header using OS-appropriate tools.
Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19498
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Correct the default GBB_HWID to "ROWAN TEST 9387"
BRANCH=chromeos-2016.05
BUG=b:35774871
TEST=emerge-rowan coreboot chromeos-bootimage,
strings /build/rowan/firmware/image.bin | grep "ROWAN TEST"
and look for 9387 in output
Change-Id: I7851010305caf056958c8a6a328b0506bf2208cd
Signed-off-by: Patrick Berny <pberny@chromium.org>
Reviewed-on: https://review.coreboot.org/19488
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.
BUG=b:37682566
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.
Change-Id: I4c748a316436001c5a33754084ab4a74243e21df
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19457
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=b:35647967
TEST=boot from bob
Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820
Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/452286
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19434
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SD card detect pins should normally have a pull-up. It seems that for
micro-SD cards this doesn't really matter all that much, but for the
full-size slots we have on some Oak-derivatives (like Hana) it does.
BRANCH=oak
BUG=b:35854317
TEST=Booted Hana, confirmed that card detect no longer seemed stuck-on.
Booted Elm and confirmed that SD card behavior didn't change.
Change-Id: I9b20e0f6fe310e724d191e36ca0a81ab4fe5f593
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2781eeef50f52c6f02ee9344274ddf4dcb0a946
Original-Change-Id: I428ac92efb07f94265673b04e0e0dd452649b9fd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/452861
Original-Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/19432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The new touchpad firmware uses i2c-hid instead of custom reporting
protocol. The touchpad also exposed another slave address (0x1e) for
kernel to communicate with the touchpad EC.
Change-Id: Iecaf14f7b8aed836120569e9ade9c3115bc00264
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://review.coreboot.org/19461
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=b:35586577
BRANCH=none
TEST=On a poppy board that has the VBUS rework applied, plug in a charger to
either port and see charge status updated to indicate charging in the
power_supply_info tool and the Chrome OS UI.
Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/19441
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
BUG=b:37486021
BRANCH=None
TEST=compile coreboot and make sure sda and sdb show
up in /sys/class/block.
Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19450
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the safety considerations, we should make sure the slot of SD is
enabled first, since we want to the power switch of corresponding is
powered up.
The different boards have the different power switch for sdmmc.
Some power switch IC need turn on delay for long time.
let's move the slot power of SD to romstage and avoid explicit delays
or per-board.
BRANCH=none
BUG=b:35813418, b:35573103
TEST=check the signal for children of gru, and boot up from sd card.
Change-Id: Id164e4c4c900c6b1ca0251fc27db4cd36c56f6ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea1b01cc13628033b85251dbb44407f075efdc85
Original-Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/447076
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19430
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Unlike other oak derivatives, Rowan uses an 8-lane BOE tv097qxm-nu0
MIPI/DSI panel that requires dual DSI support.
Rework oak display initialization to special case Rowan, which uses a
provided edid struct for its panel, special panel backlight sequencing
and needs to configure mtk_ddp and mtk_dsi to use dual dsi mode.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: I136ba5bd1ab12c4ad92995e066fc6d6cf54d0898
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19389
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The MT817x display output pipeline can be configured to drive an 8-lane
MIPI/DSI panel using "dual DSI" mode. For the "dual DSI" video data path,
the UFO block is configured to reorder the data stream into left and right
halves which are then sent by the SPLIT1 block to the DSI0 and DSI1
respectively. The DSI0 and DSI1 outputs are then synchronously clocked at
half the nominal data rate by their respective MIPI_TX0/MIPI_TX1 phys.
Also, update the call sites in oak mainboard to avoid build breakage.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: Id47dfd7d9e98689b54398fc8d9142336b41dc29f
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19361
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
This helper function was introduced so that mainboards don't need
to manually fill in these struct edid fields.
BRANCH=none
BUG=b:35774871
TEST=Boot Rowan in developer mode and see output on the panel
Change-Id: Ic9404a786a28b314b710e037dcae776be4b584ca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19388
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch enables TPM2 using cr50 over I2C for the Rowan board, and
adds an mt8173 specific TPM IRQ polling function. The function relies on
the appropriate EINT input configured to trigger the ready status on
the rising edge.
The cr50 TPM is on I2C address 0x50.
The cr50 interrupt GPIO is also made available for use by depthcharge
via the coreboot tables.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19364
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: If66a2a1d461a411e112589c84a434066d48b9399
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19410
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies
the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: Ia1eacd15e71a46a37457ee2f117b156393c3393d
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19409
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's
tis_plat_irq_status() routine.
BRANCH=none
BUG=b:36786804
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM".
Change-Id: Ifeb09a0a35bff7cd9091f6d027f0065288ca35c9
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19407
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Utilize the intel/common code for tis_plat_irq_status() to remove
dependencies and code duplication on for bringing up a board
requiring tis_plat_irq_status().
Change-Id: I2aaa1d7d3ce171dc1788438ff9990fce533deb6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19371
Tested-by: build bot (Jenkins)
The CR50 TPM can do both SPI and I2C communication. However,
there's situations where policy needs to be applied for CR50
generically regardless of the I/O transport. Therefore add
MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally,
once the mainboard has selected CR50 TPM automatically select
MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0.
Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19370
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Lid switch is not available.
Hence report lid state as always open.
Change-Id: Ia9c82c3ad323912bad51cf55ed80a37b3110b1ef
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19219
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Read DRAM SPD and populate MemorySpdPtr fields
in UPD data structure for FSP.
BUG=b:36490168, b:35775024
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/fizz -x -a
We are currently working on bringup and have no
hardware to test on yet.
Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19205
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit changes the interrupt configuration for the touchpad to be
level triggered so it matches what the device is actually using.
When the system wakes from suspend by way of touchpad interrupt, or
there is touchpad input while in suspend that does not wake the device
(when the device is in tablet mode) the interrupt edge is not seen by
the AP so the driver does not handle the event and the touchpad keeps
the interrupt asserted and does not send further interrupts. The end
result is a non-functional touchpad after resume until it is reset or
the driver is reloaded.
This happens because the touchpad is actually treating the interrupt as
level triggered and expects the kernel driver to read a data packet over
I2C before it will de-assert the pending interrupt.
BUG=b:35774857
BRANCH=none
TEST=Test that the system can reliably wake from suspend by touchpad
event via the EC and continue to have a functional touchpad after resume.
Change-Id: Iaf7c04d9bc9d945bdcc196dff54c92a2a68368f3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19382
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kevin's center logic isn't super clean so it needs 925 mV for center
logic. All newer gru variants only need 900 mV.
BRANCH=gru
BUG=b:37429075
TEST=Reboot tests
Change-Id: I8c3bd6c245700b23c27cd5758c35c9993f801cb4
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/479463
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19357
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It seems that we should only ever run at 900mV on center logic.
Changing it to 950mV before might have just masked over problems that
are now fixed.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=on kevin, run
stressapptest -M 1536 -s 1000
Change-Id: I5a09b1b403df800396bb2f2e8c76d14a4519d44a
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391032
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Commit-Queue: Lin Huang <hl@rock-chips.com>
Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Create Soraka board which derives from Poppy, a KBL reference board.
More Soraka specific changes need to be done later on.
BRANCH=master
BUG=b:36995255
TEST=Build (as initial setup)
Change-Id: I8af68d2cf475df56336aa0e3bebe86a54ece1999
Signed-off-by: YH Lin <yueherngl@chromium.org>
Reviewed-on: https://review.coreboot.org/19343
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move current NHLT configuration implementation to baseboard so that
variants can leverage it or provide their own configuration.
BUG=b:37375693
Change-Id: I2a4317c112f9e3614bd01eb6809727b73328d29d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19326
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for memory configuration by providing weak implementation
from the baseboard. All SPD files are present under spd/
directory. SPD_SOURCES must be provided by the variants to ensure that
required SPD hex files are included in the SPD binary.
BUG=b:37375693
Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19325
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to be able to share code across different poppy variants,
provide the concept of baseboard and variants. New directory layout:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/poppy - code
variants/poppy/include/variant - headers
New boards would then add themselves under their board name within
"variants" directory.
This is purely an organizational change.
BUG=b:37375693
Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19322
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up Kconfig file in order to support variants for poppy. Add
BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants
to use the common baseboard configs.
BUG=b:37375693
Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19321
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add camera related support
* Enable the SA Imaging Unit and CIO2 devices.
* Enable TPS68470 PMIC and populate related ACPI objects.
* Enable OV cameras and populate related ACPI objects.
* Enable Dongwoon AF DAC and populate related ACPI objects.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that ACPI tables
have the required entries for all the camera devices.
Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18969
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch includes ipu.asl file in the main DSDT definition
to add ACPI entries for IMGU and CIO2 devices.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that DSDT table
has the entries for IMGU and CIO2 devices.
Change-Id: Ib7485315cb9468da7c6aa090862657a265121493
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19110
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Update formatting of gpio table to fit everything within 80 column
limit.
2. PEN_RESET gpio is non-existent. Get rid of it.
BUG=b:37375693
Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19320
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable lower power state when running on battery. Deep S3 is not
enabled when in AC mode to support standard "docked" config.
BUG=b:36087058,b:36723679
TEST=Verified following behavior with USB mouse:
1. If AC is connected when entering S3, USB mouse is able to wake up.
2. If AC is not connected when entering S3, USB mouse does not wake up.
3. If AC is connected when entering S3 and removed after entering S3,
USB mouse does not wake up.
4. If AC is not connected when entering S3 and attached after entering
S3, USB mouse does not wake up.
Change-Id: I141a8d4779de004e27fcd9357cef787a38a27b24
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19276
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The HDA verb for falco/wolf's internal mic was wrong, preventing the mic
from working properly in Windows and macOS (the Linux driver overrides
the verb table, so wasn't affected). Set the verb connector/jack bits
properly, to no connector / no jack detect, in order to fix.
Also, make (2) small non-functional fixes:
On falco, NID 0x1A was being disabled twice (instead of 0x1A and 0x1B
both being disabled - copy/paste error).
On wolf, NID 0x19 was set to an internal analog mic, where it should have
been disabled (again, copy/paste error).
Both these errors were introduced when consolidating/upstreaming
and were not present in the original Chromium sources.
Test: boot Windows [8/8.1/10] and verify mic functional with Realtek
drivers on both falco and wolf.
Change-Id: I9c343dda4762f0b1f814318c155e22c59d2da8db
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19262
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the 'probed' setting from the Realtek 5663 headset codec I2C
device. This was added when we had a hardware issue that was preventing
I2C operation because the clock/data lines were swapped.
With new and/or reworked hardware this is no longer a problem and we do
not want the I2C layer in the kernel to talk to the device before the
rt5663 driver.
BUG=b:35585307
BRANCH=none
TEST=Boot on Eve and verify rt5663 driver still loads properly.
Change-Id: Ice38889e8f5d3fd1307056cab10fbe3f4e197749
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19304
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- remove old, buggy NGI code from falco/peppy variants
- remove superfluous INTEL_DP/INTEL_DDI configs, since already
selected by northbridge/haswell
- always use libgfxinit when use native init config selected
- enable NGI/libgfxinit for all slippy variants
The reset of the old Haswell NGI code will be cleaned up in
a subsequent patchset.
Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init
using SeaBIOS and Tianocore payloads on peppy, wolf variants
Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18824
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove the ACPI ALS device from the EC configuration because this system
has an ALS that is presented through the new EC sensor interface rather
than the legacy ACPI interface.
BUG=b:37179776
BRANCH=none
TEST=Boot an Eve device and ensure that 'acpi-als' device is not present
in /sys/bus/iio/devices.
Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19265
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not
set back to native mode by FSP when configured as GPIO input by coreboot.
Now that FSP is not touching the pins I also removed the workaround to
reconfigure the pins after FSP.
BUG=b:35647877
BRANCH=none
TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS
is booted and they are not set back to native function by FSP.
Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19264
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
These lines act as inputs to both EC and AP and when the corresponding
TCPC mux is in low power mode the line is floating. Add an internal
pull-down to each GPIO to prevent it from floating in this state.
BUG=b:35775012
BRANCH=none
TEST=Verify that the kernel does not see a device present on DP when
the TCPC mux is in low power mode.
Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19263
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This configures GPIO_177 as native function.
This enables OS to boot from sdcard.
BUG=b:35648535
TEST=Check OS boot from sdcard.
Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18948
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
In order to support a standard "docked" config disable Deep S3 when
connected to AC power. This allows USB devices to wake the device
from suspend if it is externally powered, but still retains the
lower power state when running on battery.
BUG=b:36723679
BRANCH=none
TEST=manual testing on Eve for USB wake behavior:
1) when suspended on battery USB keyboard does not wake
2) when suspended while connected to AC a USB keyboard does wake
3) if suspended with AC, and then AC is removed, system does not
wake with USB keyboard
4) if suspended without AC, and then AC is added, system does not
wake with USB keyboard (it cannot get enabled without waking and
re-suspending)
Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19240
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the Intel WiFi SAR feature for Eve, which will be used to
provide wifi power tables based on values read from VPD.
This is enabled based on CONFIG_CHROMEOS because it relies on the
presence of VPD code from vendorcode/google/chromeos.
BUG=b:36727652
BRANCH=none
TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that
the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables
with the values that were set in VPD.
Change-Id: I11c129baca891221177575108ac09ba1707b516e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19241
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states. However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.
To address this split the setting and add a separate config for Deep Sx in
AC and DC states.
All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.
BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.
Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19239
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
These lines act as inputs to both EC and AP. Thus, add internal
pull-downs to prevent them from floating.
BUG=b:35648530
Change-Id: I42326c810775d5449e99e52e81870970247ce335
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19243
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Put all configs required for enabling cr50 SPI TPM on poppy under
POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI
TPM on this board.
Also, add required callback for irq status and devicetree config for
GSPI0.
BUG=b:36873582
Change-Id: I67793093c006c1325fc16f669a96126525f83243
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.
TEST=boot to kernel on Scarlet
Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19237
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.
BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory
Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update the I2C rise/fall timings based on newly measured values
on a new board with updated pull-up resistor values.
Touchscreen: rise time 98ns, fall time 38ms
Touchpad: rise time 111ns, fall time 41ns
TPM: rise time 112ns, fall time 34ns
BUG=b:35583133
BRANCH=none
TEST=Each I2C bus frequency was verified on a scope to be ~400MHz
Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
BUG=b:35583511
TEST=check i2c bus 0 initializes from ap console log
Change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19105
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Even though the i2c spec has no minimum data hold time in fast
mode the trackpad vendor indicates 300ns is their minimum. However,
the topology of the board uses FET isolation to cross voltage
domains. Therefore, the default 300ns which should work isn't reflected
on the device side of the voltage isolation circuit. Therefore,
increase the data hold time to show an observed data hold time of
more than 300ns on the device side.
BUG=b:36469182
Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19065
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Wake On Voice stream capture configuration is mono. It is sufficient
to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1.
Power saving should be visible in the boards which has more
than one DMIC connected.
BUG=None
BRANCH=None
TEST=WoV and quad channel DMIC capture works
Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/19018
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Tested-by: build bot (Jenkins)
This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This callback was only required for a single mainboard, and it can
easily be moved to mainboard-specific code. This patch removes it from
the global namespace and isolates it to the Jecht board. (This makes
it easier to separate vboot and chromeos code in a later patch.)
Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The virtualized developer switch was invented five years ago and has
been used on every vboot system ever since. We shouldn't need to specify
it again and again for every new board. This patch flips the Kconfig
logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with
CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to
set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the
latter for Lumpy which seems to have been omitted incorrectly, and hide
it from menuconfig since it's a hardware parameter that shouldn't be
configurable.)
Since almost all our developer switches are virtual, it doesn't make
sense for every board to pass a non-existent or non-functional developer
mode switch in the coreboot tables, so let's get rid of that. It's also
dangerously confusing for many boards to define a get_developer_mode()
function that reads an actual pin (often from a debug header) which will
not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set.
Therefore, this patch removes all those non-functional instances of that
function. In the future, either the board has a physical dev switch and
must define it, or it doesn't and must not.
In a similar sense (and since I'm touching so many board configs
anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC.
Instead, it should just be assumed by default whenever a Chrome EC is
present in the system. This way, it can also still be overridden by
menuconfig.
CQ-DEPEND=CL:459701
Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18980
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
VBOOT_DYNAMIC_WORK_BUFFER and VBOOT_STARTS_IN_ROMSTAGE are equivalent in
practice. We can't have a dynamic work buffer unless we start in/after
romstage, and there'd be no reason to go with a static buffer if we do.
Let's get rid of one extra option and merge the two.
Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18979
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of defining SIO_EC_ENABLE_PS2K by default for all boards and
doing an undef in variant/onboard.h, move the definition of
SIO_EC_ENABLE_PS2K to variant/onboard.h. This avoids dependency
between different *.asl files.
Change-Id: I83e4ce42a594e952a443c618d7ef9840113027b9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18965
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Remove CPU throttling effect of the charger sensor
Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
2. Change TSR1 influence from 200 to 100
3. Change TSR2 sample period from 120s to 30s
BUG=b:35585781
BRANCH=reef
TEST=built, and verified on snappy by thermal team.
Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Creating google/fizz directory based on poppy (using kabylake and FSP
2.0). Only making name changes and Copyright year changes. Many
poppy-specific configs left in and will be updated in follup CLs.
BUG=b:35775024
BRANCH=None
TEST=Compile fizz board
Change-Id: Icab3639a53fef65e904e797028916fda879fff7c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/18796
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. correct DPTF TCHG target device to TSR2
2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
BUG=b:35586881
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18920
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since SD card controller is expected to enter D3hot by runtime power
management if there is no card inserted, we need to use a sideband IRQ
pin which is not under the control of the controller. Thus, configure
GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect
pin.
BUG=b:35586693
BRANCH=None
TEST=Verified on a reworked poppy board that card detect works fine.
Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18926
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We just support Raydium touchscreen instead of Elan.
Thus we have to remove Elan touchscreen device
and add Raydium touchsrcreen device.
BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot
Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18789
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by
standard hid i2c Linux driver.
BUG=b:35586513
BRANCH=reef
TEST=build, boot on snappy, and verified acpi node "WDHT0002" created.
Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18874
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
It's not relevant to throttle CPU based on the charger sensor.
So, remove this CPU throttling effect.
BUG=b:35908799
BRANCH=master
TEST=Built and booted on Electro DUT
Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
We have code for certain Veyron variant names that were either never
made into an actual board (Gus, Nicky, Thea) or used for Google-internal
test boards that no longer exist (Pinky, Shark). Let's clean them out to
avoid confusing people.
Change-Id: Icdce5f0f3613e089d0994318b02dba54170f0c42
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With a recent patch (google/veyron_*: Add new Micron and Hynix modules)
we switched RAM codes for Veyron boards to tri-state since we were
running out of binary numbers. Unfortunately we only tested that change
on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and
Mighty. The "high" RAM code pins on those boards were incorrectly
strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and
Speedy), which is too high to overpower the SoC-internal pull-down we
use to differentiate "high" from "tri-state". Since we already used
tri-state codes on some Minnie and Speedy SKUs we have to hack up the
code to work differently on these two groups of boards to keep
everything working.
BRANCH=veyron
BUG=b:36279493
TEST=Compiled, confirmed ram_code called the right function depending on
board.
Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18859
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that EC on poppy is stable, it is time to switch on EC SW sync.
BUG=b:36178824
BRANCH=None
TEST=Verified that EC SW sync is done properly and device boots to OS.
Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18838
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.
Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller. This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.
This is a clone of Duncan's patch for eve
at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
BUG=none
BRANCH=none
TEST=test on poppy that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.
Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.
Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller. This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.
BUG=b:35585307
BRANCH=none
TEST=test on Eve that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.
Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18836
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_DVT_v0.6_20170314.xlsx)
1. Increase PL2 Max to 15W.
BUG=b:35583586
BRANCH=reef
TEST=build and verify PL2 Max value on electro dut
Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18807
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Keep the BOOT0 pin triggering the MCU bootloader as an input,
so the Servo debug board doesn't have to fight with the PCH to program
it, the net already has an external pull-down to ensure that the MCU is
in normal mode at boot.
By default, do not drive the FP sensor reset from the PCH, the MCU is
now managing the reset line (but the PCH still has a connection on the
current boards).
BRANCH=none
BUG=b:36025702
TEST=manual testing, program the MCU through a Servo v2 board, and use
the FP sensor through the MCU and verify it is not stuck under reset.
Change-Id: I19113b5d78013d0ab6ec5a72c6f71dd4c67a88e8
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/18830
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Set the AC and DC loadline values based on the KBL-Y 2+2 defaults
that are applied by FSP. These will be tuned later and are exposed
as defaults so the engineers know what to start with.
BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values
Change-Id: Ieae4f2b201d8210e75bdb9438070a3a2e1fda6b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
With the move to FSP 2.0 the number of VR types supported was
reduced to 4, and the VR_RING type is no longer present.
This means all existing boards using FSP 2.0 are incorrectly
passing VR configuration into FSP as the values corresponding to
"GT Sliced" and "GT Unsliced" have changed.
Fix this by updating the skylake SOC VR handling to account for
changes in the FSP configuration and no longer provide VR_RING
type when using FSP 2.0.
BUG=b:36228330
BRANCH=none
TEST=manual: build and boot on Eve
Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
On this platform the DMICs are connected to the rt5514 DSP instead
of directly connected to the SOC. Use the new rt5514 NHLT blob
instead of the 4ch DMIC blob and add the required I2C and SPI
entries in devicetree so this can get probed properly.
BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1 and check for rt5514 driver enumerated
by the kernel
Change-Id: I0f2cb532771ee1857df7f33c52a96acf96dc1f54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18817
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add FPF_STATUS region under MISC_RW. The purpose of the region is to
store FPF status.
Change-Id: I2997b3d39a94bf444df51068f254edcf49c47afd
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18773
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sand is not convertible and no EC sensor sends event from EC to AP.
That event default is tablet mode, we don't have to enable tablet event.
Modify the ec.h, is based on <baseboard/ec.h>
BUG=b:36108742
BRANCH=reef
TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work.
Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18737
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable an internal pull-up on the power button input as short
press is resulting in power button override being asserted.
BUG=b:36111214
BRANCH=none
TEST=tested on poppy board to ensure quick power button press does
not result in a shutdown due to power button override.
Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/18734
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.
Assign the sdcard card detect pin in devicetree for reef variants.
CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=None
Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Going forward it's important to note when a CR50 is expected
to be present in the system. Additionally, this Kconfig addition
provides symmetry with the equivalent i2c Kconfig option.
BUG=b:35775104
Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
verstage can be pretty chatty so bump the pre cbmem console size
when building for Chrome OS so that all messages can be observed.
BUG=b:35775104
BRANCH=reef
TEST=Booted and noted no cutoff of console when sec data being saved.
Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18679
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
