Commit Graph

39304 Commits

Author SHA1 Message Date
Werner Zeh 257e2507fa mb/siemens/mc_ehl: Disable HS400 mode for eMMC
In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.

Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-03-02 18:25:54 +00:00
Arthur Heymans f879d36551 device/pci_device.c: Improve pci_bridge_route() readability
Both the secondary and subordinate bus numbers are configured in this
function but it's not easy to search for in the tree as the PCI writes
are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate
variables and PCI config writes to improve the readability.

Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-02 13:15:12 +00:00
Rex-BC Chen c89f252608 soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.

This implementation is according to chapter 5.13 in MT8186 Functional
Specification.

BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02 13:13:24 +00:00
Rex-BC Chen 025fb17372 soc/mediatek: remove unused RTC_GPIO_USER_MASK
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02 13:13:10 +00:00
Zhuohao Lee d036a70d74 mb/google/brya: enable the SPD_CACHE_ENABLE
google/brask is using SODIMMs for DRAM. Reading spd data is
surprisingly slow (~170 ms), therefore enable the SPD cache.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=run on the device and measure the boot time decrease.

Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:10:47 +00:00
Zhuohao Lee 84eb532ec3 mb/google/brya/variants: add the smbus addr for dimm1
Align the setting with the adlrvp

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and works correctly in the brask

Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:10:33 +00:00
Zhuohao Lee b8b40964fc mb, soc: Add the SPD_CACHE_ENABLE
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
     the device could speed up around 150ms with this feature.

Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:10:21 +00:00
Gaggery Tsai 9d0fc3f396 mb/google/brya/var/vell: Remove Rcomp settings
This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.

BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
     PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
     filled properly by MRC.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:09:28 +00:00
Casper Chang 7a7a533725 mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.

BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
     test reboot 30 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-02 07:41:43 +00:00
Julian Schroeder 017ad9a41d soc/amd/common/fsp/fsp_validate.c: print warning instead of error
If an AMD FSP binary has no valid image revision information, print a
warning instead of an error.

Change-Id: Ie9c5a387b81205fe93382778090260e41e261776
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01 20:59:29 +00:00
Raul E Rangel 554f9e6b20 mb/amd/chausie: Always enable developer mode
Chausie doesn't have recovery mode buttons so it's impossible to
manually enter recovery mode to enable developer mode. This means we
need to force developer mode.

BUG=none
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 17:29:58 +00:00
Tim Wawrzynczak 63632d7d82 security/tpm: Add vendor-specific tis functions to read/write TPM regs
In order to abstract bus-specific logic from TPM logic, the prototype
for two vendor-specific tis functions are added in this
patch. tis_vendor_read() can be used to read directly from TPM
registers, and tis_vendor_write() can be used to write directly to TPM
registers.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-01 16:52:31 +00:00
Tim Wawrzynczak 591c7ebf18 drivers/tpm/spi: Convert static functions to enum cb_err return types
Instead of using raw integers to indicate success/failure, enum cb_err
can be used to makes things clearer, so this patch converts most
functions to return that instead of int.

TEST=boot to OS on google/dratini, no TPM errors seen

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 16:52:21 +00:00
Kevin Chiu d736fd4ea7 mb/google/guybrush/var/nipperkin: update thermal setting
Enable STT and decrease sustained_power_limit_mW to 12W

BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-01 11:57:58 +00:00
MAULIK V VAGHELA a4af1b58a5 intelblocks/cse: Skip sending EOP during S3 resume
coreboot should skip sending EOP during S3 resume since CSE doesn't
require EOP in resume path.

Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage
which doesn't get called during S3 resume.

In case EOP is moved in earlier stage, coreboot might send EOP in S3
resume as well. This patch adds check before calling cse_send_eop.

BUG=b:211085685
BRANCH=None
TEST=Check by moving EOP to earlier stage. EOP sending is skipped during
S3 resume.

Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-01 11:57:38 +00:00
Sean Rhodes 5da05b6e35 mb/starlabs/lite: Add StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-01 11:56:26 +00:00
Sean Rhodes c64626c9d9 ec/starlabs/merlin: Remove unused keyboard.asl
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01 11:55:06 +00:00
Sean Rhodes f6ea89d684 ec/starlabs/merlin: Add spaces to adhere to coding style
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e965513d5888398834cab8c8445e97372f2b115
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01 11:54:53 +00:00
Krishna Prasad Bhat e1ff978c9a mb/intel/adlrvp: Enable eMMC device for ADL-N RVP
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.

Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-01 11:54:26 +00:00
Raul E Rangel 56dbb4ac39 lib/Makefile: Add ability to specify -ldflags for rmodules
This will allow linker flag customization for rmodules.

BUG=b:221231786
TEST=Build guybrush with patch train and verify ldflags are passed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-28 22:02:22 +00:00
Fred Reitberger 527d73f1bf mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLY
Include chausie EC and EFS only in the RO region when building with
vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B
regions.

Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28 21:28:13 +00:00
Tim Wawrzynczak 7a94ad720e soc/intel/common/block/acpi: Return existing Object for _DSM subfunction
Currently the LPIT Get Constraints _DSM subfunction returns a package
containing the path to a nonexistent device (\NULL). This is used to
work around an issue with Windows, where returning an empty package will
cause a BSOD.  However, using this non-existent device can also cause
confusion, as on Linux, it shows an error in dmesg, e.g.

    ACPI Error: AE_NOT_FOUND, While resolving a named reference package
    element - \NULL (20200925/dspkginit-438)

Therefore, this patch modifies this returned package slightly to include
the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on
Intel platforms that use the PEP driver.

Tested on google/brya0 on ChromeOS 5.10 kernel
Tested with current Windows 11 ISO

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
2022-02-28 18:50:13 +00:00
Arthur Heymans b4ba289fa5 cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
This will allow to migrate all platform to the parallel_mp init code
and drop the old lapic_init code.

Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28 13:33:59 +00:00
David Wu 6179f7b618 mb/google/brya/var/kano: add enable_off_delay_ms to 30
Kano changes load switch of touch screen to TPS22914C (is not with
discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms
to fix DUT can't enter S0ix issue.

BUG=b:220811619
TEST=Boot kano to OS and run S0iX test 2500 cycles.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2022-02-28 13:32:04 +00:00
Jon Murphy e6e46c968a mb/google/skyrim: Enable PCIe devices in devicetree
BUG=b:214414301
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:31:40 +00:00
Jon Murphy 0bc013b15a mb/google/skyrim: Enable AP <-> D2 communication
Configure D2 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for D2 device and enable the required
config items.

BUG=b:214414776
TEST=Build

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:31:27 +00:00
Jon Murphy ee67ddc707 mb/google/skyrim: Add eSPI configuration
BUG=b:214413613
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:30:58 +00:00
Jon Murphy 4f4f32ba20 mb/google/skyrim: Add initial fch irq routing
BUG=b:214417045
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:30:31 +00:00
Jon Murphy 410b7cb97e mb/google/skyrim: Add initial I2C configuration
Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.

BUG=b:214414677
TEST=Build

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:30:13 +00:00
Jon Murphy f79cc51b3f mb/google/skyrim: Log mainboard events to elog
BUG=b:214414851
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:29:57 +00:00
Jon Murphy 6ad5f4ec16 mb/google/skyrim: Add ACPI configuration for USB ports
The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:29:42 +00:00
Jon Murphy 6e368f79ec soc/amd/sabrina: Add XHCI configuration
Add xhci 2 controller support for additional USB port/ Dummy setting

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28 13:29:24 +00:00
Cliff Huang 96bb0ba9e7 drivers/wwan/fm: Add support for _PTS for Fibocom 5G WWAN
Add DPTS (device prepare to sleep) method that is to be called in
mainboard's \_SB.MPTS, which is called in _PTS.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-28 13:29:02 +00:00
Nico Huber f514b8ae82 device/pci_device: Fix PCIe bridge detection
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(),
it's our virtual `domain` device.

Expecting a PCI device above bus 0 resulted in undefined behavior for
all boards with PCI. Only boards with a PCI device 00:00.0 that looked
like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake).

Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28 13:28:12 +00:00
David Wu e6ab52e289 mb/google/brya/var/kano: Add wifi sar table
1. Add wifi sar table for kano
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

BUG=b:214393458
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-02-28 13:27:53 +00:00
Angel Pons 0cd1a87d50 sb/intel/lynxpoint: Fix up comment
Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-28 13:27:22 +00:00
Frank Chu 9fc741d32f mb/google/dedede/var/pirika: Add Wifi SAR for pasara
Add wifi sar for pasara

BUG=b:216411442
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:27:11 +00:00
Jon Murphy b4156412db mb/google/skyrim: Enable USB controllers in devicetree
BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:39:02 +00:00
Jon Murphy 10ff9375ae mb/google/skyrim: Enable internal graphics
BUG=b:214416935
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-26 00:19:36 +00:00
Jon Murphy 4b2e04a53b mb/google/skyrim: Enable console UART
BUG=b:214414501
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:18:40 +00:00
Jon Murphy eab1827b66 mb/google/skyrim: Set up FW_CONFIG
BUG=b:214415048
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:18:09 +00:00
Jon Murphy e3e1801a33 mb/google/skyrim: Enable eSPI SCI events
Enable ESPI SCI events

BUG=b:214416630
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:40 +00:00
Jon Murphy 2a7445a165 mb/google/skyrim: Add smihandler
BUG=b:214415408
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:25 +00:00
Jon Murphy cbf0f98c61 mb/google/skyrim: Enable Chrome EC
BUG=b:214413613
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:10 +00:00
Jon Murphy 9e00571b49 mb/google/skyrim: Enable variants for Skyrim
BUG=b:214414033
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:16:39 +00:00
Jon Murphy af025d6ee1 mb/google/skyrim: CONFIG_CHROMEOS
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:16:17 +00:00
Jon Murphy 960fb2f4b8 mb/google/skyrim: Enable ACPI tables
Add GPIO initialization and ACPI generation for tables

BUG=b:214415303
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:15:58 +00:00
Subrata Banik 4de2c342fb soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
This fixes no practical problem, especially for coreboot where only
one process should access the SPI controller. It makes the code look
more spec compliant.

As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.

Software must initiate the next SPI transaction when this bit is 0.

Add non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.

BUG=b:215255210
TEST=Able to boot brya and verified SPI read/write is successful.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-26 00:15:28 +00:00
Raul E Rangel 737ad67d12 soc/amd/common/psp_verstage: Add missing post codes on S0i3 resume
We print these out in the normal flow, so lets add them for S0i3 resume
as well.

BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:09:27 +00:00
Raul E Rangel 5e0ed5016c soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinking
This feature was never used. Let's remove it to keep things simple.

BUG=221231786
TEST=Boot test guybrush and morphius and verify transfer buffer is
correctly passed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-26 00:09:18 +00:00
Zhuohao Lee 0b108a14c0 mb/google/brask: Update PCH power cycle related durations
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.

BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.

Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:46:19 +00:00
Zhuohao Lee 09f3b6cf21 mb, soc: change mainboard_memory_init_params prototype
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass

Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:45:49 +00:00
Usha P 3ecee3cdd9 mb/intel/adlrvp: Add support for MAX98373 codec
- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board

Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25 20:44:27 +00:00
Elyes Haouas 92c2ccda0c sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 20:42:36 +00:00
Arthur Heymans bd90a226a3 nb/intel/ironlake: Fix sending HECI messages
This code only worked when the payload (a packed struct) was 4 byte
aligned. With gcc11 this happens to not be the case.

Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 20:41:54 +00:00
MAULIK V VAGHELA d9c5b14f1e intelblocks/pcie: Correct mapping between LCAP port and coreboot index
coreboot uses port index which is 0 based for all PCIe root ports.
In case of PCIe remapping logic, coreboot reads LCAP register from PCIe
configuration space which contains port number (mostly 1 based). This
assumption might not be true for all the ports in coreboot.

TBT's LCAP registers are returning port index which are based on 2.
coreboot's PCIe remapping logic returns port index based on index 1.

This patch adds variable to pcie_rp_config to pass lcap_port_base to the
pcie remapping function, so coreboot can map any n-based LCAP encoding
to 0-based indexing scheme.

This patch updates correct lcap_port_base variable for all PCIe root
ports for all SOCs, so that function returns correct 0-based index from
LCAP port number.

BUG=b:210933428
BRANCH=None
TEST=Check if code compiles for all ADL boards

Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 18:59:51 +00:00
Felix Held 928a9c8f04 cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:44:45 +00:00
Felix Held 972d9f2cce arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:44:11 +00:00
Felix Held 887d4ed912 soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR define
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:43:11 +00:00
Felix Held f47d17d81e sb/intel/common/hpet: use HPET_BASE_ADDRESS definition
Use the definition from arch/x86 instead of a local redefinition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:42:59 +00:00
Felix Held 4b2464fc90 arch/x86: factor out and commonize HPET_BASE_ADDRESS definition
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-25 17:42:45 +00:00
Felix Held 46a3a044ad soc/intel/baytrail,braswell/include/iomap: drop unused HPET_BASE_SIZE
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I875916488a99af768d087691549a93f6fd5169ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:42:31 +00:00
Felix Held 4e03727e63 arch/x86/Kconfig: add HPET_MIN_TICKS
Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but
the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in
acpi/acpi.c, so define this option in arch/x86/Kconfig to have it
defined in all cases where the function that ends up using this
information gets called. Since we now have the type information for this
Kconfig option in a central place, it can be dropped from the Kconfig
file of the Intel southbridges that change the default value.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:42:20 +00:00
Felix Held 7f8c737fe9 acpi/acpi: use read32p instead of pointer dereferencing
Using read32p to get the contents of the first 4 bytes of the HPET MMIO
region instead of a pointer dereference should clarify what's done in
that piece of code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:41:58 +00:00
Jason Glenesk ce876aaa8f mb/google/guybrush: enable coreboot to request spl fuse
Enable guybrush based platforms to send fuse spl command to PSP when
required.

BUG=b:180701885
TEST=On a platform that supports SPL fusing. Confirm that PSP indicates
fusing is required, and confirm coreboot sends command. Fusing is
required when the image is built with an SPL table requiring newer
minimum versions. A message indicating fusing was requested will appear
in the serial log. "PSP: Fuse SPL requested"

Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-25 16:43:15 +00:00
FrankChu 85c64e3ff6 mb/google/volteer/var/collis: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:192535692
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-25 16:39:47 +00:00
Shelley Chen 1d72afbd2a herobrine: Add Villager variant
BUG=b:218415722
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B

Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-25 07:01:48 +00:00
Jon Murphy d2873756a7 mb/google/skyrim: First pass GPIO configuriation for Skyrim
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 02:07:10 +00:00
Felix Held 26f0310317 mb/amd/chausie/devicetree: add i2c_scl_reset
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:45 +00:00
Felix Held 9ec4bf2fcb mb/amd/chausie/devicetree: enable I2C controllers
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:36 +00:00
Kevin Chang f1313ece44 mb/google/brya/var/taeko: Add GL9750 SD card reader support
Add GL9750 SD card reader support.

BUG=b:220987566
TEST=Build FW and check device function normally.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I8f6ca45a320d34dfd820ef0b6e0d3163fab26027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 21:39:25 +00:00
Jon Murphy 9042427ea2 mb/google/skyrim: Add stubs to configure GPIOs
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 21:38:18 +00:00
Sean Rhodes 3a260ad8f1 soc/apollolake: Allow configuring individual USB ports on GLK
Allow configuring the limited fields that FSP-S provides.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-24 17:10:37 +00:00
Elyes Haouas 532e043b66 treewide: Write minor version at acpi_create_fadt() function
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0".
So set it correctly for treewide.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Lance Zhao
2022-02-24 17:10:02 +00:00
Terry Chen 95f8f92451 mb/google/brya: Add SPD configs for Crota
Add a mem_parts_used.txt for Crota, containing the
memory parts used in proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.

DRAM Part Name                 ID to assign
MT62F1G32D4DR-031 WT:B         0 (0000)
MT62F512M32D2DR-031 WT:B       1 (0001)
H9JCNNNBK3MLYR-N6E             1 (0001)
H9JCNNNCP3MLYR-N6E             0 (0000)
K3LKBKB0BM-MGCP                2 (0010)

BUG=b:215443524
TEST=emerge-brya coreboot

Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-24 01:25:32 +00:00
Angel Pons 4cee77bce3 nb/intel/ironlake: Clean up `jedec_read()` function
Deduplicate a condition and reflow some lines.

Tested on HP ProBook 6550b, still reaches TianoCore payload.

Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-24 01:20:41 +00:00
Angel Pons fa5ed059eb nb/intel/ironlake: Fix some quickpath init magic
Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.

The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.

Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).

Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24 01:18:56 +00:00
Angel Pons e2531ffaa8 nb/intel/ironlake: Move out HECI remainders into southbridge
Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.

Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24 01:18:03 +00:00
Robert Chen e39d371909 mb/google/brya/var/vell: Corrects ACPI _PLD macro setting
This patch is to denote the correct side of ACPI _PLD usb C ports.

        +-------------------------+
        |        LCD              |
        |                         |
        |                         |
        +-------------------------+
PORT_C2 |                         | PORT_C1
PORT_C3 |  DB                 MB  | PORT_C0
        |                         |
        +-------------------------+

BUG=b:220634230
TEST=emerge-brya coreboot

Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:32:24 +00:00
Wisley Chen 77711b8677 mb/google/brya/var/anahera{4es}: Add MT53E2G32D4NQ-046 WT:C support
Add new memory MT53E2G32D4NQ-046 WT:C support

BUG=b:220821471
TEST=emerge-brya coreboot

Change-Id: I4c21254213c2107d015adebb510612e0256ffb5c
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:31:58 +00:00
Wisley Chen a243111a6d mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:C
Add new memory MT53E2G32D4NQ-046 WT:C support.

BUG=b:220804962
TEST=emerge-brya coreboot

Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:31:41 +00:00
Eugene Myers b2c681fc4a security/intel/stm: Make STM setup MP safe
Some processor families allow for SMM setup to be done in parallel.

On processors that have this feature, the BIOS resource list becomes
unusable for some processors during STM startup.

This patch covers two cases: (1) The BIOS resource list becomes twice
as long because the smm_relocation function is called twice - this is
resolved by recreating the list on each invocation. (2) Not all
processors receive the correct resource list pointer - this is resolved
by having every processor execute the pointer calculation code, which is
a lot faster then forcing all processors to spin lock waiting for this
value to be calculated.

This patch has been tested on a Purism L1UM-1X8C and Purism 15v4.

Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2022-02-24 00:27:37 +00:00
Eugene Myers a514192ffe security/intel/stm: Use correct SMBASE for SMM descriptor setup
Commit ea3376c (SMM module loader version 2) changedhow the
SMBASE is calculated.

This patch modifies setup_smm_descriptor to properly acquire the
SMBASE.

This patch has been tested on a Purism L1UM-1X8C and a Purism 15v4.

Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I1d62a36cdcbc20a19c42266164e612fb96f91953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61688
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:27:08 +00:00
Felix Held b582ce0814 arch/x86/Kconfig: drop HPET_ADDRESS_OVERRIDE
Commit b433d26ef1 (arch/x86: Define
HPET_ADDRESS_OVERRIDE) added this Kconfig option and referenced the
via/cx700 chipset which has been dropped before the 4.9 release. No SoC
in the current tree selects HPET_ADDRESS_OVERRIDE and all SoCs have
their HPET mapped at 0xfed00000, so drop this unused and no longer
needed Kconfig option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4021ed6f84473c7a9223323fc8aa5d3f935d8084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62276
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:14:10 +00:00
Felix Held 6f413d1c3f soc/amd/*/include/soc/iomap.h: rework HPET base address check
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't
set so that the HPET_ADDRESS Kconfig option will have the right default
value. Instead check if the HPET_ADDRESS Kconfig value matches the
HPET_BASE_ADDRESS define in the SoC code which is the case if
HPET_ADDRESS_OVERRIDE isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:14:02 +00:00
Rob Barnes 22372f4ac9 cr50: Increase cr50 i2c probe timeout
Turns out 200ms still isn't enough in the worst reset conditions.
There's been some reports of failures at 200ms with some older
cr50 versions. Let's not take any chances and bump this way up
since if this fails, it prevents boot.

BUG=b:213828947
BRANCH=None
TEST=Reboot and suspend_stress on Nipperkin

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-23 16:26:03 +00:00
Xi Chen d239aaf741 src/mediatek: Refactor dramc_param to share more structures
The ddr_base_info struct, which stores basic DDR information, should be
platform independent. Currently the struct is defined in each SoC's
dramc_parah.h. To prevent code duplication, move it as well as other
related structs and enums to a common header.

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-23 15:06:27 +00:00
Rex-BC Chen 3a3920263a soc/mediatek/mt8186: disable VSRAM_CORE
VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.

BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23 15:05:40 +00:00
Uwe Poeche eee62c1537 drivers/mrc_cache/mrc_cache.c: Change loglevels
Since commit 7cd8ba6eda (console: Add loglevel prefix to interactive
consoles) on the very first boot some errors occur because no MRC data
is present in the MRC cache. This is normal because the memory training
is not done yet.

This patch changes the loglevel to BIOS_NOTICE which will prevent an
error in the log in this case.

Change-Id: I1e36590e33507515e5b9dd4eb361b3dbe165511e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61973
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23 15:05:12 +00:00
Mario Scheithauer f6056113e5 console: Fix LOG_FAST macro
In the LOG_FAST macro, the comparison was incorrectly made with 'level'
value. Correct is the comparison with 'speed'.
With the wrong comparison you cannot set a lower level for console log,
the highest level is always output.

TEST:
- Boot mc_ehl2 with console log level 5 and check output

Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-22 23:13:50 +00:00
Elyes Haouas e6ce594da6 mb/gizmosphere/gizmo/OptionsIds.h: Remove extra empty line
Change-Id: I8ad968da1771004f7f5869e5434473a498edeaa2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:25:38 +00:00
Elyes Haouas d08a76e3ea mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"
Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:25:25 +00:00
Elyes Haouas 6d508dfc2d mb/lenovo/g505s: Format code
Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:23:24 +00:00
Elyes Haouas 8f38e5f5dc sb/amd/cimx/sb800/amd_pci_int_defs.h: Fix serial IRQ INT name in comment
Change-Id: If351d93c47de2ef76fb24525ff6d134b35c5f3fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:18:24 +00:00
Elyes Haouas 4450bee6b3 sb/amd/pi/hudson/early_setup.c: Fix typo in comment
Change-Id: Ib631cdc0794dc91df27cb984d5c585e0eee4a2ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:17:15 +00:00
Elyes Haouas 090fcec945 southbridge/amd/*/*/reset.c: Reduce stylistic differences
Change-Id: I2f58098e786e9b61b0d059723c375a90559e95a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:15:39 +00:00
Elyes Haouas 2a6cc959ee southbridge/amd/*/*/smbus.c: Reformat code and reduce difference
Change-Id: I43644b757a5a85864162da6a35f7f2a5335f8007
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:13:43 +00:00
Elyes Haouas f0d4f930a0 mb/gizmosphere/gizmo/acpi/gpe.asl: Remove extra blank line
Change-Id: I0d9b07183b06915799f221390406e930ca253a0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:11:46 +00:00
Elyes Haouas a789643ac9 mb/gizmosphere/gizmo/devicetree.cb: Fix typo on 'pci'
While on it, use tab for indent.

Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:11:27 +00:00
Elyes Haouas 5996eea5af sb/intel/i82371eb: Constify pci_devfn_t devices
Change-Id: I9056464b36cde89d2fe88ff27531e467297bed0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 20:58:14 +00:00
Elyes Haouas d3687cd994 sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_config
Change-Id: I096ccd0ec224b98038d290422f568666bbede43a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 20:57:20 +00:00
Elyes Haouas 95231b264d src/Kconfig: Update the path to 'c_start.S' for GDB_STUB config
Change-Id: Ib31defde0d4983a9418f05e0b812a7bbbe4fe2b7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 20:49:10 +00:00
Sean Rhodes 16a55f7a56 mb/starlabs/labtop: Reconfigure GPIOs
Reconfigure the GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I27ecf066685f2a81ac884a9f276c518544449443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22 19:21:36 +00:00
Sean Rhodes 70a1ef0716 mb/starlabs/labtop: Reconfigure CNVi GPIOs
Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22 19:21:22 +00:00
Sean Rhodes ad58a188e8 mb/starlabs/labtop: Update trackpad GPIO configuration
Update trackpad GPIO to avoid IRQ Storm, that causes high power
consumption when idling or in S3.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22 19:21:07 +00:00
Sean Rhodes 6306fc2127 mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGL
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the
hardware TPM can be used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22 19:20:49 +00:00
Sean Rhodes 3830d7a7f5 mb/starlabs/labtop: Don't configure ESPI GPIOs
Don't configure ESPI GPIOs as the default values are correct.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22 19:20:30 +00:00
Elyes Haouas 36bf0947b9 soc/intel/common/block/acpi: Drop duplicated 'fadt->header.revision'
The 'fadt->header.revision' is already done at src/acpi/acpi.c acpi_create_fadt().

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib9b6dc7e86ca17e0b2d374ee2c3bdf06f8b82dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62222
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22 19:03:38 +00:00
Sean Rhodes 0884f21042 payloads/tianocore: Rework Makefile
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.

This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox

Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22 18:53:17 +00:00
Ronak Kanabar e0e6f07220 vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02
The headers added are generated as per FSP v3054.02.
Previous FSP version was v2503_00.
Changes Include:
- UPD Offset Update in FspmUpd.h

BUG=b:220076892
BRANCH=None
TEST=Build and boot adlnrvp

Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-22 18:27:06 +00:00
Felix Held 9478527966 soc/amd/sabrina/i2c: remove TODO
The SoC-specific I2C code and header file have been verified some time
ago, but it seems that I forgot to remove the corresponding TODOs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-22 18:20:18 +00:00
Elyes Haouas fd93cff329 treewide: Get rid of CONFIG_AZALIA_MAX_CODECS
Get rid of Kconfig symbol introduced at commit 5d31dfa8
High Definition Audio Specification Revision 1.0a says, there
are 15 SDIWAKE bits.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22 17:40:30 +00:00
Varshit B Pandya 7f7ac206f8 src/driver/intel/mipi_camera: Update ACPI entry to provide silicon info
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-22 15:58:37 +00:00
Felix Held cbaf753012 soc/amd/common/block/lpc/espi_util: use __fallthrough
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-22 15:56:55 +00:00
Felix Held 6f4a5454ac vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency
Compiling vboot_check.c depends on fmap_config.h already being generated
so add this dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-02-22 15:56:03 +00:00
Werner Zeh 6f74d38dc8 mb/siemens/mc_apl2: Enable PCI device for I2C bus 0
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.

Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.

Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 15:25:00 +00:00
Elyes Haouas 4045935eb8 include/acpi/acpi.h: Drop non-existing acpi_create_madt_lapic_nmis()
Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-22 00:02:27 +00:00
FrankChu 53d13cbb21 mb/google/volteer/var/drobit: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21 23:59:41 +00:00
FrankChu e46e9b04ae mb/google/volteer/var/delbin: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21 23:59:21 +00:00
FrankChu 994c1910e8 mb/google/volteer/var/copano: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21 23:58:58 +00:00
Zheng Bao f08705db4e soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21 23:49:35 +00:00
Zheng Bao 1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 21:29:50 +00:00
Reka Norman 5bba93e08a mb/google/brya: Enable eMMC HS400 mode for nissa
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.

BUG=b:197479026
TEST=Build test nivviks and nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21 17:05:45 +00:00
Felix Held aade40c3f6 mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByte
Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21 16:02:41 +00:00
Arthur Heymans b4389598cf soc/intel/alderlake: Make clang static assert happy
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:30:13 +00:00
Arthur Heymans 141163d5ea drivers/intel/pmc_mux: Fix printing type
Change-Id: I1cb517323e7d609ae6624363e116e9814fc631cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 15:29:55 +00:00
Arthur Heymans 02967e6113 soc/intel/alderlake: Fix function pointer type
const void is not a proper return type for a function. It's the
function pointer themselves that need to be const.

This fixes building with clang.

Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:28:46 +00:00
Arthur Heymans b53a55930e drivers/intel/fsp2_0/hob: Remove unused variable
Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-21 15:28:06 +00:00
Arthur Heymans 138db0601d soc/intel/adl/bootblock/report_platform.c: Use the correct format
Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:27:35 +00:00
Arthur Heymans 4998aaee23 ec/google/chromeec/ec_acpi.c: Cast compatible enum types
Clang complains about this.

Change-Id: If7af9d5a81c1c381490c9634e3da68ff7f5edda8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:27:15 +00:00
Elyes Haouas b55ac09ce3 [acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in comments
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 15:26:30 +00:00
Elyes HAOUAS 2164c308b4 include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file

Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-21 15:23:12 +00:00
Subrata Banik e0ddea49d1 soc/intel/denverton_ns: Add `pmc_mmio_regs` as public function
This patch adds `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.

BUG=none
TEST=none

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21 15:22:35 +00:00
Subrata Banik fac11d000a soc/intel/denverton_ns: Select PMC PCI discoverable config
This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to
reflect the SoC actual behaviour where PMC PCI device is still
visible over bus even after FSP-S exit.

Additionally, add DNV PMC PCI ID into PMC IA-common code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-02-21 15:22:01 +00:00
John Su bf81c24e07 mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHz
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.

Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz

BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
     measure by scope with felwinter.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-21 15:21:28 +00:00
Fred Reitberger aa41f77397 mb/amd/chausie/Kconfig: Move EC firmware image in CBFS
Move the EC to a location that does not conflict with where the main
CBFS is in the chromeos FMAP

Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21 15:20:47 +00:00
Elyes Haouas 1f5e1b4f3c src/acpi/acpigen.c: Reformat code
Change-Id: I58851c8a26cad61975f8ba2910eedef3029aab6f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
2022-02-21 15:19:24 +00:00
Krishna Prasad Bhat dbbb391700 mb/intel/adlrvp_n: Update devicetree
Update devicetree according to schematics.

TEST=Build and boot Alder Lake N RVP.

Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21 15:17:55 +00:00
Krishna Prasad Bhat a6d642fa8d soc/intel/alderlake: Enable eMMC based on dev enabled
1. Add eMMC device function in pci_devs.h.
2. Enable eMMC device and configuration based on dev enabled.
3. Add SOC acpi name for eMMC.

Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:17:26 +00:00
Krishna Prasad Bhat d2ca5be61a soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it.

Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21 15:17:07 +00:00
Elyes Haouas 8b950f4d7a src/acpi: Add macro for FADT Minor Version and use it
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
2022-02-21 15:16:37 +00:00
Felix Held 4ded64c1be mb/amd/chausie: increase RW_MRC_CACHE size in FMAP
On Sabrina SoCs the size of the APOB has increased, so the size of the
RW_MRC_CACHE FMAP sections needs to be increased in order for the data
to still fit in the corresponding FMAP partition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-19 00:46:50 +00:00
Cliff Huang 23f33546bb mb/google/brya: remove the delay from for WWAN _ON method.
Remove unecessary delay in RTD3 _ON Method after PERST# dessartion.

TEST:
2022-02-10T18:22:53.204391Z INFO kernel: [    0.190287] ACPI: Power Resource [RTD3] (on)
2022-02-10T18:22:53.204395Z INFO kernel: [    0.194252] ACPI: Power Resource [RTD3] (off)

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-02-18 23:23:27 +00:00
Elyes Haouas a1f5ad0849 nb/amd/pi/00730F01/northbridge.c: Use 'pci_{and,or}_config'
Change-Id: Ifd77c90fe82e20df91562fccea8b5d89dd4a193d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-18 23:23:07 +00:00
Subrata Banik e284ca26bf soc/intel/apollolake: Create alias for GEN_PMCON1 as GEN_PMCON_A
This patch creates alias for GEN_PMCON_A to maintain parity with other
IA SoC PMC register definitions.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id9a23c58a325cb544c50cbda432fe3117eea22fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 20:23:51 +00:00
Subrata Banik 7848aa9335 soc/intel/denverton_ns: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579.

Additionally, removed `PMC_` prefix from PMC configuration register
macros GEN_PMCON_A/B and ETR3.

Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV
to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on
function numbers.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 20:23:33 +00:00
Subrata Banik 95986169f9 soc/intel/alderlake: Skip FSP Notify APIs
Alder Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.

Additionally, created a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.

TODO: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.

BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 20:22:58 +00:00
Subrata Banik 90e318bba4 soc/intel/common/cse: Add `finalize` operation for CSE
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects all required configs:

BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-18 20:22:23 +00:00
Subrata Banik 34f26b2989 drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-18 20:21:45 +00:00
Wisley Chen 03c0853f4d mb/google/brya/redrix{4es}: Disable unused USB2/TCSS ports
Disable unused USB2/TCSS Ports.

BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18 20:18:58 +00:00
Boris Mittelberg 130de14a05 arch/x86/acpi: Add code for KEY_MENU
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi
keyboard

BUG=b:215038215
TEST=manually tested on Anahera device: pressing T13 key opens menu

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 20:18:41 +00:00
Boris Mittelberg 0c3b7f5411 ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h directly from the Chromium OS EC repo,
with the exception of changing the copyright header to SPDX format.
Update to commit hash af9a119

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18 20:18:21 +00:00
Felix Held 655caa2da0 soc/amd/common/block/psp/Makefile: add fmap_config.h dependency
Compiling efs_fmap_check.c depends on fmap_config.h already being
generated, so add this dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:14:33 +00:00
Felix Held 63226901c7 soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAP
Also add the Makefile dependency on the fmap_config.h file to make sure
that this file already exists when it's included.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:14:12 +00:00
Elyes Haouas 14976dbed0 include/acpi/acpi.h: Drop non-existing update_ssdt()
Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:13:23 +00:00
Elyes Haouas 61c9440888 include/acpi/acpi.h: Drop non-existing update_ssdtx()
Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:13:08 +00:00
Subrata Banik ef47212bf8 mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18 15:24:23 +00:00
John Su 41994fee94 mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter
Follow thermal team design to remove TSR3 sensor and update thermal
table for next build. The DPTF parameters were verified by thermal
team.

BUG=b:219690502
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:57:44 +00:00
Shon Wang d91a6842bf mb/google/brya/var/vell: Correct MIPI camera info
The CIO2 port was incorrectly set to 2, while the correct port is 1

BUG=b:210801553
TEST=Build and boot on vell, camera works correctly now

Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:57:27 +00:00
Subrata Banik d1275fb886 mb/google/brya/var/volmar: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:55 +00:00
Subrata Banik 5b0ce06d3d mb/google/brya/var/vell: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:45 +00:00
Subrata Banik d55a08242b mb/google/brya/var/taniks: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:33 +00:00
Subrata Banik f04faa149f mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:15 +00:00
Subrata Banik b6d522f6c7 mb/google/brya/var/{primus, primus4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:55:11 +00:00
Subrata Banik bf265b456b mb/google/brya/var/kano: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:59 +00:00
Subrata Banik 11fb6a87d7 mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0274f03926d97fc543b98f3fb961580283202806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:52 +00:00
Subrata Banik 159db81b64 mb/google/brya/var/felwinter: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:43 +00:00
Subrata Banik d2133c2ebf mb/google/brya/var/{brya0, brya4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:27 +00:00
Subrata Banik 08ec66dd12 mb/google/brya/var/{anahera, anahera4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:17 +00:00
Subrata Banik a55e5b7739 mb/google/brya/var/agah: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:07 +00:00
Subrata Banik b832955161 acpi: Use ACPI macros to configure USB port _PLD object
This patch adds two ACPI macros for USB port A and C _PLD object
configuration as:
1. ACPI_PLD_TYPE_A
2. ACPI_PLD_TYPE_C

The configurable parameters are
- Panel, Port is exposed on which face of a panel.
- Horizontal, Horizontal position on the panel where the device
               connection point resides.
- Group
   - Token, Unique numerical value identifying a group.
   - Position, Identifies this device connection point’s position
                 in the group (i.e. 1st, 2nd).

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:53:49 +00:00
Subrata Banik cb6e4926e7 mb/google/brya/var/volmar: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:53:27 +00:00
Subrata Banik b29d128023 mb/google/brya/var/vell: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:53:18 +00:00
Subrata Banik df533e6911 mb/google/brya/var/taniks: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:53:07 +00:00
Subrata Banik 0724ab1335 mb/google/brya/var/taeko4es: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:52:58 +00:00
Subrata Banik 782d012590 mb/google/brya/var/{redrix, redrix4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:52:48 +00:00
Subrata Banik 8c83e3f7fd mb/google/brya/var/{primus, primus4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:52:39 +00:00
Subrata Banik dc07db0c76 mb/google/brya/var/kano: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I78734f685672347b06783f834643347a35c59e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:52:29 +00:00
Subrata Banik 166b35210c mb/google/brya/var/{gimble, gimble4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:52:15 +00:00
Subrata Banik 5a0432182f mb/google/brya/var/{anahera, anahera4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:52:05 +00:00
Subrata Banik 895691a783 mb/google/brya/var/agah: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:51:57 +00:00
Jan Dabros 559563aaaa mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
Guybrush platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.

With this change in place it is important to use correct kernel version
which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3
available and thus TPM device available in OS, what may end up as a
serious error - guybrush refuses to boot without access to TPM.

BUG=b:204508404
BRANCH=guybrush
TEST=Build proper kernel and firmware. Run on guybrush and verify TPM
     functionality.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 23:14:19 +00:00
Jan Dabros 282d715133 soc/amd/common/block/i2c: Add support for shared TPM_I2C controller
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP. An example of
implementation within Linux kernel is available [1].

There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated
driver on OS side can bind to it and handle this special setup. Since
PSP takes care of I2C controller power management, we need to remove
PowerResource object from DSDT.

BUG=b:204508404
BRANCH=guybrush

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 23:14:02 +00:00
Fred Reitberger c17330c1dd mb/amd/chausie: Add EC blob into CBFS
Add chausie EC blob into CBFS at specified location

Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17 23:08:25 +00:00
Ravi Kumar Bokka ca7c9cc3f2 mb/google/herobrine: Disable fingerprint sensor on CRD devices
Qualcomm CRD devices do not have a fingerprint sensor so removing the
QUP configuration for it.  This QUP also coincidentally is the same as
the one used for the TPM, so this initially was also causing TPM
communication issues during bootup as the QUP was being reconfigured
during the later stages after QcLib execution.

BUG=b:206581077
BRANCH=None
TEST=Boot to kernel without any CR50 communication errors

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 22:43:28 +00:00
Robert Chen 6c4135e636 mb/google/brya/var/vell: Add Wifi SAR for vell
Add wifi sar for vell

BUG=b:218992598
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17 17:13:27 +00:00
Gaggery Tsai a7305c19e6 mb/google/brya/var/vell: Correct the DQ mapping
This patch corrects the DQ mapping and enable ECT. In Vell design,
the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2
but the DQ mappings are not swapped and that causes ECT training
failure.

BUT=b:208719081
TEST=emerge-brya coreboot chromeos-bootimage && ensure the system
     passes ECT training and all the way booting to the OS.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17 17:13:03 +00:00
Elyes Haouas 0ff941dd20 src/soc: Remove space before tab
Spaces before tabs are not allowed.

Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 17:12:49 +00:00
Elyes Haouas 5b0103f9b5 drivers/intel/usb4/retimer/retimer.c: Remove space before tab
Spaces before tabs are not allowed.

Change-Id: I1aa8490cb81a77f48d69c16c175eb4fec70dc0db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62054
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 17:12:23 +00:00
Varshit B Pandya 2938c46765 soc/intel/alderlake: Add CNVi common driver Kconfig
Alder Lake has CNVI device. Select SOC_INTEL_COMMON_BLOCK_CNVI
for Alder Lake.


Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6bf2292e870c990deb63fbf6e841ae7c5c63b3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-17 17:12:09 +00:00
Elyes Haouas 9647e630a0 soc/mediatek/mt8195/include/soc/addressmap.h: Remove space before tab
Spaces before tabs are not allowed.

Change-Id: I2732c01fd87c56227d47a4c0104de8e227b0cc34
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62018
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 17:11:56 +00:00
Felix Held 727a224aed amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32
The and-mask passed to the gpio_update32 call needs all 32 bits to be
set to ones. When building as 32 bit binary the -1UL will result in the
needed bit mask, but for a 64 bit build the constant would have 64 bits
set to ones which then gets truncated to 32 bits causing a compiler
error. Use 0xffffffff as bit mask instead which behaves correctly in
both cases and also clarifies what this is doing.

TEST=Timeless build for Chausie results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 15:44:42 +00:00
Felix Held 79313528cd amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addresses
This fixes a build failure when trying to build the code in 64 bit mode.

TEST=Timeless build for Chausie results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-17 15:44:26 +00:00
Shelley Chen ffc8532869 mb/google/herobrine: Add Gigadevice SPI Part
BUG=b:182963902
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16 23:42:44 +00:00
Shelley Chen 4ffdd075af mb/google/herobrine: Alphabetize SPI_FLASH configs
BUG=b:182963902
BRANCH=None
TEST=None

Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16 23:42:35 +00:00
Raul E Rangel de66e66517 soc/amd/cezanne/psp_verstage/uart: Fix off by 1 error
We only allow index = {0, 1}. Fix the check.

BUG=b:215599230
TEST=Build guybrush
BRANCH=guybrush

Found-by: Coverity CID 1469611
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I59615ab39faeded43b3803b4450c84ab8a8b81ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61988
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16 22:08:54 +00:00
Arthur Heymans fff20212af Use the fallthrough statement in switch loops
Clang does not seem to work with 'fall through' in comments.

Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16 21:29:53 +00:00
Arthur Heymans 97a0d61f0d compiler.h: Define a __fallthrough statement
Change-Id: I0487698290992162fac6bb74b5082901415e917e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16 21:28:09 +00:00
Tim Wawrzynczak 33b7bb6ee5 mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARS
The google/agah variant will use a peripheral that will require the use
of the PCIe Resizable BAR feature from the PCIe spec. Thus, select
the new Kconfig option to enable it. The appropriate Resizable BAR size
will be updated later.

BUG=b:214443809
TEST=build

Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-16 20:19:54 +00:00
Tim Wawrzynczak 8c93feda7f device: Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.

When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.

This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.

BUG=b:214443809
TEST=compile (device with this capability not available yet),
also verify that no changes are seen in resource allocation for
google/brya0 before and after this change.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16 20:19:07 +00:00