Commit Graph

39304 Commits

Author SHA1 Message Date
Zhuohao Lee 0b108a14c0 mb/google/brask: Update PCH power cycle related durations
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.

BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.

Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:46:19 +00:00
Zhuohao Lee 09f3b6cf21 mb, soc: change mainboard_memory_init_params prototype
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass

Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:45:49 +00:00
Usha P 3ecee3cdd9 mb/intel/adlrvp: Add support for MAX98373 codec
- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board

Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-25 20:44:27 +00:00
Elyes Haouas 92c2ccda0c sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 20:42:36 +00:00
Arthur Heymans bd90a226a3 nb/intel/ironlake: Fix sending HECI messages
This code only worked when the payload (a packed struct) was 4 byte
aligned. With gcc11 this happens to not be the case.

Change-Id: I5bb4ca4b27f8554208b12da177c51091ea6a108f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 20:41:54 +00:00
MAULIK V VAGHELA d9c5b14f1e intelblocks/pcie: Correct mapping between LCAP port and coreboot index
coreboot uses port index which is 0 based for all PCIe root ports.
In case of PCIe remapping logic, coreboot reads LCAP register from PCIe
configuration space which contains port number (mostly 1 based). This
assumption might not be true for all the ports in coreboot.

TBT's LCAP registers are returning port index which are based on 2.
coreboot's PCIe remapping logic returns port index based on index 1.

This patch adds variable to pcie_rp_config to pass lcap_port_base to the
pcie remapping function, so coreboot can map any n-based LCAP encoding
to 0-based indexing scheme.

This patch updates correct lcap_port_base variable for all PCIe root
ports for all SOCs, so that function returns correct 0-based index from
LCAP port number.

BUG=b:210933428
BRANCH=None
TEST=Check if code compiles for all ADL boards

Change-Id: I7f9c3c8e753b982e2ede1a41bf87d6355b82da0f
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61936
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 18:59:51 +00:00
Felix Held 928a9c8f04 cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic number
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:44:45 +00:00
Felix Held 972d9f2cce arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:44:11 +00:00
Felix Held 887d4ed912 soc/intel/denverton/include/iomap: drop unused DEFAULT_HPET_ADDR define
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie92bd54b072d545944b3d0251e9727ce493bb864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:43:11 +00:00
Felix Held f47d17d81e sb/intel/common/hpet: use HPET_BASE_ADDRESS definition
Use the definition from arch/x86 instead of a local redefinition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If172cde267062a8e759a9670ac93f4e74e8c94d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:42:59 +00:00
Felix Held 4b2464fc90 arch/x86: factor out and commonize HPET_BASE_ADDRESS definition
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-25 17:42:45 +00:00
Felix Held 46a3a044ad soc/intel/baytrail,braswell/include/iomap: drop unused HPET_BASE_SIZE
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I875916488a99af768d087691549a93f6fd5169ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-25 17:42:31 +00:00
Felix Held 4e03727e63 arch/x86/Kconfig: add HPET_MIN_TICKS
Some Intel southbridges have HPET_MIN_TICKS in their Kconfig files, but
the CONFIG_HPET_MIN_TICKS symbol is used in the common acpi code in
acpi/acpi.c, so define this option in arch/x86/Kconfig to have it
defined in all cases where the function that ends up using this
information gets called. Since we now have the type information for this
Kconfig option in a central place, it can be dropped from the Kconfig
file of the Intel southbridges that change the default value.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe012069dd4b51c15a8fbc6459186ad2ea405a03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:42:20 +00:00
Felix Held 7f8c737fe9 acpi/acpi: use read32p instead of pointer dereferencing
Using read32p to get the contents of the first 4 bytes of the HPET MMIO
region instead of a pointer dereference should clarify what's done in
that piece of code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecf5452c63635666d7d6b17e07a1bc6aa52e72fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 17:41:58 +00:00
Jason Glenesk ce876aaa8f mb/google/guybrush: enable coreboot to request spl fuse
Enable guybrush based platforms to send fuse spl command to PSP when
required.

BUG=b:180701885
TEST=On a platform that supports SPL fusing. Confirm that PSP indicates
fusing is required, and confirm coreboot sends command. Fusing is
required when the image is built with an SPL table requiring newer
minimum versions. A message indicating fusing was requested will appear
in the serial log. "PSP: Fuse SPL requested"

Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-02-25 16:43:15 +00:00
FrankChu 85c64e3ff6 mb/google/volteer/var/collis: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:192535692
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-25 16:39:47 +00:00
Shelley Chen 1d72afbd2a herobrine: Add Villager variant
BUG=b:218415722
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_VILLAGER -x -a -B

Change-Id: I84935ea280023cb0df1dd51fcd2a83d80db17710
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-25 07:01:48 +00:00
Jon Murphy d2873756a7 mb/google/skyrim: First pass GPIO configuriation for Skyrim
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 02:07:10 +00:00
Felix Held 26f0310317 mb/amd/chausie/devicetree: add i2c_scl_reset
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:45 +00:00
Felix Held 9ec4bf2fcb mb/amd/chausie/devicetree: enable I2C controllers
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:36 +00:00
Kevin Chang f1313ece44 mb/google/brya/var/taeko: Add GL9750 SD card reader support
Add GL9750 SD card reader support.

BUG=b:220987566
TEST=Build FW and check device function normally.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I8f6ca45a320d34dfd820ef0b6e0d3163fab26027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 21:39:25 +00:00
Jon Murphy 9042427ea2 mb/google/skyrim: Add stubs to configure GPIOs
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 21:38:18 +00:00
Sean Rhodes 3a260ad8f1 soc/apollolake: Allow configuring individual USB ports on GLK
Allow configuring the limited fields that FSP-S provides.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I56c37338eaa978fdb2c63807331493e8aecbdf60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-24 17:10:37 +00:00
Elyes Haouas 532e043b66 treewide: Write minor version at acpi_create_fadt() function
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0".
So set it correctly for treewide.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Lance Zhao
2022-02-24 17:10:02 +00:00
Terry Chen 95f8f92451 mb/google/brya: Add SPD configs for Crota
Add a mem_parts_used.txt for Crota, containing the
memory parts used in proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.

DRAM Part Name                 ID to assign
MT62F1G32D4DR-031 WT:B         0 (0000)
MT62F512M32D2DR-031 WT:B       1 (0001)
H9JCNNNBK3MLYR-N6E             1 (0001)
H9JCNNNCP3MLYR-N6E             0 (0000)
K3LKBKB0BM-MGCP                2 (0010)

BUG=b:215443524
TEST=emerge-brya coreboot

Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-24 01:25:32 +00:00
Angel Pons 4cee77bce3 nb/intel/ironlake: Clean up `jedec_read()` function
Deduplicate a condition and reflow some lines.

Tested on HP ProBook 6550b, still reaches TianoCore payload.

Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-24 01:20:41 +00:00
Angel Pons fa5ed059eb nb/intel/ironlake: Fix some quickpath init magic
Correct some Quickpath initialisation steps according to findings from
two different Intel reference code binaries as well as MCHBAR register
dump comparisons between vendor firmware and coreboot.

The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources.

Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init
now completes successfully instead of causing hangs before raminit.
Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still
reaches payload (e.g. TianoCore).

Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24 01:18:56 +00:00
Angel Pons e2531ffaa8 nb/intel/ironlake: Move out HECI remainders into southbridge
Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.

Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24 01:18:03 +00:00
Robert Chen e39d371909 mb/google/brya/var/vell: Corrects ACPI _PLD macro setting
This patch is to denote the correct side of ACPI _PLD usb C ports.

        +-------------------------+
        |        LCD              |
        |                         |
        |                         |
        +-------------------------+
PORT_C2 |                         | PORT_C1
PORT_C3 |  DB                 MB  | PORT_C0
        |                         |
        +-------------------------+

BUG=b:220634230
TEST=emerge-brya coreboot

Change-Id: I84515f98b6cdab5768df75690b0f5ca1bb9ad96d
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:32:24 +00:00
Wisley Chen 77711b8677 mb/google/brya/var/anahera{4es}: Add MT53E2G32D4NQ-046 WT:C support
Add new memory MT53E2G32D4NQ-046 WT:C support

BUG=b:220821471
TEST=emerge-brya coreboot

Change-Id: I4c21254213c2107d015adebb510612e0256ffb5c
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:31:58 +00:00
Wisley Chen a243111a6d mb/google/brya/var/redrix{4es}: Add MT53E2G32D4NQ-046 WT:C
Add new memory MT53E2G32D4NQ-046 WT:C support.

BUG=b:220804962
TEST=emerge-brya coreboot

Change-Id: I3353d7c119798ebb0b5ee1ea32161e54b4eec826
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-24 00:31:41 +00:00
Eugene Myers b2c681fc4a security/intel/stm: Make STM setup MP safe
Some processor families allow for SMM setup to be done in parallel.

On processors that have this feature, the BIOS resource list becomes
unusable for some processors during STM startup.

This patch covers two cases: (1) The BIOS resource list becomes twice
as long because the smm_relocation function is called twice - this is
resolved by recreating the list on each invocation. (2) Not all
processors receive the correct resource list pointer - this is resolved
by having every processor execute the pointer calculation code, which is
a lot faster then forcing all processors to spin lock waiting for this
value to be calculated.

This patch has been tested on a Purism L1UM-1X8C and Purism 15v4.

Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2022-02-24 00:27:37 +00:00
Eugene Myers a514192ffe security/intel/stm: Use correct SMBASE for SMM descriptor setup
Commit ea3376c (SMM module loader version 2) changedhow the
SMBASE is calculated.

This patch modifies setup_smm_descriptor to properly acquire the
SMBASE.

This patch has been tested on a Purism L1UM-1X8C and a Purism 15v4.

Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I1d62a36cdcbc20a19c42266164e612fb96f91953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61688
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:27:08 +00:00
Felix Held b582ce0814 arch/x86/Kconfig: drop HPET_ADDRESS_OVERRIDE
Commit b433d26ef1 (arch/x86: Define
HPET_ADDRESS_OVERRIDE) added this Kconfig option and referenced the
via/cx700 chipset which has been dropped before the 4.9 release. No SoC
in the current tree selects HPET_ADDRESS_OVERRIDE and all SoCs have
their HPET mapped at 0xfed00000, so drop this unused and no longer
needed Kconfig option.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4021ed6f84473c7a9223323fc8aa5d3f935d8084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62276
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:14:10 +00:00
Felix Held 6f413d1c3f soc/amd/*/include/soc/iomap.h: rework HPET base address check
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't
set so that the HPET_ADDRESS Kconfig option will have the right default
value. Instead check if the HPET_ADDRESS Kconfig value matches the
HPET_BASE_ADDRESS define in the SoC code which is the case if
HPET_ADDRESS_OVERRIDE isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24 00:14:02 +00:00
Rob Barnes 22372f4ac9 cr50: Increase cr50 i2c probe timeout
Turns out 200ms still isn't enough in the worst reset conditions.
There's been some reports of failures at 200ms with some older
cr50 versions. Let's not take any chances and bump this way up
since if this fails, it prevents boot.

BUG=b:213828947
BRANCH=None
TEST=Reboot and suspend_stress on Nipperkin

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-23 16:26:03 +00:00
Xi Chen d239aaf741 src/mediatek: Refactor dramc_param to share more structures
The ddr_base_info struct, which stores basic DDR information, should be
platform independent. Currently the struct is defined in each SoC's
dramc_parah.h. To prevent code duplication, move it as well as other
related structs and enums to a common header.

Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-02-23 15:06:27 +00:00
Rex-BC Chen 3a3920263a soc/mediatek/mt8186: disable VSRAM_CORE
VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.

BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23 15:05:40 +00:00
Uwe Poeche eee62c1537 drivers/mrc_cache/mrc_cache.c: Change loglevels
Since commit 7cd8ba6eda (console: Add loglevel prefix to interactive
consoles) on the very first boot some errors occur because no MRC data
is present in the MRC cache. This is normal because the memory training
is not done yet.

This patch changes the loglevel to BIOS_NOTICE which will prevent an
error in the log in this case.

Change-Id: I1e36590e33507515e5b9dd4eb361b3dbe165511e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61973
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-23 15:05:12 +00:00
Mario Scheithauer f6056113e5 console: Fix LOG_FAST macro
In the LOG_FAST macro, the comparison was incorrectly made with 'level'
value. Correct is the comparison with 'speed'.
With the wrong comparison you cannot set a lower level for console log,
the highest level is always output.

TEST:
- Boot mc_ehl2 with console log level 5 and check output

Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-22 23:13:50 +00:00
Elyes Haouas e6ce594da6 mb/gizmosphere/gizmo/OptionsIds.h: Remove extra empty line
Change-Id: I8ad968da1771004f7f5869e5434473a498edeaa2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:25:38 +00:00
Elyes Haouas d08a76e3ea mb/lenovo/g505s/acpi/ec.asl: Correct the path to "mainboard.h"
Change-Id: I273e29a26cf1c1ba34b95eb11bcb59a1360371e1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:25:25 +00:00
Elyes Haouas 6d508dfc2d mb/lenovo/g505s: Format code
Change-Id: I9cce00e1634d62a63b3563d54a7a0c56058d0e39
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:23:24 +00:00
Elyes Haouas 8f38e5f5dc sb/amd/cimx/sb800/amd_pci_int_defs.h: Fix serial IRQ INT name in comment
Change-Id: If351d93c47de2ef76fb24525ff6d134b35c5f3fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:18:24 +00:00
Elyes Haouas 4450bee6b3 sb/amd/pi/hudson/early_setup.c: Fix typo in comment
Change-Id: Ib631cdc0794dc91df27cb984d5c585e0eee4a2ad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:17:15 +00:00
Elyes Haouas 090fcec945 southbridge/amd/*/*/reset.c: Reduce stylistic differences
Change-Id: I2f58098e786e9b61b0d059723c375a90559e95a6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:15:39 +00:00
Elyes Haouas 2a6cc959ee southbridge/amd/*/*/smbus.c: Reformat code and reduce difference
Change-Id: I43644b757a5a85864162da6a35f7f2a5335f8007
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:13:43 +00:00
Elyes Haouas f0d4f930a0 mb/gizmosphere/gizmo/acpi/gpe.asl: Remove extra blank line
Change-Id: I0d9b07183b06915799f221390406e930ca253a0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:11:46 +00:00
Elyes Haouas a789643ac9 mb/gizmosphere/gizmo/devicetree.cb: Fix typo on 'pci'
While on it, use tab for indent.

Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 21:11:27 +00:00
Elyes Haouas 5996eea5af sb/intel/i82371eb: Constify pci_devfn_t devices
Change-Id: I9056464b36cde89d2fe88ff27531e467297bed0b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 20:58:14 +00:00
Elyes Haouas d3687cd994 sb/intel/ibexpeak: Constify struct southbridge_intel_ibexpeak_config
Change-Id: I096ccd0ec224b98038d290422f568666bbede43a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 20:57:20 +00:00
Elyes Haouas 95231b264d src/Kconfig: Update the path to 'c_start.S' for GDB_STUB config
Change-Id: Ib31defde0d4983a9418f05e0b812a7bbbe4fe2b7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 20:49:10 +00:00
Sean Rhodes 16a55f7a56 mb/starlabs/labtop: Reconfigure GPIOs
Reconfigure the GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I27ecf066685f2a81ac884a9f276c518544449443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22 19:21:36 +00:00
Sean Rhodes 70a1ef0716 mb/starlabs/labtop: Reconfigure CNVi GPIOs
Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22 19:21:22 +00:00
Sean Rhodes ad58a188e8 mb/starlabs/labtop: Update trackpad GPIO configuration
Update trackpad GPIO to avoid IRQ Storm, that causes high power
consumption when idling or in S3.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-22 19:21:07 +00:00
Sean Rhodes 6306fc2127 mb/starlabs/labtop: Configure TPM_IRQ GPIO for TGL
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the
hardware TPM can be used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22 19:20:49 +00:00
Sean Rhodes 3830d7a7f5 mb/starlabs/labtop: Don't configure ESPI GPIOs
Don't configure ESPI GPIOs as the default values are correct.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22 19:20:30 +00:00
Elyes Haouas 36bf0947b9 soc/intel/common/block/acpi: Drop duplicated 'fadt->header.revision'
The 'fadt->header.revision' is already done at src/acpi/acpi.c acpi_create_fadt().

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib9b6dc7e86ca17e0b2d374ee2c3bdf06f8b82dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62222
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22 19:03:38 +00:00
Sean Rhodes 0884f21042 payloads/tianocore: Rework Makefile
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.

This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox

Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
2022-02-22 18:53:17 +00:00
Ronak Kanabar e0e6f07220 vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3054.02
The headers added are generated as per FSP v3054.02.
Previous FSP version was v2503_00.
Changes Include:
- UPD Offset Update in FspmUpd.h

BUG=b:220076892
BRANCH=None
TEST=Build and boot adlnrvp

Change-Id: I7b921e2aa467597a1c764fc554e2e83e5bb522e8
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-22 18:27:06 +00:00
Felix Held 9478527966 soc/amd/sabrina/i2c: remove TODO
The SoC-specific I2C code and header file have been verified some time
ago, but it seems that I forgot to remove the corresponding TODOs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-22 18:20:18 +00:00
Elyes Haouas fd93cff329 treewide: Get rid of CONFIG_AZALIA_MAX_CODECS
Get rid of Kconfig symbol introduced at commit 5d31dfa8
High Definition Audio Specification Revision 1.0a says, there
are 15 SDIWAKE bits.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22 17:40:30 +00:00
Varshit B Pandya 7f7ac206f8 src/driver/intel/mipi_camera: Update ACPI entry to provide silicon info
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-22 15:58:37 +00:00
Felix Held cbaf753012 soc/amd/common/block/lpc/espi_util: use __fallthrough
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-22 15:56:55 +00:00
Felix Held 6f4a5454ac vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency
Compiling vboot_check.c depends on fmap_config.h already being generated
so add this dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2022-02-22 15:56:03 +00:00
Werner Zeh 6f74d38dc8 mb/siemens/mc_apl2: Enable PCI device for I2C bus 0
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.

Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.

Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-22 15:25:00 +00:00
Elyes Haouas 4045935eb8 include/acpi/acpi.h: Drop non-existing acpi_create_madt_lapic_nmis()
Change-Id: Ide854e5c8e2ed507548047cb6e1fad49efaffbb8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-22 00:02:27 +00:00
FrankChu 53d13cbb21 mb/google/volteer/var/drobit: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21 23:59:41 +00:00
FrankChu e46e9b04ae mb/google/volteer/var/delbin: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21 23:59:21 +00:00
FrankChu 994c1910e8 mb/google/volteer/var/copano: update default codec HID to 10EC5682
Modify function to set default audio codec HID
to be original setting 10EC5682.

BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work

Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-21 23:58:58 +00:00
Zheng Bao f08705db4e soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21 23:49:35 +00:00
Zheng Bao 1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 21:29:50 +00:00
Reka Norman 5bba93e08a mb/google/brya: Enable eMMC HS400 mode for nissa
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.

BUG=b:197479026
TEST=Build test nivviks and nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21 17:05:45 +00:00
Felix Held aade40c3f6 mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByte
Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21 16:02:41 +00:00
Arthur Heymans b4389598cf soc/intel/alderlake: Make clang static assert happy
Change-Id: Ia3cd66f6b735f7430abcdba8a9323d5ee1320fd4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:30:13 +00:00
Arthur Heymans 141163d5ea drivers/intel/pmc_mux: Fix printing type
Change-Id: I1cb517323e7d609ae6624363e116e9814fc631cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 15:29:55 +00:00
Arthur Heymans 02967e6113 soc/intel/alderlake: Fix function pointer type
const void is not a proper return type for a function. It's the
function pointer themselves that need to be const.

This fixes building with clang.

Change-Id: I99888ab9d9d80f1d6edb33b9f4a3f556f211a6e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:28:46 +00:00
Arthur Heymans b53a55930e drivers/intel/fsp2_0/hob: Remove unused variable
Change-Id: Ie9f4562be9b019d8dd65d4e9040fefbb6834fa03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-21 15:28:06 +00:00
Arthur Heymans 138db0601d soc/intel/adl/bootblock/report_platform.c: Use the correct format
Change-Id: I54c40434f44621c4ea6564ac9c87c5b2fa083b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:27:35 +00:00
Arthur Heymans 4998aaee23 ec/google/chromeec/ec_acpi.c: Cast compatible enum types
Clang complains about this.

Change-Id: If7af9d5a81c1c381490c9634e3da68ff7f5edda8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:27:15 +00:00
Elyes Haouas b55ac09ce3 [acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in comments
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 15:26:30 +00:00
Elyes HAOUAS 2164c308b4 include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'
'printram(x, ...)' is already defined in 'include/device/dram/common.h' file

Change-Id: I75e19065b9e713df3190202b7ca9e9cd8f3f44a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-21 15:23:12 +00:00
Subrata Banik e0ddea49d1 soc/intel/denverton_ns: Add `pmc_mmio_regs` as public function
This patch adds `pmc_mmio_regs` a public function for other IA common
code may need to get access to this function.

BUG=none
TEST=none

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I67a0f7fdcd0827172426bc938569a5022eff16f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21 15:22:35 +00:00
Subrata Banik fac11d000a soc/intel/denverton_ns: Select PMC PCI discoverable config
This patch selects SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE config to
reflect the SoC actual behaviour where PMC PCI device is still
visible over bus even after FSP-S exit.

Additionally, add DNV PMC PCI ID into PMC IA-common code.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaaea20e54c909800e4d75b58c29507fc1944cfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2022-02-21 15:22:01 +00:00
John Su bf81c24e07 mb/google/brya/variants/felwinter: Adjust I2Cs CLK to be around 400 kHz
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.

Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz

BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
     measure by scope with felwinter.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-21 15:21:28 +00:00
Fred Reitberger aa41f77397 mb/amd/chausie/Kconfig: Move EC firmware image in CBFS
Move the EC to a location that does not conflict with where the main
CBFS is in the chromeos FMAP

Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21 15:20:47 +00:00
Elyes Haouas 1f5e1b4f3c src/acpi/acpigen.c: Reformat code
Change-Id: I58851c8a26cad61975f8ba2910eedef3029aab6f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
2022-02-21 15:19:24 +00:00
Krishna Prasad Bhat dbbb391700 mb/intel/adlrvp_n: Update devicetree
Update devicetree according to schematics.

TEST=Build and boot Alder Lake N RVP.

Change-Id: I9faee1cb3539a0246fc6a87e15b3150533de1ee5
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21 15:17:55 +00:00
Krishna Prasad Bhat a6d642fa8d soc/intel/alderlake: Enable eMMC based on dev enabled
1. Add eMMC device function in pci_devs.h.
2. Enable eMMC device and configuration based on dev enabled.
3. Add SOC acpi name for eMMC.

Change-Id: I44f17420f7a2a1ca0fbb6cfb1886b1617c5a5064
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-21 15:17:26 +00:00
Krishna Prasad Bhat d2ca5be61a soc/intel/alderlake: Add eMMC ACPI methods for Alder Lake N
Alder Lake N SOC has eMMC device. Add ACPI ASL methods for it.

Change-Id: I53f04e81584493049d37b46e078d394d3c8a2f09
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-21 15:17:07 +00:00
Elyes Haouas 8b950f4d7a src/acpi: Add macro for FADT Minor Version and use it
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
2022-02-21 15:16:37 +00:00
Felix Held 4ded64c1be mb/amd/chausie: increase RW_MRC_CACHE size in FMAP
On Sabrina SoCs the size of the APOB has increased, so the size of the
RW_MRC_CACHE FMAP sections needs to be increased in order for the data
to still fit in the corresponding FMAP partition.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-19 00:46:50 +00:00
Cliff Huang 23f33546bb mb/google/brya: remove the delay from for WWAN _ON method.
Remove unecessary delay in RTD3 _ON Method after PERST# dessartion.

TEST:
2022-02-10T18:22:53.204391Z INFO kernel: [    0.190287] ACPI: Power Resource [RTD3] (on)
2022-02-10T18:22:53.204395Z INFO kernel: [    0.194252] ACPI: Power Resource [RTD3] (off)

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-02-18 23:23:27 +00:00
Elyes Haouas a1f5ad0849 nb/amd/pi/00730F01/northbridge.c: Use 'pci_{and,or}_config'
Change-Id: Ifd77c90fe82e20df91562fccea8b5d89dd4a193d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-18 23:23:07 +00:00
Subrata Banik e284ca26bf soc/intel/apollolake: Create alias for GEN_PMCON1 as GEN_PMCON_A
This patch creates alias for GEN_PMCON_A to maintain parity with other
IA SoC PMC register definitions.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id9a23c58a325cb544c50cbda432fe3117eea22fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 20:23:51 +00:00
Subrata Banik 7848aa9335 soc/intel/denverton_ns: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Added `MS4V` macro for GEN_PMCON_A bit 18 as per EDS doc:558579.

Additionally, removed `PMC_` prefix from PMC configuration register
macros GEN_PMCON_A/B and ETR3.

Moved PMC PCI device macro from pmc.h to pci_devs.h and name PCH_PMC_DEV
to PCH_DEV_PMC. Also, adjust PCI macros under B0:D31:Fx based on
function numbers.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2690ccd387b40c0d89cf133117fd91914e1b71a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 20:23:33 +00:00
Subrata Banik 95986169f9 soc/intel/alderlake: Skip FSP Notify APIs
Alder Lake SoC deselects Kconfigs as below:
- USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
- USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
to skip FSP notify APIs (Ready to boot and End of Firmware) and make
use of native coreboot driver to perform SoC recommended operations
prior booting to payload/OS.

Additionally, created a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again config.

TODO: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.

BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 20:22:58 +00:00
Subrata Banik 90e318bba4 soc/intel/common/cse: Add `finalize` operation for CSE
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects all required configs:

BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-18 20:22:23 +00:00
Subrata Banik 34f26b2989 drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_"  prefix.

1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
          USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
          USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
          USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE

The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.

For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.

Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.

Additionally, fixed SoC configs inclusion order alphabetically. 

BUG=b:211954778
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-18 20:21:45 +00:00
Wisley Chen 03c0853f4d mb/google/brya/redrix{4es}: Disable unused USB2/TCSS ports
Disable unused USB2/TCSS Ports.

BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18 20:18:58 +00:00
Boris Mittelberg 130de14a05 arch/x86/acpi: Add code for KEY_MENU
Support of MENU key (aka hamburger) for Chromebooks with Vivaldi
keyboard

BUG=b:215038215
TEST=manually tested on Anahera device: pressing T13 key opens menu

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I07873dd9385c743a6512408688ec44a5e97219f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61835
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 20:18:41 +00:00
Boris Mittelberg 0c3b7f5411 ec/google/chromeec: Update ec_commands.h
This change copies ec_commands.h directly from the Chromium OS EC repo,
with the exception of changing the copyright header to SPDX format.
Update to commit hash af9a119

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I1f2a140257d6127fb19bb514bc345466247b7499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18 20:18:21 +00:00
Felix Held 655caa2da0 soc/amd/common/block/psp/Makefile: add fmap_config.h dependency
Compiling efs_fmap_check.c depends on fmap_config.h already being
generated, so add this dependency.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:14:33 +00:00
Felix Held 63226901c7 soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAP
Also add the Makefile dependency on the fmap_config.h file to make sure
that this file already exists when it's included.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:14:12 +00:00
Elyes Haouas 14976dbed0 include/acpi/acpi.h: Drop non-existing update_ssdt()
Change-Id: Ie8535d97e883d3fed9414fb5ba65a0797b989c0d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:13:23 +00:00
Elyes Haouas 61c9440888 include/acpi/acpi.h: Drop non-existing update_ssdtx()
Change-Id: I2fd8470ed2b8e8f00de4ba64258aac1db52744c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18 17:13:08 +00:00
Subrata Banik ef47212bf8 mb/google/brya/var/{redrix, redrix4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-18 15:24:23 +00:00
John Su 41994fee94 mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter
Follow thermal team design to remove TSR3 sensor and update thermal
table for next build. The DPTF parameters were verified by thermal
team.

BUG=b:219690502
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:57:44 +00:00
Shon Wang d91a6842bf mb/google/brya/var/vell: Correct MIPI camera info
The CIO2 port was incorrectly set to 2, while the correct port is 1

BUG=b:210801553
TEST=Build and boot on vell, camera works correctly now

Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:57:27 +00:00
Subrata Banik d1275fb886 mb/google/brya/var/volmar: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:55 +00:00
Subrata Banik 5b0ce06d3d mb/google/brya/var/vell: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:45 +00:00
Subrata Banik d55a08242b mb/google/brya/var/taniks: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:33 +00:00
Subrata Banik f04faa149f mb/google/brya/var/{taeko, taeko4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:56:15 +00:00
Subrata Banik b6d522f6c7 mb/google/brya/var/{primus, primus4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:55:11 +00:00
Subrata Banik bf265b456b mb/google/brya/var/kano: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:59 +00:00
Subrata Banik 11fb6a87d7 mb/google/brya/var/{gimble, gimble4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0274f03926d97fc543b98f3fb961580283202806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:52 +00:00
Subrata Banik 159db81b64 mb/google/brya/var/felwinter: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:43 +00:00
Subrata Banik d2133c2ebf mb/google/brya/var/{brya0, brya4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:27 +00:00
Subrata Banik 08ec66dd12 mb/google/brya/var/{anahera, anahera4es}: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:17 +00:00
Subrata Banik a55e5b7739 mb/google/brya/var/agah: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:54:07 +00:00
Subrata Banik b832955161 acpi: Use ACPI macros to configure USB port _PLD object
This patch adds two ACPI macros for USB port A and C _PLD object
configuration as:
1. ACPI_PLD_TYPE_A
2. ACPI_PLD_TYPE_C

The configurable parameters are
- Panel, Port is exposed on which face of a panel.
- Horizontal, Horizontal position on the panel where the device
               connection point resides.
- Group
   - Token, Unique numerical value identifying a group.
   - Position, Identifies this device connection point’s position
                 in the group (i.e. 1st, 2nd).

BUG=b:216490477
TEST=emerge-brya coreboot

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I245b17019b6d3c5e380c16cb3c9f4edc4dd10cc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:53:49 +00:00
Subrata Banik cb6e4926e7 mb/google/brya/var/volmar: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:53:27 +00:00
Subrata Banik b29d128023 mb/google/brya/var/vell: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:53:18 +00:00
Subrata Banik df533e6911 mb/google/brya/var/taniks: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:53:07 +00:00
Subrata Banik 0724ab1335 mb/google/brya/var/taeko4es: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:52:58 +00:00
Subrata Banik 782d012590 mb/google/brya/var/{redrix, redrix4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:52:48 +00:00
Subrata Banik 8c83e3f7fd mb/google/brya/var/{primus, primus4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:52:39 +00:00
Subrata Banik dc07db0c76 mb/google/brya/var/kano: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I78734f685672347b06783f834643347a35c59e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:52:29 +00:00
Subrata Banik 166b35210c mb/google/brya/var/{gimble, gimble4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18 14:52:15 +00:00
Subrata Banik 5a0432182f mb/google/brya/var/{anahera, anahera4es}: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-02-18 14:52:05 +00:00
Subrata Banik 895691a783 mb/google/brya/var/agah: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.

This patch ensures USB _PLD group numbers are appear in order.

BUG=b:216490477
TEST=build coreboot and system boot into OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-18 14:51:57 +00:00
Jan Dabros 559563aaaa mb/google/guybrush: Enable SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP
Guybrush platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.

With this change in place it is important to use correct kernel version
which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3
available and thus TPM device available in OS, what may end up as a
serious error - guybrush refuses to boot without access to TPM.

BUG=b:204508404
BRANCH=guybrush
TEST=Build proper kernel and firmware. Run on guybrush and verify TPM
     functionality.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 23:14:19 +00:00
Jan Dabros 282d715133 soc/amd/common/block/i2c: Add support for shared TPM_I2C controller
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP. An example of
implementation within Linux kernel is available [1].

There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated
driver on OS side can bind to it and handle this special setup. Since
PSP takes care of I2C controller power management, we need to remove
PowerResource object from DSDT.

BUG=b:204508404
BRANCH=guybrush

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 23:14:02 +00:00
Fred Reitberger c17330c1dd mb/amd/chausie: Add EC blob into CBFS
Add chausie EC blob into CBFS at specified location

Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-17 23:08:25 +00:00
Ravi Kumar Bokka ca7c9cc3f2 mb/google/herobrine: Disable fingerprint sensor on CRD devices
Qualcomm CRD devices do not have a fingerprint sensor so removing the
QUP configuration for it.  This QUP also coincidentally is the same as
the one used for the TPM, so this initially was also causing TPM
communication issues during bootup as the QUP was being reconfigured
during the later stages after QcLib execution.

BUG=b:206581077
BRANCH=None
TEST=Boot to kernel without any CR50 communication errors

Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 22:43:28 +00:00
Robert Chen 6c4135e636 mb/google/brya/var/vell: Add Wifi SAR for vell
Add wifi sar for vell

BUG=b:218992598
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Change-Id: I74fddd1dbcb7019fd5fe394da291f125f0d4960f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17 17:13:27 +00:00
Gaggery Tsai a7305c19e6 mb/google/brya/var/vell: Correct the DQ mapping
This patch corrects the DQ mapping and enable ECT. In Vell design,
the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2
but the DQ mappings are not swapped and that causes ECT training
failure.

BUT=b:208719081
TEST=emerge-brya coreboot chromeos-bootimage && ensure the system
     passes ECT training and all the way booting to the OS.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-17 17:13:03 +00:00
Elyes Haouas 0ff941dd20 src/soc: Remove space before tab
Spaces before tabs are not allowed.

Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 17:12:49 +00:00
Elyes Haouas 5b0103f9b5 drivers/intel/usb4/retimer/retimer.c: Remove space before tab
Spaces before tabs are not allowed.

Change-Id: I1aa8490cb81a77f48d69c16c175eb4fec70dc0db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62054
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 17:12:23 +00:00
Varshit B Pandya 2938c46765 soc/intel/alderlake: Add CNVi common driver Kconfig
Alder Lake has CNVI device. Select SOC_INTEL_COMMON_BLOCK_CNVI
for Alder Lake.


Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6bf2292e870c990deb63fbf6e841ae7c5c63b3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-17 17:12:09 +00:00
Elyes Haouas 9647e630a0 soc/mediatek/mt8195/include/soc/addressmap.h: Remove space before tab
Spaces before tabs are not allowed.

Change-Id: I2732c01fd87c56227d47a4c0104de8e227b0cc34
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62018
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 17:11:56 +00:00
Felix Held 727a224aed amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32
The and-mask passed to the gpio_update32 call needs all 32 bits to be
set to ones. When building as 32 bit binary the -1UL will result in the
needed bit mask, but for a 64 bit build the constant would have 64 bits
set to ones which then gets truncated to 32 bits causing a compiler
error. Use 0xffffffff as bit mask instead which behaves correctly in
both cases and also clarifies what this is doing.

TEST=Timeless build for Chausie results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17 15:44:42 +00:00
Felix Held 79313528cd amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addresses
This fixes a build failure when trying to build the code in 64 bit mode.

TEST=Timeless build for Chausie results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-17 15:44:26 +00:00
Shelley Chen ffc8532869 mb/google/herobrine: Add Gigadevice SPI Part
BUG=b:182963902
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16 23:42:44 +00:00
Shelley Chen 4ffdd075af mb/google/herobrine: Alphabetize SPI_FLASH configs
BUG=b:182963902
BRANCH=None
TEST=None

Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16 23:42:35 +00:00
Raul E Rangel de66e66517 soc/amd/cezanne/psp_verstage/uart: Fix off by 1 error
We only allow index = {0, 1}. Fix the check.

BUG=b:215599230
TEST=Build guybrush
BRANCH=guybrush

Found-by: Coverity CID 1469611
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I59615ab39faeded43b3803b4450c84ab8a8b81ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61988
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16 22:08:54 +00:00
Arthur Heymans fff20212af Use the fallthrough statement in switch loops
Clang does not seem to work with 'fall through' in comments.

Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16 21:29:53 +00:00
Arthur Heymans 97a0d61f0d compiler.h: Define a __fallthrough statement
Change-Id: I0487698290992162fac6bb74b5082901415e917e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16 21:28:09 +00:00
Tim Wawrzynczak 33b7bb6ee5 mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARS
The google/agah variant will use a peripheral that will require the use
of the PCIe Resizable BAR feature from the PCIe spec. Thus, select
the new Kconfig option to enable it. The appropriate Resizable BAR size
will be updated later.

BUG=b:214443809
TEST=build

Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-16 20:19:54 +00:00
Tim Wawrzynczak 8c93feda7f device: Add support for PCIe Resizable BARs
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can
indicates support for "Resizable BARs" via a PCIe extended capability.

When support this capability is indicated by the device, the size of
each BAR is determined in a different way than the normal "moving
bits" method. Instead, a pair of capability and control registers is
allocated in config space for each BAR, which can be used to both
indicate the different sizes the device is capable of supporting for
the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and
to also inform the device of the size that the allocator actually
reserved for the MMIO range.

This patch adds a Kconfig for a mainboard to select if it knows that it
will have a device that requires this support during PCI enumeration.
If so, there is a corresponding Kconfig to indicate the maximum number
of bits of address space to hand out to devices this way (again, limited
by what devices can support and each individual system may want to
support, but just like above, this number can range from 20 to 63) If
the device can support more bits than this Kconfig, the resource request
is truncated to the number indicated by this Kconfig.

BUG=b:214443809
TEST=compile (device with this capability not available yet),
also verify that no changes are seen in resource allocation for
google/brya0 before and after this change.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16 20:19:07 +00:00
Ronak Kanabar 53c2250dbf vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v2503_00
The headers added are generated as per Alder Lake N FSP v2503_00.
Previous FSP version was v2503_00.
Change include: Add following Emmc UPDs in Fsps.h
- ScsEmmcEnabled
- ScsEmmcHs400Enabled
- EmmcUseCustomDlls
- EmmcTxCmdDelayRegValue
- EmmcTxDataDelay1RegValue
- EmmcTxDataDelay2RegValue
- EmmcRxCmdDataDelay1RegValue
- EmmcRxCmdDataDelay2RegValue
- EmmcRxStrobeDelayRegValue

BUG=b:213828776
BRANCH=None

Change-Id: I617673a0cb12e7165f2f63cce73fff38bc7bf827
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-16 20:17:46 +00:00
Tony Huang 83881e7824 mb/google/brya/var/agah: Change ELAN touchpad driver for eKT3744
Change to use i2c/generic to match ELAN FW update script.

BUG=b:210970640
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16 20:17:06 +00:00
Jason Glenesk fd539b40af soc/amd/common/block/psp: add PSP command
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is required. Also add Kconfig option to enable sending message.

BUG=b:180701885
TEST=On a platform that supports SPL fusing. Build an image with an SPL
table indicating fusing is required, confirm that PSP indicates fusing
required and coreboot sends the appropriate command. A message indicating
PSP requested fusing will appear in the log: "PSP: Fuse SPL requested"

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-02-16 18:33:56 +00:00
Sergii Dmytruk a816c29882 payloads/external: add skiboot (for QEMU/Power9)
Add an option to build skiboot as a payload. This makes QEMU Power9
board simpler to use as skiboot is necessary anyway.

Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-16 15:39:19 +00:00
Krishna Prasad Bhat 8d436cfc1a soc/intel/alderlake: Correct Alder Lake M/N ESPI device ID
Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign
it to the correct value.
Reference documents: 619501, 645548.

Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16 15:38:34 +00:00
Eric Lai 7d8b553608 mb/google/brya: Update memory DQ map
Follow latest schematic to update the DQ map.

BUG=b:218939997
TEST=boot into OS without issue.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16 15:38:12 +00:00
Kane Chen 5e8dd5d24a drivers/intel/fsp: Set FSP_LOG_LEVEL_ERR_WARN_INFO for DEBUG_RAM_SETUP
To get verbose MRC log includes RMT log, we need to set
FSP_LOG_LEVEL_ERR_WARN_INFO instead.

TEST=tested on gimble, see MRC verbose and RMT log are printed

Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Change-Id: I3896f0482dfde090b4e087490b7937683b5de091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16 15:38:00 +00:00
Sean Rhodes c249c4b8f0 mb/starlabs/labtop: Disconnect unused GPIO's
Disconnect all GPIO's that aren't connected to anything.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15 23:49:25 +00:00
Sean Rhodes 3307451752 mb/starlabs/labtop: Add comments for GPIOs
Add comment for each GPIO details its endpoint based
on the schematic.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15 23:48:49 +00:00
Sean Rhodes 55e43d82ac ec/starlabs/merlin: Adjust Keyboard Backlight configuration
* Change TGL Q Event for Keyboard Backlight to Q4A
* Change enabled value to 0xdd

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibae95e458f14b9d03ff50cb6222b336fd015d0e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15 23:47:31 +00:00
Sean Rhodes 45f9ca4824 ec/starlabs/merlin: Apply EC settings when suspending
Currently, the settings from CMOS were written to the
EC, which was pointless.

Now, when suspending, the EC values are stored in CMOS
when suspending and subsequently restored when waking.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15 23:44:16 +00:00
Angel Pons d00cfcb0a1 nb/intel/ironlake/raminit_heci.c: Move to southbridge scope
HECI stuff is in the southbridge, so put the code in there. Rename the
file to match the name of the function it provides.

Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15 23:39:12 +00:00
Angel Pons 3461917898 nb/intel/ironlake: Decouple `setup_heci_uma()` from northbridge
Remove all northbridge dependencies in the `setup_heci_uma()` function.
Update its signature to not pull in raminit internals and drop a dummy
read that doesn't have any side-effects (it's probably a leftover from
a replay of vendor firmware). This code will be moved into southbridge
scope in a follow-up.

Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15 23:38:37 +00:00
Angel Pons c35ce0e2a6 nb/intel/ironlake/raminit_heci.c: Turn into compilation unit
Remove the temporary `raminit_heci.c` include and make it a proper
compilation unit. Export the `setup_heci_uma()` function.

Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15 23:37:25 +00:00
Angel Pons 4e722d0766 nb/intel/ironlake: Split out HECI code out of raminit
Move HECI code out of raminit.c into a separate raminit_heci.c file. To
preserve reproducibility, use a temporary .c include. This will be gone
in a follow-up.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I240552c9628f613fcfa8d2dd09b8e59c87df6019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-15 23:37:06 +00:00
Angel Pons c063b5d08e arch/x86/id.S: Fix building with clang
Commit 0e688b113d (arch/x86/id.S: Fix
building with clang) broke building with GCC 8.3 so this approach
should work for both GCC 8.3 and clang. The clang error is:

     CC         bootblock/arch/x86/id.o
/tmp/id-35b17a.s:35:7: error: expected relocatable expression
.long - ver
      ^
/tmp/id-35b17a.s:36:7: error: expected relocatable expression
.long - vendor
      ^
/tmp/id-35b17a.s:37:7: error: expected relocatable expression
.long - part
      ^

Change-Id: Ide3d313800641d4d9b5f79127f84d9fdb4ec2b96
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15 23:36:33 +00:00
Angel Pons 17fbf58fdb Revert "arch/x86/id.S: Fix building with clang"
This reverts commit 0e688b113d.

Reason for revert: Breaks building with GCC 8.3 which is currently
needed to build bootable coreboot images for Ironlake boards:

src/arch/x86/id.S: Assembler messages:
src/arch/x86/id.S:14: Error: value of 4294967344 too large for field of 4 bytes at 48
src/arch/x86/id.S:15: Error: value of 4294967327 too large for field of 4 bytes at 52
src/arch/x86/id.S:16: Error: value of 4294967318 too large for field of 4 bytes at 56

Change-Id: I9e13b15c062bc6598717382b1fedfa120c6d7209
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15 23:36:02 +00:00
Felix Held 80ddd29adb mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblock
The SPI ROM REQ/GNT pins are used in systems where the EC and the APU
share one flash chip to make sure that not both devices will try to
access the flash at the same time. The firmware running before the x86
cores are released from reset has likely already done this, but do it
again in bootblock just to be sure. The KBRST_L pin can be used to reset
the APU from the EC.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:34:33 +00:00
Matt DeVillier 0de0254a1f soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboard
Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1]

moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig,
but in doing so inadvertently disabled HECI1 for Puff-based boards which
previously had HECI1 enabled by default. To correct this, move the Kconfig
selection back into the mainboard Kconfig, and set defaults to match values
prior to refactoring in 805956bce.

Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and
ensure Disable HECI1 option defaults to selected for all except Puff.

Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15 18:11:22 +00:00
Matt DeVillier 575a2e589d soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKE
Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1]

switched CNL-based mainboards from using FSP for HECI disablement to SBI
msg, but this causes google/hatch to hang when attempting to unhide p2sb
as part of disabling HECI1 via SBI during SMM, so switch to using
PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not
support PMC disablement method, so they remain using SBI.

Test: build/boot google/hatch, verify HECI1 disabled via console log and
lspci in booted OS.

Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15 18:10:59 +00:00
Matt DeVillier 148b545671 soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.c
Move cse_disable_mei_devices() from cse_eop.c into heci_disable.c,
so that platforms needing to use heci1_disable_using_pmc() can do so
without requiring cse_eop.c be unnecessarily compiled in as well.

This will allow Cannon Lake platforms to use PMC to disable HECI1 instead
of SBI, which is currently causing a hang on google/hatch (and will be
changed in a follow-on patch).

Test: build test google/{ampton,drobit,eve,akemi} boards to ensure no breakage.

Change-Id: Iee6aff570aa4465ced6ffe2968412bcbb5ff3a8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15 18:10:33 +00:00
Teddy Shih 49e669f955 mb/google/dedede/var/beadrix: Add LTE power off sequence
This change adds LTE power off sequence for beadrix.

BUG=b:204882915
BRANCH=dedede
TEST=FW_NAME=beadrix emerge-dedede coreboot

Change-Id: I11370bf69438465d2230e2633044ba42685a152b
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61329
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15 17:26:57 +00:00
Matt DeVillier bb052ced54 soc/intel/apollolake: Fix overlapping ACPI resource ranges
The address space allotted to MCRS in the northbridge needs to be exclusive
of the address space allotted to the GPIO controllers in the southbridge,
otherwise Windows complains of overlapping resource ranges and disables
the GPIO controllers. To prevent overlap, use CONFIG_PCR_BASE_ADDRESS
to set the upper bound of MCRS rather than MMCONF.

Test: boot Windows 10/11 on google/{reef,ampton} and verify that
GPIO controllers are indicated as without fault in Device Manager.

Change-Id: I2117054edb448e717b7cbe80958c9c4e6c996e2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
2022-02-15 17:26:44 +00:00
Subrata Banik 7c31d17317 soc/intel/common/cse: Add `cse_send_end_of_post()` as a public function
This patch creates a global function `cse_send_end_of_post()` so
that IA common code may get access to this function for sending EOP
command to the HECI1/CSE device.

Additionally, use static variable to track and prevent sending EOP
command more than once in boot flow.

BUG=b:211954778
TEST=Able to build and boot Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-15 17:21:10 +00:00
Subrata Banik b3671ec5de soc/intel/*/pmc: Add `finalize` operation for pmc
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware.

Additionally, move the PMCON status bit clear operation to `.final` ops
to cover any such chances where FSP-S Notify Phase or any other later
boot stage may request a global reset and PMCON status bit remains set.

BUG=b:211954778
TEST=Able to build brya with these changes.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15 17:20:43 +00:00
Subrata Banik 9e00a817f3 soc/intel/xeon_sp: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15 17:17:09 +00:00
Subrata Banik 42914feb1f soc/intel/apollolake: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15 17:16:51 +00:00
Subrata Banik 112ffd7642 soc/intel/skylake: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Additionally, move the PMCON status bit clear operation to finalize.c
to cover any such chances where FSP-S NotifyPhase requested a global
reset and PMCON status bit remains set.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15 17:16:32 +00:00
Zheng Bao b09166d0e6 mb/google/guybrush: Add a mainboard specific SPL table
Chromebook needs to do some additional check, which is not
available in the AMD's PI released SPL table.

BUG=b:216096562

Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15 17:14:35 +00:00
Werner Zeh 6c5efcd268 soc/intel/elkhartlake: Fix PCR ID for eSPI
According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID
for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file.

[1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true

Test=Read and modify PCR registers of eSPI controller.

Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15 17:08:10 +00:00
Reka Norman 975c5e5ab0 mb/google/brya/var/nereid: Disable LTE-related GPIOs
Nereid does not support the LTE sub-board, so disable the LTE-related
GPIOs.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6d6b5babeefb7c4b79adab5e756f37616c2338d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15 16:21:43 +00:00
Reka Norman b63d5f8b9c mb/google/brya/var/nereid: Initialise overridetree
Add an initial overridetree for nereid based on the pre-proto schematic
and build matrix.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nereid

Change-Id: I7d313439337c84ab1024b3570cc7b57b4255af5d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15 16:21:30 +00:00
Reka Norman 002d9b2a7a mb/google/brya/var/nereid: Add H9JCNNNBK3MLYR-N6E for P1 build
Nereid P1 will also use Hynix H9JCNNNBK3MLYR-N6E. Add it to the parts
list and regenerate the memory IDs using part_id_gen.

BUG=b:217096008
TEST=abuild -a -x -c max -p none -t google/brya -b nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ibacb9dfb336967dd7fffe351d785cbbff9ba8b7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15 16:21:04 +00:00
Dtrain Hsu e8c160e6af mb/google/brya: Create kinox variant
Create the kinox variant of the brask reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:215049181
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KINOX

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I68cac421f6299a5f82f2ab51633173648c993060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61789
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15 16:20:34 +00:00
Angel Pons 92d449902e drivers/wwan/fm/acpi_fm350gl.c: Fix bit checks
Fix always-true conditions to properly test whether a bit is set.

Change-Id: I54b5dbfdbb99a47ef0dfdb9497179f516d6e1f23
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15 16:19:57 +00:00
Angel Pons d85319a12d soc/intel/common/block/pcie/rtd3: Fix bit checks
Fix always-true conditions to properly test whether a bit is set.

Change-Id: Ibfeafe222c0c2b39ced5b77f79ceb0c679a471b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15 16:19:37 +00:00
MAULIK V VAGHELA dfde9b125c Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"
This reverts commit 9a7fbbc98e.

SkipMbpHob UPD skips generation of MBP Hob within FSP. Skipping MBP
Hob generation also skips syncing correct version of chipset
data with CSE since FSP uses version information from MBP HOB.
In absence of MBP Hob, FSP is unable to get version information and
hence chipset data sync is skipped.

This creates an issue while platform tries to enter deeper sleep
states.

BUG=b:215448362
BRANCH=None
TEST= FSP can get version information from MBP HOB and chipset sync
is performed. It has been Verified using FSP debug logs on Brya
board.

Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15 16:19:02 +00:00
Sean Rhodes 2d58d5c052 soc/apollolake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-15 16:18:20 +00:00
Matt DeVillier 7c2f57a4c7 soc/intel/cnl: Enable CSE FW sync for CSE LITE SKU
Boards based on google/puff baseboard (hatch variant) use CSE LITE,
which utilizes RO and RW firmware. If the CSE does not switch to the
RW firmware, the HECI1 interface is disabled, and dependent drivers
(like SOF audio firmware) fail to load. Use the same logic as other
platforms utilizing CSE LITE (eg, TGL/JSL) to check if an ME RW
firmware update is available, and if not jump to the onboard RW
firmware.

Test: built/boot Manjaro 21.x on google/wyvern, verify CSE RW firmware
loaded via cbmem console, HECI1 interface is present vis lspci, and
the SOF DSP firmware is correctly loaded via dmesg.

Change-Id: I0ae21adde4a64bbcc5fa4fb144436a0430e92280
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15 16:17:56 +00:00
Fred Reitberger 81d3cdeab2 soc/amd/sabrina: Select ACP gen2
Select ACP gen2 for Sabrina

Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15 16:17:31 +00:00
Fred Reitberger 0fcf8356eb soc/amd/common/acp: add acp_gen2
The gen2 ACP register definitions and locations are different from
previous models. Specific code is refactored into acp_gen1 and acp_gen2.
Update ACP register locations and definitions for gen2.

Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15 16:17:24 +00:00
T Michael Turney df81e07c37 herobrine: update SPI-NOR config options
Configuration support for 4k-byte addressing mode

BUG=b:215605946
TEST=Validated on qualcomm sc7280 developement board

Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
Signed-off-by: T Michael Turney <quic_mturney@quicinc.com>
Change-Id: If82de6204446251dded1b83684677e6eb536e6fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-15 02:36:59 +00:00
T Michael Turney d43e688ed2 drivers: spi_flash: Addressing mode change for SPI NOR
As 4-byte addressing mode is not support in coreboot, change the
addressing mode of SPI NOR from 4-bytes to 3-bytes.

BUG=b:215605946
TEST=Validated on qualcomm sc7280 development board

Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com>
Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-15 01:11:26 +00:00
Shon Wang 02b2afa8e9 mb/google/brya/var/vell: update gpio for DMIC
Data on channel 0 & 1 are normal (from DMIC)
but there is noise on channel 2 & 3, so change to NF
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE),
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE),

BUG=b:210802722
TEST=FW_NAME=vell emerge-brya coreboot

Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14 21:12:59 +00:00
Raul E Rangel 9fc5166ca7 mb/google/guybrush: Enable power resource for BT
The `reset` gpio is currently being consumed by the btusb kernel driver.
The functionality was added in https://crrev.com/c/3342774. The goal of
the patch was to reset the BT device when command timeouts occur. This
works, but it doesn't support the case where the BT device is having
problems with USB enumeration. In that case the device can't enumerate
so the driver can't help resetting the device.

If we instead switch to using an ACPI power resource, the kernel can
control the BT device's power. This is beneficial when the device is
having USB communication problems since the kernel will try and power
cycle the device.

We don't lose the ability to reset the device on command timeouts
either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if
there is no `reset` GPIO. So win / win.

This results in the following power resource:
        PowerResource (PR02, 0x00, 0x0000)
        {
            Method (_STA, 0, NotSerialized)  // _STA: Status
            {
                Return (0x01)
            }

            Method (_ON, 0, Serialized)  // _ON_: Power On
            {
                \_SB.CTXS (0x84)
                Sleep (0x01F4)
            }

            Method (_OFF, 0, Serialized)  // _OFF: Power Off
            {
                \_SB.STXS (0x84)
                Sleep (0x0A)
            }
        }

I switched the device tree entry from using reset_gpio to enable_gpio
because the acpi_device_add_power_res method asserts the reset in the
_ON method unconditionally. This results in a small glitch on the line.
By using the enable_gpio we get the correct behavior.

I don't have a datasheet right now, so I just picked some values for the
reset timing. The kernel driver was using 200ms. We can revisit the
numbers when we get a datasheet.

BUG=b:218295688
TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power
resource is created on the kernel. This should allow the kernel to
power cycle the device via usb_acpi_set_power_state.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-14 16:23:59 +00:00
Tracy Wu cae27ebf49 mb/google/brya: Adjust FMD file for some boards
When brya boards that use ChromeOS autoupdate update their firmware,
devices with SOC_INTEL_CSE_SUB_PART_UPDATE will end up attempting to
replace IOM and NPHY BPDT firmware in the CSE region. However, because
of the way the autoupdate works, the CSE RO will not be updated during
autoupdate. This means that these boards now have different stitching
schemes between CSE RO and RW and this causes the sub-partition update
to fail and the boot hangs. To remedy the situation for these boards,
a separate FMD files is provided so they can continue to use the
cse_serger tool for stitching. The only boards affected were kano and
brask, so they are updated here.

BUG=b:218376385
TEST=use flashrom to downgrade to 14474 then use futility to update to
image with this patch and system boots.

Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: Ia8bdf6b28d952f6d983b84e39da96e159027a822
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-14 16:13:58 +00:00
Arthur Heymans 8b875d028d drivers/smmstore/store.c: Add fmap_config.h dependency
This fixes building with -jx

Change-Id: I51efc03839c53b96fa248e6fe5dc0e00b773aa53
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-14 16:13:41 +00:00
Ethan Tsao 646b6a0f6f soc/intel/graphics: Repurpose graphics_get_memory_base()
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.

BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.

Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14 16:13:11 +00:00
Alan Huang aae362c4ed mb/google/brya/var/brask: Enable ASPM of RTL8125
Brask cannot pass powerd_dbus_suspend test because the NIC does not
enter ASPM L1.2. Here we add "enable_aspm_l1_2" in devicetree for
RTL8125 to enable ASPM L1.2.

BUG=b:204309459
BRANCH=None
TEST=emerge and test with command powerd_dbus_suspend

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-14 16:12:21 +00:00
Alan Huang ad90edc3e0 drivers/net/r8168: Add ASPM control mechanism
Add a new configuration parameter "enable_aspm_l1_2".

Write value 0xe059000f to register offset 0xb0 to allow kernel driver to
enable ASPM L1.2.

Use Kconfig "PCIEXP_ASPM" and "enable_aspm_l1_2" to decide whether to
enable ASPM L1.2.

BUG=b:204309459
TEST=emerge and test if the driver can read the correct value

Change-Id: I944dbf04d3ca19df4de224540bee538bff4d1f12
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-14 16:12:07 +00:00
Fred Reitberger 28894c5798 mb/amd/chausie: update GPIO for chausie
Add/update initial GPIO pin descriptions and initialization types for
chausie mainboard.

Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-13 21:22:52 +00:00
Felix Held 399d3cf878 soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUS
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC
talk to each other via the system bus, there is no longer the
requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that
start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2
as the IOAPIC ID while most of their CPUs have more than 2 logical cores
resulting in the IOAPIC having the same ID as one of the LAPICs.

All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and
GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT
and IVRS ACPI tables and there's no MPTable support for those SoCs that
might also rely on those IDs being consistent.

This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID
from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes
sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a
CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4
bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of
IOAPIC IDs, this is non-standard.

TEST=AMD Mandolin and Google Liara still work.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-13 19:23:26 +00:00
Arthur Heymans 0e688b113d arch/x86/id.S: Fix building with clang
The following error message is now gone:
     CC         bootblock/arch/x86/id.o
/tmp/id-35b17a.s:35:7: error: expected relocatable expression
.long - ver
      ^
/tmp/id-35b17a.s:36:7: error: expected relocatable expression
.long - vendor
      ^
/tmp/id-35b17a.s:37:7: error: expected relocatable expression
.long - part
      ^

Tested with BUILD_TIMELESS=1 on x86_32 with gcc. The binary stays the
same.

Change-Id: I930e7b96c4428bcb95ff1903e6a3e7679171ffee
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12 19:00:00 +00:00
Sean Rhodes fafcb749b4 soc/intel/apl: Use Kconfig to enable CseRbp
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is
memory mapped and ensures SkipCseRbp UPD is guarded against this config.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12 18:45:36 +00:00
Teddy Shih eaee04b4a1 mb/google/dedede/var/beadrix: Add LTE modem support
This change adds LTE modem for beadrix.

BUG=b:204882915
BRANCH=dedede
TEST=Build and boot beadrix, check with command modem status

Change-Id: I7acb88634478ff486810b2c3fc14d6739c3268e1
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61328
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12 18:45:09 +00:00
Raul E Rangel 507064b835 soc/amd/cezanne/psp_verstage/uart: Fix off by 1 error
FCH_UART_ID_MAX == 2, and there are 2 UARTS, so we don't need the -1.

BUG=b:215599230
TEST=Build guybrush

Found-by: Coverity CID 1469611
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5f0171ed2d3da7f86ba3cfd0457f60d2d5722625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61869
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12 18:44:43 +00:00
Felix Singer d8cf72f7e6 arch/x86/acpi: Replace LEqual(a,b) with ASL 2.0 syntax
Replace `LEqual(a, b)` with `a == b`.

Change-Id: Iabfaaee22011a75cc981607d366d61660838ab21
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12 17:26:46 +00:00
Tony Huang 4893003581 mb/google/brya/var/agah: Update Aux settings
Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.

Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.

BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage

Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12 17:26:15 +00:00
Krishna Prasad Bhat b2e9193231 mb/google/nissa: Set half_populated true
Alder Lake N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.

Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.

Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-12 17:25:57 +00:00
Elyes HAOUAS f91538c3ec sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config'
Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12 17:24:46 +00:00
Werner Zeh bc13c64a2d mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cache
The mainboards mc_apl{2,4,5,6} use VBOOT for verification and can be in
a recovery state for different reasons. In this case we still want the
MRC cache to be around to avoid the DRAM retraining on every boot.

This patch enables the Kconfig switch HAS_RECOVERY_MRC_CACHE which makes
the already available MRC recovery region in FMAP useable.

Test=Boot mc_apl2 in recovery mode and make sure the recovery MRC
cache is used.

Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-02-12 17:24:25 +00:00
Zheng Bao c5b912f788 soc/amd/cezanne: Allow to specify SPL table path in Kconfig
BUG=b:216096562

Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 17:07:09 +00:00
Felix Held 514965a9ce mb/amd/majolica/mainboard: add initial IRQ routing
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing
on Chausie that was a 1:1 copy caused some issues with the I2C driver,
so port the Chausie IRQ mapping change back to Majolica.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 16:58:38 +00:00
Felix Held aa3a42df44 mb/amd/chausie/mainboard: add initial IRQ routing
This IRQ routing info is taken from mb/google/guybrush. This should fix
these errors:

[    0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found
[    0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found
[    0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found
[    0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-12 16:58:24 +00:00
Kevin Chiu b3b17b2a3f mb/google/guybrush/var/nipperkin: Add _HID for privacy screen device
BUG=b:204401306
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     dump SSDT, see _HID instead of _ADR

Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 16:46:30 +00:00
Kevin Chiu e80e53cac6 soc/amd/common: Scan bridge devices behind SoCs GPU Controller
Scan devices behind SoCs GPU controller to expose more buses.

BUG=b:204401306
BRANCH=guybrush
TEST=emerge-guybrush coreboot

Change-Id: Ib78e6570f101c71efaf9cc1843defcb05301cd30
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 16:46:07 +00:00
Yu-Ping Wu 2fdcb64ec9 soc/mediatek: Fix printing SPM version
Currently the SPM version string is stored at the end of the blob,
possibly without a trailing '\0'. Therefore, we should be careful not to
print characters beyond the blob size.

BUG=b:211944565
TEST=emerge-corsola coreboot
TEST=SPM version looked good in AP console
BRANCH=asurada,cherry

Change-Id: Icfeb686539dc20cf5b78de77c27bdbb137b5d624
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-12 00:45:54 +00:00
Casper Chang 1169e5943c mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
Config USE_PM_ACPI_TIMER to y for primus4es only as
commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression)
breaks suspend stress test on ES CPU SKU.

BUG=b:211377699
TEST=USE="project_primus emerge-brya coreboot" and verified
     the suspend stress test works on primus4es.

Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-11 23:55:51 +00:00
Usha P af5a9d64a5 soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M
IDs in the current code. Hence rename those device IDs as ADL_M_N and
use them for Alder Lake-N platform.

Document Number: 619501, 645548

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11 23:55:20 +00:00
Fred Reitberger 6f0b5b3e6b soc/amd/common/acp: introduce acp_gen1
Refactor existing acp code into acp_gen1 variant as preparation for gen2
variant in sabrina.

Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11 23:30:34 +00:00
Julian Schroeder d2e278df33 soc/amd/common/fsp: check fsp image revision
Check if FSP binary and coreboot FSP structures (fspmupd.h) match
sufficiently.

A change in minor number denotes less critical changes or additions
to the FSP API that still allow for the boot process to proceed.
A change of the AMD image revision major number will halt boot.
The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD
Picasso, Cezanne and Sabrina APUs.

BUG=b:184650244
TEST=build, boot and check fsp image revision info. Example:

FSP major    = 1
FSP minor    = 0
FSP revision = 5
FSP build    = 0

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11 20:40:49 +00:00
Sergii Dmytruk 3a96074441 src/arch/ppc64/*: pass FDT address to payload
It's available in %r3 in bootblock and needs to be passed to payload in
%r27.  We use one of two hypervisor's special registers as a buffer,
which aren't used for anything by the code.

Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-02-11 20:18:05 +00:00
Sergii Dmytruk dba9b54731 arch/ppc64/boot.c: handle non-OPD entry point
Change-Id: I309be370d66a808b355241fcee880883631f38ce
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-11 20:17:45 +00:00
Yaroslav Kurlaev 956a8b69d2 src/mainboard/emulation/qemu-power9: require hb-mode=on
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which
is OpenPower firmware created by IBM.

QEMU for PPC64 can run initial program in two different modes:
 * hb-mode=off with load address 0x00000000
 * hb-mode=on with load address 0x08000000

Real hardware always loads firmware at 0x08000000 and coreboot shouldn't
require a special build to be run on QEMU.

Memory layout is updated to reflect change of load address.

Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11 20:17:18 +00:00
Yaroslav Kurlaev bcbcdf7394 src/mainboard/emulation/qemu-power9: add RAM detection
Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11 20:16:44 +00:00
Yaroslav Kurlaev e985d211fb ppc64/arch/mmio.h: ignore HRMOR and inhibit cache
Change-Id: I9895fc0dcc0ab72151f3b2bde409c8556525433d
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11 20:15:10 +00:00
Yaroslav Kurlaev c1de9e88e7 src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboard
Add initial implementation for booting on QEMU POWER9 emulation.

Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11 20:14:55 +00:00
Malik_Hsu d495456429 mb/google/brya/variants/primus: add dram part id
This change adds mem_parts_uesd.txt that contains the new memory parts
used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc
generated by gen_part_id using mem_parts_used.txt.

BUG=b:218415732

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11 20:09:19 +00:00
Robert Zieba b26d005bbe soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well.

BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-11 20:08:47 +00:00
Felix Held 6ba6bc24eb soc/amd/common/block/lpc/espi_util: add decode range register helpers
Introduce and use functions to translate eSPI IO/MMIO decode range IDs
into the corresponding register bits and the IO/MMIO range and size
register IDs into register offsets. This is a preparation to support the
additional eSPI decode ranges on Sabrina where not all enable bits and
base/size registers for one type of decode ranges are consecutive.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 14:18:54 +00:00
Felix Held cdbfa6e637 soc/amd/common/block/include/espi: rename IO/MMIO base/size registers
This aligns the register names more with the PPR.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 14:18:44 +00:00
Reka Norman b0947172c8 mb/google/brya/var/nivviks: Implement WWAN power sequencing
Nissa is using the FM101, which has the following power sequencing
requirements:

Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L
Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN

Add a power resource to the USB device, and use wwan_power.asl to
handle the power off sequence.

BUG=b:217092522
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11 14:11:53 +00:00
Reka Norman 19567d8ec2 mb/google/brya: Support power sequencing for USB-only WWAN
Nissa is using the FM101 which is USB only. To allow us to reuse the
existing wwan_power.asl for power sequencing, move the PCIe-specific
part behind a new Kconfig HAVE_PCIE_WWAN.

BUG=b:217092522
TEST=Build brya0 and check that generated dsdt.asl doesn't change.

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11 14:11:33 +00:00
Reka Norman 457d98d130 mb/google/brya/var/nivviks: Disable LTE-related GPIOs based on fw_config
If the LTE USB DB is not connected, disable the LTE-related GPIOs.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I86251d8ad58d82ff2112ac5f2dfafdabbff4c76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11 14:11:07 +00:00
Reka Norman 8d6ebe9d31 mb/google/brya/var/nivviks: Initialise overridetree
Add an initial overridetree for nivviks based on the pre-proto schematic
and build matrix.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-11 14:10:54 +00:00
Tim Wawrzynczak 7a91a10c61 src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
There may be occasions where an I2C device was initialized during
"early initialization," but when used again in ENV_PAYLOAD_LOADER
before resource allocation happens, it would currently return that it
has not been assigned a BAR. However, because of the early BAR
assigned to it, it should still be valid to use that until proper
resources have been assigned, therefore return any BAR that may have
been assigned to the device during early initialization.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-11 14:09:23 +00:00
Tim Wawrzynczak eb1891a9a8 drivers/i2c/tpm/cr50: Remove unused `chip` function arguments
The `chip` argument passed around to many functions in this driver is
actualy unused, so remove it where it is unused.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8d32fdf340c8ef49fefd11da433e3b6ee561f29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-11 14:08:15 +00:00
Elyes HAOUAS 8b5841e9ea lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'
Change-Id: Ie20a2c35afc2b849396ddb023b99aab33836b8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-11 14:07:37 +00:00
Yu-Ping Wu 08d2016e50 soc/mediatek/mt8186: Lower SPI NOR speed to 52MHiz
The current SPI NOR speed mainpll_d7_d2 (78MHz) is too fast for MT8186's
HW design, which is capable of up to 52MHz. Therefore, lower the speed
to univpll_d3_d8 (52MHz).

BUG=b:218775654
TEST=emerge-corsola coreboot
TEST=Boot time didn't increase significantly
BRAHCH=none

Change-Id: I5a03e41d4ce47d45b97a805b9b98877ef0dac7b7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11 14:07:18 +00:00
Krystian Hebel e527c713bd ppc64/bootblock_crt0.S: minimal implementation for bootblock C environment
BSS is loaded as part of the bootblock, it is zeroed in the file so it
doesn't have to be cleared explicitly by the code.

Code for clearing is left as a comment along with a warning about alignment
requirements.

Vector operations are sometimes generated for code such as
'uint8_t x[32] = {0}', this results in an exception when vector registers
(VR) are not enabled. VSR (vector-scalar register) operations are also
enabled, there is no reason not to.

Change-Id: I878ef61619eb4a191805c8911d001312a0d717a0
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11 13:54:26 +00:00
Kyösti Mälkki 707e5452e7 cpu/x86/lapic: Fix SMP=n case with LEGACY_SMP_INIT
Fix regression after commit 9ec7227c9b
  cpu/x86/lapic: Move LAPIC configuration to MP init

The call to disable_lapic() got removed and with asus/p2b
SeaBIOS payload was unable to load kernel.

The combination of entering SeaBIOS payload with an
enabled lapic but not having programmed LAPIC_LVT0
for DELIVERY_MODE_EXTINT apparently disconnects i8259
PIC interrupt delivery pin.

Change-Id: If51e5d65153a02ac7af191e7897c04bd4e298006
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-11 13:53:56 +00:00
Michał Żygowski ed04aab813 src/arch/ppc64/arch_timer.c: implement timer functions
Change-Id: I4a244df01f6d15cbefb3b01079f6eec943136983
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-11 13:53:54 +00:00
Igor Bagnucki 252fc29d1a src/cpu/power9: add file structure for power9, implement SCOM access
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11 13:53:29 +00:00
Rex-BC Chen 3c00c7ec6b soc/mediatek: Only update required bits when triggering WDT reset
To prevent to modify original value of wdt_mode, we use setbits32 to
update required bits.

BUG=b:218420108
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61729
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-11 12:19:54 +00:00
Arthur Heymans 9813544151 mb/google/octopus,reef: Align SMMSTORE region in default.fmd
The SMMSTORE region needs to be 64K aligned or error will be thrown.

Change-Id: I5d4f71f80c3219ac2c7000e1fa95fd04100d9cfe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-10 21:26:56 +00:00
Arthur Heymans 1ba6049ad9 drivers/smmstore/store.c: Add static assertion based on fmap
Instead of having runtime failures that are hard to debug because SMM
debugging is disabled by default assert some properties of fmap at
buildtime.

Change-Id: I5b5b511142d93d5799565a8936e9a087117044b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-10 21:26:09 +00:00
Matt DeVillier b8a23013c5 drivers/intel/gma: Guard add_vbt_to_cbfs macro
Guard macro via CONFIG_INTEL_GMA_ADD_VBT, rather than guarding
each of the calls to it (most of which are currently unguarded).

Test: build google/coral w/ and w/o CONFIG_INTEL_GMA_ADD_VBT selected,
verify VBTs added (or not) to CBFS based on Kconfig selection.

Change-Id: Ic25554cb2c61b81bdb4b0987094c3558e0bbcbd8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10 21:23:48 +00:00
Matt DeVillier cfc594cddd mb/google/reef: Add VBTs for all variants
Adjust Kconfig so all variants use proper VBTs.
Add Makefile entries for variants which use multiple VBTs.

extracted from ChromeOS firmwares:
Google_Coral.10068.113.0
Google_Pyro.9042.233.0
Google_Reef.9042.233.0
Google_Sand.9042.220.0
Google_Snappy.9042.253.0

Change-Id: I46ad4ec321e32d019e44f0741956b18a464fb8ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10 21:22:55 +00:00
Matt DeVillier c9f6baf425 mb/google/reef/coral/mainboard.c: Drop break after return inside switch
Drop unnecessary switch break after return, to alleviate linter warnings.

Change-Id: I7cc49caaeafb490cb62b75ec5c3ca4822573464b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-10 21:21:59 +00:00
Matt DeVillier 2481f1e7b5 mb/google/reef/coral: Sync mainboard.c with Chromium fork
Several commits were made to the Chromium coral branch
(firmware-coral-10068.B) which were not committed upstream first.
Pull them in here:

486ce56 mainboard/google/coral: Override VBT selection for babymako
c1d7720 Babymako: add touchpad i2c speed config
911d547 mainboard/google/coral: Override VBT selection for babytiger
730a5af Babytiger: add touchpad i2c speed config
724711e rabbid: add the touchpad i2c speed config
80c5d16 mainboard/google/coral: Override VBT selection for babymega
e8931a4 Babymega: add touchpad i2c speed config

These add support for additional coral sub-variants. The I2C speed config
changes were adapted to account for upstream changes not present in the
coral Chromium branch.

Change-Id: Idf2a53a351138aff310385f4026197d74ab6848b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-10 21:21:33 +00:00