The touchpad and touch-panel CLK frequency should be smaller
than 400 kHz which described in spec.
Overwrite i2c speed parameters by overridetree.cb
BUG=b:119540449
BRANCH=master
TEST=emerge-octopus coreboot chromeos-bootimage
flash bios and check the touchpad i2c frequency meets the spec.
Change-Id: I32c3e1bbfc2cdf39e9b7865a69996e54346d5f93
Signed-off-by: Carl Yang <carl_yang@asus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
MTRR addresses are publicly available at cpu/x86/mtrr.h, so use
macros instead of "magic" numbers.
Change-Id: I224136ed4a19199bae0223a1aae366b3dd4ef9cf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29580
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change deprecates boards with id < 2. It updates touchscreen enable
GPIO in overridetree and gets rid of variant.c to update enable GPIO at
runtime. Additionally, it configures old enable GPIO as NC.
BUG=b:119885949
Change-Id: I42fb7ef90e421118a8fdfa0d343d0bcf4a9bc087
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change gets rid of bid0_override_table as part of clean up effort
to deprecate bid0. Additionally, it updates the touchscreen enable
GPIO in overridetree and gets rid of variant.c to update enable gpio at
runtime.
BUG=b:119885949
Change-Id: If14abb324d9422720ca4d0f0859e092319d454ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change updates the configuration of GPIO_178 to be active low as
per latest revision on different octopus variants. This effectively:
1. Gets rid of early_gpio_table in different variants -- phaser, meep,
fleex, bobba.
2. Deprecates board id < 2 for bobba, board id < 1 for fleex and
phaser.
3. Adds special early_gpio_table in yorp which has GPIO_178 as an
active high signal.
BUG=b:119885949
Change-Id: I024199a8f1f96db57f8fa60c4d265789cd3a0493
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.
Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29810
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PL4 is a preemptive CPU package peak power limit,it will never be exceeded.
Power is preemptively lowered before limit is reached.
This change provides option in devicetree and feeds FSP PowerLimit4 UPD for
power limit purpose.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8
Reviewed-on: https://review.coreboot.org/c/29808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ife8f7f164b26bea65a0dcde0cab339a1bb599e38
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/29834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan T <stefan.tauner@gmx.at>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always.
This hob is only generated by FSP during non-S3 and MRC data is changed.
Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is
required.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
An additional read of PTN configuration data at the end of the
ptn3460_init function is not necessary.
Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some registers are not documented in "Mobile Intel 945 Express
Chipset Family" datasheet but they are in "Intel 945G/945GZ/
945GC/945P/945PL Express Chipset Family" datasheet.
Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This bug/typo was spoted by Felix Held.
As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need
to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control"
located at 0xec.
Used address at 0x114 to enable GPEs is likely a typo.
Patch not tested.
Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove whitespace between the function name and open
parenthesis, and fix 81+ characters lines.
Unnecessary comment about 'include sandybridge.h'removed.
Change-Id: I0db1263ec11240003fe1f7080c758994fc0224d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29428
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the board id detection to support rev5, since the 2T mode still
needed in DVT build.
BUG=b:116082728
TEST=verify by ODM.
Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/29779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
CBFS used to have a special region for the x86 bootblock, which also
contained a pointer to a CBFS master header, which describes the
layout of the CBFS.
Since we adopted other architectures, we got rid of the bootblock region
as a separate entity and add the x86 bootblock as a CBFS file now.
The master header still exists for compatibility with old cbfstool
versions, but it's neatly wrapped in either the bootblock file or in a
file carefully crafted at the right location (on all other architectures).
All the layout information we need is now available from FMAP, a core
part of a contemporary coreboot image, even on x86, so we can just use
the generic master header locator in src/lib/cbfs.c and get rid of the
special version.
Among the advantages: the x86 header locator reduced the size of the
CBFS by 64 bytes assuming that there's the bootblock region of at least
that size - this breaks assumptions elsewhere (eg. when walking CBFS in
cbfs_boot_locate() because the last file, the bootblock, will exceed the
CBFS region as seen by coreboot (since it's CBFS - 64bytes).
TEST=emulation/qemu-q35 still boots
Change-Id: I6fa78073ee4015d7769ed588dc67f9b019d42d07
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29788
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.
BUG=N/A
TEST=Intel BayTrail CRB
Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Huang Jin <huang.jin@intel.com>
It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.
Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.
TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
configs with and without this patch: binaries stay the same.
Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
According to newest TCG ACPI Specification for Family 1.2 and 2.0
Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA.
Update the table structure definition, create the log area for TPM2 in
coreboot tables and fill the missing fields in TPM2 table. TPM2 should be
now probed well in SeaBIOS rel-1.12.0 or master.
Tested on apu2 with Infineon SLB9665 TT2.0.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The mentioned bits 14:8 are wrong as the functions always write
bits 15:8. What happens is visible in the written code. There is no need
for an extra comment.
Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The power budget for this mainboard is very limited while the
performance demand is low. Set the CPU clock to the lowest value to
enable maximum efficiency and thus lowest power dissipation.
Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a Kconfig switch to be able to set the CPU clock to the lowest
possible ratio. If enabled the CPU will consume as little power as
possible while providing the lowest performance.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to its need.
Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Provide a library function to set the CPU frequency to minimum
value. This will result in the lowest possible CPU clock with
the lowest possible power consumption. This can be useful in mobile
devices where the power dissipation is limited.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to it's need.
Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
No need to hide prompts, it's a user choice anyway, they should know.
The help texts were just rephrasing the prompts or stating the obvious.
Change-Id: I5694a88f2da57af2a20357c4e22c7c648053cc26
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Gather x86 specific debug options and deflate their code a little. We
keep their hiding rules and help texts, although they don't seem much
useful.
Change-Id: I3bb8e759fc6a4871d30fccff47babfb7a291b45c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29751
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of ICL board variants
1. ICL-U
DDR4 - All possible DDR4 memory type
LPDDR4 - Memory down fixed DIMM configuration
2. ICL-Y
All LPDDR4 DIMM on platform
This patch ensures to have all proper SPD configuration.
Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
We need to default this to low so the speakers don't activate in S3.
BUG=b:118248953
TEST=Used a scope to look at the line and made sure depthcharge still
beeps.
Change-Id: I70d2f4a3261d212b62e784fa7414e45b1d575612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29783
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.
BUG=NA
TEST=NA
Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
CONFIG_FSP_USES_UPD is not used by FSP 1.1.
Remove this config from this file.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Returned status code FspTempRamInit() is not displayed when error occurs.
Move the printk() call before the check for status.
BUG=NA
TEST=Portwell PQ7-M107
Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29695
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ability to define a reset gpio in acpi for a USB device.
BUG=b:119275094
Change-Id: Ife3ea43a1eadf2548aa52b8fbd792e691d7cc7f2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
Make sure that the Pre-Op register is cleared when an atomic cycle has
been finished without errors.
Change-Id: Ied88337125b125474b411e2f39f668171d15bfac
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
We are seeing problems (interrupt storm) with using the same gpio for
FP MCU wake and irq signals. Reverting back to using separate gpios
for wake and irq until we resolve the issue.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop
into S0ix in the EC console. Also, unlock from lock screen with
fingerprint.
Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/29665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Vincent Wang <vwang@google.com>
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow
backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART,
because it's using its interface. The individual UART drivers
select DRIVERS_UART, because they implement the interface and
depend on the common UART code.
Some guards had to be fixed (using CONSOLE_SERIAL now instead of
DRIVERS_UART). Some other guards that were only about compilation
of units were removed. We want to build test as much as possible,
right?
Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update passive temperature threshold value from 50C to 52C and
critical temperature threshold from 90C to 80C for TSR1 sensor.
BUG=b:79779737
TEST=Build and verified on Bobba/Bobba360/Sparky/Sparky360 boards
Change-Id: Iffef8afe0f1c6c80a6ae8ecb831aaf749443980e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The timer interrupts don't appear when HPET is enabled. This
result in Linux reporting 'MP-BIOS bug: 8254 timer not connected
to IO-APIC'
Enabling CONFIG_DISABLE_HPET disables OS use of HPET.
Intel issue 4800413 (doc #5965535) reports Windows7/Ubuntu Installation
Hang or Slow Boot Issue.
BUG=Intel #4800413
TEST=Portwell PQ7-M107
Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change makes the early IO decode setup mirror that of other
Intel SOCs and fixes issues with COM1 not being enabled properly.
Tested by successfully successfully receiving serial output from
an 8250IO UART device at the standard 0x3f8 base address.
Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
It defaults to y to avoid having to select it per mainboard. But that
makes a mess because it results in linker conflicts unless other UART
drivers disable it explicitly.
We try to be smarter about the default value for now. The real solu-
tion would be to hardcode it per mainboard. But who knows which boards
actually have it?
Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds ACPI properties for WDT8752A device.
BUG=b:117174180
BRANCH=master
TEST=Verify touchscreen on delan works with this change
Change-Id: Id1484a482de6282c97f3aac329f217bbcb7dbd18
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Working:
- SATA on southbridge ports
- SATA on Marvell IDE controller ports
- USB
- COM1
- PS/2 keyboard
- DDR2 DIMMs
- PCIe x16 PEG port
- PCIe x1 ports
- PCI ports
- NIC (MAC address needs to be set in Kconfig or in a CBFS file)
- S3 resume
- Green audio line out connector (the rest is untested)
Not working:
- Floppy port. Does not seem to be mainboard-specific, though.
Untested:
- EHCI debug
TODO:
- Add documentation
Change-Id: I6ed434a691e8ef2a61e0acb1f986a59b8e1ad818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/25691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl5 mainboard will follow in separate commits.
Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There's a typo in the cpu driver causing it to always use the weak
implementation defined in the devicetree instead of the real
implementation.
Tested on qemu-q35, the CPU driver contains valid values.
Change-Id: I4a6bb447bfdb3df6053c0df8be9d7c6aa8f689be
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Even though these two mainboards use the same gpio.c file, other boards
such as the p5ql_pro do not.
Change-Id: I2f7c8c12cb1bdcf47f3b4d4cef0b11e44a5b8863
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The register values in dram width programming changed in
commit a4fc7bef7f which broke booting on getac/p470.
TEST=getac/p470 with 2 X8DDS DRAM boots again
Change-Id: I8b3eedc8c5234e8a28948d4dc58bf565024f62ce
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I9693f2a52529961e6b611b69e389f01f77f77d63
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/icelake/acpi/
Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is
active low. Keeps device awake otherwise.
BUG=b:119447525, b:115706071
BRANCH=Nami
TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into
S0ix in the EC console.
Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting sku_id() is not enough to get a value to show up in the SMBIOS
tables, it also needs to be returned as a string for the table creation
to consume. This change defines the smbios_mainboard_sku() function
and returns a string constant of "sku#" as expected.
Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Trent Begin <tbegin@google.com>
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.
BUG=none
TEST=none
Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with
kernel 4.9.
This board works quite well under coreboot. A list of what works and
what doesn't can be found in the documentation part of this commit.
The file `data.vbt` matches the VBT in the latest stable version of the
vendor firmware (version 2.20).
Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With this change, coreboot thinks we're running at 1MHz:
DW I2C bus 2 at 0xd1133000 (1000 KHz)
Elan eKT3644 IC Specification (trackpad) requires:
Low Time larger than 500ns (61 * 8.3ns = 506ns).
High Time larger than 260ns (32 * 8.3ns = 265ns),
Data Hold_time larger than 0ns.
Start Condition Hold time larger than 250ns.
Rise/Fall time of less than 120ns.
HCNT controls both High Time and Start Condition Hold time.
LCNT controls Low Time.
SDA_HOLD controls Data Hold Time.
P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned
using resistors on the board and must be considered when
adjusting any of the parameters since these times are all measured
at 30 or 70% of base and peak voltages (0v/1.8v).
The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20
which yields the SCL at around 950KHz - suboptimal but compliant.
Lower LCNT or HCNT results in "lost arbitration" errors or not complying
with eKT3644 requirements.
Verified by gaggery.tsai@intel.corp-partner.google.com.
Scope shots posted here:
https://b.corp.google.com/issues/78601949#comment177
BUG=b:78601949
BRANCH=none
TEST=Farzam provided test points on track pad for SCL/SDA/GND.
Waveforms measured with oscilloscope and screen shots attached
to bug (comment #177, #155, #100).
Operate trackpad/touchscreen
Review dmesg (kernel) output for correct speed, parameters, and
no errors (e.g. "lost arbitration" or "host controller timeout")
Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Signed-off-by: Grant Grundler <grundler@chromium.org>
Tested-by: gaggery.tsai@intel.corp-partner.google.com
Tested-by: grundler@chromium.org
Reviewed-on: https://review.coreboot.org/29553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Enable HDA controller coreboot driver for Whiskey Lake RVP platform on
top of common code.
BUG=N/A
TEST=Build and boot up on whiskey lake rvp board, comfirm audio playback
is working.
Change-Id: I7daf1c741b92ff59b9cb4030d218e9c1054c4b79
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
This macro is no longer used since commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite").
Change-Id: Iabf927d8462673cb96851c01318d826d4c422e0d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Only input from the BJ port is wired to VSYS on Kalista. VBUS from
USB-C is for output only. In other words, Kalista is a source only
device from a USB/PD perspective.
This patch disables EC-EFS, which would be needed for the EC to jump
to RW to get PD power before the AP boots. Kalista will be always
supplied enough power to boot the AP through the BJ port.
CQ-DEPEND=CL:1330171
BUG=b:118386511
BRANCH=none
TEST=Boot Fizz. Verify normal boot, soft sync, recovery mode work.
Change-Id: Icd18662ae1e76f35eb9bcd521b1951aacc713252
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/29564
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor PMIC wrapper code which will be reused among similar SoCs.
Move reusable code into the common folder.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot
Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Braswell allready supported vmx, but offered no mechanism to unset it, nor
to set the lock bit required for Windows to recognize virtualization.
Enable this functionality by adding CPU_INTEL_COMMON config.
Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/29570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0
for only 2nd SKU.
BUG=none
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/29631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPP_E1 gpio was incorrectly being defined as a no-connect.
Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic.
BUG=b:119508897
TEST=Build and flash nocturne, boot nocturne and
1) Verify nocturne can successfully suspend/resume from S3 and S0ix.
2) Verify wake from wlan wakes device from S3 and S0ix.
To do so,
a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT
b) connect DUT to mobile hotspot
c) sleep device via "powerd_dbus_suspend"
d) turn off hotspot, verify DUT wakes from S0ix
e) enable hotspot again
f) connect DUT to hotspot
g) sleep DUT via "sudo echo mem > /sys/power/state"
h) turn off hotspot, verify DUT wakes from S3
Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The common SPI controller driver in src/southbridge/intel/common does
match the SPI controller included in the PCH of Broadwell-DE SoC. Switch
to the usage of this driver and delete the dedicated one for the FSP
based Broadwell-DE implementation.
TEST: Boot mc_bdx1 with SPI driver active in romstage
Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There are several files under soc/amd that use units defined by file
porting.h. These units use upper case, and are not recognized by checkpatch,
thus causing problems when defining a pointer (request to use space before
and after the star symbol). These are the definitions from porting.h showing
the units that this patch will change and their coreboot definitions (not all
are actually used):
typedef uintptr_t UINTN;
typedef int64_t INT64;
typedef uint64_t UINT64;
typedef int32_t INT32;
typedef uint32_t UINT32;
typedef int16_t INT16;
typedef uint16_t UINT16;
typedef int8_t INT8;
typedef uint8_t UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
typedef unsigned char BOOLEAN;
typedef void VOID;
BUG=b:118775313
TEST=Build and boot grunt.
Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Function write_pci_cfg_irqs() has "no function" variables. One variable is
set and never used, the other is only used to control a print. Remove them.
BUG=b:117950052
TEST=Build grunt.
Change-Id: Icd98db3e794e609b112f15979a3a00a2977a0fdb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Value stored to 'cmd' is never read
Change-Id: I794b6e12f5af272705cd996f7ca5099e9b9dbfc7
Found-by: scan-build from clang 6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/29568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, there is nothing for this mainboard to do in ramstage.
Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard is equipped with LPDDR4 modules. The corresponding memory
swizzle data must be set for this purpose.
Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
OEM name can be stored in CBI. This change can support for fetching
the OEM name from CBI.
BUG=b:118798180
TEST=Verified to get data from CBI
Change-Id: I4938c4d60fcad9e1f43ef69cc4441d1653de7e24
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Currently mode-aware DPTF depends on Tablet Mode Switch to load the
right table. This does not scale well with device types and configuration.
This change helps to decouple the mode-aware DPTF from Tablet Mode Switch.
This change allows ACPI to load the appropriate DPTF table based on the
profile number as detected by EC.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ibffe9c58f970aec37aa74a040170c4cf559bab33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29249
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support Multi-DPTF profile, Device DPTF Profile Number is
introduced into EC_ACPI_MEM_DEVICE_ORIENTATION ACPI Space at offset
0x09. This bit field stays along with Tablet Mode Device flag.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ie14916ac16c50cbe0990021e2eb03d5121cd0e07
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES
since it aligns with the use-case.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes (base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29629
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/
Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Current implementation works by luck as DCACHE area is actually RAM and
stack can grow and use that RAM outside of the area.
* Set DCACHE_BSP_STACK_SIZE to 0x4000.
* Add an assert to make sure it is set to a sane value on all platforms.
Change-Id: I71f9d74d89e4129cdc4a850acc4fc1ac90e5f628
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29611
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a helper function specific to ramstage to add the boot count
information into event log at ramstage.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group event log state information together to manage them better during
different stages of coreboot.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the SmbusEnable parameter from all Cannon Lake mainboards.
Instead this will be determined by the enable state of the SMBUS
PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some embedded controllers expect to be sent a command when the OS
calls the ACPI \_PTS and \_WAK methods. For example see the code
in ec/google/wilco/acpi/platform.asl that tells the EC when the
methods have been executed by the OS.
Not all ECs may define these methods so this change requires also
setting a Kconfig option to enable it.
Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change updates the configuration of EC_SYNC IRQ to be level
triggered to match the EC behavior.
Change-Id: I8e3cb2ae8016ea183d9067697aa5d4b9caa2d07e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.
Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary
Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35
Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working
Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On some boards the devicetree and Function Disable register did not
match. In this case the FD values are put in the devicetree as these
were the values that were actually used in practice.
A complete devicetree will make it easier to automatically disable
devices in ramstage.
Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
