The bug is in src/arch/i386/boot/boot.c. The inline assembly in
jmp_to_elf_entry uses the "g" flag to pass in parameters. However,
"g" allows gcc to use stack relative addressing of parameters.
Easiest fix would be to change "g" to "ri" - put the parameter either
in a register or as an immediate value.
That's what this patch does.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.
By moving the table to the high tables area (if it's activated), this problem
is fixed.
In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.
This patch also adds "table forward" support to flashrom and nvramtool.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code expecting too old binutils(?).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.
It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
doesn't make no sense. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The attached patch fixes this. I did not spotted that because the return arg is
moved just outside of method and I have overseen the closing }
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
sense, too). Have one u64 instead of three.
In order to use the old bios emulator, you have to do nothing. (Default, if
CONFIG_PCI_ROM_RUN is enabled)
In order to use yabel in your target, you need to add the following lines to
your config:
uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1
In order to use vm86 in your target, you need to add the following lines to
your config:
uses CONFIG_PCI_OPTION_ROM_RUN_VM86
default CONFIG_PCI_OPTION_ROM_RUN_VM86=1
Note: vm86 only works on platforms with _RAMBASE in the lower megabyte.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(in addition to their low locations)
This adds the kontron 986LCD-M and the i945 as a sample.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add TOM2 to the K8 DSDT.
Thanks to Rudolf Marek for testing and fixing this patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generate run-time ACPI ASL code.
Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
generated by new function k8acpi_write_vars (technically similar to
update_ssdt). But lot of nicer.
x
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
during bootup (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fix a warning that should not be one.
* fix capitalization typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Jordan Crouse <jordan@cosmicpneguin.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also use different console messages for copying and uncompressing, like
it's already done in similar code in other places.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All the PCIe slots are enabled in this patch except power management.
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The change in tables.c protects the legacy x86 BIOS data segment
(0x400-0x4ff) from being used for storing coreboot tables. Some
bytes from the segment are used by the kernel and should not be
garbled.
The change in coreboot_table.c is not strictly necessary. It removes
some redundancy and confusion.
Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs.
Signed-off-by: Marc Jones(marc.jones@amd.com)
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code it should have contained.
This patch updates the PCI IDs for Intel 3100 devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Don't enable pin0 for ioapic of io-4.
1. apic error in kernel for MB with mcp55+io55
2. some pcie-cards could have pci bridge there, so need to put entries
for device under them in mptable.
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
about a serial port. If a port is defined in the board configuration,
add it to lbtable.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
MMCONFIG for memory mapped PCIe config.
However this patch is not enough to enable it on Linux, Linux do not trust
BIOSes too much, so a small patch to kernel to disable the check if this
region is e820 reserved.
PCI: BIOS Bug: MCFG area at e0000000 is not E820-reserved
PCI: Not using MMCONFIG.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2936 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(or at least most) mainboards. This should put and end to
copy-paste'ing the same file again and again for every mainboard.
Fix the build for the MSI MS-6178 target (wrong location of the common
failover.c file).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
changes are correct. If someone could look into this, thank you.
Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
likely break the build, since it is only a small part, but it needs to
go in at some point and doing it directory by directory makes things
easier.
Signed-off-by: Yinghai Lu <yinghai.lu at amd.com>
Signed-off-by: Ed Swierk <eswierk at arastra.com>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward at gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop empty file (0 bytes) northbridge/amd/amdk8/cpu_rev.c
and references to it.
* move config option decision to preprocessor instead of code
since config options can not change during runtime
* slightly more verbose output in built_opt_tbl.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
overview of the code, facilitate future cleanups and reduce the
diff to Yinghai's tree at the same time.
No functional changes, only moving lines between files.
Copyright headers will be added later. Right now we benefit from
keeping the diff as small as possible.
Most of the work was done by Yinghai Lu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Linuxbios boots an Opteron motherboard with 1GB memory.
Linuxbios directly loads a recent linux kernel.
The memory layout is like this:
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
BIOS-e820: 00000000000f0000 - 00000000000f0400 (reserved)
BIOS-e820: 00000000000f0400 - 0000000040000000 (usable)
The f0000-f0400 region contains IRQ and ACPI tables.
At some point the kernel builds a resource table containing
all physical address ranges and type of hardware the addresses
are mapped to. The table is accessible via /proc/iomem:
# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
e0000000-efffffff : PCI Bus #03
e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
f4000000-f4ffffff : 0000:03:00.0
f5000000-f5ffffff : 0000:03:00.0
f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0
As you can see, the 00000000000f0400-0000000040000000
region is not listed.
It is not listed because the kernel unconditionally adds
"000f0000-000fffff : System ROM" first (look for
"request_resource(&iomem_resource, &system_rom_resource)"),
and then the attempt to add f0400-40000000 range fails
because of overlapping.
The kernel does not care that the range is not listed there.
Kexec does. It uses the /proc/iomem file to instruct the
kexec system call how to place the segments of a new kernel
in the physical memory. Kexec fails to start a new kernel
because it cannot locate enough physical memory.
This must be fixed either in linux or linuxbios.
Assuming that linuxbios is to be fixed, I cooked a patch
which provides this memory layout:
BIOS-provided physical RAM map:
BIOS-e820: 0000000000000000 - 0000000000000e18 (reserved)
BIOS-e820: 0000000000000e18 - 00000000000a0000 (usable)
BIOS-e820: 00000000000c0000 - 00000000000f0000 (usable)
BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000040000000 (usable)
The /proc/iomem contains:
# cat /proc/iomem
00000000-00000e17 : reserved
00000e18-0009ffff : System RAM
000a0000-000bffff : Video RAM area
000c0000-000cbfff : Video ROM
000f0000-000fffff : System ROM
00100000-3fffffff : System RAM
00100000-00203c61 : Kernel code
00203c62-00248c3f : Kernel data
e0000000-efffffff : PCI Bus #03
e0000000-efffffff : 0000:03:00.0
f0000000-f3ffffff : GART
f4000000-f60fffff : PCI Bus #03
f4000000-f4ffffff : 0000:03:00.0
f5000000-f5ffffff : 0000:03:00.0
f6000000-f601ffff : 0000:03:00.0
f6100000-f6100fff : 0000:00:01.0
f6101000-f6101fff : 0000:00:02.0
f6101000-f6101fff : ohci_hcd
f6102000-f6102fff : 0000:00:04.0
f6103000-f6103fff : 0000:00:07.0
f6103000-f6103fff : sata_nv
f6104000-f6104fff : 0000:00:08.0
f6104000-f6104fff : sata_nv
f6105000-f6105fff : 0000:00:0a.0
f6106000-f61060ff : 0000:00:02.1
f6200000-f620ffff : 0000:40:01.0
Kexec is happier with the patch.
Regards,
Signed-off-by: Roman Kononov <kononov195-lbl@yahoo.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Carl-Daniel Hailfinger
Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
https://openbios.org/roundup/linuxbios/issue55
This patch is a little bit enhanced, it keeps the ppc table consistent,
which Yinghai's original patch did not.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Default is 255.
This allows mainboard configs for working across various groups
of boards that differ a device that may not loaded.
If you search for a device that is not loaded and max buses is 255
then there can be up to a 8 second delay to search the entire PCI space.
Board configs that know thier max bus can limit this search space.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Special version for HDAMA rev G with 33Mhz test and reboot out.
- Support for CPU rev E, dual core, memory hoisting,
- corrected an SST flashing problem. Kernel bug work around (NUMA)
- added a Kernel bug work around for assigning CPU's to memory.
r2@gog: svnadmin | 2005-08-03 08:47:54 -0600
Create local LNXI branch
r1110@gog: jschildt | 2005-08-09 10:35:51 -0600
- Merge from Tom Zimmerman's additions to the hdama code for dual core
and 33Mhz fix.
r1111@gog: jschildt | 2005-08-09 11:07:11 -0600
Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL
r1112@gog: jschildt | 2005-08-09 15:09:32 -0600
- temporarily removing hdama tag to update to public repository. Will
reset tag after update.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
write_pirq_routing_table for x86
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
x96emu update from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
Correction to the reduce emulator from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Li-Ta Lo <ollie@lanl.gov>
trival test commit
This is my first tla commit
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
ide_enable in MB Config and jmp_auto ( it will make start in the 64k boundary)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Eric Biederman <ebiederman@lnxi.com>
Add read[bwl] write[bwl] to arch/io.h for i386
A pending patch requires needs this and ppc already has them
so it is a good idea to implement them :)
I don't know why this was not implemented earlier.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
will generate the struct lb_memory_range the same.
- Add a few pci_ids.
- Small readabiltiy clean ups to debug_dev
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
crt0.S.lb: Modified so that it is safe to include console.inc
console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions
div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc
socket_754/Config.lb Conditionally set config chip.h
socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
slot_2/slot2.c: The same spelling fix
socket_mPGA603/chip.h: again
socket_mPGA603/socket_mPGA603_400Mhz.c: and again
socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
socket_mPGA604_800Mhz/chip.h: Another spelling fix
socket_mPGA604_800Mhz.c and again
via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
earlymtrr.c: Remove work around for older versions of romcc
pci_ids.h: More ids.
malloc.c: We don't need string.h any longer
uart8250.c: Be consistent when delcaring functions static inline
arima/hdama/mptable.c: Cleanup to be a little more consistent
amdk8/coherent_ht.c:
- Talk about nodes not cpus (In preparation for dual cores)
- Remove clear_temp_row (as it is no longer needed)
- Demoted the failure messages to spew.
- Modified to gracefully handle failure (It should work now if cpus are removed)
- Handle the non-SMP case in verify_mp_capabilities
- Add clear_dead_routes which replaces clear_temp_row and does more
- Reorganize setup_coherent_ht_domain to cleanly handle failure.
- incoherent_ht.c: Clean up the indenation a little.
i8259.c: remove blank lines at the start of the file.
keyboard.c: Make pc_keyboard_init static
ramtest.c: Add a print out limiter, and cleanup the printout a little.
amd8111/Config.lb: Mention amd8111_smbus.c
amd8111_usb.c: Call the structure usb_ops not smbus_ops.
NSC/pc97307/chip.h: Fix spelling issue
pc97307/superio.c: Use &ops no &pnp_ops.
w83627hf/suerio.c: ditto
w83627thf/suerio.c: ditto
buildrom.c: Use braces around the body of a for loop. It's more maintainable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The static device tree is not built properly at all yet, but at least we get through it.
FIXME (What is the proper way to handle add in boards?)
- Add generic div64 support and ppc div64 support
- Fix abuild so it properly generates the CC line when cross compiling.
- Add one more possible ppc cross compiler target
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Set the bootstrap processor flag in the mptable.
- Implement 64bit support in our print statements
- Fix the reporting of how many cpus we are waiting to stop.
It is the 1 less than the actual number of cpus running.
- Actually enable cpu_initialization.
- Fix firstsiblingdevice in config.g
- Add IORESOURCE_FIXED to all of the resources set by config.g
- Fix the apic_cluster rule to add an apic_cluster path not an apic path.
- Add a div64.h to assist in the 64bit printf.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Rename sdram_init to memory_init
NOTE: need to test sandpoint and ep boards!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Updated the romcc version in Config.lb
- Fixed type sizes in romcc_io.h and io.h inl() returning a byte was nasty
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Reworked pnp superio device support. Now complete superio support is less than 100 lines.
- Added support for hard coding resource assignments in Config.lb
- Minor bug fixes to romcc
- Initial support for catching the x86 processor BIST error codes. I've only seen
this trigger once in production during a very suspcious reset but...
- added raminit_test to test the code paths in raminit.c for the Opteron
- Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED
so we can tell what we have really done.
- Added generic AGP/IOMMU setting code to x86
- Added an implementation of memmove and removed reserved identifiers from memcpy
- Added minimal support for booting on pre b3 stepping K8 cores
- Moved the checksum on amd8111 boards because our default location was on top of
extended RTC registers
- On the Hdama added support for enabling i2c hub so we can get at the temperature
sensors. Not that i2c bus was implemented well enough to make that useful.
- Redid the Opteron port so we should only need one reset and most of memory initialization
is done in cpu_fixup. This is much, much faster.
- Attempted to make the VGA IO region assigment work. The code seems to work now...
- Redid the error handling in amdk8/raminit.c to distinguish between a bad value
and a smbus error, and moved memory clearing out to cpufixup.
- Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to
setup a legacy keyboard properly.
- Reworked the register values for standard hardware, moving the defintions from
chip.h into the headers of the initialization routines. This is much saner
and is actually implemented.
- Made the hdama port an under clockers BIOS. I debuged so many interesting problems.
- On amd8111_lpc added setup of architectural/legacy hardware
- Enabled PCI error reporting as much as possible.
- Enhanded build_opt_tbl to generate a header of the cmos option locations so
that romcc compiled code can query the cmos options.
- In romcc gracefully handle function names that degenerate into function pointers
- Bumped the version to 1.1.6 as we are getting closer to 2.0
TODO finish optimizing the HT links of non dual boards
TODO make all Opteron board work again
TODO convert all superio devices to use the new helpers
TODO convert the via/epia to freebios2 conventions
TODO cpu fixup/setup by cpu type
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* move acpi to right position
* change acpi checksums
* clean hpet area before creating table
* calculate hpet checksum
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* subtractive resources
* merging with the static device tree
* more device types than just pci
- The piece to watch out for is the new enable_resources method that was needed in all of the drivers
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
- Updates to config.g so that it works more reliably and has initial support
for paths
- Renamed some configuration variables
SMP -> CONFIG_SMP
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
- Removed some dead configuration variables
MAX_CPUS -> CONFIG_MAX_CPUS
MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS
SMP -> CONFIG_SMP
FINAL_MAINBOARD_FIXUP
SIO_BASE
SIO_SYSTEM_CLK_INPUT
NO_KEYBOARD
USE_NORMAL_IMAGE
SERIAL_CONSOLE
USE_ELF_BOOT
ENABLE_FIXED_AND_VARIABLE_MTRRS
START_CPU_SEG
DISABLE_WATCHDOG
ENABLE_IOMMU
AMD8111_DEV
- Removed some assembly files that are no longer needed
killed src/southbridge/amd/amd8111/smbus.inc
killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc
killed src/ram/ramtest.inc
killed src/sdram/generic_dump_spd.inc
killed src/sdram/generic_dump_spd.inc
- Updated the arima/hdama to build with the new configuration system
- Updated config.g to list all of the variables with make echo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- SMP cleanups (remove SMP only use CONFIG_SMP)
- Minor tweaks to romcc to keep it from taking forever compiling
- failover fixes
- Get a good implementation of k8_cpufixup and sizeram for the opteron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Changes to allow more code to be compiled both ways
- Working SMP support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- romcc_io.h Add include guards.
- hdama/Config nothing really but I have been moving the setting back and forth between 1 and 2 cpus
- auto.c Changed the enabled debugging comments. This almost works with 2 cpus
- coherent_ht.c First pass at getting this right. It can now find 2 cpus and place them
in some semblance of a working state.
- raminit.c Fix problems with 4GB of ram. Disable some of the debugging code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Minor romcc fixes
- In smbus_wail_until_done a romcc glitch with || in romcc where it likes
to run out of registers. Use | to be explicit that I don't need the short
circuiting behavior.
- Remove unused #defines from coherent_ht.c
- Update the test in auto.c to 512M
- Add definition of log2 to romcc_io.h
- Implement SPD memory sizing in raminit.c
- Reduce the number of memory devices back 2 to for the SOLO board.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The goal is to have the same interface with or without romcc.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Implementation of fallback/normal support for the amd solo board
- Minor bugfix in romcc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I need a very early Hypertransport setup to get anything more going.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Myles Watson