DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.
Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")
Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide.
Clamp any values that would overflow this field. Bits in TC_DTP already
get set when the tXP and/or tXPDLL values are large.
Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are platforms that support error correction types other than
single-bit ECC. Extend meminfo to accomodate additional ECC types.
It is assumed that `struct memory_info` is packed to save space. Thus,
use `uint8_t` instead of an enum type (which are usually 4 bytes wide).
Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead, convert the struct to a union and pass in a pointer to it.
Tested on out-of-tree HP ProBook 6550b, still boots.
Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows booting without ME firmware, even though the 30-minute
auto-shutdown still happens. Without this patch, an HP ProBook 6550b
cannot get past the `setup_heci_uma` function call.
Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.
Tested on out-of-tree HP 630, still boots.
Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPR size is in MiB, but the range boundaries are expressed in KiB. In
addition, DPR and TSEG use the same attributes, so unify both regions.
Also improve a comment about DPR, since `is special` is uninformative.
Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.
Tested on out-of-tree HP 630, still boots.
Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Given that the PCI devices/registers being accessed are about QuickPath,
this code must be part of QuickPath init. Move it with the other code.
Tested on out-of-tree HP 630, still boots.
Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Transform the existing functions so that their functionality does not
overlap. Also, deduplicate printing these values in debug builds.
Tested on out-of-tree HP 630, still boots.
Change-Id: I3f50dcf56284c9648b116bc5aacc0adf2d863b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49583
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The platform performs a CPU-only reset after initializing QPI (QuickPath
Interconnect) and before actually performing raminit. The state is saved
in the sticky scratchpad register at MCHBAR + 0x2ca8.
Relocate some QuickPath init to a separate file. All moved functions are
only used within QPI init code, and had to be relocated in one commit.
Tested on out-of-tree HP 630, still boots.
Change-Id: I48e3517285d8fd4b448add131cd8bfb80641e7ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `get_bits_420` helper to avoid doing the same thing in
three different ways, and also correct a related register write.
Tested on out-of-tree HP 630, still boots.
Change-Id: Iec87f080714f0f07f5d43200ec01d6d3f31e8120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49579
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Dummy reads followed by writes are actually read-modify-write operations
in disassembled binaries. Handling of the scratchpad register 0x2ca8 is
still nonsense, but that should be taken care of in a separate commit.
Tested on out-of-tree HP 630, still boots.
Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only need to toggle one bit at a time. Introduce `rmw_500` to
simplify the code. The rank population doesn't seem to matter.
Tested on out-of-tree HP 630, still boots.
Change-Id: Ic1a680dae90889c84c9b2c536745e254475ff878
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49577
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes it clear what this function pointer is used for.
Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I6888b08ac11ba2431601fa179d063cee0bb93370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Let's not have CBMEM hooks in between the different
INITRAM timestamps.
Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.
Tested on out-of-tree HP 630, still boots.
Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not used, and GPIO registers are on the southbridge.
Change-Id: I0b7b6edc22d461007f24618eca42091439a53d3c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45423
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 100 MHz reference clock seems to be unstable when using high
multipliers. Use the 133 MHz reference clock instead.
Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The thing that this function initializes is the MPLL (Memory PLL). So,
call it by its name. Also add a missing newline in a printk, and update
a comment on the callsite of this function.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I86ab643bc87253554346dfed3630eb9ddbd44eb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This write was copied from Sandy Bridge. Neither Haswell reference code
nor Broadwell perform this write. Therefore, it seems safe to remove it.
Change-Id: I8869ff3e66362d9910235c554c3a07e91f479a82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This bit is primarily used to issue RDA commands. There doesn't seem to
be any limitation regarding the number of address bits.
Change-Id: I2804f67319c9bc736f9086af408853056aabedd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
QCLK means "quadrature clock", and is equivalent to one half of a full
clock cycle (tCK). Fix the comment. The `QCLK_PI` value is still valid.
Change-Id: I7089fc32381addc280a71761a377075f107b5c62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49363
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was copy-pasted from bd82x6x and no mainboard actually needs it.
The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.
Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Comparing against MRC, looks like the values for TA3 and TA4 are
backwards. All of them. Thus, correct the tables accordingly.
Tested on Acer G43T-AM3, DDR3-1066 and CL = 8 now works.
Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4
Tested-by: Michael Büchler <michael.buechler@posteo.net>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49388
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Büchler <michael.buechler@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix a typo and do some style improvements.
Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using MCHBAR32_AND_OR() in these two cases changes the order of
additions slightly. Originally, the MCHBAR offset and the base
register offset (0x5a4/0x5b4) were added first. Due to the added
parentheses in the register macros, now the complete register
offset is calculated first and then added to MCHBAR. Associativity
tells us that this doesn't change the result.
Changes in the resulting binary were verified manually on the
object file.
Change-Id: Id10882225c8e82b02583aa73e73d661c25abdef9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up cosmetics after refactoring the code. Reflow long lines and
align values in the tables, and also remove a now-unnecessary scope.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I2712c1ad5404d6968d18d762e6048c5da120ff78
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The first RCOMP group (data) is programmed differently, and has its own
tables. Remove the unused first index from the other tables, and adjust
the loop bound accordingly. Cosmetics are cleaned up in a follow-up.
Tested on Asus P5QL PRO (DDR2), still boots.
Change-Id: I3010acbd00f762c91aebeaf1625ed7543b14bf74
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The RCOMP data group is special and is programmed differently. Prepare
to simplify the code by programming it outside of the loop. Subsequent
commits will simplify the logic even further, then clean up cosmetics.
The special DDR3 case in the loop overwrites the command group strength
multiplier value. It doesn't need to be programmed for each RCOMP group.
Add a comment to justify not programming this register while programming
the settings for the RCOMP data group.
Tested on Asus P5QL PRO (DDR2), still boots.
Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These settings can be programmed with a single register write. Factor
the writes out into a single function to avoid some redundancy.
Tested on Asus P5QL PRO, still boots.
Change-Id: I3a08c255dd2b0deae650c7fe2ba4e1f4d1cef581
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
MRC uses an incorrect mask when programming this register, but the reset
default value is zero and it is only programmed once. As it makes no
difference, we can safely use the correct mask. Document this difference
in a comment to indicate the deviation from MRC behavior is intentional.
The default value for this register was dumped from Asus P5QL PRO.
Change-Id: I93b0c382f76e141b319414258e40a8bfe6c7848a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Consistently use commas after the last element of arrays, and also align
columns of values and comments. Remove `MHz` units from DDR speed values
to avoid confusion, as the memory's actual clock speed is half of these.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: Id13022483c6221ce87d21dd21a5cfe4317a55ccd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Time has proven this statement to be unnecessary. Uncommenting it would
not have any effect on the existing code, thus remove it completely.
Change-Id: Iff4cdd71435e4fd69d4f3284e9fb2830fdd5b173
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop casts to prevent pointer arithmetic and for consistency with other
platforms. These macros will be factored out in a subsequent commit.
Change-Id: I959e7378a8bf46fd1772192090a751d7a2f6f470
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49747
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guarding the MCHBAR macro breaks reproducibility, but should not have
any functional impact.
Change-Id: I8be8d7b8a0f289d2be76d3dec43999f6b42e3265
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49746
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was commented that the need for the delay was mainly related
to external displays and only with VBIOS execution. Move the
delay such that it is done only when we actually need to execute
the VBIOS aka option rom.
A delay is currently only defined for librem/purism_bdw in
its Kconfig. As the description of the issue sounds like it
would equally happen on other platforms when VBIOS is involved,
promote the Kconfig visible option to global scope.
Change-Id: I4503158576f35057373f003586bbf76af4d59b3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts:
- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e
It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.
Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Moreover, the ASL reservation for MMCONFIG was only for 64 busses.
Change-Id: I7366a5096aacd92401535be020358447650b4247
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.
With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.
Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.
Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Angel Pons