Keep track of the active timestamp table location using
a CAR_GLOBAL variable. Done this way, the entire table
can be located outside _car_relocatable_data and we only
switch the pointer to CBMEM and copy the data before
CAR gets torn down.
Fix comments about requirements of timestamp_init() usage.
Remove timestamp_cache from postcar and ramstage, as CBMEM
is available early on.
Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35032
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8183_DRAM_EMCP is enabled for devices using eMCP to run at a high DRAM
frequency (e.g., 3600Mbps).
BUG=b:80501386
BRANCH=none
TEST=Memory test passes on EMCP platform
Change-Id: Icf875427347418f796cbf193070bf047844d2267
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34433
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbs)
while those with discrete DRAM can only run at 3200Mbps. A new option
MT8183_DRAM_EMCP is added to Kconfig for a mainboard to select,
depending on whether it supports eMCP or not.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9b73c8b512db5104896ea0d330d56e63eb50a44b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id6070fb586896653a1e44951a6af8f42f93b5a7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I39f52764dc377c25953ef5dba16982a0b4637cdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I77275adb7c15b242e319805b8a60b7755fa25db5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I2f350cc3008b17516b5a42cdf07e28d2da5995e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4c9351652d81040cc4e7b85bdd1ba85709a74192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
pull in the FPU VDDIO turn on to fix the power leakage problem
on FPU VDDIO and FPU CS during power on sequence.
BUG=b:138638571
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tune I2C bus 1, 2 and 3 clock and make them meet spec.
BUG=b:140665478
TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock
frequency less than 400KHz
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. SKU1 for eMMC
2. SKU2 for SSD
BUG=b:140008849, b:140573677
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso's TimeStamp Counter is a new design and different than
Stoney Ridge. Although advertised as invariant, the ST TSC did
not become so until midway through POST making it an unreliable
source for measuring time. This is not the case for Picasso.
Remove the Stoney Ridge monotonic timer code and rely on the TSC.
Modify the calculation used in Family 15h of finding the number
of boost states first, and get the frequency directly out of the
Pstate0 register.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I909743483309279eb8c3bf68852d6082381f0dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
It is already trivial to set D14F3x44 to 0, but add a function to wipe
both that and the settings in D14F3x48, along with x48's associated
addresses.
Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Include the file containing the typedefs for uint_*.
Change-Id: If33765b6dc4236c4b38860bfc4f2cef9b226b81d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
These platforms return to romstage from FSP only after
already having torn CAR down. A copy of the entire CAR
region is available and discoverable via HOB.
Previously, CBMEM console detected on-the-fly that CAR
migration had happened and relocated cbmem_console_p
accoringlin with car_sync_var(). However, if the CAR_GLOBAL
pointing to another object inside CAR is a relative offset
instead, we have a more generic solution that can be used
with timestamps code as well.
Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify intel/fsp_broadwell_de such that timestamp_init() is
before raminit (and CAR teardown of FSP1.0), adding two new
early timestamps while doing so.
Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already
do it this way.
Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the very early days of FSP 1.0 this did not work so
we kept it disabled.
Change-Id: I8a88be6df335598d4c6007a8b7ff307b293e1f97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
From DDR4 SPD spec:
Byte 4 (0x004): SDRAM Density and Banks
Bits [7, 6]:
00 = 0 (no bank groups)
01 = 1 (2 bank groups)
10 = 2 (4 bank groups)
11 = reserved
Bit [5, 4] :
00 = 2 (4 banks)
01 = 3 (8 banks)
All others reserved
Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks.
Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Based on HW schematic to modify USB setting.
Drallion has two type C on left and two type A on right.
BUG=b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Sets all unused sata ports to disable in the device tree
Note:
SATA4 and SATA5 are located at the bottom of the board, but there
is no connector for this. Apparently, a board with an increased
number of ports is very rare. Perhaps this is a separate variant
of the Asrock motherboard. For this reason, these ports are also
disabled
Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Disable spi0, i2c0 and i2c1 in the “SerialIoDevMode” register for the
following reasons:
1. when the AMI BIOS is used, these pci devices are disabled in
lspci.log;
2. there are no pads in the inteltool.log that use the functions of
these buses
Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35070
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The string "register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" was mistakenly
taken from the Intel KBL-RVP8 devicetree.cb. Remove it, since the i2c4
bus is disabled in the "SerialIoDevMode" register
Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1) VR domains current limit Icc max for Sky/Kaby Lake S is set based
on the processor TDP [1]. Updates information about this
2) Sets VR voltage limit to 1.52V, as described in the datasheets [2,3]
[1] Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde
[2] page 112-119, 6th Generation Intel(R) Processor Families
for S-Platforms, Volume 1 of 2, Datasheet, August 2018.
Document Number: 332687-008EN
[3] 7th Generation Intel(R) Processor Families for S Platforms and
Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1,
December 2018, Document Number: 335195-003
Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The MCFG ACPI table was not being created.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35bdefb2a565d18917a2f6517d443890f93bd252
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Decide if HECI1 should be hidden prior to boot to OS.
BUG=none
TEST=Boot to OS, verify if Heci1 is disabled on hatch system
using FSP 1344.
Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The documentation for StackBase and StackSize in FSPM_ARCH_UPD is
confusing. Previously the region was shared for heap and stack,
starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs.
Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of
stack guards and reduces amount of reserved CAR for bootblock and
verstage, as the new allocation in .bss is only taken in romstage.
BUG=b:140268415
Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TPMU_HA is a union of all the different hash digests, and so
sizeof(TPMU_HA) evaluates to 64 (the size of the largest one). This will
lead to out-of-bounds writes when copying smaller digests, so use the
specific digest size for each algorithm.
Change-Id: Ic9101f157d5a19836b200ecd99f060de552498d2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 14049{49,50,51,52,53,54,55,56,57,58,60,61,62}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Include the file containing the typedefs for uint_*.
Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35268
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Include the file containing the typedefs for uint_*.
Change-Id: Ib0eea9bfd0c8d9e3eba257b561980accf5b4bab4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35267
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the new SuperIO ACPI generator to make includes in DSDT obsolete.
Manually tested on X11SSH-TF and verified that ACPI tables are correct.
Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds Lewisburg C62x Series PCH support by adding the
Production and Super SKUs of the following PCI devices:
- LPC or eSPI Controllers,
- PCI Express Root Ports,
- SSATA and SATA Controllers,
- SMBus,
- SPI Controller,
- ME/HECI,
- Audio,
- P2SB,
- Power Management Controller.
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.
It generates a device HID based on the decoded I/O range.
Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.
Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
resource settings on specific LDNs
Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.
USB designers suggest changing discth to 15.
BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage
Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu <changqi.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Vendor only does dummy reads right after JEDEC init is finished
and dram init was marked as finished.
Dummy reads also make much more sense after JEDEC init as a way to
send a few JEDEC commands, presumably as a way to make sure it is
ready.
TESTED on ga-g41m-es2l (still boots fine)
Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on HW schematic to modify PCIE setting.
BUG=b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Use sku-id to load the SAR values for Bloog device.
BUG=b:138180187
BRANCH=octopus
TEST=build and verify load Bloog SAR by sku-id
Cq-Depend: chromium:1771477
Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To avoid possible panel failures due to incorrect timing settings for
PTN3460, the internal graphic device should be disabled.
Change-Id: Ie0b9ed99fb78461bb48d6f2ff328643cd8c2cd15
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add printing SPD data for debug usage.
BUG=b:139397313
BRANCH=N/A
TEST=Tested the on Hatch and checked cbmem log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To support multi digists the tlcl_extend() for TPM2 expects
TPML_DIGEST_VALUE pointer as input argument.
BUG=N/A
TEST=Build binary and verified logging on Facebook FBG-1701
Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions
are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use
it at spi_flash.c
BUG=b:136595978
TEST=Build test of several platforms that don't use stoneyridge. Build and boot
grunt (using stoneyridge new fch_spi).
Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Rename the table from Liara specific to simply specifying
that it's using 2T command rate
BUG=139841929
TEST=build and do stress test
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
override 'uint32_t sku_id(void)' so that lib_sysinfo.sku_id get a
correct value in depthcharge
BUG=b:140010592
BRANCH=none
TEST=boot treeya board, in depthcharge stage, lib_sysinfo.sku_id
print correct value.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I631f62021e8104a69a43667a811c9c23e3105596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Magf - <magf@bitland.corp-partner.google.com>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Padmelon board code was written for Merlin Falcon (family 15h models 60h-6fh),
but as the needed binaries are not yet merged (commit 33615), a config
HAVE_MERLINFALCON_BINARIES was added. If the binaries are not available,
the board defaults to Prairie Falcon, which use the same binaries as Stoney
Ridge. Once the binaries are merged, the config will be eliminated. Fan
control is done through F81803A SIO, and IRQ/GPIO and other board
characteristics are the same regardless of Merlin Falcon or Prairie Falcon.
Padmelon board was created to accept Prairie Falcon, Brown Falcon and Merlin
Falcon. The requested development was for Merlin Falcon. There are some small
spec changes (such as number of memory channels) between SOCs. Brown Falcon
was not investigated, Prairie Falcon is very similar to Stoney Ridge.
Started from Gardenia code, added changes created by Marc Jones and finally
revised against schematic, which added changes to GPIO settings.
BUG=none.
TEST=Both versions tested and boot to Linux using SeaBIOS.
Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Consider the association between modem[1] and DCXO, this patch is a fix for
eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [2]
We should not disable XO_CEL and block the bblpm request when modem is still ON.
For power-saving, we still could disable unused XO_CEL and
mask request to disable unused power mode when modem is no longer be used.
[1] https://review.coreboot.org/c/coreboot/+/32666
[2] https://review.coreboot.org/c/coreboot/+/32323
BRANCH=none
TEST=Boots correctly on Krane.
Change-Id: I047ebed615e874977ca211aafd52b5551c71b764
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
mashal_TPMT_HA() uses size of SHA-256 hash.
Use tlcll_get_hash_size_from_algo() to determince the hash size.
BUG=N/A
TEST=Build binary and verified logging on Facebook FBG-1701
Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The P2SB PCI device can be "hidden", which causes all sorts of
nightmares and bugs. Moreover, FSP tends to hide it, so finding
a good solution to this problem is impossible with FSP into the mix.
Since the values for IBDF and HBDF were already hardcoded as FSP
parameters, define them as macros and use these values directly to
generate the DRHD.
Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add fan based active cooling for TSR sensors temperature range.
BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR sensors on Hatch.
Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
tsc_freq_mhz() had a static table of Intel CPU families and crystal
clock, but it is possible to calculate the crystal clock speed dynamically,
and this is preferred over hardcoded table.
On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz
hence we had to use static table to calculate crystal clock.
Recommendation is to make use of CPUID.16h where crystal clock frequency
was not reported by CPUID.15h to calculate the crystal clock.
BUG=b:139798422, b:129839774
TEST=Able to build and boot KBL/CML/ICL.
Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables Gaussian Mixture Model (GMM) only if the corresponding pci
device is enabled in the device tree
Tested on Asrock H110M DVS motherboard
Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Select NO_UART_ON_SUPERIO as the SoC internal UART is used.
The current code is working, so this is just a cosmetic fix to remove
some unused options from Kconfig.
Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35151
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion will use soldered down memory and use
GPP_F12 to GPP_F16 indicates mem_id.
BUG=b:139397313
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Its entirely no-op and is getting in the way of real hardware timers for
power9/talos ii.
Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35082
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per GT7375P programming guide rev0.4, we want to enforce a delay
of 120ms after the reset is completed, before HID_I2C starts.
BUG=b:140276418
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Summary:
This patch calls monolake board specific function to query
settings stored in VPD binary blob to configure FSP UPD
variable HyperThreading.
Test Plan:
* Build an OCP MonoLake coreboot image, run following command
to initialize RW_VPD and insert HyperThreading key:
vpd -f build/coreboot.rom -O -i RW_VPD -s 'HyperThreading=0'
* Flash the image to MonoLake, boot and observe following
message in boot log:
Detected 16 CPU threads
If RW_VPD partition does not exist, or if HyperThreading
key/value pair does not exist, the boot log has:
Detected 32 CPU threads
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Summary:
Added a framework to search VPD in romstage before memory is
avilable. vpd_cbmem.c and vpd_premem.c are added for
code specific for premem environment and for environment that
cbmem can be used.
Since global variable is forbidden in romstage. A CAR_GLOBAL
variable is defined in vpd.c. This variable holds VPD binary
blobs' base address and size from memory mapped flash.
The overall flow is:
* The CAR variable g_vpd_blob is initialized if it was not,
either at romstage (before FSP-M execution in case of FSP UPD
customization), or at ramstage.
* At ramstage, during CBMEM_INIT, the VPD binary blob contents
are copied into CBMEM.
* At vpd_find() which may be called at romstage or at ramstage,
it sets storage for a local struct vpd_blob variable.
* The variable gets contents duplicated from g_vpd_blob, if
vpd_find() is called at romstage.
* The variable gets contents obtained from CBMEM, if vpd_find()
is called at ramstage.
Added a call vpd_get_bool(). Given a key/value pair in VPD
binary blob, and name of a bool type variable, set the variable
value if there is a match.
Several checks are in place:
* The key/value length needs to be correct.
* The key name needs to match.
* THe value is either '1' or '0'.
Test Plan:
* Build an OCP MonoLake coreboot image, flash and run.
Tags:
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Fastboot support in vboot_reference is unused, unmaintained, and
produces compile errors when enabled. Since there is no current
or planned use cases for fastboot, remove it.
BUG=b:124141368, chromium:995172
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35002
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove duplicated code and instead use the IPMI KCS driver, which provides
the same functionality.
Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Advertise the register spacing used by the BMC as set by the Kconfig.
Tested on OCP Monolake.
Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Add Kconfig to enable TXT
* Add possibility to add BIOS and SINIT ACMs
* Set default BIOS ACM alignment
* Increase FIT space if TXT is enabled
The following commits depend on the basic Kconfig infrastructure.
Intel TXT isn't supported until all following commits are merged.
Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 [1]
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The pad configuration in this patch was
generated using the pch-pads-parser utility [2]. The inteltool dump
before and after the patch is identical (see notes)
Notes:
1. For some reason, GPIO RX State (RO) for the GPP_F4 and GPP_G10
changed the value to 0, but this doesn't affect the motherboard
operation. Perhaps this is because PAD_CFG1_GPIO_DRIVER is set to
PAD_CFG_GPI_INT(), and the pad is not actually connected. So far I
haven't circuit diagram to check this out.
2. According to the documentation [1], the value 3h for RXEVCFG is
implemented as setting 0h.
3. If the available macros from gpio_defs.h [3] can't determine the
configuration of the pad, the utility [2] generates common
_PAD_CFG_STRUCT() macros
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
[2] https://github.com/maxpoliak/pch-pads-parser/tree/stable_1.0
[3] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for the X11SSH-TF which is based on Intel KBL.
Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init
Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common
For more details have a look at the documentation.
Please apply those patches as well for good user experience:
Ica0c20255f661dd61edc3a7d15646b7447c4658e
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They
don't benefit from having low-memory set as writeback-cacheable.
This also fixes regression from CB:34893 that caused some random
hangs with more recent intel SoCs in ramstage.
BUG=b:140250314
Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adjust CID to allow for Windows driver to attach without breaking
functionality under Linux. Same change made as to google/cyan
(which uses same Realtek RT5650 codec) in commit 607d72b.
Test: build/boot Windowns 10 on google/buddy, observe audio
drivers correctly attached to codec and Intel SST devices.
Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Increase CBFS and RAMSTAGE size to accommodate larger binary component.
BUG=b:77641795
TEST=Build and test on Gale.
BRANCH=none
Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0
Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1366388
Original-Reviewed-by: Zhihong Yu <zhihongyu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35134
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel platforms using eSPI EC communication have just been enabling
the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically
the same, but at least marks it as eSPI in Kconfig for clarity.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35128
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH
[3] supports up to 16 PCIe ports. However, ACPI contains a description
for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.
BUG=b:139095062
BRANCH=N/A
TEST=Build without error
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Enable acoustic noise mitgation for hatch platform, the slow slew rates
are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA).
BUG=b:131779678
TEST=waveform test and reduce the noise level.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h,
respectively. That name is closer to the terminology used in most
functions related to Trusted Firmware, and it removes the annoying
auto-completion clash between arm64/arm_tf.c and arm64/armv8.
Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Also don't define the default as this result in spurious lines in the
.config.
The only difference in config.h is on boards with the Nvidia tegra210
SOC that now select ARCH_ARM64, because its ramstage runs in that
mode. The resulting binary is identical however.
Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31315
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need to select ARCH_ARM in SOC Kconfig
Also don't define the default as this result in spurious lines in the
.config.
Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There will be inlined smm_lock() that would conflict
with this special case.
Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34874
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current HWID for drallion is reported as invalid by chrome, generate
new valid HWID with the following command and taking last 4 digits.
`printf "%d\n" 0x$(crc32 <(echo -n '$1'))`
BUG=b:140013681
Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Many (if not all) platforms have moved to using consistent
boot flow constructs where a weak car_stage_entry() is no longer
necessary to avoid the complexity of handling the numerous and
different boot flow combinations. The weak symbol is just causing
issues so remove it.
Change-Id: I7e7897c0609aac8eef96a08bb789374b2403956d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35135
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement sa_get_tseg_base and sa_get_tseg_size.
Used by Intel TXT and the new SMM API.
Tested on OCP/Wedge100S.
Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There are no more cases that need to override this.
Change-Id: Iafa94af19eae00cc5be5d4ff7454066558e3c74f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34741
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MSRs were already named as PRMRR in broadwell, just
mismatching with the rest of the code. All later devices
use the names PRMRR and UNCORE_PRMRR for these MSRs.
Reflect the name change in structures and local variables.
Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During boot sequence sometime touchscreen reset keeps failing. Also, kernel
dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message.
This adds around 4 more seconds to the boot sequence. Setting the appropriate
delay of 120ms between enable and reset for Goodix Touchscreen helps to
synchronize and address this failure. This value is 120 ms as per Goodix Spec.
BUG=b:138413748
BRANCH=None
TEST=Built and tested on Hatch system
Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
postcar_commit_mtrrs() isn't used outside the postcar_loader
compilation unit. Make it static to reduce API surface area.
Additionally the return value was not being utilized. Modify
the return type to be void to align with the current usage.
Change-Id: If07f34467941d00de731489867e485cfff80ea63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is LVDS bridge, I assume this was lost while upstreaming
or converting boards to variants.
Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Device is present in devicetree but not included in
the build.
Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, we don't have UPDs to set emmc settings per mainboard on CML.
This code change is to create mmc.c to provide interface to override dll
settings per mainboard.
Notice: set_mmc_dll function will override the dll values in FSP.
BUG=b:131401116
BRANCH=none
TEST=Boot to OS and confirm the dll values have been overridden.
Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383
Signed-off-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
New emmc DLL values for Kindred
BUG=b:136784418
BRANCH=none
TEST=Boot to OS 100 times on Kindred proto 1 board.
Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Move descriptions below the license header
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion doesn't have on board LAN, remove GBE bin file config.
BUG=b:139906731
TEST=emerge-drallion coreboot chromeos-bootimage and check
image-drallion.bin not include GBE region
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mathew King <mathewk@chromium.org>
Drallion will use soldered down memory. Add dummy spd file.
BUG=b:139397313
BRANCH=N/A
TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The file chip.h has a special purpose for defining the
configuration structure used in static devicetree.
Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch includes common romstage code to setup the console
and load postcar.
Fix booting regression issue on all latest IA-SOC introduced by CB:34893
Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Remove comments saying that a file is based on another file from the
coreboot project.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34607
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This timestamp also got unintentionally removed from some
boards as they were transformed to use common romstage entry.
Change-Id: I12be278a674f9a2ea073b170a223c41c7fc01a94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34970
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a new Kconfig symbol that allows an x86 device to begin execution
when its reset vector is in DRAM and not at the traditional 0xfffffff0.
The implementation will follow later, this is just to setup various
ENV_xxx definitions correctly for the build environment.
Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This enables the use of .bss section for ENV_BOOTBLOCK
and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y.
In practice, boards with CAR_GLOBAL_MIGRATION=y currently
build with romcc-bootblock so they will not be using .bss.
Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This provides stack guards with checking and common
entry into postcar.
Change-Id: If0729721f0165187946107eb98e8bc754f28e517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34973
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows for minor optimization as num_timestamps becomes
a constant zero for a function with local scope. The loop
with calls to timestamp_add() gets removed from bootblock.
Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ENV_ROMSTAGE_OR_BEFORE is a direct replacement for testing
defined(__PRE_RAM__) as a true statement instead of with the
help of the preprocessor.
Note that for x86, due to existence of ENV_POSTCAR and ENV_SMM,
ENV_ROMSTAGE_OR_BEFORE and ENV_RAMSTAGE are not the inverse of
each other.
Change-Id: Ibd2292f922ccb9e79d10ca9bc35797048d174287
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34939
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently only x86 requires special handling here, for simplicity
avoid introducing <arch/rules.h> and deal with this directly in
<rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a
variable that was previously declared with CAR_GLOBAL.
Test for !defined(__PRE_RAM__) can be transformed into
ENV_RAMSTAGE here as the warnings about invalid bmcinfo
structure do not need to be repeated in SMM console, which
is generally disabled anyways due to DEBUG_SMI=n.
Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header
Note that the file include/arch/acpi.h is a fantastic example of why
moving to the authors file is needed. Excluding the guard statements,
it has 8 lines of copyrights for 3 function declarations.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kukui AP doesn't remember if the last AP reset was due to AP watchdog.
We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query
the reset reason from EC.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog'
2. wait for watchdog reset
3. check 'mosys eventlog list | grep watchdog'
Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header
- Fix some spacing
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34605
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
