The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file
and use this definition in the mainboard code, so port this back to
Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This reverts commit 0e945a3426.
Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the
register that this patch enables
Signed-off-by: Martin L Roth <gaumless@gmail.com>
Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id53c9a6495d584c374e89b76d1fd4258654b6f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Now that multiple platforms are trying to initialize eMMC in coreboot
instead of depthcharge, lets move common functionality into commonlib
instead of copying the same functionality between multiple platforms.
Note for consistency, changed name of set_early_mmc_wake_status() to
mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function
for retrieving the Operating Conditions Register (OCR) contents.
BUG=b:218406702
BRANCH=None
TEST=emerge-herobrine coreboot chromeos-bootimage
flash onto villager device and make sure still boots ChromeOS
Change-Id: Id00535b05bbd379081712601ef10e762c1831747
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The Bostentech mainboard appears out of order - this can be fixed either
by renaming the mainboard to start with S, or by the simpler method
used here by putting the mainboard directory name as the main name, then
noting that the full name is "Shenzhen Bostrontium Teng Technology".
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I31b4c663b68cdcde2d175f080f011f2998e56074
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL
MSR at a late BS_PAYLOAD_LOAD boot state.
This MSR is in platform scope and must only be locked once on each
socket. Add a spinlock to do so.
Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Select HSP config to indicate that the SoC includes Hardware Security
Processor. This will allow PSP verstage to get and report the HSP state.
BUG=None
TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify
that HSP is reported during the boot sequence.
Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Get Hardware Security Processor(HSP) state in PSP Verstage through the
SVC call and report it in cbmem logs.
BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.
Change-Id: Ic4875d1732f22783a90434329188192b106168f4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add an SVC call to get the state of Hardware Security Processor (HSP) in
AMD SoCs. This SVC call will be used from PSP verstage to get and
report HSP state.
BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state
is read and reported in the firmware logs.
Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove TODO comment after checking against Mendocino PPR #57243, rev
3.02.
BUG=b:263563246
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e35f4c68ec09304eb892888759c7e5ef3dd0ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71911
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update USB port Type-A Port A0 setting.
BUG=b:261650602
TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command.
Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Follow hardware design to correct aux setting on USB-C ports to
fix DP monitor can not output data through type-C port 0
USB-C port 0 did not have retimer.
USB-C port 1 have retimer.
USB-C port 0 AUX_DC_P connect to GPP_E22.
USB-C port 0 AUX_DC_N connect to GPP_E23.
BUG=b:263212450
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
DP monitor display normally
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I3af7522f7b6477edcd88004ce1d5f86aeebe3393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71222
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Update settings for touchpad I2C frequency and data hold time.
I2C frequency and data hold time need to meet touchpad spec.
- I2C frequency: 380kHz - 400kHz
- Data hold time: 0.3us - 0.9us
BUG=b:262320419
TEST=On winterhold, touchpad i2c measurement from vendor,
Frequencies: 395 kHz, Data hold time: 0.66 us
Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
This mirrors the change made for drivers/i2c/generic.
TEST=untested, as no boards selected this option.
Change-Id: Icb60502a4a7c5e7a1fcf1ee60e23c77e00d6de7b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71851
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
This mirrors the change made for drivers/i2c/generic.
TEST=untested, as no boards selected this option.
Change-Id: I4f95d0e453d89b7e1978d3efac304518304495d1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71850
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The patch uses cb_err enum values as return values for function
cse_get_boot_performance_data() instead of true/false.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
When pulling in commonlib/storage/pci_sdhci.c into herobrine, am
seeing an "error: cast to pointer from integer of different size
[-Werror=int-to-pointer-cast]", so fixing that.
BUG=b:254092907
BRANCH=None
TEST=emerge-herobrine coreboot
Make sure that we can build without errors
Change-Id: Ib1718f156708a619f7eeb181e19b1a8c620de1f8
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71828
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The headers added are generated as per FSP v3503.00
BUG=b:261159242
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Cq-Depend: chrome-internal:5318308, chrome-internal:5318129
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
0xF8000000 was taken from old platform during phoenix porting, updating
it to 0xE0000000 to make room for 256 pci busses which is required for
usb4 and hotplug support. mmconf size gets set to 0x10000000 when 256
busses are used.
Change-Id: Ic143171f5650aff5db48c8f477d7aca3e7f5c1e7
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71870
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I62b15d59cc4a5f214e45c3995f651228b1ae6ea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71900
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7ded68f4732ec12a1c7e59445d572763a03c3b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71879
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ief1e9c6d6fa0889b947863837bedb2fbdf3120c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71878
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b9f1b71a5f8b2776c8b338351b2cca723d00598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71877
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iedd99cfb64809c4e111e0931c2260981f465035b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The smu_sx_entry function is identical for all AMD SoCs, so introduce it
as common code that can be selected to be included in the build via the
SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific
difference in this function is the ID of the SMC_MSG_S3ENTRY message
which is defined in each SoC's soc/smu.h include file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Morthal has been overcome by events.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use the common preloader for fsp-s
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I32f8ca02c4de9e882f207c2dd2378b6b44dc61ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71848
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common preloader for fsp-s
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iea7011d37667f3f04ce842038346741fba66b1dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71847
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a discoverable device (e.g. a PCI device) does not appear in the
devicetree (typically because it is removable), coreboot enables it
by default. Disable the SATA2 (device for SATA ports 4 and 5, which
is not used in AHCI mode) and Thermal devices on W520 as well. Both
devices were only disabled on the T520.
Tested, this change fixes a long boot time when using MrChromebox's
edk2 payload on the W520, likely related to the following errors:
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 0
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 1
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 2
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 3
AHCI: Error interrupt reported PxIS: 40000001
Non data transfer failed at retry 4
Change-Id: I0b0483aae05fa84d97987a93db634b740f830e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71857
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per Kendo3-WS schematics, the conventional PCI bridge is not used.
Change-Id: Ic3aa11cc3a3028c31b06ad8f74875db8c5626a89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71856
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- Drive is functional and has no unrecoverable errors on boot
- Drive is functional and has no unrecoverable errors after S0ix
Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested with the following drives:
- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)
Test:
- System still asserts `SLP_S0#` during suspend (power LED blinks)
- `slp_s0_residency_usec` still increases after suspend
Change-Id: I919d75cb2a88c0d623c46e44c506ec2d85567995
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
"extern" is always implied with function declarations.
Also remove the comment as the linker will just tell you the same if a
definition is missing.
Change-Id: I53679ab57981790f82affb46a006281b348af574
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71869
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The DDR5 board is almost identical to the DDR4 one. The only major
difference is the board's DDR5 memory design.
TEST=Boot MSI PRO Z690-A board successfully to Ubuntu 22.04. Memory:
Crucial CT8G48C40U5.M4A1 in all 4 slots.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I652a879d1616df4708fe4690797ad98384897f53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This avoids runtime failures of lacking a RW_NVRAM section in fmap or
one having a size too small.
Change-Id: I3415bd719428a23b21210eb2176dbe15fa44eb9c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71868
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Use 'enum cb_err' values for below cse lite functions instead of true or
false.
Functions whose return values updated in this patch:
1. cse_set_next_boot_partition()
2. cse_data_clear_request()
3. cse_set_and_boot_from_next_bp()
4. cse_boot_to_rw()
5. cse_fix_data_failure_err()
TEST= Do boot test on Gimble.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch uses 'enum cb_err' values as return values for
cse_get_bp_info() function.
TEST=Build the code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I900e40b699de344f497e61d974bca3fee7f6ecbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use the common preloader for fsp-s
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I74ef10347c37c8371156f89da9f234d170ab1aa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71846
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use the common preloader for fsp-s
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ibbed17445c3cd8fa4da671f2a90532d3c39ad08b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The function to start preloading the fsp-s is identical in cezanne and
newer socs, so move it to common with a new Kconfig option to enable it.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia572c99928f4a60896b7a861ab6fb3f1257ac1cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove TODO comment after reviewing against mendocino ppr #57243, rev
3.00
BUG=b:263563246
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id517ce6e5f5bee5deffe509d748b16be0eefca96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
This header file is correct for Mendocino, so remove the TODO.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85b47491863bff731b86cf0523253cb547dbb76a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71794
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates return type for below functions as they uses
'enum csme_failure_reason' type return values.
1. cse_sub_part_trigger_update()
2. handle_cse_sub_part_fw_update_rv()
3. cse_sub_part_fw_update()
TEST=Build coreboot code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43bc2d518a275894860e4d3c930c3c4d9685fb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix:
cc1: error: 3rdparty/blobs/mainboard/asrock/h110m: No such file or directory [-Werror=missing-include-dirs]
cc1: error: 3rdparty/blobs/mainboard/acer/aspire_vn7_572g: No such file or directory [-Werror=missing-include-dirs]
...
Change-Id: Icc43e40514a12944fa180197ffe3230ff9800de9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Fix:
cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Update devicetree based on the schematic_20230105.
BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
This picks up the following changes:
acf73954 phoenix: rename morgana to phoenix
a2c15297 mendocino: Upgrade SMU to 90.35.166
28983855 Update Picasso FSP binaries
This also updates the phoenix fw.cfg file that points to the submodule.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1d04d6232307dc913645a3d60ac3711018e2bdfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71803
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been reported that the PEIM graphics driver may temporarily
fail communication with the display if the time between libgfxinit
turning off the displays and the PEIM driver initialization is too
short. 200 ms has been identified as a safe delay.
This is a temporary workaround and an investigation is in progress to
come up with a better and long term solution.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is systematically seen
Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If memory training is going to happen and early graphics is supported
by the mainboard, an on-screen text message is displayed to inform the
end user.
Memory training can take a while and an impatient end user facing a
black screen for a while may reset the device unnecessarily.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On screen text message during MRC training observed on skolas
Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On-screen text message seen during MRC training on skolas
with a few extra patches
Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b514
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71696
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Verify that VGA text mode is functional in romstage
Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces an early graphics driver which can be used in
romstage in cache-as-ram mode. The implementation relies on
`libgfxinit' and provide VGA text mode support.
SoCs wanting to take advantage of this driver must implement the
`early_graphics_soc_panel_init' function to set the panel power
sequence timing parameters.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Graphics bring up observed on skolas with extra patches
Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the real-time tuning to improve performance in the real-time
environment for this mainboard.
Change-Id: I91ad7ca58add92b5cc66148aff8378890ee217eb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71234
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve
real-time behaviour of the SoC (see Intel doc #640979). It describes,
amongst knobs for the OS, a couple of firmware settings that need to be
set properly to reduce latencies in all the subsystems. Things like
clock and power gating as well as low power states for peripherals and
buses are disabled in this scenario.
This patch takes the mentioned UEFI parameters from the guide and
translates them to FSP-M and FSP-S parameters. In addition, a chip
config switch guards this tuning which can be selected on mainboard
level if needed.
When this real-time tuning is enabled, the overall system performance
in a real-time environment can be increased by 2-3%.
Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
pertinent header file
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarilly share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot Google/rex
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
pertinent header file
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarilly share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot Google/brya.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make will not find the build targets unless quotes are removed.
Change-Id: Iddf4e0cd8a11eaf327d6f55baf38a30c566d0f28
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71519
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch that introduced the selection of software connection manager,
CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for
SCM and FCM) added a default to enable the software configuration
manager directly in the choice.
This leads to warnings when running make menuconfig:
src/soc/intel/alderlake/Kconfig:439:
warning: defaults for choice values not supported
src/soc/intel/meteorlake/Kconfig:337:
warning: defaults for choice values not supported
src/soc/intel/tigerlake/Kconfig:299:
warning: defaults for choice values not supported
I'm not sure why the Kconfig linter didn't catch this, but this
issue is currently breaking the build for me. This patch fixes
it so that instead of setting the default directly, a new Kconfig
value is selected that then sets the default correctly.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I674046a93af8f7c2f3003900804deefa89dae295
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Not all ports have retimers. Add a property to denote that a particular
port has a retimer (instead of assuming that all ports have retimers).
BUG=b:263964979
TEST=Verified on guybrush; SSDT shows retimer-switch on port1 when
device tree is updated accordingly.
Change-Id: I754323236d2912777b63cede0fce2ccf7882cfea
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71663
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TCPA usually refers to log described by TPM 1.2 specification.
Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022
Ticket: https://ticket.coreboot.org/issues/423
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We will use BOE_TV110C9M_LL0 for geralt proto board, so update the
panel setting.
BUG=none
TEST=emerge-geralt coreboot;
see panel-BOE_TV110C9M_LL0 in coreboot.rom
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I28e9dd87350b55fdc609dd2c562c5a2ad578187c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71786
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should keep booting even failed to get the MIPI panel.
BUG=none
TEST=emerge-geralt coreboot;
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I39d9e04e5908f669ae2a1a8ce8858b93cae20654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71785
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Data Protected Range (DPR) needs to be set for all DPR devices,
not only the root device. Separate the setup from the memory
resource map reservation.
Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ
define name.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
A mainboard port needs to:
- select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT'
- implement the Ada package `GMA.Mainboard' with a single function
`ports' that returns a list of ports to be probed for displays.
- set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use
in romstage (and ramstage) for the graphic device.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libgfxinit compiles in romstage.
libgfxinit successfully executes in romstage and ramstage using
the requested MMIO setting on skolas.
Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SA_DEV_IGD is used by the early graphics feature implemented by the
Intel common block.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Compilation
Change-Id: Ic9f0fe1683d55a53c705ae717fe9e40fd8873d1f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
As the used 'bool' type is defined in stdbool.h, include types.h
(instead of stdint.h) which includes all needed header files.
Change-Id: I3f75776575a7a5f70484411b9f3458530f706ec4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71790
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:263920313
TEST=Boot to OS on craask eMMC and NVMe SKUs with both unprovisioned
fw_config and fw_config set correctly.
Change-Id: I4167ee4d00b9ae8fe074c6f5e7a2d5a7382bfe6d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:251055188
TEST=Boot to OS on yaviks eMMC and UFS SKUs with both unprovisioned
fw_config and fw_config set correctly.
On UFS SKU with fw_config set, eMMC no longer shows up in lspci.
(On eMMC SKU, UFS and ISH were already disabled by the coreboot PCI scan
so there's no change in behaviour.)
Change-Id: I31402cb49cffefd98b6fed971f249528448b1d0d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I699070596a77c975254660a1ba74b0f40026186d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
It used to say "FSP-M binary larger than FSP_M_FILE", but
FSP_M_FILE is the binary itself. The binary file size is
actually compared with FSP_M_SIZE.
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
BUG=b:260934724, b:255447299
BRANCH=dedede
TEST=build
Change-Id: I8c95ced79e14bb4a99aa1fa5f4fc3bc0681cc1cc
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71710
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the first version DPTF parameters.
BUG=b:264217345
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I55a3066ef61ce461f40b425a6549d083c29256e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71634
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch adds Kconfigs to define scaling factor for Efficient and
Performance cores instead of using hard coded values in the soc code.
Also, the patches uses the Kconfigs directly to calculate the core's
nominal performance. So, we don't need to implement soc function
soc_get_scaling_factor() to get the scaling factor data for different
core types. Hence, soc_get_scaling_factor() function is removed.
TEST=Build the code for Gimble and Rex. Also, I have verified that
build system logs error when the Kconfigs are undefined.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h
includes with the common gpio.h which will include soc/gpio.h
which will include intelblocks/gpio.h which will include
soc/gpio_defs.h
BUG=b:261778357
TEST=Able to build and boot Google/rex.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I58e428cde5e13f4f0dfe528d798c0613b7f8a94a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71630
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
When the watchdog timer reaches 0, the timer value won't reset to the
default value unless there is an external reset or a kick. It will
result in the watchdog failing to trigger the reset signal.
We kick the watchdog to reset the timer to the default value. Also,
because WDT hardware needs about 94us to synchronize the registers,
add a 100us delay before triggering the reset signal.
BUG=b:264003005, b:264017048
BRANCH=corsola
TEST= Reboot successfully with the following cmd
stop daisydog
sleep 60 > /dev/watchdog&
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When AP boots up after Cr50 firmware update and reboot, AP finds
that Cr50 reset is required for Cr50 to pick the new firmware so
it trigger Cr50 reset and power off the system, AP expects system
will power on automatically after Cr50 reset. However this is not
the case for Chromebox, Chromebox EC set AP_IDLE flag when system
is shutting down, when AP_IDLE flag is set in EC, the system stays
at S5/G3 and wait for power button presssend. It cause an issue in
factory that the operator needs to press power button to power on
the DUT after Cr50 firmware update.
This patch sends EC command to direct EC to clear AP_IDLE flag
after AP shutdown so AP can boot up when Cr50 reset.
BUG=b:261119366
BRANCH=firmware-brya-14505.B
TEST=DUT boots up after Cr50 firmware update in factory test flow
Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces a new config named `DEFAULT_ADL_NEM` and
allows respective brya variants with Alder Lake ESx samples to
choose NEM over eNEM as eNEM was fuse disabled till ESx.
TEST=The boot flow related to eNEM and NEM behaviour remains the
same with and without this patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibbd492a3d210739120c7ad16415cb7912f5b70ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause
issues as the margin is not big enough. Limit SATA speed to Gen 2 to
achieve a more robust SATA connection.
Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SataSpeedLimit' allows to set the speed limit.
This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.
Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on multiple dedede variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I91e03bd1d96a6b2f0c3813665910133db0d6c308
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I212533ffdfb05f841e722c130b52c2976272e670
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
For touchscreens on dedede variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).
Since the fast majority of dedede variants have a touchscreen option,
and those that do use the same GPIOs for enable/reset, set the GPIOs for
touchscreen operation in the baseboard and then override for the few (3)
variants that do not have a touchscreen.
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: Ib95e23545cc3e8589ddbd9e18cd0533bec9333e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: Ic216827a4b53d1d35913efca63a43d4672791c54
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Replace spaces with tabs for consistency.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This avoids the warning of casting pointers to integers of different
size.
Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69389
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The dGPU used for some Brya projects requests 33 bits of address
space for one of its BARs via the Resizable BAR mechanism
(requires 6GB).
This Kconfig is currently set at 32 bits for brya, so the allocation currently is capped at 32 bits (4GB). This patch sets the limit to 33
bits for brya boards, which is enough for the GPU.
BUG=b:214443809
TEST=all of the dGPU PCI BARs on agah can be successfully allocated
Change-Id: Ia791be5108fb07a256ae62fc2aee2f057909ef12
Signed-off-by: Tarun Tuli <tarun@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
get_cpu_index() helper function returns cpu's index based on it's APIC
id position from the ascending order list of cpus' APIC IDs.
In order to calculate the cpu's index, the helper function needs to
traverse through each cpu node to find their APIC IDs. So, the function
traverse the CPU node list from the cpu whose APIC ID is 0 assuming it
is the first cpu node in the list. This logic works fine where BSP's
APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as
APIC ID numbering first get assigned for CPU Die Efficient cores, then
Performance cores.
Please refer section# 6.1 of doc#643504 for more details on APIC IDs.
Considering the APIC Id allotment for MTL cores, as existing code
traversing begins from the cpu that has APIC Id#0 which may not be the
first cpu node in the list so index calculation results in wrong value.
The patch addresses above described issue by traversing all the CPU
nodes to calculate the cpu index. Also, prevents inconsistent report
of /sys/devices/system/cpu/cpu*/cpufreq/* and
/sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot.
TEST=Verified that the get_cpu_index helper function returns the correct
index id for a CPU on Rex.
The coreboot log with code instrumentation, before this patch:
[DEBUG] my_apic_id:0x10 cpu_index: 0x6
[DEBUG] my_apic_id:0x11 cpu_index: 0x6
[DEBUG] my_apic_id:0x42 cpu_index: 0x6
[DEBUG] my_apic_id:0x21 cpu_index: 0x6
[DEBUG] my_apic_id:0x40 cpu_index: 0x6
[DEBUG] my_apic_id:0x31 cpu_index: 0x6
[DEBUG] my_apic_id:0x39 cpu_index: 0x6
[DEBUG] my_apic_id:0xa cpu_index: 0x3
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x8 cpu_index: 0x2
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x28 cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x38 cpu_index: 0x6
[DEBUG] my_apic_id:0x29 cpu_index: 0x6
[DEBUG] my_apic_id:0xe cpu_index: 0x5
[DEBUG] my_apic_id:0x6 cpu_index: 0x2
[DEBUG] my_apic_id:0x20 cpu_index: 0x6
[DEBUG] my_apic_id:0x30 cpu_index: 0x6
[DEBUG] my_apic_id:0x19 cpu_index: 0x6
[DEBUG] my_apic_id:0xc cpu_index: 0x4
[DEBUG] my_apic_id:0x18 cpu_index: 0x6
We can see same cpu_index for multiple cores before fix.
After this patch..
[DEBUG] my_apic_id:0x10 cpu_index: 0x8
[DEBUG] my_apic_id:019 cpu_index: 0xb
[DEBUG] my_apic_id:0x11 cpu_index: 0x9
[DEBUG] my_apic_id:0x18 cpu_index: 0xa
[DEBUG] my_apic_id:0x40 cpu_index: 0x14
[DEBUG] my_apic_id:0x30 cpu_index: 0x10
[DEBUG] my_apic_id:0x42 cpu_index: 0x15
[DEBUG] my_apic_id:0xc cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x29 cpu_index: 0xf
[DEBUG] my_apic_id:0xe cpu_index: 0x7
[DEBUG] my_apic_id:0x20 cpu_index: 0xc
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x31 cpu_index: 0x11
[DEBUG] my_apic_id:0x28 cpu_index: 0xe
[DEBUG] my_apic_id:0x21 cpu_index: 0xd
[DEBUG] my_apic_id:0xa cpu_index: 0x5
[DEBUG] my_apic_id:0x38 cpu_index: 0x12
[DEBUG] my_apic_id:0x8 cpu_index: 0x4
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x39 cpu_index: 0x13
Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes the call into TXT lib in order to disable the TXT
if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT
would be helpful to access VGA framebuffer prior calling into FSP-M.
TEST=Able to perform disable_txt and unlock memory which helped to
access VGA framebuffer prior calling into FSP-M.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add a function to disable TXT as per TXT BIOS spec Section 6.2.5. AP
firmware can disable TXT if TXT fails or TPM is already enabled.
On platforms with TXT disabled, the memory can be unlocked using
MSR 0x2e6.
TEST=Able to perform disable_txt on SoC SKUs with TXT enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27f613428e82a1dd924172eab853d2ce9c32b473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Enable DPTC support for markarth.
BUG=b:263216451
TEST=emerge-skyrim coreboot
Change-Id: I18c2c840037f65f4f2ca92054247cece28843e45
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71720
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Follow thermal table from thermal team.
1. Enable TS3 thermal sensor.
2. Set TS3 passive policy to 63.
3. Set TS3 critical policy to 73.
4. Modify TSR2 passive policy to CPU.
BUG=b:263554342
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ia1fcaee15a8b58b755ce0a48a1978e795b66efd7
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71658
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add ACPI DmaProperty for gladios.
BUG=b:239513596
TEST=Verified SSDT on gladios unit.
Before:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
}
}
After:
Scope (\_SB.PCI0.RP01)
{
Device (RLTK)
{
Name (_HID, "R8168") // _HID: Hardware ID
Name (_UID, 0xD0E889DD) // _UID: Unique ID
Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x07,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
}
Change-Id: I1c4f6ff7b3eda114f4f365a963c089fe584d8aee
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71699
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
PRMRR is used by many Intel SOC features, not just Intel SGX.
As of now SGX and Key Locker are the features that need PRMRR.
Untie it from Intel SGX specific files and move to common cpulib.
Also rename PRMRR size config option. Use the renamed PRMRR size
config option to set the PRMRR size.
TEST=Able to set PRMRR size using config.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This patch decouples useful TXT related operations from the romstage.c
file alone and moves them into a helper txtlib.c. This effort will be
helpful for SoC users to perform TXT related operations
(like Disabling TXT) even without selecting INTEL_TXT config.
At present, those helper functions are only available upon selecting
INTEL_TXT which is not getting enabled for most of the SoC platform in
the scope of the Chromebooks.
TEST=Able to access functions from txtlib.c even without selecting
INTEL_TXT config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iff5b4e705e18cbaf181b4c71bfed368c3ed047ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Sometimes, server platforms may have more than one socket on server
board. However, there's no field to store information about which
socket the DIMM comes from in dimm_info structure.
This patch adds soc_num field in dimm_info structure to store socket
ID of the DIMM.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I1b9e2b87fda2d7c32ecb8ce9d989795c8b869cea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Also disable TCO timer through calling tco_configure().
If tco_configure() is not called, the TCO timeout would
trigger SMI periodically about every 2 seconds with SMM log:
"TCO_STS: BIT18 TIMEOUT"
Tested=On AC CRB, does not see periodic SMI log.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
If cbmem_top is not 1M aligned there will be a hole between DPR base
and cbmem_top that the allocator will consider as unassigned memory.
Resources could incorrectly be assigned to that region and the final
MTRR solution will also try to skip that hole, therefore using a lot
more variable MTRRs than needed.
TESTED on Archer City 2S system: Uses 1 variable MTRR in the final
setup instead of 7.
Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Software Connection Manager doesn't work with Linux 5.13 or later,
resulting in TBT ports timing out. Not advertising this results
in Firmware Connection Manager being used and TBT works
correctly.
Add Kconfig options to chose between SCM (Software Connection
Manager) and FCM (Firmware Connection Manager). FCM is primary, as
it's more compatible save for ChromeOS devices as ChromeOS uses
SCM.
Linux patch:
torvalds/linux@c6da62a
c6da62a219d028de10f2e22e93a34c7ee2b88d03
Tested with StarBook Mk VI (i7-1260P).
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch adds the support to enable/disable package c-state demotion
feature from the devicetree based on mainboard requirement.
Port of commit 4be8d9e80d ("soc/intel/adl: Add support to configure
package c-state demotion")
BUG=none
TEST=Boot to the OS on Google/Rex.
Snippet from FSP log:
[SPEW ] PkgCState Demotion : 0x1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch configures max Pkg C-state to Auto which limits the max
C-state to deep C-state.
Port of commit af42906efa ("soc/intel/alderlake: Set max Pkg C-states
to Auto")
BUG=none
TEST=Boot to the OS on Google/Rex.
Snippet from FSP log:
[SPEW ] PkgCStateLimit : 0xFF
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Because skyrim is loading ramstage from SPI with the DMA engine, the
size of the compressed image is less important to load speed than
decompression time.
Because the LZ4 decompression is so much faster than LZMA, compressing
with LZ4 saves us roughly 30ms in boot time.
For size, we're spending roughly 57KiB:
fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed)
fallback/ramstage 0x9b00 stage 189126 LZ4 (305316 decompressed)
Right now we have 2MiB empty space in Skyrim's RO before this change,
and roughly 550KiB empty space in RW, so there aren't currently any
size worries.
Just for fun, I also tested uncompressed ramstage, and it was still
18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4.
BUG=b:264409477
TEST=Boot skyrim, look at boot speed.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Previously, LZMA was included in romstage because it was almost always
needed to decompress ramstage. When compressing ramstage with LZ4, but
using LZMA compression for FSP-M, we still need the LZMA decompression
to be present, so update when the Makefile includes the LZMA decoder.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Id52d25a13420f05db8b2b563de0448f9d44638e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When ramstage is loaded asynchronously, as on the skyrim boards, the
faster decompression of LZ4 allows for faster boot times than the
tighter compression of LZMA.
To make this change, the name of the existing ramstage_compression
option needs to be updated.
BUG=b:264409477
TEST=Boot skyrim, look at boot speed
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I27dd1a8def024e0efd466cef9ffd9ca71717486a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71673
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the dibbi variant of the waddledee reference board by
copying the template files to a new directory.
BUG=b:260934018
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a includes
GOOGLE_DIBBI
Change-Id: I3b8d4e7f8a53323f56567cbbc03bab7f8804f286
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71709
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B.
Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
MT62F1G32D2DS-026 WT:B 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
MT62F512M32D2DR-031 WT:B 2 (0010)
BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Enable eNEM for all nissa variants. This is mostly done to be consistent
with other recent Intel platforms. It's not strictly necessary since on
nissa the LLC size is larger than the total code + data size used in
CAR. There is no change in boot time.
BUG=None
TEST=Boot to OS on craask
Change-Id: Iad48976e405403ab61c71d8f72e0616ea8b85ebd
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This bit is dropped in factory. All skus can use table ID_0.
BUG=b:251287101
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I4298376899f881dd2265aef5a0bbc5bcc46728a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71690
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and
SSFC is not set, it will treat missing SSFC as zero, so Kano needs
to set the ov2740 to 0 to avoid probing wrong mipi camera.
Before patch
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: ZYDRON_UFC=UFC_MIPI_HI556
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: STYLUS=STYLUS_PRESENT
After patch
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>I2C: 00:20 disabled by fw_config
>fw_config match found: UFC=UFC_MIPI_OVTI2740
>fw_config match found: STYLUS=STYLUS_PRESENT
BUG=b:262939431
TEST=Boot on kano and check functional with ov2740 camera.
Change-Id: I46fac6c820d6006956680a07198db82225630905
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This is support for adding legacy VGA support into romstage.
Support for this is being provided by libgfxinit.
The current use case allows us to initialize the display
before memory init (prior to physical memory init) to inform
the user when lengthy memory training is needed.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=VGA code compiles for romstage
Change-Id: I81309871e8db71657b2a9816708141f121d767d3
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70278
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch disables the stage cache to save boot time.
Note: S3 is not POR for Intel MTL mobile skus.
Boot time is reduced by ~8ms.
Boot time before:
4:end of romstage 1,391,225 (13,724)
100:start of postcar 1,403,339 (12,114)
Boot time after:
4:end of romstage 1,380,262 (5,618)
100:start of postcar 1,392,323 (12,060)
Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
While pademelon may be a desktop board, it's not available for purchase,
which means it should be presented here as an eval board.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5038935bb6f2ba530ea6e16ac84c1746efec8e48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove smbios_mainboard_bios_version so that the default
CONFIG_LOCALVERSION can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia94f8683a54a98f4e3b1f51521db7e3ccb56ba48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The CR50 code clears the post code value. Add this as a #define.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch addresses Intel heterogeneous cores as `Efficient` and
`Performance` cores instead of `small` and `big` cores. It is to ensure
coreboot code has uniform reference to the heterogeneous cores. So, the
patch renames all `small` and `big` core references to `efficient` (eff)
and `performance` (perf) cores respectively.
TEST=Build the code for Brya and Rex boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add below mentioned functions:
is_sgx_configured_and_supported():
Checks if SGX is configured and supported
is_keylocker_configured_and_supported():
Checks if Key Locker is configured and supported
check_prm_features_enabled():
Checks if any of the features that need PRM are configured
and supported. As of now SGX and Key Locker are the only
features that need PRM.
Also, call check_prm_features_enabled() from get_valid_prmrr_size()
to make sure PRM dependent features are enabled and configured before
returning PRMRR size.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The
specification of Key Locker can be found via document #343965
on Intel's site.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
omnigul variant.
BUG=b:263060849
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I42528d73a4f83bd409cb4a1bd51f2e4e82ee7804
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
To support an RPL SKU on omnigul, omnigul must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for omnigul so that it will use the RPL
FSP headers for omnigul.
BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Change-Id: If3cfbaeff0472012cb8f30ed8fff3bf5cac23f85
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Change-Id: I6a0afb04bea4940e13ea62c2cd0a09500b8b5335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71702
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for
commonality of GPIO settings. To reserve craask GPIO table and add
craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will
be 2 and clksrc is still 1.
BUG=b:259211172
TEST=Verify on reworked craask DUT to boot up from NVMe.
Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Although S3 is supported on nissa, only S0ix is used on user devices,
so we can ignore optimising the S3 resume time. Disable the stage
cache to save boot time at the cost on increasing the S3 resume time.
Boot time is reduced by ~6 ms. This is mostly from adding postcar to
the stage cache, which is slow since TSEG is not cached in romstage.
Adding ramstage and FSP-S take negligible time.
The S3 resume time is increased by ~89 ms total from loading and
decompressing ramstage and FSP-S.
Boot time before:
3:after RAM initialization 573,295 (931)
4:end of romstage 583,569 (10,274)
100:start of postcar 587,729 (4,160)
Boot time after:
3:after RAM initialization 571,527 (830)
4:end of romstage 575,712 (4,185)
100:start of postcar 579,866 (4,153)
S3 resume time before:
101:end of postcar 368,904 (0)
10:start of ramstage 369,165 (260)
971:loading FSP-S 385,742 (16,577)
30:device enumeration 407,105 (21,362)
S3 resume time after:
101:end of postcar 363,101 (0)
8:starting to load ramstage 363,101 (0)
15:starting LZMA decompress (ignore for x86) 382,802 (19,701)
16:finished LZMA decompress (ignore for x86) 431,620 (48,817)
9:finished loading ramstage 431,850 (230)
10:start of ramstage 431,927 (76)
971:loading FSP-S 448,357 (16,430)
17:starting LZ4 decompress (ignore for x86) 474,420 (26,062)
18:finished LZ4 decompress (ignore for x86) 474,627 (206)
BUG=b:247940538, b:192032803
TEST=Boot and S3 suspend/resume on craask
Change-Id: I8015dc0808ee19cac67c2a6573d52781c6120e8c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71677
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
On recent Intel ChromeOS devices, although S3 is still supported, only
S0ix is used on user devices, so we don't care about optimising S3
resume time. Disabing the stage cache saves boot time at the cost of
increasing the S3 resume time. E.g. on nissa this reduces boot time by
6 ms and increases S3 resume time by 89 ms.
BUG=b:247940538, b:192032803
TEST=Build and boot on nissa with MAINBOARD_DISABLE_STAGE_CACHE
selected.
Change-Id: I243a401a112a12bb824c5447a8fecc99500f7739
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Configure GPIOs based on b/263534907#comment4 from EE.
BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
the FSP log.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Configure CPU PCIe RP and IOM per variant.
Change-Id: I9c38af42206497dbb9436e9f2b8aff46fa4d3fb9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Create the omnigul variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:263060849
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_OMNIGUL
Change-Id: I6b4123db9cb77dc050a81f1cb83ef10e2fbffe8d
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This reverts commit e45f70423e.
Reason for revert: Merged out of order, broke tree
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I38a7be6b94199d3a23e78114fb6708c535f241cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This reverts commit 96d9b75669.
Reason for revert: Merged out of order, broke tree
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This message is designed to reduce end-user confusion who may not
know what memory training is. It also provides a maximum time
estimation calibrated for brya devices.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=New message observed on skolas
Change-Id: Ie71cd86746427789b3694d41224bf2c170af0f91
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70796
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On-screen text message seen during MRC training on skolas
with a few extra patches
Change-Id: I41c9cccb09dea52e2318f8f9ebeeda3697a7b513
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required
to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig
option, CSE reboots the system into CSE_RW FW region on cold reboot.
BUG=b:224325352
TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe
CSE boot to RW FW region as part of coreboot console log,
localhost ~ # cbmem -c | grep cse
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the UPD dxio_tx_vboost_enable for PCIe optimization.
It will impact the PCIe signal integrity, need to double-confirm
the SI result after enabling this setting.
BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
the FSP log.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Create the markarth variant of the skyrim reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:262092858
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MARKARTH
Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82
Signed-off-by: Chao Gui <chaogui@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
In next phase, yaviks will remove external fivr. Use the board version
to config external fivr for backward compatibility and show message.
BUG=b:263842258
TEST=build, boot to OS, suspend/resume work normally.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id85570046c5b8e9d90a112793c1ec8604e6bf533
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into
safe state aka LOW/PD.
BUG=b:263411621
TEST=Able to build and boot Google, Rex to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
TEST=Verify presence of subsystem ID for fast_spi device on google/rex.
lspci output before this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
lspci output after this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
Subsystem: Intel Corporation Device [8086:7e23]
Note: UPD SiSkipSsidProgramming was set to 1 for above test.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add is_keylocker_supported() API in common cpulib.
This function checks if the CPU supports Key Locker feature.
Returns true if Key Locker feature is supported otherwise false.
Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71117
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP.
Since we use RPL FSP and it will support ADL as well, we rename
"Gaelin4ADL" to "Gaelin".
BUG=b:258603624
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot
Cq-Depend: chrome-internal:5227091, chromium:4113361
Change-Id: Ie7349f3670aeec166228e7df55300cd30d0ca16c
Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
winterhold/whiterun has different H/W topology to skyrim that the eMMC device
is on a different GPP:
skyrim: GPP1 -> SD
winterhold : GPP1 -> eMMC
BUG=b:263763288
BRANCH=none
TEST=s0i3 stress over 2500 cycles.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Fix:
CC romstage/mainboard/amd/pademelon/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/amd/gardenia/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
CC romstage/mainboard/google/kahlee/static.o
cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs]
Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
For some reason, the Windows LPEA drivers won't attach without
_HRV (hardware version) defined for the GPIO controllers.
Add it, using value taken from Intel baytrail/valleyview edk2
reference code.
TEST=boot Windows 10/11 on google/rambi, verify LPEA drivers load
properly.
Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For some reason, the Windows i2c drivers won't attach without
_HRV (hardware version) defined for the i2c controllers.
Add it, using value taken from Intel baytrail/valleyview edk2
reference code.
TEST=boot Windows 10/11 on google/rambi, verify i2c drivers load
properly.
Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coolstar's Windows drivers don't utilize it, and the Linux drivers
don't care about _STA, so hide it from Windows to tidy up Device
Manager.
Change-Id: I2eb4b3aeed50b9f3ee9f73a57d6585068aa31fbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Change the IRQ triggering from edge to level for cypress touchpad
on peppy variant for compatibility with Windows drivers.
TEST=boot Linux 5.x/6.x, Windows 10/11 on peppy, verify touchpad
functional.
Change-Id: Iecf6cb919bf16ec9180ca050e7eafe55247337ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on drallion, verify touchscreen functional
in OS, dump ACPI and verify only i2c devices actually present on the
board have entries in the SSDT.
Change-Id: I67c3d1fc3d34e9b67ddb26afcaad3a47ffa92e2f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I1bdbf017bc7480f59cec85c70d6e71dac294dcd2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For touchscreens on drallion, drive the enable GPIO high starting in
romstage while holding in reset, then disable the reset GPIO in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens during ACPI SSDT generation (implemented in a subsequent
commit).
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: I6825345f35a7415020e77edf781139f0c9b5f875
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add method variant_romstage_gpio_table() with empty implementation to
be used in a subsequent commit for touchscreen power sequencing.
Call method in romstage to program any GPIOs that may need to be set.
TEST=tested with rest of patch train
Change-Id: I0ad0c18a8b61e59a943a453882bf74762bac4700
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1
as per latest Rex schematics dated 12/06/2022.
TEST=Hardward awaited.
Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides an API to allow users to output multi-line
messages using VGA framebuffer.
The current limitation with multiline message is that,
vga_line_write() function is unable to understand newline character
hence, eventually output multiple lines separated with a newline
character with a single line statement.
This patch ensures to parse the entire string and split it into
multiple lines based on the newline character and print each line
separately to the VFG framebuffer.
User can choose to align the output video message as per given choice
between left/center/right of the screen
(i.e. enum VGA_TEXT_ALIGNMENT ).
Additionally, added macros to define the horizontal screen alignment
as well. Ideally if user would like to print the video message at the
middle of the screen then the vertical alignment would be
`VGA_TEXT_CENTER` and horizontal alignment would be
`VGA_TEXT_HORIZONTAL_MIDDLE`.
TEST=Able to build and boot Google/Taeko.
While output a video message such as :
"Your device is finishing an update. This may take 1-2 minutes.\nPlease
do not turn off your device."
Without this patch:
Your device is finishing an update. This may take 1-2 minutes. nPlease
do not turn off your device.
With this patch:
(in Left Alignment):
Your device is finishing an update. This may take 1-2 minutes.
Please do not turn off your device.
(in Right Alignment):
Your device is finishing an update. This may take 1-2 minutes.
Please do not turn off your device.
(in Center Alignment):
Your device is finishing an update. This may take 1-2 minutes.
Please do not turn off your device.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib837e4deeba9b84038a91c93a68f03cee3474f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Move is_sgx_supported() API to common cpulib code, so that
this function can be used by other code without enabling
SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option.
Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for boards using SOC_INTEL_BRASWELL.
Currently BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is selected for
CPU_INTEL_HASWELL, SOC_INTEL_BRASWELL and others (see [2]). However,
there seems to be no particular reason on those platforms. We've dropped
the config for haswell. Now do the same for SOC_INTEL_BRASWELL, so that
VBOOT_VBNV_FLASH can be enabled.
VBOOT_VBNV_FLASH is enabled for the following boards:
- facebook/fbg1701: A 0x2000 RW_NVRAM region is allocated, with the
FW_MAIN_A(CBFS) size reduced by 0x2000.
- google/cyan, intel/strago: Repurpose RW_UNUSED as RW_NVRAM.
[1] https://issuetracker.google.com/issues/235293589
[2] commit 6c2568f4f5
("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config")
BUG=b:235293589
TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected)
TEST=./util/abuild/abuild -x -t GOOGLE_CYAN -a
TEST=./util/abuild/abuild -x -t INTEL_STRAGO -a
Change-Id: I46542c2887b254f59245f20b8642b023a7871708
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
When VBOOT is enabled, the COREBOOT region (of size 0x09B000) is not
large enough. Therefore, adjust vboot-rw.fmd (which is used only with
VBOOT) layout by moving 0x10000 space from FW_MAIN_A(CBFS) region to
COREBOOT(CBFS) region.
TEST=./util/abuild/abuild -t FACEBOOK_FBG1701 -a (with VBOOT selected)
Change-Id: I1bc0d6981b873ca631cc4cc0720ab212700a65aa
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
There is an ongoing effort to deprecate VBOOT_VBNV_CMOS [1] and replace
with VBOOT_VBNV_FLASH. However, the rambi's CAR is too small for early
flash access in romstage:
/usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd:
Cache as RAM area is too full
/usr/local/google/home/yupingso/projects/coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd:
section .car.mrc_var VMA [00000000fe008000,00000000fe00ffff] overlaps
section .car.data VMA [00000000fe000000,00000000fe008787]
make: *** [src/arch/x86/Makefile.inc:194:
coreboot-builds/GOOGLE_RAMBI/cbfs/fallback/romstage.debug] Error 1
More precisely, DCACHE_RAM_SIZE is 0x8000, and the current .car.data
size is 0x76c0. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is unselected,
then the _bss region will increase by 0x10c8 bytes (for global variables
such as `elog_mirror_buf` and `sfg`), so that .car.data will exceed
0x8000.
Since rambi has reached its AUE (2021-09-01), disable
MAINBOARD_HAS_CHROMEOS and VBOOT configs.
[1] https://issuetracker.google.com/issues/235293589
BUG=b:235293589
TEST=./util/abuild/abuild -t GOOGLE_RAMBI -a
TEST=./util/abuild/abuild -x -t GOOGLE_RAMBI -a
Change-Id: Id56795dd0653784b4d7141142ebef0b19a46ddc3
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71545
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch adds below configuration for MTL-RVP UART devices,
Interface -> UART0
PCI -> 0:0x1e:0
Device -> AP UART
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp ito chromeOS
using subsequent patches in the train. UART logs appear on AP console.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Configure GPIO Tier-1 GPE's that defines the route for GPE
events for MTL-RVP. Configure GPE route as below,
PMC_GPE0_DW0 -> GPP_B
PMC_GPE0_DW1 -> GPP_D
PMC_GPE0_DW2 -> GPP_E
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to ChromeOS
using subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds a new section to the coding style which codifies
existing practices about how to handle errors and how to use the die()
and assert() macros. Also clean up some references to Linux-specific
facilities that do not exist in coreboot in the adjacent function return
type guidelines, and add a small blurb of documentation to the
definition of the assert() macro itself.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ice37ed9f995a56d69476e95a352209041b337284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70775
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Replace the intelblocks/gpio.h and soc/gpio.h includes with the
common gpio.h which will include soc/gpio.h which will include
intelblocks/gpio.h
BUG=b:261778357
TEST=Able to build and boot Google/brya.
Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:252966799
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I15c3eea6ebb7f104bce0ba8cb544ecde7f488343
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add devicetree and GPIO configuration for MTL-RVP
Changes include,
1. Add initial devicetree to support MTL-RVP board & variant
2. Add initial setup for ramstage gpio config
BRANCH=none
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
using subsequent patches in the train.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3173c3f32b36d24467431df3652badd70efeab93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch adds initial bootblock code. This also configures required
GPIOs for early board initialization.
1. Add bootblock file for MTL-RVP
2. Add early gpio config for MTL-P variant in gpio.c
BRANCH=none
BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp platform to
ChromeOS with the subsequent patches in the train
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
On Marasov, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on Marasov.
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.
Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
Change-Id: I4b65b8909c41b06852fe7771375029bd2e76e111
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71263
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch adds ISH ID for ADL-P to ensure dynamic ASL code is
added into SSDT.
With this patch:
Scope (\_SB.PCI0.ISHB)
{
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
}
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48dc6056155824239bb88eda2b0ff5bcd36ced15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71262
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
For marasov, the ISH main firmware will be included in the CSE region in
flash instead of loading it from rootfs. So remove the ISH
firmware-name.
TEST=Boot to OS on Marasov UFS SKUs. Check ISH firmware is not
loaded by kernel, and device still goes to S0i3.
Change-Id: I278e5d403ef9515e538a527f43949e505d750bb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71261
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Replace Divide (a,b,c,d) with:
c = a % b
d = a / b
Change-Id: I0e9fdabbb4b5bd9698968cd8acb497dcde14e433
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71508
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace `Divide (a, b, c, d)` with these instructions:
c = a % b
d = a / b
Change-Id: I44366be5b5145a5d19f85df7a2f338866cb9c8b0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
1. Replace all pcidev_path_on_root() and is_dev_enabled()
functions combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
TEST=Able to build and boot without any regression seen on MTL.
Port of 'commit 50134eccbd ("soc/intel/alderlake: Make use
of is_devfn_enabled() function")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I54bbd2bdba69a19e0559738035916fa7ac60faaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves API "smbios_cpu_get_max_speed_mhz()"
to common code from board specific. This API was made
generic in 'commit d34364bdea ("soc/intel/alderlake:
Utilize `CPU_BCLK_MHZ` over dedicated macro")'
BUG=NONE
TEST=Boot and verified that SMBIOS max speed value is
correct on brya and rex.
(brya) dmidecode -t : "Max Speed: 4400 MHz"
(rex) dmidecode -t : "Max Speed: 3400 MHz"
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I87040ab23319097287e191d7fc9579f16d716e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DPTF functionality for Meteor Lake Rex board.
BUG=b:262498724
TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board.
Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With enabling FSP Notify Phase APIs, it has chance to issue a global
reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY
), which CSE already in idle mode and cause failure. For this reason we
should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select
SOC_INTEL_CSE_SEND_EOP_LATE instead.
BUG=b:261544011
BRANCH=firmware-brya-14505.B
TEST=tested and verified on Marasov, make sure this kind of global
reset can be executed successfully.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Correct DDR4 SPDs from H5AG36EXNDX019 to H5AG36EXNDX017.
DRAM Part Name ID to assign
H5AG36EXNDX017 0 (0000)
BUG=b:236739240
BRANCH=Volteer
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If248714088835eb5dd48fa12223c273199297228
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71160
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kano didn't use SSFC in mass production, however
Zydron needs SSFC for 2rd source mipi instead of fw_config.
BUG=b:262939431
TEST=Boot to OS and check functional with ov2740/hi556 camera.
Change-Id: Idb2a35d67af0b5a7dedc66b0f7eccd8a3b4612d1
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Contents of unsigned AMDFW in RW sections are verified twice in PSP
verstage - first time by vboot verifying the firmware body, second time
by CBFS verification while the file is loaded to update PSP about the
boot region. This redundant verification adds to boot time. Minimize the
redundancy by splitting the EFS header from the AMDFW body and keep them
as 2 separate CBFS files. This helps to improve the boot time by another
25 ms.
BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe boot time
improvement of ~25ms.
Before:
6:end of verified boot 363,676 (16)
11:start of bootblock 641,392 (277,716)
After:
6:end of verified boot 361,655 (16)
11:start of bootblock 616,967 (255,312)
Change-Id: Ib18a4f5c6781e5a7868e9395c0f1212da0823100
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70839
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist
id has the same outcome.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Use get_wifi_sar_fw_config_filename to remove the duplicate code.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Use fw_config field to return sar filename instead of fw_config probe.
Return filename unconditionly because the sar_id must be valid in
CBI. If invalid sar_id, the file won't exist in CBFS by design.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7b75c5d4fd3c459ad7232bb16c6218a6218f1f77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This reverts commit d43154486d.
From CB:68991: This causes CraterLake boot up process to die.
Investigation in progress.
Change-Id: I4a6c11b0e638a891108fe230bdaea92d5fbca020
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: siemens-bot
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens/digitizers.
This removes non-present devices from the SSDT and relieves the OS of
the burden of probing.
BUG=b:121309055
TEST=build/boot Windows/linux on all poppy variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For touchscreens/digitizers on poppy variants, drive the enable
GPIO high and hold in reset in romstage, then release from reset in
ramstage. This will allow coreboot to detect the presence of i2c
touchscreens/digitizers during ACPI SSDT generation (enabled in a
subsequent commit).
TEST=tested with the rest of patch train
Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz
leads to poor signaling. Therefore limit the I2C speed to 100 kHz for
this bus. In addition, add a generic I2C device with 100 kHz bus speed
to the devicetree so that the OS will not switch to higher clock rates,
too.
Test= Measure the I2C signals at coreboot and OS runtime and ensure the
clock is always at 100 kHz.
Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When PTN3460_EARLY_INIT is selected, the PTN3460 (DP-2-LVDS-bridge) will
be initialized before all devices are initialized. This is necessary to
get a valid EDID data set into the PTN3460 before the graphic controller
is initialized in order to be able to show a splash screen.
For ptn3460_init() to work properly the I2C bus this bridge is connected
to needs to be initialized. As this I2C bus initialization would be done
too late in the normal flow, it needs to be called here explicitly
before ptn3460_init() to initialize the I2C bus with the needed
conditions. Otherwise the default I2C settings of the controller will be
used which results in a clock rate too high for this mainboard.
Test=Measure I2C bus signals and make sure that the clock is <= 400 kHz.
Change-Id: I1775fb7c2d29f765224d0e7c7ff9fcd4dbf847c5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71226
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
APs use a lot less stack, so set up a separate stack for those in .bss.
Now that CPU_INFO_V2 is the only code path that is used, there is no
need to align stacks in c_start.S.
Change-Id: I7a681a2e3003da0400843daa5d6d6180d952abf5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On broadwell devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.
Change-Id: If670d548c46834740f4e21bb2361b537807c32bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
On lynxpoint devices, coreboot currently disables and hides the ME PCI
interface by default, without any way to opt out of this behavior.
Add a Kconfig option to allow for leaving the ME PCI interface
enabled, but set the default to disabled as to leave the current
behavior unchanged.
Change-Id: I994cb5b05829eddad2e423a7440a9458f9952370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch drops the SoC specific implementation as DPTF driver can
now fillin those platform specific data using SoC specific macros.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If65976f15374ba2410b537b1646ce466ba02969b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch fills in a generic platform info structure based on the
inputs from the SoC dptf header file (soc/dptf.h).
It will help to make things common and drop unnecessary back and
forth call between common code and SoC code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3521882495485cef686655abd65337515bae5faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71111
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DEVAPC_DEBUG option and set this option to disabled by default.
This option prevents DEVAPC log flooding during the boot process. Enable
this option when we need to debug DEVAPC issues.
TEST=DEVAPC log is disabled by default.
Change-Id: I26bc0378b8a766c6a8cc4903d64a921c3e96b93f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71158
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was
simplified to just `a >> b`.
Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an
internal pull-down, which puts it in a state of contention when the
reset pin is released / set to high. Fix this by changing the reset
GPIO to PAD_CFG_GPO like all other poppy variants use for the
touchscreen reset.
TEST=build/boot nocturne, touchscreen still works.
Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on multiple hatch variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some ELAN touchscreens were missing the entries for the enable GPIO
and associated delays. Add them to variants with ELAN0001 touchscreens
missing the entries.
TEST=tested with rest of patch train
Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
For touchscreens on hatch variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit).
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With xDCI enabled, the right USB-C port does not work for USB data.
Additionally, it was disabled in stock ChromeOS firmware.
TEST=build/boot rammus, confirm right USB-C port works for booting,
under OS in Windows/Linux.
Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on berknip/morphius, verify all
touchpad functions work correctly.
Change-Id: I9d8362719ddbfe523dd83964556b05bb8f1bb1ba
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad
functions work correctly.
Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This should only contain resources that the PCI domain uses. Stolen
memory prevents the PCI domain from allocating anything where it is.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1562396f0b747a81bbc584314956809bd3865ff9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9a4a05f9c764eecaac3d473ba612dca6cc81518f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove Top of Upper Usable DRAM Low from MCHC as it isn't needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifdd8c9ba61c5b1c6b154369413470e431ce8f5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current implementation of the MCRS had several issues with BARs
and MMCONF not being available:
[ 0.156231] pci 0000:00:02.0: BAR 2: assigned to efifb
[ 0.165302] pci 0000:00:18.2: can't claim BAR 0 [mem 0xddffc000-0xddffcfff 64bit]: no compatible bridge window
[ 0.192896] pci 0000:00:18.2: BAR 0: assigned [mem 0x280000000-0x280000fff 64bit]
...
[ 0.138300] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.138300] PCI: not using MMCONFIG
[ 0.148014] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.149674] [Firmware Info]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources
[ 0.149679] PCI: not using MMCONFIG
[ 0.155052] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.
This new MCRS, tested on the Star Lite Mk IV, resolves these issues:
[ 0.158786] pci 0000:00:02.0: BAR 2: assigned to efifb
[ 0.197391] pci 0000:00:1f.1: BAR 0: assigned [mem 0x280000000-0x2800000ff 64bit]
...
[ 0.138460] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.138460] PCI: not using MMCONFIG
[ 0.150889] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem
0xe0000000-0xefffffff] (base 0xe0000000)
[ 0.152548] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib6fc58efc9aadb5828251e0260622dac7ea3ef2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on coral, verify all touchpad
functions work correctly.
Change-Id: I161eb953bf8bceb353cf43803ee948c522928892
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on nami, verify all touchpad
functions work correctly.
Change-Id: I0611da8bbea41565e603a1a1b7cc20226ba21c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on bobba, verify all touchpad
functions work correctly.
Change-Id: I4fd66be21eeff5f37b58a8922c49683a28685064
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on liara, verify all touchpad
functions work correctly.
Change-Id: I89ca02629803882e7ed2048a5a26868fc2de41a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on akemi/kohaku, verify all touchpad
functions work correctly.
Change-Id: Icb552caa69428908e5e3342139b578a145fa2797
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot ChromeOS, Linux 5.1x, Windows 10 on dewatt, verify all
touchpad functions work correctly.
Change-Id: I00efde6f007d57166cd82f76d2f389dedce57466
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=boot Linux 5.1x, Windows 10 on drawcia, verify all touchpad
functions work correctly.
Change-Id: I43eb5bc394a3fbfd4109f2e6c274ec66fc01d46d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows
WHQL validation tests. To ensure compatibility with both Windows and
Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously
done for other boards (eg, google/lulu).
TEST=untested on brya, but tested under Windows/Linux on all other
boards in the tree using Synaptics touchpads.
Change-Id: Ia9351185b918f2d6f2d2be110b88e8310d37a03f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Audio codec RT1011_ALC5682I_I2S is listed as a fw_config option in the
baseboard, but missing from the HDA device probe list in the variant
overridetrees, preventing it from being detected at boot.
TEST=build/boot lindar, verify audio codec identified and HDA device not
disabled by fw_config.
Change-Id: Ib40b095688aac5cf4e0a60dcac250023c4f04c9f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on multiple reef variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I8c90074515b1c7d3ab742768d7bbd904fec256d4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71154
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I1000df10eea5670bf1bc8d04c736150b6a5e26a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For touchscreens on reef variants, drive the enable GPIO high starting
in romstage, then disable the reset GPIO in ramstage. This will allow
coreboot to detect the presence of i2c touchscreens during ACPI SSDT
generation (implemented in a subsequent commit). As the GPIOs are
already correct in ramstage, only the romstage ones need to be set.
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: I10d1789c8de23653bac81e1f9604a47f93fa3f7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: Id3ab412183e5c5d534b2e1dea3222c729c25118b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now that power sequencing has been implemented, switch from using ACPI
"probed" flag to "detect" flag for all i2c touchscreens. This removes
non-present devices from the SSDT and relieves the OS of the burden of
probing.
BUG=b:121309055
TEST=build/boot Windows/linux on multiple volteer variants, verify all
touchscreens functional in OS, dump ACPI and verify only i2c devices
actually present on the board have entries in the SSDT.
Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs themselves are configured as level triggered, and the drivers
(both Linux and Windows) work better with LEVEL vs EDGE triggering.
TEST=tested with rest of patch train
Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For touchscreens on volteer variants, drive the enable GPIO high
starting in romstage, then disable the reset GPIO in ramstage. This will
allow coreboot to detect the presence of i2c touchscreens during ACPI
SSDT generation (implemented in a subsequent commit).
BUG=b:121309055
TEST=tested with rest of patch train
Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add method variant_romstage_gpio_table() with empty weak implementation
to allow variants to override as needed for touchscreen power
sequencing (to be implemented in a subsequent commit). Call method
in romstage to program any GPIOs the variant may need to set.
TEST=tested with rest of patch train
Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the UART port but only enable UART debug for EDK2
debug builds.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Root Complex Event Collector Endpoint Association Extended
Capability is defined in section 7.9.10 of PCIe 5.0 spec.
Add its Extended Capability ID, association bitmap for RCiEPs
register, and RCEC associated bus numbers register.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7bede8ed88304a2925e6e1e4128bcdd625ee0e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Different PCHs have different definitions for registers. Here create
a lbg folder and move lbg specific codes to this folder so that we
can add new PCH code under xeon_sp folder.
* Create lbg folder and move lbg specific codes from pch.c to soc_pch.c
under lbg folder.
* Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg
folder.
* Rename gpio.c to soc_gpio.c and move to lbg folder.
* Move pcr_ids.h to lbg folder.
* Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg
folder.
* Create and revise makefile for files under lbg folder.
TEST=Can boot into OS on OCP Delta Lake.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change provides config for devicetree to control ASPM per port
TEST=Build and Boot verified on google/rex
Port of 'commit 6e52c1da4a ("soc/intel/{adl,common}:
Add ASPM setting in pcie_rp_config)'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I284bf51628193aa5f82f21fbf29c57a6ea5f9cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<commonlib/bsd/compiler.h> is automatically included in all
compilation units by the build system.
(see Documentation/contributing/coding_style.md)
Change-Id: I09ed0c5eb2054c3add026f200c0fd3f609f73197
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67905
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add VPD processing framework to be shared by OCP mainboards:
* define VPD configuration items in vpd.h.
* add helper functions:
** get_bool_from_vpd()
** get_int_from_vpd_range()
Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
For LPC, set BIOS interface lock.
Also set the LPC BIOS control to match the SPI BIOS control settings.
BIOS control EISS and WPD are set when the BOOTMEDIA_SMM_BWP config
option is set.
Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add system agent ID for RPL QDF#Q2MB/Q2PS
TEST=able to build coreboot successfully
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
There seem to be some recurring vague concerns about the alignment of
coreboot table entries. While the existing implementation has been
producing tables with a well-defined alignment (4 bytes) for a long
time, the code doesn't always make it very clear. This patch adds an
explicit constant to codify that alignment, assertions to check it after
each entry, and adds explicit padding to the few entry structures that
were relying on compiler padding to return a correct sizeof() value.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaeef29ef255047a855066469e03b5481812e5975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.
This patch is backported from
commit 8c46232005 (soc/intel/alderlake:
Disable L1 substates for PCIe compliance test mode).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I490a3e8158472fdd3bbc1aec74b2658b0fab56e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71169
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch avoids hardcoding to the `use_eisa_hids` variable instead
relying on the SoC config to choose if the SoC platform supports
EISA HID.
If any SoC platform has the support then the `use_eisa_hids` variable
would be set to `true` based on the selection of `DPTF_USE_EISA_HID`
config.
Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA
IDs. If selected, the 7-character _HIDs will be emitted,
otherwise, it will use the "new" style, which are regular
8-character _HIDs.
Ideally, the platform prior to Tiger Lake would set `use_eisa_hids`
to `true` and platform posts that would set `use_eisa_hids` to
`false`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds config to let SoC users (config) to choose if EISA HID
is supported. All SoC config would like to support EISA HID need to
select `HAVE_DPTF_EISA_HID` config.
Prior to Tiger Lake, all DPTF devices used 7-character EISA
IDs. If selected, the 7-character _HIDs will be emitted,
otherwise, it will use the "new" style, which are regular
8-character _HIDs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bf64f74c447b28665d31a64181c33df882d5d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71108
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Volteer.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I111fa9b2672ad01268bb2620b47a53a7a5b00f3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71107
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibb31ab29c803dde70ef9ccf2b7c7c2ca0845b568
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71106
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Hatch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7a9218a41825d2fa40a1c1b96a333465b7f617c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71105
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Reef.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0ce956351afc06871c465b67f51cba8786ce52db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71104
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ied32eb301b0702ad7cf12b662886c9060415eb72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71103
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds DPTF ACPI Device IDs into the header file (soc/dptf.h)
so that upcoming patches in this patch train can achieve more
common code.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia4c3f1dbca2c0099cbf00137008c1aa1bcb196b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71125
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes the SoC specific callback code more readable by adding
`soc_` prefix into the `get_dptf_platform_info()`.
In nutshell this patch renames `get_dptf_platform_info()` to
`soc_get_dptf_platform_info()`.
TEST=Able to build Google/Rex without any compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
dapc_init flow is the same on MT8186, MT8188 and MT8195. So move this
function to common/devapc.c
TEST=emerge-corsola coreboot; emerge-cherry coreboot;
emerge-geralt coreboot
TEST=devapc log is shown as expected and the system boots to kernel
Change-Id: I979c3a3721a82d40c9e2db7fbe62e14a9bbd53d8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71137
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move a "NOTE" message from BIOS_DEBUG to BIOS_NOTICE log level.
Change-Id: If92c1ccb5b10a4b29a5006a41ebd0855294f354e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69498
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Extend sd_hold to meet touchpad/touchscreen SPEC.
touchscreen:
tHD > 0.2 us
touchpad:
0.3 us < tHD < 0.9 us
After applied the change, the tHD meets reqirement.
touchscreen:
0.056 us -> 0.28 us
touchpad:
0.056 us -> 0.384 us
BUG=b:263340540
TEST=build and measure the timing meet SPEC
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
