- Consistently use the same wording and formatting for all license headers.
- Remove useless whitespace, add missing whitespace, fix indentation.
- Add missing "This file is part of the coreboot project." where needed.
- Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency.
- Add some missing "(C)" strings and copyright years where needed.
- Move random comments and file descriptions out of the license header.
- Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc).
There should be no changes in _content_ of the license headers, if you spot
such changes that's a bug, please report!
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cache_as_ram_auto.c and auto.c are both called "romstage.c" now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's supposed to be a userspace regression test for ram init, but
in fact, it doesn't even execute ram init. This was suggested by
Carl-Daniel on 2009-08-27
Thus, dropping it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
be possible to support i955 and i975 relatively easy, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* drop debug.c files from 945 mainboards (and share it in the northbridge code)
* adapt the mainboard and auto.c files for above changes.
Rather trivial
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
440lx using the 440bx code as a template.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Of course, the user can still override those defaults, if needed.
Add defaults for VIA pc2500e, Kontron 986LCD-M/mITX, MSI MS-6178.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add static and const where possible.
- Turn some #warning entries into TODO comments.
- Add missing prototypes.
- Remove unused variables.
- Fix printf arguments or cast them as needed.
- Make sconfig output look better. Drop useless "PARSED THE TREE" output.
- Print "(this may take a while)" while building romcc. Add missing "\n".
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watosn <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- run ACPI code through preprocessor so we get the same values
as the C code
- fix PCIe x16 slot
- fix ICH7 Azalia/HDA driver
- SMI/GNVS update security fix (only allow struct pointer update once)
- ACPI updates
- IDE driver fixes
- add cmos options for disabling onboard ethernet and controlling system fan
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Change HAVE_FAN_CTL to be specific to the SuperIO that supports it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to build, but by default all the tables that are available are built.
Make PIRQ table build for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Sorry, but I've forgotten where I found them. :\
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
the socket it has, and the CPUs are pulled in automatically. There is
some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
- intel/eagleheights
- intel/jarrell
- intel/mtarvon
- intel/truxton
- intel/xe7501devkit
- sunw/ultra40
- supermicro/h8dme
- tyan/s2850
- tyan/s2875
- via/epia
- via/epia-cn
- via/epia-m
- via/epia-m700
- via/epia-n
- via/pc2500e
(PPC not considered, probably overlooked something)
All of them only _build_, but some options are probably completely
wrong. To be fixed later
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's only three files. Also fix up all the paths (Gotta love included C files)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig_bools.diff: Change some more ints to bools, change some default values.
xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB.
smp.diff: set CONFIG_SMP based on MAX_CPUS.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch tries to improve the pcie portA configuration.
The Matrox G550e PCIe gfx card shipped along with the dev board is supported.
Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only build-tested so far, not tested on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
At the same time also make the 82810 code handle 82810E.
- Set SMRAM register according to CONFIG_VIDEO_MB value:
- 512 means 512 KB
- 1 means 1 MB
- Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA.
This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB
in a future patch may be nicer.
- Set MISSC2 register bits as required per datasheet to make VGA work.
The code handles both 82810 and 82810E.
- northbridge.c: Add __pci_driver entry for the Intel 82810E.
Also:
- Rename PAM register #define to PAMR as per datasheet.
- Drop unused/commented code for now.
- Don't explicitly set GMCHCFG for now, the default works ok. We'll
have to figure out the proper/ideal settings later.
The code is based on a patch from Elia Yehuda <z4ziggy@gmail.com> but
has been modified quite a bit for correctness and minimalism.
Tested on hardware with a slightly modified MS-6178 target,
patches to enable onboard-VGA for MS-6178 will follow.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources
Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.
Domains usually start with base = 0 and limit = 2^address_bits - 1.
I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.
Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, enable HIGH_TABLES support for this board.
The HIGH_TABLES failed with:
No matching ram area found for range:
[0x00000000000f0000, 0x0000000000100000)
Ram areas
[0x0000000000000000, 0x0000000000001000) Reserved
[0x0000000000001000, 0x00000000000a0000) RAM
[0x0000000000100000, 0x000000000fff0000) RAM
[0x000000000fff0000, 0x0000000010000000) Reserved
SELFBOOT RETURNED!
Boot failed.
The fix was to change northbridge.c as follows:
- ram_resource(dev, idx++, 1024, tolmk - 1024);
+ ram_resource(dev, idx++, 768, tolmk - 768);
This is build-tested and tested on hardware by me. It boots fine,
for instace with SeaBIOS and the standard GRUB1 from my disk.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
function based on test results with many different DIMMs.
Tested by Uwe Hermann <uwe@hermann-uwe.de> on hardware.
Might need a small increase of ROM_IMAGE_SIZE for some boards, we'll see.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
3 (with one of them way too much assembler code).
On the way, I had to make some changes to the way the code is built,
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects
lots of post-raminit code (memcpy doesn't really make sense before
raminit, or at least CAR)
The coreboot_apc code (AMD boards) gained some .c includes because I
don't know that part of the code enough to really rework it and only
have limited possibilities to test it. The includes should give an
identical situation for this part of the code.
This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
support for it.
The related mainboards don't need to activate it
themselves anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as "driver" instead of "object" in order to get the init code actually
executed.
This patch fixes up all northbridges that did not do this before.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- lots of PCIe updates
- various bug fixes to early init
- some fixes for typos and warnings
- initial support for PCIe x16
- some minor fixes to memory init code
- some subsystem vendor id patches, to be consistent with ICH7
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(in addition to their low locations)
This adds the kontron 986LCD-M and the i945 as a sample.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
almost three years. Let's put it somewher so people find it if they're looking
for it. Someone dare sending a late announcement to the coreboot-announce list?
:-)
Add (preliminary) support for Intel 855GME (Mobile version of the 855) chipset
to coreboot.
There are some holes in the code to be filled out, but unlike the code for the
855pm this has booted a mainboard before.
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is tested on hardware with four 128MB DIMMs and works ok, _iff_
you also fix additional registers (e.g. DRB, RPS, ...) for your setup.
This requirement will be eliminated in another upcoming patch (i.e. all
of the required settings will be auto-detected).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
memory controller.
Also, drop some unused '#if 0' code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as well as most (all?) combinations thereof.
Drop some unused code, the unused row_offset variable, and obsolete comments.
Also, fix a typo (thanks to Stefan Reinauer for noticing).
This is tested on the MSI MS-6178 with a number of different DIMM
combinations and so far all of them worked fine.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.
This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.
Build-tested with all three boards using the Intel 810 chipset.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
values for different DIMM configurations. This should be converted to a
table or code later on and actually be used for BUFF_SC.
Many thanks to Elia Yehuda <z4ziggy@gmail.com> for testing and collecting
the table entries.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, add missing C1DRA2 #define (as per public datasheet).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Build-tested with the kontron/986lcd-m target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
lib/debug.c and use that one.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
A trivial fix to correct the address of the high byte in SDRAMC.
Thus the leadoff timing IPDLT will be correctly referenced.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
EP80579 Integrated Processor (codename "Tolapai"). The memory
controller code supports only 64-bit-wide DIMMs with x8 devices and
ECC. It has been tested on a development board using a single Micron
MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
DIMMs.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100
raminit code.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and renames some existing macros for clarity.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
northbridge and RAM controller.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is generic PCI stuff, not nothbridge-specific in any way.
The respective #defines are already present in src/include/device/pci_def.h.
Abuild-tested, so shouldn't break anything.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the system boot to a command line.
This patch comments out the code to set up the vga framebuffer to allow
the system to boot, without this fix the system hangs during elfboot.
The only line that is absolutely necessary to change is the SMRAM setup,
however I've commented out all vga setup to make it very obvious to both
the kernel/payload and anyone looking at the code that vga isn't
currently working. This setup might also be better handled in
northbridge.c, if it doesn't need to be done before ram init, yet
another reason to comment it all. In the future, LinuxBIOS needs to be
told that the graphics memory area, 1mb or 512kb (at the user or
developer's option), is reserved for the onchip vga, but I'm not sure if
it's taken at the top or bottom of the memory, yet. LB may also need to
set a base address for the AGP aperture and/or be told that range is
reserved as well, whether this was originally the job of the system bios
or vga bios is still a mystery. It also corrects the number of entries
in irq_tables.c, without this fix the kernel would probably complain and
hang due to unmapped IRQs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Still hardcoded for Tyan S1846.
This slightly increases performance, but it's still pretty horrible.
Some RAM settings are causing a dramatically slow system (confirmed
by comparing memtest performance results of the proprietary BIOS
and our code). Haven't found the problem, yet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).
All other delays are so low that we get away with just waiting 1us.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
available on all boards, regardless of what DIMMs you use.
Tested on the Tyan S1846, works fine.
- Properly set the PAM registers to allow the region from 768 KB - 1 MB
to be used as normal RAM (required for the above).
- Document all of this properly. Add/improve other documentation, too.
- Simplify and document code in northbridge.c.
- Cosmetics and coding style.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB.
Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com>
Signed-off-by: Roger Zauner <roger@eskimo.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This does _not_ fully work, yet. You will _not_ be able to boot any
payload with this code, yet.
Add missing license headers.
Base the northbridge.c file on the Intel 855PM version, that comes
closer to what we want.
The raminit.c file is written from scratch and hardcodes several
values for now. This needs to be fixed later by reading the
correct values via SPD.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Added information on the relevant datasheet(s) and where to get them.
* Added missing #defines for some other config bytes.
* Documented all config bytes a bit better.
* Renamed some #defines to hopefully make their names clearer.
(closes#38)
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Intel 440BX northbridge (Closes#39).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Richard Smith <smithbone@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same format for all CHIP_NAME() entries in LinuxBIOS (Closes#20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
will then rename the E7520 and E7525 directories respectively.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
here's a patch which replaces all DOS newlines with Unix newlines, and
removes some useless $Rev$, $Id$, and $Header$ tags.
(part 1)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- New superIO winbond/w83977tf
- Add single memory controller SBbus debug routine
into a file private to the i440bx
This adds support the start of support for an Asus p2b
mainboard. Current limitations are the same as for the
Bitworks IMS board. Reads from the SMbus don't work.
Moving dump_spd_registers() into its own private copy
solves the problem of having to go hack on the version that
included in src/sdram to only do one memory controller.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
add support for NSC pc87351 SuperIO
add Bitworks/IMS manboard config
This is a very basic framework for the i440bx chipset and the
Bitworks IMS board that uses it. Most things are
structure only.
Known issues:
- SMbus reads to the RAM SPD come back
all zero.
- dump_spd_registers() is commented out since it breaks with
the default setting of generic_dump_spd.c where it wants
2 memory controllers.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Added code to support remap window for 3 - 4 GB systems
* Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html).
* Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted.
* Disabled subsystem (vendor) ID configuration
* #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html)
* Added optional run-time checking of dual-channel compatibility of installed DIMMs
* Move JEDEC SPD and SDRAM definitions into reusable #include files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
cache_as_ram for AMD and some intel
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Set adl855pc ROM_SIZE to 1M
Other minor debug prints until we get this fixed.
We're almost as far along as we were before the Change :-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
