It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In general, third party code (such as vboot) doesn't know what the
underlying types are for the integers in <stdint.h>, so these macros are
useful for portably printing them. Of these definitions, coreboot so far
has only used PRIu64 (in one place), which isn't needed anymore since we
know what the underlying type of a u64 is.
Change-Id: I9e3a300f9b1c38e4831b030ff8af3fed2fa60f14
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The <inttypes.h> header currently does nothing but include the
definitions from <stdint.h>, so let's #include that directly instead.
Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change-Id: Id8fa880357124b620bde8884949bd8ffff7d0762
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add explicit CBMEM_STAGE_CACHE option. Rename
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to TSEG_STAGE_CACHE.
Platforms with SMM_TSEG=y always need to implement
stage_cache_external_region(). It is allowed to return with a
region of size 0 to effectively disable the cache.
There are no provisions in Kconfig to degrade from
TSEG_STAGE_CACHE to CBMEM_STAGE_CACHE.
As a security measure CBMEM_STAGE_CACHE default is changed to
disabled. AGESA platforms without TSEG will experience slower
S3 resume speed unless they explicitly select the option.
Change-Id: Ibbdc701ea85b5a3208ca4e98c428b05b6d4e5340
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sometimes the display native orientation does not match the device
default orientation. We add a parameter to be passed to libpayload,
which can then do the rotation.
BUG=b:132049716
TEST=Boot krane, see that FW screen is orientation properly.
Change-Id: I5e1d94b973a3f615b73eebe0ca1202ba03731844
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It fails if you call extract() when ramdisk is present but initrd
size is 0. This CL adds if-statement to throw an error when initrd
size is 0.
Change-Id: I85aa33d2c2846b6b3a58df834dda18c47433257d
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a new bootmem memory type OpenSBI.
It's similar to BL31 on aarch64.
Required for OpenSBI integration.
Change-Id: I5ceafd5a295f4284e99e12f7ea2aa4c6d1dbb188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This reverts commit 598af2e2c2.
Reason for revert: This commit breaks every board with VBOOT enabled
if the platform is apollolake, broadwell, skylake, baswell, baytrails
or icelake. The reason is, that the SoC selects
VBOOT_MUST_REQUEST_DISPLAY by default, and this has a dependency now
on VBOOT_MAY_SKIP_DISPLAY_INIT. This will only be auto-selected if
it is a CHROMEOS platform.
Change-Id: I3872d9aa993326ded135d8a5d950d5b1b1eddf34
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34308
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move armv7 RAM dection to a common place
* Enable it for all emulated platforms
* Use 32bit probe values and restore memory even on failure
* Use the new logic on the following boards:
** qemu-armv7
** qemu-riscv
Tested on qemu-system-riscv:
Fixes kernel panic due to wrong memory limits reported.
Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I5aa3bb2c72dcf127d418c989f6b63c9b1f412f08
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
So far the bootsplash is only correctly rendered if the framebuffer is
set up as 1024x768@16.
Different resolutions did not show anything, differnent depth resulted
in the distorted images.
This commit removes this limit by using the actual framebuffer resolutions
and combines the code for x86 and yabel.
For the moment the bootsplash is still limited to VGA-OptionROM
framebuffer init.
It was tested in 1280x1024@32 on the wip razer blade stealth using the
intel vgabios.
Change-Id: I5ab7b8a0f28badaa16e25dbe807158870d06e26a
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34537
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
vboot_handoff is no longer used in coreboot, and is not
needed in CBMEM or cbtable.
BUG=b:124141368, b:124192753
TEST=make clean && make runtests
BRANCH=none
Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implicit fall throughs are a perpetual source of bugs and Coverity Scan
issues, so let's squash them once and for all. GCC can flag implicit fall
throughs using the -Wimplicit-fallthrough warning, and this should
ensure no more enter the code base. However, many fall throughs are
intentional, and we can use the following comment style to have GCC
suppress the warning.
switch (x) {
case 1:
y += 1;
/* fall through */
case 2:
y += 2;
/* fall through - but this time with an explanation */
default:
y += 3;
}
This patch adds comments for all remaining intentional fall throughs,
and tweaks some existing fall through comments to fit the syntax that
GCC expects.
Change-Id: I1d75637a434a955a58d166ad203e49620d7395ed
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This CL allows that everyone can use main() in lib/bootblock.c
even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main
functions used in some soc/ to avoid the collision with the
main function defined at lib/bootblock.c.
Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:32870 changed FIT loading code to make an FDT mandatory (because the
platforms that can use FIT images always need an FDT). Remove one
left-over conditional that is now dead code.
Found by Coverity.
Change-Id: Ia7765d45f068ab4bdc720ea7ae87dcc62a4b7d3d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
No reason why the files could not be used with ASEG.
Attempts to use malloc() from ASEG would still fail,
though, due the lack of heap.
Change-Id: Idf470ae84eb34c442e833925510b08d5314e7638
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34126
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After platforms have moved to POSTCAR_STAGE=y the only
remaining user is binaryPI now. Make it simpler.
Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This config option, when set, will allow the platform to skip display
initialization in normal (non-developer, non-recovery) mode. This allows
platforms that do not implement firmware UI in normal mode to skip the
display init in firmware.
TEST=Set option CONFIG_VBOOT and clear CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT
and the display should initialize in ramstage when platform boots. Set
CONFIG_VBOOT and set CONFIG_VBOOT_MAY_SKIP_DISPLAY_INIT and the display
initialization should be skipped in coreboot.
Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar@intel.com>
Change-Id: Icadad6da34dcb817af02868e89a94ea62dbfa7b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
We want to catch warnings as early as possible.
Change-Id: Ifdb2ff8f7973d557a437ac127e073306f76ca6f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33848
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sometimes coreboot needs to compile external code (e.g.
vboot_reference) using its own set of system header files. When
these headers don't line up with C Standard Library, it causes
problems.
Create ctype.h header file. Relocate ctype.h functions from
string.h into ctype.h. Update source files which call ctype.h
functions accordingly.
Note that ctype.h still lacks five functions which are not used
in coreboot source:
isalnum, isalpha, iscntrl, isgraph, ispunct
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I31b5e8af49956ec024a392a73c3c9024b9a9c194
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
This code was copied from depthcharge which uses C99 comment style, but
coreboot uses C89 comment style. Update to match coreboot.
Change-Id: Ib67bb9ff17b7688826071453ab58894a0835ce10
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32875
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The compat string matching code was mostly copied from depthcharge. One
of the few differences is that we now store the list of compat strings
we're willing to match in a list rather than an array. Since our lists
insert at the front, that means the strings are now ordered lowest to
highest (not highest to lowest like in depthcharge).
We did rewrite the compat_rank matching code to accomodate for that...
however, what we didn't do is remove the break-statement in the loop
that matches all compat strings. When we search the lowest priority
first, we can't abort the search as soon as we found a match -- we have
to keep looking because we might find a higher priority match later.
This patch fixes the issue so that my Kevin can actually match for
google,kevin-rev5 (and doesn't just jump at the first best google,kevin
match).
Change-Id: Ibe3d84bbce6de3cd49c746a667ae1ccfdc843105
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32874
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to boot FIT image configurations consisting of
a base device tree and one or more overlays. Since extracting the right
compatible string from overlay FDTs is problematic, we'll only support
this for FIT images that have the compatible string pulled out into the
config node.
This patch was adapted from depthcharge's http://crosreview.com/1555293
Change-Id: I0943f9a1869c9e416887c7ff16e33f7d91b74989
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32873
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for compressing individual device trees in the
FIT image. In order to make this efficient, we'll have to pull the
compatible property out of the FDT and store it directly in the config
node of the FIT image, so that we don't have to scan (and therefore
decompress) every single FDT on boot. Device tree compression is only
supported for FIT images that have this external compatible property.
For older images with no compression, we still support fallback to
scanning the FDT for the property.
This patch was adapted from depthcharge's http://crosreview.com/1553458
Change-Id: Ifcb6997782c480c8ef6692df17b66ad96264e623
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32872
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kernel handoff on all architectures supporting FIT images already
includes flushing and disabling the cache. No need to waste any more
time flushing individual components (especially since in the case of
compressed DT overlays they will still get accessed again afterwards).
Change-Id: I7b483e920c5a71663b024b5b50804ffc84939830
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32871
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes some minor refactoring to the way the FIT parser
handles config nodes. A lot of this code was written in the dawn age of
depthcharge when its device tree library wasn't as well-stocked yet, so
some of it can be rewritten nicer with more high-level primitives.
There's no point in storing both the string name and the actual FDT node
of a FIT image node separately, since the latter also contains the
former, so remove that. Also eliminate code for the case of not having
an FDT (which makes no sense), and move some more FDT validity/compat
checking into fit_update_compat() (mostly in anticipation of later
changes).
This patch was adapted from depthcharge's http://crosreview.com/1553456
with a couple of modifications specific to coreboot's custom FIT loading
code.
Change-Id: Ia79e0fd0e1159c4aca64c453b82a0379b133350d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32870
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for merging a device tree overlay (as defined in
Documentation/dt-object-internal.txt in the dtc repository) into a base
device tree. It was adapted from depthcharge's
http://crosreview.com/1536387.
Change-Id: Ibec833cd471201bcc7a79eebf360d5f12adb8ff9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32869
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Free the tree before returning to prevent a leak.
Change-Id: I1132c0e7404eec1af3adc19a83257f28563f8a58
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401799
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
hexdump() is not available in postcar stage.
Add hexdump() functionality to postcar stage.
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Change-Id: Ibdce911065c01b0a1aa81dc248557257d0e420b0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
FDT property data should not be const -- sometimes we need to update it,
for example when fixing up phandles in an overlay. On the other hand
it's occasionally desirable to put a string constant in there without
having to strdup() it all the time... let's just live with the tiny
implicit assumption that the data we'd want to modify (phandle
references, mostly) will never be added from string constants, and put a
cast in dt_add_string_prop().
Change-Id: Ifac103fcff0520cc427ab9a2aa141c65e12507ac
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32868
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the device tree dumping functions (not compiled by
default but available for debugging) to output properties and nodes in a
format similar to .dts files that is very close to what dtc outputs when
you decompile a .dtb with it. This makes it easier to match device tree
dumps from coreboot with device tree dumps generated by other device
tree tooling.
This patch was adapted from depthcharge's http://crosreview.com/1536386
Change-Id: Ib40e50d906aff05473a70c4fc9b124d63232558c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32867
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support to lookup nodes via the "/aliases" mechanism in
device trees. This may be required for overlay support (don't quite
remember tbh) and is also just a generally useful feature. It was
adapted from depthcharge's http://crosreview.com/1249703 and
http://crosreview.com/1542702.
Change-Id: I1289ab2f02c4877a2d0111040384827e2b48a34a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32866
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently DT paths are *not* expected to start with '/'. This is not
what the spec says (see Devicetree Specification v0.2, 2.2.3 Path Names)
and also not what is done by Linux.
Change dt_find_node_by_path() to expect paths to start with '/' and add
a leading '/' to all DT path strings. Besides the compatibility with the
spec this change is also needed to support aliases in the future.
This patch was adapted from depthcharge's http://crosreview.com/1252770
Change-Id: Ibdf59ccbb4ead38c6193b630642fd1f1e847dd89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32865
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Besides looking up a node with an absolute path dt_find_node_by_path()
currently also supports finding a sub-node of a non-root node. All
callers of the function pass the root node though, so it seems there
is no real need for this functionality. Also it is planned to support
DT path names with aliases, which would become messy in combination with
the lookup from a sub-node.
Change the interface of dt_find_node_by_path() to receive the DT tree
object instead of a parent node and adapt all callers accordingly.
This patch was adapted from depthcharge's http://crosreview.com/1252769
Change-Id: Iff56be4da2461ae73a7301dcaa315758d2a8c999
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch caches phandles when unflattening the device tree, so we
don't have to look up the phandle property again every time we're trying
to find the phandle of a node. This is especially important when
supporting phandle lookups, which are also added. In addition we keep
track of the highest phandle in the whole tree, which will be important
for applying overlays later.
With this, dt_get_phandle(node) becomes obsolete because the phandle is
already available as a member variable in the node.
This patch was adapted from depthcharge's http://crosreview.com/1536385
Change-Id: I9cbd67d1d13e57c25d068b3db18bb75c709d7ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32863
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a few more sanity checks to the FDT header parsing to
make sure that our code can support the version that is passed in.
This patch was adapted from depthcharge's http://crosreview.com/1536384
Change-Id: I06c112f540213c8db7c2455c2e8a4e8e4f337b78
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32862
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FIT code is already using xzalloc() everywhere, and that's the only
real consumer of device tree code right now. Chances are if you're
trying to unflatten an FDT and it doesn't fit into the heap you're
pretty much screwed anyway, so all the OOM handling feels a bit
unnecessary (and some functions will just silently fail because they
don't have a return value, which is bad). Let's just switch this all to
die on failed allocations.
Change-Id: I738f24d550a776653b2becd3d4f7d4d2cb3cc048
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32861
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no clear reason why most of coreboot's basic string functions
are static inline. These functions don't particularly benefit from
inlining (at least not notably more than other functions). This patch
moves them to string.c to be more consistent with our usual coding
practices.
Leaving the ctype functions as static inline because they actually seem
small and collapsible enough that inlining seems reasonable.
Also clarified the situation of strdup() and strconcat() a bit more,
optimized strrchr() to be single-pass, fixed a bug with using strchr()
to find '\0' and got rid of unnecessary register keywords.
Change-Id: I88166ba9876e94dfa3cfc06969c78a9e1bc6fc36
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Also adapt all users of these symbols
Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Pass the return value from early_mmc_wake_hw() to the payload so that
payload can skip sending CMD0 and resetting the card in case of success
or in case of a failure in firmware, payload can recover by sending
CMD0 and resetting the card.
BUG=b:78106689
TEST=Boot to OS
Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CMOS isn't used that early, but the chipset initialization may be
required to access it.
In one instance, Intel Apollo Lake, the sanitize_cmos() function
seems to hang if called before bootblock_soc_early_init(). The
missing step is fast_spi_early_init(). But even without, one might
expect sanitize_cmos() to return eventually (it didn't within
about 20min).
Change-Id: I6e1a029e4be7e109be43a3dad944bd7e05ea1f02
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
This patch rewrites some of the device tree code to use the new
be32dec/be32enc helpers where they can make the code cleaner.
Change-Id: I437bbd6645a556ae9a0cfe6ea14638098e4c3606
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32860
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some cases we may have boards that need to differentiate SKUs but
don't really want to differentiate revisions (at least for some SKUs).
Let's add a compatible string match that includes only the SKU but not
the revision so that kernel DTSes don't have to specify every possible
revision if they want to match this.
This patch was adapted from depthcharge's http://crosreview.com/1512004
Change-Id: Ib88862424b350a213761f5662fe170a1f8fccc7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32859
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new post code, POST_INVALID_ROM, used when coreboot fails to
locate or validate a resource that is stored in ROM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
With CB:32726 ("lib/timestamp: Make timestamp_sync_cache_to_cbmem() in
postcar") timestamps are synced from cache to cbmem in postcar as
well. For postcar, the cache lives in BSS just like ramstage. This
change updates TIMESTAMP_CACHE_IN_BSS to include both ramstage and
postcar and uses this instead of ENV_RAMSTAGE to check for cache
location.
Ideally, it would be good to get rid of timestamp cache in postcar and
ramstage completely since early cbmem init is enabled by default in
coreboot and it is guaranteed that cbmem is recovered before
timestamps are added in ramstage or postcar. This change is being
pushed in as a temporary fix while I make the changes to remove
timestamp cache from romstage and postcar completely.
BUG=b:132939309
Change-Id: I2d82a96aba954df77c9386b7bd2e2ec0973881be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch ensures to have correct timestamp value in postcar.
Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The name OPROM is somewhat inaccurate, since other steps to bring
up display and graphics are needed depending on mainboard/SoC.
This patch cleans up OPROM code nomenclature, and works towards
the goal of deprecating vboot1:
* Rename CONFIG_VBOOT_OPROM_MATTERS to
CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig
description
* Remove function vboot_handoff_skip_display_init
* Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY
* Add |flags| field to vboot_working_data struct
* Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff
BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
TEST=build and flash eve device; attempt loading dev/rec modes
BRANCH=none
Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7669b8dc07b1aa5f00e7d8d0b1305b3de6c5949c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Skipping display init on normal-mode boot is a vboot feature, not
specific to Chrome OS. Fix the code in display_init_required() and
pci_dev_init() to check CONFIG_VBOOT rather than CONFIG_CHROMEOS now
that the two aren't always the same anymore.
Also add a check to guarantee at compile time that
CONFIG_VBOOT_OPROM_MATTERS is enabled on all platforms that make a check
to this function (when CONFIG_VBOOT is also enabled). The whole display
skipping mechanism is based on the oprom_needed NVRAM flag, and skipping
display init without enabling the option to tell vboot that it needs to
pay attention to that flag would make the whole thing not work right.
Change-Id: I5d6421509bdcdaa61b78015af3fa6241fe75bb7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was flagged as CID 1229647 (MISSING_BREAK). It was
originally fixed in e211bd9, but then reverted in 1c8ee21.
Hopefully fix it for good now.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib25b07b633ed02c466391050df15eaf9c36a3199
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Failure to find an edid or header is more serious than the spew
log level and should be an error.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I660218f8b5f5e7f0b01daef0739db79418941515
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32084
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The edid variable was being dereferenced before the null check. Split
off the null check to before dumping and update the error message.
Fixes CID 1370576 (REVERSE_INULL)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I8fe3d911df3a11a873056d3a5c05c5a3cbcfe2c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Create a new cbtable entry called VBOOT_WORKBUF for
storing a pointer to the vboot workbuf within the
vboot_working_data structure.
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none
Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds timestamp for "end of romstage" with postcar if platform
has selected postcar as dedicated stage.
If postcar stage doesn't exist then "end of romstage" timestamp will get
call while starting of ramstage as exist today.
TEST=It's been observed that "end of romstage" timestamp doesn't appear
in "cbmem -t" log when ramstage is not getting executed. As part of this fix
"end of romstage" timestamp is showing in "cbmem -t" log on Intel platform
where POSTCAR is a dedicated stage.
Change-Id: I17fd89296354b66a5538f85737c79145232593d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds dedicated timestamp value for postcar stage.
TEST=Able to see "start of postcar" and "end of postcar" timestamp
while executing cbmem -t after booting to chrome console.
> cbmem -t
951:returning from FspMemoryInit 20,485,324 (20,103,067)
4:end of romstage 20,559,235 (73,910)
100:start of postcar 20,560,266 (1,031)
101:end of postcar 20,570,038 (9,772)
Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Qemu does not have a real CAR but postcar stage is still useful
for testing the stage.
The postcar stage is also mandatory for x86_64 to setup
pagetables for x86_64 ramstage.
Do not set up MTRRs, as qemu ignores them anyways.
Tested on qemu-i440fx and qemu-q35.
Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function appeared previously unused (called only from rtc_display, also unused),
but it returned an incorrect weekday. Change the algorithm to use Zeller's Rule, a
well-known algorithm for calculuating weekdays.
Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Old location caused spurious error messages when
called from APs, where timestamp_add_now() should
do nothing.
Moving the test also makes get_us_from_boot() usable
from APs (assuming cache coherency).
Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31524
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
We generate a $(obj)/cb-config.ads once and copy it per stage that uses
it to $(obj)/<stage>/cb-config.ads (to simplify the gnat-bind step). The
Ada package is called `CB.Config`. As there was no `CB` package yet, add
that too.
Change-Id: I963a6517ef4bcf84f2c8e9ae8d24a0d6b971d2b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
After CL:31122, we can finally define a memory type specific for BL31,
to make sure BL31 is not loaded on other reserved area.
Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move functions not available in PRE_RAM into seperate file.
Makes it easier to share code between rom and ramstage.
Change-Id: I0b9833fbf6742d110ee4bfc00cd650f219aebb2c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently, selflock_check() verifies that the binary is loaded in an
usable RAM area.
Extend its functionality so we can also check that BL31 is loaded in
a manually reserved area, and fail early if the range is not protected.
Change-Id: Iecdeedd9e8da67f73ac47d2a82e85b306469a626
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add API that should be implemented by the boot media drivers
for write-protecting a subregion.
Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/28724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
```
if (!(a & (0xffff << 16))) {
^~
src/lib/libgcc.c:40:18: error: result of '255 << 24' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]
if (!(a & (0xff << 24))) {
^~
src/lib/libgcc.c:45:17: error: result of '15 << 28' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=]
if (!(a & (0xf << 28))) {
^~
```
Change-Id: I7bdd75c20a76b303743d7e7e0d3a6503760284fd
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/23361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Use of device_t is deprecated.
Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30047
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all cases in code where we tested for
EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set.
This also removes all references to LATE_CBMEM_INIT
in comments.
Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26827
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_MAINBOARD_PART_NUMBER sometimes contains spaces, but spaces
inside compat strings aren't nice, so let's convert all spaces to
dashes.
Change-Id: I46f2b2d7091782e04df5476e50698001511f664b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It's more theoretical, but lest somebody calls extract_string()
with too large a length...
Change-Id: I3934bd6965318cdffe5c636b01b3e0c4426e8d1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #1374795
Reviewed-on: https://review.coreboot.org/28659
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that bounce buffers are gone, and we can elide the selfload checking
code at build time, it is safe to add selfboot to the romstage.
Make it so.
This required a few other tweaks to rules.h and selfboot.c
to make it buildon ARM.
Change-Id: Ib6540921ad7cd7d58bfeab881d3978325b303cc2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/29338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The selfboot function was changed at some point to take a parameter
which meant "check the allocated descriptors to see if they target
regions of real memory."
The region check had to be buried deep in the last step of loading since
that is where those descriptors were created and used.
An issue with the use of the parameter was that it was not possible
for compilers to easily divine whether the check code was used,
and it was hence possible for the code, and its dependencies, to be
compiled in even if never used (which caused problems for the
rampayload code).
Now that bounce buffers are gone, we can hoist the check code
to the outermost level. Further, by creating a selfload_check
and selfload function, we can make it easy for compilers
to discard unused code: if selfload_check is never called, all
the code it uses can be discarded too.
Change-Id: Id5b3f450fd18480d54ffb6e395429fba71edcd77
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/29259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
board_reset() replaces the existing common reset API. There is no common
distinction between reset types across platforms, hence, common code
could never decide which one to call.
Currently only hard_reset() is used by common code. We replace these
calls and provide a fall-back to the current hard_reset() implemen-
tation. The fall-back will be removed along with hard_reset() after the
transition of all boards.
Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since `#if 1` is rather useless, and the code inside it is just several
`printk(BIOS_SPEW)`, using `if (console_log_level(BIOS_SPEW))` instead
seems more reasonable.
Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace
current users with the macro.
Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Coverity CID 1395334: (BAD_SHIFT) - In function _gpio_base3_value(), if
gpio_num is 32 and gpio[31] is floating, the end result is 1 << 32, which
does not fit into a int. To avoid a possible error, make it an error to have
num_gpio > 31. Function _gpio_base2_value also have the same issue, but the
limit would be 32. As in practice it'll never be used with more than 20 GPIO,
create a helper function to limit it to 31 and call it everywhere needed.
BUG=b:113788440
TEST=Add a fake code to southbridge_final calling the function and printing
the result. Build and boot grunt, check result.
Change-Id: I0b79725bcbaf120587c7440e176643aaa7a1d5bb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28445
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return
of an undefined value, as no for loop will be executed. Assert that it's
not 0.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Set NHLT version with get_acpi_revision(NHLT) to keep all table versions
in sync.
Change-Id: I4ea9d511142e4ea68e651e58c2c985e739c032d9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28279
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add const quailifier to arguments and elements.
* Add casts where necessary in cn81xx/soc.
Tested on Cavium CN81xx EVB SFF.
Change-Id: Id27966427fb97457fe883be32685d1397fb0781f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy code of depthcharge boot/coreboot.c and adapt it.
Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable
and prints the log.
Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Within procedure LzmaDecode(), the variable len can be assigned a value
that is never read after, thus causing a static analysis error. Tell the
coreboot scan-build static analysis we know it can happen.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I37bc3ff19ca85f819ba1cbb2a281c1ad55619da9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There is a confusingly named section in cbmem called vdat.
This section holds a data structure called chromeos_acpi_t,
which exposes some system information to the Chrome OS
userland utility crossystem.
Within the chromeos_acpi_t structure, there is a member
called vdat. This (currently) holds a VbSharedDataHeader.
Rename the outer vdat to chromeos_acpi to make its purpose
clear, and prevent the bizarreness of being able to access
vdat->vdat.
Additionally, disallow external references to the
chromeos_acpi data structure in gnvs.c.
BUG=b:112288216
TEST=emerge-eve coreboot, run on eve
CQ-DEPEND=CL:1164722
Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/27888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store initrd offset as 64bit integer.
Tested on Cavium CN81XX EVB: The initrd could be loaded when placed
above 4GiB. Previously it failed to find the initrd.
Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Set payload to NULL in case of decompression errors.
Fixes the attempt to boot a kernel that couldn't be decompressed.
Change-Id: I3a602b0e90923a0b5a3683c4a0adf9e4733d5a2a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Within procedure cea_hdmi_block, the variable "b" is used as an index into
a buffer of EDID bytes. At the end, it's incremented but not used, thus
causing a static analysis error. Add a "(void)b;" at the end to avoid the
static analysis error.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: Ibd0b4a21bf82fcc46a627bc75564a850b7374989
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27929
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The variable "begin" is extracted from the structure, but 4 lines below
it's overwritten with "end - size". This causes a static build scan error
that should be fixed. Remove the initial assignment of variable "begin".
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I0a265747e61289f045c5cac09e40478bd31e16fc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27886
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the return type of gpio_base2_value() and related
functions from int to uint32_t. This makes more sense now that
board_id() and related functions (which are the primary use case) also
return that type. It's unlikely that we'll ever read a strapping of 32
GPIOs in a row, but if we did, we'd probably want to treat it as
unsigned.
Change-Id: I8fb7e3a7c76cb886aed40d0ada1f545180e43117
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The write_tables function was void. It is a bit more
useful for loading payloads from the romstage
if it returns a pointer to the table it creates.
Change-Id: I6eeaf3e16bcbaf1e7ec3eada8026c466d2fb6f5a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27537
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Will be used on Cavium SoC to delete devicetree entries that aren't
available with the board/configuration.
Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled.
Make use of cbfs_locate_file_in_region() and always search the
cmos_layout.bin in the 'COREBOOT' region.
With this change applied there's no need to include the vboot_locator
in SMM any more, we can't break NVRAM with different CMOS layouts,
and we keep VBOOT and non VBOOT behaviour the same.
Only include cmos_layout.bin and cmos.default in RO region.
Add notes explaining the decisions.
Tested on Intel Sandybridge, builds and boots with vboot enabled.
Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't consume CBMEM for stage cache when we would
never use it.
Change-Id: I606e0457ff3085822554c4041fc56f0d28cc9c2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set the payload argument in selfload, as other (non self) payloads, are
going to set a different argument.
Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a method to retrieve a node's phandle.
Useful for board specific devicetree manipulations.
Change-Id: I966151ad7e82fc678ab4f56cf9b5868ef39398e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Fix regression (supposedly) after commit:
23d62dd lib/bootmem: Add more bootmem tags
Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite
memory regions of the running ramstage. This case is handled
gracefully via a bounce-buffer implementation in arch/x86/boot.c.
Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Making exceptions for some payload to be loaded near
and under 1 MiB boundary sounds like a legacy 16-bit
x86 BIOS thing we generally do not want under lib/.
Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If we have POSTCAR_STAGE there is no need for
romstage to include LZMA decompression code.
Reduces romstage by about 4 kiB on x86.
Change-Id: I4c475986b2a94e5cd540c3eead433ed6c0a815ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It turns out that even with the `-gnatp` switch to suppress runtime
checks, the compiler is still allowed to generate them (it only doesn't
have to). If we can't control generation of checks, we also can't
make assumptions about propagation of their exceptions.
The compiler warning that led to this change seems spurious, though
(the check might be generated, but is dropped later). So we might
revert this decision if the compiler can be fixed.
Change-Id: I7470d74b1f96f90d0d15b24dfd636d5f1c778d46
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Store the type of the loaded program after locating the file and add a
method to retrieve the type.
Will be used to distinguish between SELF and FIT payloads.
Change-Id: Ic226e7e028d722ab9e3c6f7f1c22bde2a1cd8a85
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26028
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I'm increasing the max because when AGESA tracing is enabled it will use
over 120 entries. I added some padding to the number incase more probes
are added. This only affects ramstage so the extra ram shouldn't matter.
BUG=b:64549506
TEST=boot on grunt and ran cbmem -t
Change-Id: I7a3d2d09c91c9e302d139e7f65fa9c85c4594de4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The patch series ending in 64049be (lib/bootmem: Add method to walk OS
POV memory tables) expanded the bootmem framework to also keep track of
memory regions that are only relevant while coreboot is still executing,
such as the ramstage code and data. Mixing this into the exsting bootmem
ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE
boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE
which ends up getting translated back to LB_RAM in the OS tables. This
was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to
OS) for this specific case, but unfortunately Arm boards can have a
similar problem where their stack space is sometimes located in an SRAM
region that should not be made available as RAM to the OS.
Since both the resources made available to the OS and the regions
reserved for coreboot can be different for each platform, we should find
a generic solution to this rather than trying to deal with each issue
individually. This patch solves the problem by keeping the OS point of
view and the coreboot-specific ranges separate from the start, rather
than cloning it out later. Ranges only relevant to the coreboot view
will never touch the OS-specific layout, to avoid the problem of losing
information about the original memory type of the underlying region that
needs to be restored for the OS view. This both supersedes the
RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards.
Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds subsystem_id to nhlt structure whose value is
passed on to the endpoint's structure. Its default value is
retained to be NHLT_SSID.
Change-Id: Iad53f27e958f50e02e928cd8fa60d8397ca0eb06
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When RELOCATABLE_RAMSTAGE is employed ramstage lives within the
cbmem area. Don't mark it as OS usable under that circumstance.
Change-Id: Ie15775806632bd943b8217c433bc13708904c696
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add method to walk memory tables from OS point of view.
The tables don't change when modifiying bootmem entries and doesn't contain
bootmem specific tags.
Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a method to walk bootmem memory tables and call a function
for each memory range. The tables might not match with OS sight
of view.
Return true if the callback function returned false.
Required for FIT support in coreboot to find a usable RAM region.
Tested on Cavium SoC.
Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:
BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
should not be touched by bootmem (by example: stack,
TTB, program, ...).
BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should
not be touched by bootmem.
Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.
Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.
ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.
ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.
Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.
Tested with uImage payload on Cavium SoC.
Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Adapt to coreboot coding style.
* Use coreboot's endian conversion functions.
* Fix header and header guards.
* Get rid of unused functions.
* Add Kconfig to build it on ramstage.
* Replace size32 with ALIGN_UP and DIV_ROUND_UP.
* Add NULL pointer checks
* Convert constants to defines
Required for Cavium's BDK and uImage FIT support.
Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Required for general devicetree patching and FIT support.
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Ida75d4786eae38d84bfc71bf53573dafca8eda40
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In commit d87e4b34 (stage_cache: Add rmodule params in metadata)
the cbmem stage cache was updatd to keep track of the arg from
struct prog in the metadata. However, external stage cache did
not get the same change. Fix that.
BUG=b:72728953
Change-Id: Ifdaaa255cac0f413856410ff61bfb411a9554a31
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Generalize cbfs_boot_load_struct() by passing in CBFS type
Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In https://review.coreboot.org/25383 people were confused about the
ordering of bootmem calls w.r.t. when entries are exposed to the OS. To
alleviate this add a notion of bootmem being initialized. In addition to
that, only mark bootmem initialized when bootmem_write_memory_table() is
called. Any other calls to bootmem before that will report an error on
the console.
Change-Id: I5bc31f555038ccabb82d902c54f95858679b1695
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add a new method to clone an existing memrange with all of its entries.
Required for new bootmem type LB_MEM_RAM_DONT_OVERLAP.
Change-Id: I64b27bf2611ca310385ef680f030a3e4aa0c2680
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25582
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD AGESA returns DIMM info in SMBIOS format. dimm_info expects the data
in SPD format. These methods will be used to update amd_late_init.c so
it sets the correct values.
BUG=b:65403853
TEST=Built and booted grunt. Methods are not called in this commit. So
they were tested with the later commit by verifying the output of
dmidecode.
Change-Id: Id9fa98e9aad83dfd0a86f45e18b3c312665dce9b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the error below.
```
src/lib/lzmadecode.c: In function 'LzmaDecode':
src/lib/lzmadecode.c:77:2: error: macro expands to multiple statements \
[-Werror=multistatement-macros]
Range -= bound; \
^~~~~
src/lib/lzmadecode.c:300:7: note: in expansion of macro 'UpdateBit1'
UpdateBit1(prob);
^~~~~~~~~~
src/lib/lzmadecode.c:299:8: note: some parts of macro expansion are not \
guarded by this 'else' clause
} else
^~~~
cc1: all warnings being treated as errors
```
The macro is defined as below.
#define UpdateBit1(p) \
Range -= bound; \
Code -= bound; \
*(p) -= (*(p)) >> kNumMoveBits
Found-by: gcc-8 (Debian 8-20180402-1) 8.0.1 20180402 (experimental) [trunk revision 259004]
Fixes: 35af5c47 (src/lib: Fix spacing)
Change-Id: Ife0688541e23c05e26e429a6d8caee7e2d425b1b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Don't write more bytes than the caller requests.
Based on I484b5c1e3809781033d146609a35a9e5e666c8ed.
Change-Id: I336de417c7cd6f35cf84947fc4ae161c15bd93ef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Prints the timestamp name and value to the debug console if enabled
in Kconfig.
Change-Id: Ie6e6a4877fefec45fb987ceae7d42de6ce768159
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Looks like there's a typo in the GPIO state table we print as part of
assembling the coreboot tables. Of course, high GPIOs are represented as
1 and low GPIOs as 0. Fix this display bug.
Change-Id: I59b4d49955c13f920576dd09f463e2d399ab64e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Leverage the stage_cache mechanism to store a non-specific type
of data. This is not interesting when the location for the cache
is in cbmem. However it will be more useful when an external
location is used, e.g. when the cache is in TSEG, locked from user
modification.
Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Communicate additional status to the console when the save and load
functions do not function as expected. The most likely scenario for
an error is when using a cache that is external to cbmem, and restricted
in size.
Change-Id: Ic9a709c11152b3b9cb40abfc204151f9636b5a4c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
In order to fully utilize GENERIC_UDELAY in smm and postcar
the udelay() implementation needs to be included. Do that.
BUG=b:72378235,b:72170796
Change-Id: Ia20c1ed41ee439bb079e00fb7bd9c1855e31e349
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On many recent Chrome OS boards, the desire to unite more configurations
under the same image has led to the need of a "SKU ID" that identifies
different configurations of the same board (e.g. with certain optional
components stuffed or not stuffed, or replaced with a comparable
component). This is markedly different from the existing "board ID",
because that is reserved to count "revisions" -- changes made to the
same configuration over time during the development process. This patch
adds support to have a mainboard define this SKU ID and pass it through
the coreboot table like we already have for board IDs.
Change-Id: I8aabffe8e1003b0d6fb70d689ae513ca4b46aeda
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22696
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch switches the board_id and ram_code helper framework to use
weak functions rather than Kconfigs to determine whether the board
supplies these IDs. This cuts down on the amount of boilerplate Kconfigs
many boards have to set and also gives them more flexibility, such as
being able to determine at runtime whether a given ID is present.
Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22695
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the
Urara board which is now long dead, and have never been used anywhere
else. They were trying to do something that we usually handle with a
separate SKU ID these days, whereas BOARD_ID is supposed to be reserved
for different revisions of the same board/SKU. Get rid of it to make
further refactoring of other options easier.
Also shove some stuff back into the Urara mainboard that should've never
crept into generic headers.
Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22694
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.
Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add a comment about the tested RAM region size.
Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Fix the warning below.
```
CC bootblock/lib/reg_script.o
src/lib/reg_script.c:375:11: warning: Value stored to 'value' during its \
initialization is never read
uint64_t value = msr.hi;
^~~~~ ~~~~~~
```
Found-by: Clang static analyzer scan-build
(clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: fd461e39 (regscript: Add support for MSR type)
Change-Id: I218e45d12f2f00e2ad4cfe5410029f407b57568d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change increases the spd read performance by using smbus word
access.
BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm
Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kyösti Mälkki