Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
The limitation for SD-Card was originally only made for mc_apl2
mainboard. Since other mc_apl mainboards also use the SD-Card interface,
the speed mode setting is made in the parent mainboard_final.
In additional, all UHS-I bus speed modes are disabled because of a
limitation for industry use cases. This means that only HS mode is
permitted.
Change-Id: I2f1b51f13a53c2507c52d6a169d6384b8570b3bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch makes VGPIO_3 GPIO PIN output and low independent of
cnvi is connected or not.
BUG=b:123062346
BRANCH=None
TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low.
Change-Id: I629b99676f56747de1b244724709e14069250097
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL allows that everyone can use main() in lib/bootblock.c
even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main
functions used in some soc/ to avoid the collision with the
main function defined at lib/bootblock.c.
Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, bluetooth FW is not loaded after a reboot. In order to do
this, we have to disable the bluetooth disable gpio (GPP_C14) in
bootblock and re-enable it in ramstage.
BUG=b:137307516
BRANCH=None
TEST=boot up Hatch device and make sure (in dmesg) that proper
bluetooth FW in loaded
Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These configuration files can be used to build Kodama firmware.
BUG=b:135490566
TEST=check variant: kodama via make menuconfig; make -j
Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elan's touchpad requires min 0.3us data hold time.
To fine tune the data hold time of i2c1 to meet
specification of Elan's touchpad.
BUG=None
BRANCH=None
TEST=Verified data hold time of i2c1 is around 320ns
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix
overridetree.cb to advertise the right IRQ.
Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluebird needs to use different SAR values than Casta.
Bluebird sku id is 2.
CQ-DEPEND=CL:*1435310
BUG=b:129725065
BRANCH=octopus
TEST=build
Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove implementation of 24 MHz clock, available only
on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead
for all boards.
Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.
Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Update the AC/DC loadline values for all domains. Using the same
values as in arcada.
BUG=None
BRANCH=None
TEST=Build and Boot hatch EVT
Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO46 is wired to a tiny switch on the board labelled "GPU Boost".
Since coreboot could make use of it, add a comment about it on gpio.c.
Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently some of the LCM ID voltage gaps are below 100mV. For example, the
voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of
misrecognition from the hardware level, the voltages are adjusted so that all
the voltage gaps are larger than 100mV. The RD2 resistor values are also
updated.
BUG=b:136987483
TEST=emerge-kukui coreboot
Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.
By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).
BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None
Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3. Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Include the lpit.asl file in Hatch's DSDT definition.
BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.
Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us. Disable it using FSP UPDs.
BUG=b:130764684
BRANCH=none
TEST=Compiles
Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Increases CPU max core count to 16 for coffeelake Refresh-S Platform.
TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output
of cat /proc/cpuinfo shows no of processor=16.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I579ff6ae8227844741406c503d3994408ec2b617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.
BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also removes the relevant RCBA replays the mainboard dir.
Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
The QEMU machine "PC" doesn't support MCFG.
Die after console init if the user selected the wrong qemu machine
and print a message to use the correct machine type.
Without this patch ramstage dies with non-helpful message:
"get_pbus: dev is NULL!"
Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
increase reset off delay time
Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX
dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power
sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement.
BUG=b:135287161
BRANCH=None
TEST=local build and measure sequence with Goodix touch screen
Change-Id: I33140869990aa4715c780b0fa322921e450530ef
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the following GPIO settings.
1. Set Native termination for GPP_G0 - G4 SD card pins.
2. Set GPP_B19 to NF1.
BUG=b:123907904
TEST=Verified SD card functionality on hatch. Checked for SD detection,
transferred files to and from SD card.
Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM,
so it makes sense to disable the related SeaBIOS options for this board.
This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most
recent addition). The only one with two consequent 2s as the C-types
is t60:
static acpi_cstate_t cst_entries[] = {
{ 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
{ 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
{ 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
};
It seems that 3 could be a better choice for the last line here.
UNTESTED on a real hardware.
Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Find the NIC device based on the PCIe root port function.
Change-Id: Ia8c6e115c9b836ee60862427dfc9d46ca3dd1b69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It's forbidden to use dereference CAR_GLOBAL variables
directly. The notation fails after CAR teardown for
romstage.
Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was never tested or injected.
Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Google project name is Bloog.
Bloog is 12-inch LCD.
Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
Use sku-id to load the SAR values.
BUG=b:135078377
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for
trackpad interrupts due to ITSS not honoring the INVERT config. Now
that's fixed, we can configure trackpad wake and interrupts on GPP_A21
only.
BUG=b:130436471
BRANCH=None
TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad
2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure
through "mosys eventlog list" that the wake source is the trackpad.\
3. Run "echo mem > /sys/power/state", wait until device goes into S3,
click trackpad to ensure device wakes.
Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Now that ITSS config is fixed, we can set the IOAPIC pad configs
correctly.
BUG=b:123967687
BRANCH=None
TEST=Make sure Hatch is booting and tested out trackpad to make
sure can move cursor and wake by clicking on the trackpad
after running powerd_dbus_suspend.
Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ttyS0 isn't used for UART0, configure ttyS4 as default
Change-Id: Ia0469226253b08328807d5401c05633296e43d22
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that
the boot process of this board is super slow when UART 0 is being used -
even if nothing is connected to it. Enable UART according to
CONFIG_UART_FOR_CONSOLE - and, if UART 0 is selected, it will be initialized
at romstage and this problem will not happen.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Correct i2c address of trackpad. It should be 0x20.
BUG=None
BRANCH=None
TEST=Verified trackpad works on pre-evt system
Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Drop hacked uart code and use the generic 8250 uart driver for ns16550a.
Tested on qemu-system-riscv64:
* The UART is still working.
Change-Id: I6efda913fa39e0cfa466b52c570572aca90dacdf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33735
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port
from the SurerIO chip don't work correctly after the LPC controller (PCI
0:1f.0) initialization. Console output is broken. The patch fixes this
bug by overriding the serirq_mode option in the devicetree.cb to set
Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A FPMCU power-control pin (GPP_C11) is added to the latest
hatch reference schematic.
Even though this is not implemented in hatch rev1 board, the future
hatch family boards with FPMCU should all have this control pin.
On the old boards without this control pin, GPP_C11 is a floating TP,
and thus this patch should be backward-compatible.
BUG=b:130307667, b:135216932
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no need to add internal termination (PU/PD) on the
not-connected pads. This change gets rid of the terminations on the NC
pads.
Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CBFS_SIZE equals size of whole SPI device.
The descriptor and ME need to be placed in bottom part.
Reduce the CBFS_SIZE to maximum avalaible size.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Iecfae4573100c6787b6e8b1c4f2583a7fb3d95a3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
tc348860_table contains the eDP to MIPI Bridge controller type.
b101uan08_table used the LCD Panel type.
Use LCD Panel type for name of tables.
Remove the incomplete resolution comments and specify the resolution at
the start of the table to 1200x1920.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: Ic152ea1f95f155ab76638b57a259d37ce6f43037
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33736
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that the EC on t60/x60/z61t doesn't support it. This wasn't
even introduced in z61t so let's remove the remaining bits.
This commit follows up on commit a5fcc2e4 with Change-Id
Id2964002406a5fcf992f0ffc3627e3f66a2bb13f ("mb/lenovo/x60/t60: Remove
`fn_ctrl_swap` option").
Tested on a real hardware.
Change-Id: Ifd5e7823af305cc4a0194ee2097a749e43680c55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Korolyov <andrey@xdel.ru>
Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.
The GA-H61M-S2PV has been boot-tested too, it still boots.
Working:
- S3 suspend/resume
- USB ports and headers (Intel USB2 and EtronTech USB3)
- Gigabit Ethernet
- Integrated DVI/VGA graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controllers (Intel SATA2 and Marvell SATA3)
- User-space fan control (fancontrol on Linux)
- Native raminit (4+4GB DDR3-1333)
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio: Only front/read outputs has been tested.
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs
to be configured.
Add mainboard_configure_edp_bridge() to program the controller.
CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block
write:
<Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB
first.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The asrock/h110m has a NCT6791D, but is selecting the NCT6776-specific
SUPERIO_NUVOTON_NCT6776_COM_A symbol. Use the NCT6791D symbol instead.
Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address
Tested on Wedge100s.
Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Garg proto build has 3 SKUs:
garg 2A2C DB: SKU ID - 1
garg HDMI DB: SKU ID - 9
garg LTE DB: SKU ID - 17
For SKU#9, VBT will need to be overridden to enable DDI_C output to HDMI
BUG=b:134912735
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Cq-Depend: chrome-internal:1380847
Change-Id: I6c0ec086496eaf217ea8e326f5084d886d0e698f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Make the linker script dynamic to support non default ROM sizes.
Prevents weird runtime issues due to stages overwriting parts of the
CBFS while decompressing stages.
Change-Id: I37b9187c719b907959f02a272ec0459aabbcda3c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Files onboard.h and mainboard.h are not used for building.
Remove these files as include.
BUG=N/A
TEST=Build and boot embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Ifeb0047357e641cbe1affbbaf5402213802c774c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Fix value of 1 is used for asl_compiler_revision.
Use asl_revision for this.
BUG=N/A
TEST=booting Linux 4.20 kernel on Facebook FBG1701
Change-Id: Iffd8fe637d4669b7099fb6eafc9873560502bf80
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
This does the following:
- select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1)
- Remove stale Kconfig option on intel/saddlebrook
- select SOC_INTEL_KABYLAKE on intel/kblrvp
Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Increase the size of bootblock from 96K to 128K.
Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is already an external pull-up/down resistor tied to
this pin to identify if the board is single-channel or
dual-channel memory SKU.
BUG=b:135496271
BRANCH=none
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.
Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Those are copied from Lenovo X60 code, but are unused.
NOTE: No ACPI C-state are generated on this platform but Linux has a
separate driver for that.
Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TODO: There is no reason to do this in SMM.
Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch enables TPM on SPI and adds the needed devicetree entry for
mc_apl5.
TEST=Build coreboot for mc_apl5 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33173
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase SPI flash speed from 26MHz to 56MHz and set correct tick_dly
to get faster boot process.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32462
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RTC so that we can see correct timestamp in CrOS eventlogs.
BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui
Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Adjust FMAP sections that
- ELOG only needs 4K (by driver limitation)
- SHARED_DATA only needs 4K or less (for netboot params)
- SMMSTORE is probably not needed since UEFI@ARM is not available yet
- VPD can be smaller (most x86 devices have only 16/8K for RO/RW)
- Increase RW_LEGACY to 1M (recommended value)
- Move all new saved space to CBFS
BUG=b:134624821
TEST=Built Kukui image and boots on Rev2 units.
Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.
BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter
Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb
Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.
BUG=none
TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553
BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit follows up on commit commit 89989cf6 with Change-Id:
I1f44ffeb54955ed660162a791c6281f292b1116a ("src: Drop unused include
<arch/acpi.h>").
Change-Id: I3dc12373b32b95d25ba7b302cbca5f927678315d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33365
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit follows up on commit 8b7a1614 with Change-Id:
I73c557d6ef009fb2cac35fdea500dee76f525330 ("src/mainboard: Remove
unneeded include <arch/io.h>").
Change-Id: I7f307bf5b6cdcfebe1a290ce344b962fcecc8781
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The temperature delta between on-board thermistor and
surface temp change, so update DPTF parameter accordingly.
BUG=b:113101335
TEST=Tested in thermal chamber by thermal team.
See comment 148 / 153 in the bug.
Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Move the memory strap gpios to variant/gpio.h, as the memory straps
are different for helios.
Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All usage of pci_read_config8 was removed in commit d44d4f0f with
Change-Id Ia959eb5b747846048396e66d4c926c96c27f3878 ("mb/lenovo/*:
Remove useless smihandler code"). So we don't need this include anymore.
Change-Id: Ic4f038c80e17799016ae7e92a5675cfe7c71e400
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Helios has a number of GPIO changes w/r/t to its baseboard.
Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452
BRANCH=none
TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change tcc offset from 0 to 10 degree celsius for bloog.
BUG=b:135225497
BRANCH=octopus
TEST=Build and verify test result by thermal team.
Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Memory id's are 1-indexed for DDR4, so we need to check that the SPD
index is non-zero before converting it to the 0-indexed value in the
bitmap.
Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1387028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing
devices to wake up on pen insertion instead of removal. Changed to
EV_ACT_DEASSERTED.
BUG=b:134547896
BRANCH=none
TEST=Verified in OS, device only wakes up on pen removal
Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays
for mapping SoC DQS pins to LPDDR3 pins.
BRANCH=none
BUG=b:133455595
TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec
depthcharge vboot_reference libpayload coreboot-private-files
intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`
Ensure the firmware builds without error.
Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD
for WHL/CML SoC code to set this HECI1 chip config.
Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.
Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It was determined through testing that 16MB of reserved VRAM is
sufficient. Additional RAM for the graphics driver is allocated out
of system memory.
BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.
Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One variant is asking for support for 16G 2666 LPDDR3, so adding
generic SPD for that.
BUG=b:133455595
BRANCH=None
TEST=None as this is not being used yet
Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
One variant is asking for support for 8G 3200 DDR4, so adding generic
SPD for that.
BUG=b:132920013
BRANCH=None
TEST=None as this is not being used yet
Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix
disabling iGPU in 'Dual Graphics' on Lenovo T430.
* Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select
DRIVERS_LENOVO_HYBRID_GRAPHICS.
Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The values are generated from the respective VBTs.
Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30247
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PRESERVE flag to preserve the VPD data.
Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33020
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Add initial board commit based on HP8200 SFF.
* Add documentation.
* Serial and PCIe slot are working.
Tested on HP Z220.
Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because of some differences to the baseboard this board variant needs
its own GPIO table.
Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.
Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Angel Pons