Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is required to transmit button information from EC to kernel.
BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff
Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
If we don't pretend to have binaries, there is no need to add fake ones.
This also fixes building the default config.
Change-Id: I8f933f24a734a9ce3d82ef57f7f234ee4dfa86e9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39383
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check for SSDT entries
for CNVi
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables display for use by payload.
TEST=Build and boot the mainboard. Ensure that the screens displayed by
payload are visible.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Leave all the GPIOs in not connected state so that they can be
configured depending on the use-case. This is done to park the GPIOs in
a known safe state. This will also help to ensure that the required
GPIOs are configured when the concerned use-cases are enabled.
Below GPIOs are configured in Native Function 1 and are required for
boot-up.
* VCCIN_AUX_VID0
* VCCIN_AUX_VID1
* AP_SLP_S0_L
* PLT_RST_L
* CPU_C10_GATE_L
* GPDs
BUG=None
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- declare the FPMCU interrupt to be level-triggered
- change EC_PCH_WAKE_ODL gpio to native function mode
- corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954
BRANCH=none
TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to clobber the registers with
garbage in ramstage.
Tested, my Asus P5G41T-M LX still boots and it does not need a full
reset on almost every reboot.
Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all GPIO4 pins on the SuperIO are configured as outputs.
Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to rewrite their values in
ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none
BRANCH=none
TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable DdiPortBHpd and additional pin muxes for DPs. These pin muxes
were done in FSPs, these pin muxes are for bypassing pin muxes in FSPs.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port
pin mux from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Id44cfba696b1a21296278f4de2ad6de8f6bbd63b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39229
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Took less than 30 minutes, and booted on the first try :)
Working:
- Native raminit, using two 2GB DDR3-1333 DIMMs
- S3 suspend/resume
- USB ports and headers
- EHCI Debug with an FT2232H
- Gigabit Ethernet
- Integrated DVI/VGA outputs (libgfxinit)
- PCIe x16 for a graphics card
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controller
- Audio outputs, both front and rear
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio inputs
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is an ATX mainboard with a LGA1155 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
Working:
- All four DIMM slots
- Serial port to emit spam
- PS/2 keyboard
- S3 suspend/resume
- Rear USB ports
- Integrated graphics (libgfxinit)
- HDMI and VGA
- All PCIe ports
- Realtek GbE (coreboot must set the MAC address)
- Both PCI ports behind the ASM1083 PCI bridge
- SATA ports
- Native raminit
- Flashing with flashrom
- Rear audio output
- VBT
- SeaBIOS to boot Arch Linux
Untested:
- PS/2 mouse
- The other audio jacks
- EHCI debug
- Front USB headers
- Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit creates a nuwani variant for Grunt. The initial settings
override the baseboard was copied from variant treeya.
BUG=b:144890301
TEST=emerge-grunt coreboot
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.
Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR
This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.
Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.
Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.
Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 72
On-line CPU(s) list: 0-71
Thread(s) per core: 2
Core(s) per socket: 18
Socket(s): 2
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 85
Model name: Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping: 4
CPU MHz: 140.415
BogoMIPS: 4626.46
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 1024K
L3 cache: 25344K
NUMA node0 CPU(s): 0-17,36-53
NUMA node1 CPU(s): 18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet 172.23.68.190 netmask 255.255.0.0 broadcast 172.23.255.255
inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0 prefixlen 64 //cut
inet6 fe80::268a:7ff:fe57:5af0 prefixlen 64 scopeid 0x20<link>
inet6 2620:10d:c082:9063::5d2 prefixlen 128 scopeid 0x0<global>
ether 24:8a:07:57:5a:f0 txqueuelen 1000 (Ethernet)
RX packets 84249 bytes 6371591 (6.0 MiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 8418 bytes 748781 (731.2 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
inet 127.0.0.1 netmask 255.0.0.0
inet6 ::1 prefixlen 128 scopeid 0x10<host>
loop txqueuelen 1000 (Local Loopback)
RX packets 613 bytes 63906 (62.4 KiB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 613 bytes 63906 (62.4 KiB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
[root@localhost ~]# cbmem
36 entries total:
// Lines were cut to avoid checkpatch.pl warnings
Total Time: 96,243,882,140,175,829
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
We include it only in one file. So let's simplify everything and do like
autoport does.
Change-Id: I71f092ed7582b4931122d72f41d0b42a7569b96e
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There is no need to set the NpkEn option to disable the NPK device,
since it has already been done in the devicetree.
Change-Id: I429f1129dc4149067503cd2ff9fb4c76cdc919f0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a new ripto variant based off of the volteer baseboard design.
BUG=b:148385924, b:150810535
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image
and verify ripto boots to the kernel.
Change-Id: If7606588147500a465f16c7846e2c8429ece93ec
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Enable VBOOT support on all devices that have a 12 MiB flash, using
RW_MAIN_A + RW_MAIN_B partition, allowing the use of tianocore payload
in both RW_MAIN_A, RW_MAIN_B and WP_RO.
* Add VBNV section to cmos.layout
* Add FMAP for VBOOT
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_AB by default
The VBNV is intentionally not covered by the CMOS checksum.
Tested on x230 and T440p.
Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Jonas Moehle <ad-min@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP
vboot build.
BUG=b:150742950
TEST=Puff can boot with EC EFS with hardware write protect enabled
BRANCH=none
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I0877000b7d277106436831f2d69775c25299da9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Both T530 and W530 share the same PCI device id of 0166 for the iGPU.
Change-Id: Idce809e3820a653144db424aff1c55b70c4c693a
Signed-off-by: Prasun Gera <prasun.gera@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Looks like it should select it like any other Lenovo xx20/xx30 boards
around.
UNTESTED.
Change-Id: Iaa4983c0a6365d77ac647f68d112a405d782d501
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These two variables are initialized to zero by default.
Change-Id: I590f601b5297a9bfa93607442d7e0b8d79f1ab51
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Only whitespace changes, minor comments. This helps making diff between
devicetrees shorter.
Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Leverage the common sku id space helper encoders.
dedede uses the non-legacy SKU ID space.
squash in,
mainboard/google/dedede: Migrate onto get fw_config helper
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable read SAR value from cbfs.
BUG=b:150347463
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Use CPU_QEMU_X86 as it is selected by both Qemu x86 mainboards.
Change-Id: I8d6bfbddeeb8f2c66c5ea7728a9919e7cda86e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
They are downright useless and result in ACPI errors. So, burn them.
Also, do a minor update to autoport's README about these values.
Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It provides no useful information, so it might as well vanish.
This follows commit 0142d441c6.
Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The VBOOT code can be compiled but it asserts with:
ASSERTION ERROR: file 'src/security/vboot/common.c', line 40
Start VBOOT in bootblock to fix the assertion.
Tested on Lenovo X220:
The assertion is gone, the platform boots again.
Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is new elan touch screen IC, which includes touch panel and USI pen.
BUG=b:149800883
BRANCH=octopus
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Disable EPS on the SKUs that do not have it.
Change-Id: I7305097beea3484634933ab856fd084933868a10
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Linux expects a working PSCI and hangs if not found.
Add BL31 into CBFS as '-M virt,secure=on -bios ' commands line arguments cause
qemu's internal PSCI emulation to shutdown.
BL31 is placed in qemu's SECURERAM memory region and won't conflict with
resources in DRAM.
Tested on qemu-system-aarch64:
Fixes a hang and allows to boot into Linux 5.4.14 userspace.
Change-Id: I809742522240185431621cc4fd8b9c7deaf2bb54
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable MMU in bootblock. Makes qemu look more similar to real hardware.
There's no real need to activate the MMU.
Tested on qemu-system-aarch64: 5 page entries are used out of 32.
Change-Id: Ifaed9d3cc11520f180a732d51adce634621b5844
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38534
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace DSDT ACPI code and DSDT injection with a SSDT only solution.
The current implementation shows some issues on current Linux, which
might be due to external ACPI objects, which are then injected into
DSDT or the fact that those objects only use 3 characters.
Replace all the DSDT code with an SSDT generator.
Tested on HP Z220:
Boots into Linux with no ACPI errors. The SSDT can be disassembled.
Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Leverage the common sku id space helper encoders.
volteer uses the non-legacy SKU ID space.
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.
BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.
Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Leverage the common sku id space helper encoders.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The indirection of names is exceedingly confusing for ultimately the single
interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on
the PCH side.
This helps folks chase this indirection down through the code.
BUG=b:147026979
BRANCH=none
TEST=builds
Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is
routed to GPP_C12 GPIO. Update the GPE configuration accordingly.
BUG=None
TEST=Build the mainboard.
Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Overwrite the default of 1 MiB with the actual bios region size
set in the stock IFD.
Allows to use payloads like TianoCore without manually touching
the CBFS_SIZE.
Change-Id: Ic1753a38212cc4961671fea11afe88265e73333b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39073
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix PNP warning about missing devicetree entry for SUART1/2 by setting
register 0xF0 to a sane (default) value.
Change-Id: Ie852696aae09b9b03cebd6c3d8cbbd53a7138d89
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When specifying _PAD_CFG_STRUCT with raw hex values, a logical reset
value of 0x0 is only defined for GPD pads. For any other GPIOs this maps
to 0x3.
On the Supermicro X11 boards a value of 0x0 is set for GPP_D22 and
GPP_F23, triggering the error "gpio_pad_reset_config_override: Logical
to Chipset mapping not found".
Set the right value (0x3<<30) for the affected GPIOs.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3ae17dfc4d90f88f5b8bc5bee49740745778a91a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch disables the SATA config from devicetree for JSL RVP, since we
are not planning to use the SATA storage in chrome config.
Change-Id: I9cbcbf96e70b79bfb60f228b77a1065c26cd1aa2
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Add missing include <device/pci_def.h> for the boards that are being
switched away from ROMCC_BOOTBLOCK.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I83ff712f99388c4e6ea00a942eb57bcabb53a3fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38903
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change creates gfx directory under drivers/ so that all drivers
handling gfx devices can be located in the same place. In follow-up
CLs, we will be adding another driver that handles gfx devices.
This change also updates the names used within the driver from
*generic_gfx* to *gfx_generic*. In addition to that, mainboard
drallion using this driver is updated to match the correct path and
Kconfig name.
TEST=Verified that drallion still builds.
Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:149813043
TEST=tested on sarien and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin.
This can save 1mW power comsumption.
BUG=b:149289256
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source]
partially broke resume from suspend on Auron and Slippy variants when
multiple events exist in the EC event queue. In the case of the device
suspending manually and then subsequently having the lid closed, the device
will be stuck in a resume/suspend/resume loop until the device is forcibly
powered down.
Mitigate this by clearing any pending EC events on S3 wakeup.
Test: build/boot several Auron/Slippy variants, test suspend/resume functional
with both single and multiple events in EC event queue.
Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:147994020
TEST=tested on drallion and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
The serial number and UUID returned by DMI are retrieved from VPD.
The solution supports a 16 character "serial_number" and a 36 character
"UUID" string.
BUG=N/A
TEST=tested on monolith
Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable use of VPD for monolith. This will be used to store the UUID and
Serial number.
BUG=N/A
TEST=build
Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Some Volteer variants might not use SPD files. Allow SPD_SOURCES in
spd/Makefile.inc to be empty.
BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and
the lock hotkey (KEY_COFFEE) on scancode 0x02.
On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2
and Fn-F3 are different from the default one so a new layout has to be
defined.
Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Change based on google/auron that is similar to peppy.
This will be helpful for the next follow-up commit that will
add ACPI for the ambient light sensor.
Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3
Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure UPDs to support Audio enablement.
Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Follow thermal table for fine tuning.
1. Update PSV values for sensors.
2. Change PL1 min value from 4W to 5W.
3. Change PL1 max value from 15W to 12W.
4. Change PL2 min value from 15W to 12W.
BUG=b:148627484
TEST=Built and tested on drallion
Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg.
BUG=b:148912093
BRANCH=None
TEST=build coreboot and checked IA_TDC from TAT tool.
Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
add SKU ID 3 and 4 for dood DVT
1: Dood WiFi + LTE (evt)
2: Dood WiFi (evt)
3: Dood WiFi + LTE + dual camera (dvt)
4: Dood WiFi + dual camera (dvt)
BUG=b:148988979
TEST=build firmware and verify on the DUT of sku 3 and 4
check LTE module is enabled or not
Change-Id: If86efe2a2f7b2e165ad44220b6dd59e9080b5892
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38730
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USB3 OC pin is configured for the wrong pin. Follow HW circuit
(schematics) to set it correctly.
BUG=b:147869924
TEST=USB function works well and OC function is corresponds to the
right port.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I61234a2054ab52fa508482d3dd0f94b13f96a5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38885
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Puff uses the smbus to access the SPD of memory DIMMs.
It will short the SPD reading time if enabling SPD_READ_BY_WORD.
BUG=b:149360051
BRANCH=None
TEST=build puff and boot up OS
ran cbmem -t | grep FspMemoryInit
Without this patch:
950:calling FspMemoryInit 643,199 (257,588)
With this patch:
950:calling FspMemoryInit 477,714 (154,612)
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: I161e8eb386ab604b16746f0deeecc3d6c9063c3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Fine tune the video timing of panel-BOE_TV101WUM_N53 to avoid noise. The
parameters are based on BOE NV101WUM-N53 preliminary product spec.
BRANCH=kukui
BUG=b:147378025
TEST=bootup pass
Change-Id: Ia9e2cc90f233e87d712c2dc6f4441ca2e5423162
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38401
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bipship is a sustaining project of Blooguard.
SAR value follow Blooguard.
BUG=b:149414960
BRANCH=octopus
TEST=build and verify load correct SAR value by sku-id
Change-Id: Ic45ed10fc147401d4278f1811a86cd2b2e4c63ac
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Turn on the H1 device in the devicetree. Configure the concerned GPIOs
and enable the required config items.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I37972635454cd0d35608623e7be4110012ace658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add EC ACPI reporting of current temp and platform critical temp.
Adapted from ACPI dump of ODM AMI firmware.
TEST: check reporting of current/critical temps via lm-sensors
from ACPI on Librem 13v1 and 13v4 boards.
Change-Id: I92641fbbdda46e0c388607a37f7a7cc2dcd6c26d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Pandya, Varshit B