Commit Graph

9831 Commits

Author SHA1 Message Date
Timothy Pearson e24f7d37ce cpu/amd/model_10xxx: Fix UMA memory sizes
Fix up commit 4916880 (cpu/amd/model_10xxx: Move GFXUMA size
calculation to separate function) unintentionally changing
behavior when converting the switch statement to an if-else
statement.

Change-Id: I8d126aaec1b324face6407a2b451e603e61db0e5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8748
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-19 08:27:09 +01:00
Kyösti Mälkki 4da487eae8 CBMEM: Add LATE_CBMEM_INIT guards
Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.

Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-03-19 06:17:07 +01:00
Timothy Pearson e9424c593a northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA
is enabled, however when GFXUMA is disabled an attempt was made to locate
the CBMEM memory segment above the I/O hole in certain rare cases.

Removing this special case does not impact functionality, and paves
the way for early CBMEM support.

Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19 05:00:25 +01:00
Kyösti Mälkki 1e60839be0 southbridge/amd/rs780: Remove requirement for CF8/CFC config access
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.

Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-19 04:00:08 +01:00
Aaron Durbin 9ef9d85976 bootstate: use structure pointers for scheduling callbacks
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.

In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.

Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-18 16:41:43 +01:00
Marc Jones b335c3de42 chromeec: Move SERIQ mode to LPC option
SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses.
This fixes a KCONFIG unmet dependency warning on ARM mainboards with
chromeec.

Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8665
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-18 07:08:59 +01:00
Stefan Reinauer 425b61e102 arch/x86/Kconfig: Add license header
Add license header with copyright of the original authors.

Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8691
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17 18:11:38 +01:00
Dave Frodin f364fc7682 southbridge/amd/pi: Enable early I/O decode to LPC
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.

Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-17 17:49:58 +01:00
David Hendricks 68ec2fce2b ipq806x: Break apart large transfers in spi_xfer()
The current spi_xfer() function sets the count in hardware and then
loops while waiting for the requested number of bytes to be sent or
received. However, the number of bytes to be transferred may exceed
the maximum count that can be programmed into the controller.

This patch re-factors spi_xfer() to split the low-level FIFO handling
portions for transmit/receive into their own functions to be called
by loops in spi_xfer() which will break large transfers into smaller
ones.

BUG=chrome-os-partner:30904
BRANCH=storm
TEST=built and booted with a >64KB payload on Storm

Original-Change-Id: I70743487996cf08cfc602449f2181a7fcd99bfa4
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209838
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Tested-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit 5ec28de11f12c2438356f45ce978a17fbb603bf7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0033e0dd96006cfd30a7a4f5e5a052f677e05108
Reviewed-on: http://review.coreboot.org/8676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:54:26 +01:00
Furquan Shaikh c800129009 t132: Add TTB_BUFFER to resource reserved
TTB_BUFFER holds the MMU tables. Thus, this memory needs to be preserved while
performing a wipe in depthcharge. Hence, marking it as reserved

BUG=None
BRANCH=None
TEST=Compiles successfully and boots upto depthcharge. Error wiping memory
tables is fixed.

Original-Change-Id: Idd5cd0235d50f7b9617df2cead3bf71012e3b630
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210000
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 670e21ed11f985ca6cfef4f051c71b3c06f9c6ff)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ifcbdd4fdaad0bd4bfe384698b13cc5013317345e
Reviewed-on: http://review.coreboot.org/8681
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:41:00 +01:00
Furquan Shaikh f4731afb9d rush: Update rush Kconfig file
Update rush Kconfig file to include TPM and RAMSTAGE_INDEX options

BUG=None
BRANCH=None
TEST=Compiles successfully. TPM works. Ramstage boots successfully.

Original-Change-Id: Ie55260c710ffcb6a2e04c8658ca6dd3cdec6b6db
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209978
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0088f5aade8533c6ed235de25934d47cd0743a67)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5c4a54b74546de73eee7e7bae072cc712ce1838f
Reviewed-on: http://review.coreboot.org/8680
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:40:49 +01:00
Furquan Shaikh e6ede46c33 rush: Add ec_dummy file to enable vboot compilation
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: Ic11bef85e5c7635000582f87727cd9a33b0b36e3
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209975
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 3d3f0494d8758ef5040384f63d023c042686bd2c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie15781d10a366b68f0db97378ccb348a4f074995
Reviewed-on: http://review.coreboot.org/8679
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:40:34 +01:00
Furquan Shaikh 64352a7c1b rush: Pull in chromeos.c from nyan into rush
Hardcoded values are set for developer,recovery mode. Change as per requirements

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles succesfully for rush

Original-Change-Id: Ied506a9d1c4e0ba8ee06d57c6ca8c726220998b5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2e6934d47c5b4bb98e60486202b230bae79d927b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I36e384b0d331fdd9e3f47954decfddaf4f31aed3
Reviewed-on: http://review.coreboot.org/8678
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:40:21 +01:00
Jimmy Zhang aa228d08e9 Tegra132: Configure CPU clock
Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible
from AVP, the first place that can change CPU clock is after CPU
has been brought up, ie, ramstage in this case.

CPU initial clock source is set to PLLP by MTS.

BUG=None
TEST=Norrin64 and A44

Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209698
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89
Reviewed-on: http://review.coreboot.org/8677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:39:22 +01:00
Furquan Shaikh 6ad6e3d84a t132: Add monotonic_timer.c to rmodules_arm
Update VBOOT_STUB_DEPS to include monotonic_timer.c

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: I3cc559fa21c444da1a7976e4952ea4941c2a1428
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209972
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 8096ae56c4df4013cfc798944b98dd1078c8b451)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I68c13617b96fd872d1eaa9278de6647eccb795c3
Reviewed-on: http://review.coreboot.org/8674
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:38:38 +01:00
Furquan Shaikh a742ef1a48 rmodules: Make rmodules inclusion for vboot dependent on romstage_arch
Currently, the rmodules inclusion for vboot is dependent on ramstage_arch.
This change adds dependency on romstage_arch, since vboot is associated with
romstage. Inclusion based on ramstage_arch is left as is in case someone needs
it in ramstage.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for link, rush and nyan

Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209568
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc
Reviewed-on: http://review.coreboot.org/8673
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:38:23 +01:00
Furquan Shaikh fbff908a74 coreboot classes: Add dynamic classes to coreboot
Provide functionality to create dynamic classes based on program name and the
architecture for which the program needs to be compiled/linked. define_class
takes program_name and arch as its arguments and adds the program_name to
classes-y to create dynamic class and compiler toolset is created for the
specified arch. All the files for this program can then be added to
program_name-y += .. Ensure that define_class is called before any files are
added to the class. Check subdirs-y for order of directory inclusion.

One such example of dynamic class is rmodules. Multiple rmodules can be used
which need to be compiled for different architectures. With dynamic classes,
this is possible.

BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for nyan, rush and link.

Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209379
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295)

Some of this cherry-pick had already been committed here:
commit 133096b6dc
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c
Reviewed-on: http://review.coreboot.org/8672
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:38:10 +01:00
Deepa Dinamani 74aa7770f6 soc/ipq806x: Replace GPT with fine grained DGT timer.
Support 1MHz libpayload restriction on timer implementation
by using DGT (debug) timer instead of GPT (general purpose) timer.

BUG=chrome-os-partner:28880
TEST=manual
  verified DGT timer functions in coreboot and depthcharge.

Original-Change-Id: Iab322d7e863e3959c027e9ce876223a64eb7e257
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201574
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit ddf11eee5ec2d86a62095e932dbec9313b8fb9e1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id73e805801fd8d135b607df9f4f8caf567ec5b83
Reviewed-on: http://review.coreboot.org/8596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-17 16:30:58 +01:00
Aaron Durbin f69a99dbf8 coreboot: x86: enable gc-sections
Garbage collected sections allow for trimming the size of the
binaries as well as allowing for not needing to config off
unused functions. To that end, on a rambi build the following
differences are observed:

$ diff -up \
	<(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \
	<(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf)
--- /dev/fd/63  2015-03-10 12:07:27.927985430 -0500
+++ /dev/fd/62  2015-03-10 12:07:27.927985430 -0500
@@ -6,9 +6,9 @@ There are 4 program headers, starting at
 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg
Align
   LOAD           0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0
-  LOAD           0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0
-  LOAD           0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0
-  LOAD           0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560     0
+  LOAD           0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0
+  LOAD           0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0
+  LOAD           0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888     0

  Section to Segment mapping:
   Segment Sections...

$ diff -up \
	<(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \
	<(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf)
--- /dev/fd/63  2015-03-10 12:08:16.855985880 -0500
+++ /dev/fd/62  2015-03-10 12:08:16.851985880 -0500
@@ -5,8 +5,8 @@ There are 1 program headers, starting at

 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg
Align
-  LOAD           0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E
   0x10
+  LOAD           0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E
0x10

  Section to Segment mapping:
   Segment Sections...
-   00     .rom .text
+   00     .rom

The following warnings needed to be applied to CFLAGS_common because for
some reason gcc was miraculously emitting the warnings with the
unrelated *-sections options:
  -Wno-unused-but-set-variable

Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-17 14:35:31 +01:00
Kyösti Mälkki 5179419989 rockchip/rk3288: Fix whitespace
Change-Id: I6c3c1e871de33b4d0e968b254bbcf125cee9fddb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8704
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-17 06:59:25 +01:00
Stefan Reinauer 3d78ece7d0 haswell: Fix monotonic timer integration
In some previous attempt to enable monotonic timers on all platforms,
the LAPIC monotonic timer was selected for Haswell devices, despite
the fact that LAPIC timers are not used in coreboot on Haswell
(See haswell Kconfig) and there already was a monotonic timer
implementation enabled that just needed to be added for SMM as well.

Change-Id: I6beb2977864e507956636860ed463e1991cea1ed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8702
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:56:14 +01:00
Stefan Reinauer c3d15a7210 Intel common SPI: Fix compilation breakage from refactoring
When the Intel SPI drivers were refactored, compilation for Chrome OS
devices broke, because ELOG uses the SPI driver in SMM.

Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8701
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:55:52 +01:00
Stefan Reinauer 45a225b05d elog: Fix compilation with CONFIG_CHROMEOS enabled
On ChromeOS devices the ELOG section size and offset are
provided by the FMAP, rather than KConfig. Some upstream
refactoring broke compilation in that case.

Change-Id: I8b08daa327726218815855c7c2be45f44fcffeed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:54:46 +01:00
Timothy Pearson 4916880511 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
This is required for early CBMEM support.

Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8663
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-17 04:33:06 +01:00
Timothy Pearson 447240808c lib: Add Kconfig option to enable/disable auto fallback control
Under certain conditions, e.g. automated testing, it is useful
to have the payload (e.g. Linux) reset the reboot_bits CMOS
value.  This allows automated recovery in the case of coreboot
starting properly but the payload failing to start due to bad
configuration data provided by the coreboot image under test.

Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Change-Id: Ifc8f565f8292941d90b2e520cc9c5993b41e9cdd
Reviewed-on: http://review.coreboot.org/8698
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-03-17 04:22:23 +01:00
Stefan Reinauer 87200e2aa3 Makefile.inc: Use -Og when compiling with GDB support
From GCC's documentation:

Optimize debugging experience. -Og enables optimizations that do not interfere
with debugging. It should be the optimization level of choice for the standard
edit-compile-debug cycle, offering a reasonable level of optimization while
maintaining fast compilation and a good debugging experience.

Change-Id: I9a3dadbf8e894cb28e29d7b2f4e9add252e7bbb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/8689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-17 01:08:20 +01:00
Dave Frodin 84c72dedab northbridge/amd/pi: Create common agesawrapper.c
This removes the mainboard agesawrapper.c file from binarypi
based boards and creates a common one.

Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16 21:46:17 +01:00
Dave Frodin 4b45dd3253 cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()
This makes the change to the cpu/amd/pi/00730F01 that was
made for the cpu/amd/agesa based boards in:
    commit 48518f0d
    AGESA: Add amd_initcpuio() and amd_initmmio()
    These are not wrappers for AGESA as they do not enter vendorcode at all.
    We expect most of the added fixme.c file to be written without use of AMDLIB.h
    and parts relocated as northbridge enable_resources().

The equivalent change has already been made for cpu/amd/pi/00630F01.

Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8670
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16 21:45:49 +01:00
Timothy Pearson 8e3da749ed mainboards/amd: Fix incorrect reboot_bits location
Change-Id: Iead07df714f4f1bbaae6b564431fb4edf7b18ac2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8684
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-16 07:07:18 +01:00
Francis Rowe 71512b2cf6 northbridge/i945/gma: fix build error with native graphics init
Tested on an X60, Native graphics init still works perfectly.

Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8696
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-03-16 06:46:48 +01:00
jinkun.hong ac490b8a6b coreboot: rk3288: Add a stub implementation of the rk3288 SOC
Most things still needs to be filled in, but this will allow us to build boards which use this SOC.

BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot

Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-16 04:52:46 +01:00
Alexandru Gagniuc 83b05eb0a8 google/butterfly: Drop MRC.bin in favor of native raminit
I thought this wasn't going to work, and observing the timC detection
failure of early tests, I was getting somewhat discouraged; however,
this works. I've tried it with all possible permutations of the
following memory modules:
* 2 GiB single-rank DDR3-1600
* 4 GiB single-rank DDR3-1600
* 4 GiB dual-rank DDR3-1600

I did notice a limited number of memtest errors during one of the
runs, but they were in an address range that is otherwise marked as
reserved. I wrote that off as "maybe something was doing MMIO there
just when memtest was poking the address range". I was not able to
reproduce that error.

Change-Id: Ibd52e1d52fc8d900591d6a488f9a5b4d1e5e4fd3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-03-15 05:28:29 +01:00
Timothy Pearson 21d898bad0 mainboard/asus/kfsn4-dre: Use Fallback boot image by default
Change-Id: Ib58550acda63132e35a526c72ac7d987b457cea5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:57:53 +01:00
Timothy Pearson d7210c579e mainboard/asus/kfsn4-dre: Change default debug level to Spew
This brings the KFSN4-DRE in line with other boards in the tree.

Change-Id: I9216130f51ed0576871fd27ca6ae4610c5f5810e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:57:32 +01:00
Timothy Pearson b812d5d92f northbridge/amd/amdht/h3finit.c: Fix boot failure
GIT hash 586d6e introduced a regression that causes boot failure
with an f0011449 AMD stop code.

Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8685
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:45:50 +01:00
Kyösti Mälkki 8517f94bfd OxPCIe952: Fix read8/write8 argument
This was missed in commit bde6d309 as the driver is not enabled
in any configuration by default.

Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8660
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-14 00:10:52 +01:00
Vadim Bendebury f9fb0d9bf3 Use a common boardid.h instead of per board copies
There is no point in duplicating boardid.h per board - they are all
the same. Let's keep a single instance in the common include directory
and let the linker report a problem if one tries using this function
on a board where it is not supported.

BUG=chrome-os-partner:30489
TEST=verified that coreboot builds fine for nyan_big and nyan_blaze.

Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209699
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962
Reviewed-on: http://review.coreboot.org/8666
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13 23:01:54 +01:00
Timothy Pearson 586d6e2a88 northbridge/amd/amdht: Allow mainboards to set HT frequency limit
This is useful when the PCB layout of a mainboard does not allow
stable operation at the increased HyperTransport speeds of newer
processors.

Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8464
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-13 21:17:58 +01:00
Kyösti Mälkki 668828d3b3 siemens/mc_tcu3: Fix build and ACPI IRQ bridge entry
Propagate commit d08057a change to this new FSP platform.

Change-Id: Ie83c7f3573c189f4e4576c971dbc12099bb7b123
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8662
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-03-13 19:21:25 +01:00
Julius Werner c5cd57c330 nyan: Remove broken setup_display() from romstage
This patch removes a chunk of romstage code from Tegra and all Nyan
boards that was supposed to enable some LCD power rails early, but never
really worked. The dev_find_slot() function can only find PCI devices,
which the CPU cluster is not. Since we're done with Nyan-RO and the
ramstage display code is fine as it is, there is no point in trying to
fix this... but we should remove it from ToT lest someone uses it as a
blueprint to add more dead code to future boards.

BRANCH=None
BUG=None
TEST=None

Original-Change-Id: I6eee256873299429d4e3934fe7d454120390f34d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207720
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a3df62a3bcefcc20ae59648f5d1f0a01db3c02c6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8deedea5e9787848aae3064509c611bc349313cc
Reviewed-on: http://review.coreboot.org/8638
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-13 18:43:19 +01:00
Alexander Couzens b7b83719bf northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP
This capability means:
FERR messages are sent out on system detected an
unmasked floating point x87 FPU error.

Even though this capability is supported on nehalem it doesn't
make sense to set it in early stage. This MSR
has a core scope which results in an unsync MSR because
it's not set on other cores than the BSP.

Found-by: BITS
Tested-on: lenovo thinkpad x201t

Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 14:51:42 +01:00
Alexander Couzens ed48dfdc4e cpu/intel/2065x: add define for MSR IA32_FERR_CAPABILITY
BIOS Writer's Guide, rev 1.6.0, June 2012:
This MSR controls whether and FERR message is sent over the system bus
when unmasked x87 exceptions are generated.

This feature is not supported from Sandy Bridge processor onwards.

Change-Id: I19b260ca4b62f57c26989430693b00b9853bc441
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8658
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 14:51:37 +01:00
Furquan Shaikh 144a68a4ad coreboot t132: Remove empty function cpu0_config_and_reset
This function is not used/required in t132.

BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: Iba5ea3c14cc9facbf2a86aa08021edb9907f92da
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209425
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit c615136aa82d457540eb1f1308c9e986dbc9bce7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id92d464db24298dd888cbc022204379eb8aa8aba
Reviewed-on: http://review.coreboot.org/8652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 00:19:12 +01:00
Furquan Shaikh d123f865ad coreboot t132: Stop running AVP at the end of romstage
Stop running AVP at the end of romstage until event conditions are met (JTAG,
GIC_IRQ or LIC_IRQ).

BUG=chrome-os-partner:30831
BRANCH=None
TEST=Compiles successfully and boots till last known good checkpoint.

Original-Change-Id: Ia221f08b27ac0c60a66d588e351677144cc6a322
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209424
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit df4e8b4c8a1002443a936bd0563fbc9e0710f489)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I59f7702bd50a1039b8723e9cb12b8d714e353d37
Reviewed-on: http://review.coreboot.org/8651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 00:18:59 +01:00
Furquan Shaikh 9ad04c61e9 coreboot arm64: Add int constants to stdint.h
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I395c9b7bbe34c6834abc1a169779639f940121bd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209334
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit da15df16464f4203db08fb02ad4c0a0f94d16724)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I818de7cb0d8a44fb20c2bbea108c15ecc2b724ae
Reviewed-on: http://review.coreboot.org/8650
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 00:17:55 +01:00
Aaron Durbin 44f465d21c tegra132: fix Rx FIFO underruns with slower SPI clock
The SPI controller operates on packets which can be variable
length up to 32-bit packets. It also has the ability to be
put in packed or unpacked mode w.r.t each packet. i.e. does
a single fifo register hold >= 1 packet. The current programming
uses 8-bit packets in unpacked mode which means 4 fifo slots
are used for a 32-bit DMA transfter. As the AHB can only operate
on a minimum of 32-bit bursts the triggers need to be programmed
correctly so that there is room for a full 32-bit DMA transaction.

Previously faster SPI clocks just made things magically work.

BUG=chrome-os-partner:30779
BRANCH=None
TEST=Built and booted through coreboot with 20MHz SPI clock.

Original-Change-Id: I3f1cd4dddcea9514327b2363ed450a527db7e1fe
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208862
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d9864228a2479e412d7e0d2221fe536f78329acd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I61c145f35e1f889d4f83f3dfea049bfd347c1196
Reviewed-on: http://review.coreboot.org/8649
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13 00:17:09 +01:00
Aaron Durbin 7ddb5f76fe tegra132: Add Trust Zone register access
The Trust Zone carveout registers are only accessible using
a secure access mode. The AVP runs as non-secure all the time.
In EL3 the CPU is in secure mode, but when the MMU is enabled
the page tables dictate if accesses to certain regions are
secure or not. However, ramstage is currently being loaded
into non-secure memory and the page tables will live in
non-secure memory as well. Therefore, handle all these
cases by providing global state which mirrors the TZ
register.

BUG=chrome-os-partner:30782
BRANCH=None
TEST=Built and ran through ramstage with the MMU enabled
     Resources are read and set accordingly.

Original-Change-Id: Ib76b2641497a29ef2adb75934b2df55ecf0b3e78
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/209061
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 0bcbdc56978f6ebe3e7d1b74ed2fd861e03bb562)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9c1beed443a48870ba190427e87caf90caf4ff6b
Reviewed-on: http://review.coreboot.org/8648
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13 00:15:55 +01:00
Furquan Shaikh da9b9f324b t132: Add mmu support
Add support for mmu initialization and enabling caches. mmu_operations provides
functions to add mmap_regions using memrange library and then calls mmu_init for
armv8.

BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until depthcharge load. Goes past
all the earlier alignment errors.

Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208762
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b
Reviewed-on: http://review.coreboot.org/8647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 00:12:23 +01:00
Furquan Shaikh 2486957514 armv8: Add mmu support
Add support for initializing and enabling mmu for armv8. Using 64KiB granule and
33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes
use of memrange library to get a list of all the mmap regions from the SoC to
initialize XLAT table.
Currently, all calculations in mmu.h are based on the assumptions that max 33
bits are used in VA and granule size is 64KiB. Changes in these assumptions will
have to reflect in the dependent calculations as well.

BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until "payload not found". Goes past
all the earlier alignment errors.

Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208761
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285
Reviewed-on: http://review.coreboot.org/8646
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-03-13 00:11:00 +01:00
Tom Warren a6ca9353a8 ryu: Add TPS65913 regs/init for VDD_CPU 1.0V
Other default slams should be added later to the init table
once we know what the kernel touches. But for now, only VDD_CPU
is needed.

Also slipped in a minor name change in mainboard.c

BRANCH=none
BUG=none
TEST=none, no HW here for me to test on yet

Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/208385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 00:10:33 +01:00
Tom Warren 2525885576 tegra132: Add code to setup chip operations and mem resources.
With this memory resource, the payload loading code should be
able to create a bounce buffer and load the payload successfully.

Adapted from tegra124 soc.c

BUG=None
BRANCH=None
TEST=Built and booted to ramstage on rush.

Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208121
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f
Reviewed-on: http://review.coreboot.org/8644
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13 00:09:44 +01:00
Tom Warren 31818c98af ryu: Add support for full LPDDR3 SDRAM BCT init via BootROM
Once LPDDR3 init is supported in the ryu romstage, this can
be reverted. Note that this 528MHz BCT has been pre-qualed
by NVIDIA AE's, but will be updated as more tuning is done.

BUG=none
BRANCH=none
TEST=Builds, BCT is in binary, but I have no HW here to test on

Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208384
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe
Reviewed-on: http://review.coreboot.org/8643
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13 00:04:03 +01:00
Aaron Durbin 01dde90eb9 armv8: correct dcache line size calculation
The CCSIDR_EL1 register has cache attribute information
for a given cache selection in CSSELR_EL1. However, the
cache isn't being selected before reading CCSIDR_EL1.
Instead use CTR_EL0 which better fits with the semantics
of dcache_line_bytes(). CTR_EL0 has the minimum data cache
line size of all caches in the system encoded in 19:16 encoded
as lg(line size in words).

BUG=None
TEST=Built.

Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208720
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0
Reviewed-on: http://review.coreboot.org/8642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 00:02:54 +01:00
Aaron Durbin b397f01149 tegra132: split memory range querying to above/below 4GiB
The address map code was originally assuming all carveouts would
be packed together in the upper end of the physical memory
address space. However, the trust zone carveout is always in the
32-bit address space. Therefore, one needs to query memory ranges
by above and below 4GiB with the assumption of carveouts being
packed at the top of *each* resulting range.

BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran through coreboot on rush.

Original-Change-Id: Iab134a049f3726f1ec41fc6626b1a6683d9f5362
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208101
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 8d5795fbff36e91906384e10774a32541d358324)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If15ff48d5a4c81731eb364980b30c8086deb1cca
Reviewed-on: http://review.coreboot.org/8641
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13 00:01:14 +01:00
Vadim Bendebury c20ff482a7 storm: allow to override CBFS_SIZE configuration setting
The default CBFS size configuration setting is incorrect in case of
Qualcomm SOC targets, as the coreboot blob is much smaller than the
actual bootprom. Note that this size also must match the board fmap
defined in the appropriate depthcharge board directory.

BUG=chromium:394068
TEST=manual
   . previously failing to boot coreboot image does not fail to load
     depthcharge anymore.

Original-Change-Id: I1b178970b1deee05705490542e4a0c57500379dd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208146
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 01f3561fdee7b5547534e20d423fbbb1b490532c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If573bbc6254cf6786e75970eae3ad2b327a7ecfe
Reviewed-on: http://review.coreboot.org/8640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-12 23:59:28 +01:00
Aaron Durbin bc3019cbd2 t132: handle optional Trust Zone region correctly
Provide a default Trust Zone region size of 1MiB, and
correctly account for it in the AVP and the arm64 cores.
The different path between the arm64 cores and the AVP
is because the AVP cannot access the Trust Zone region
registers. Therefore the AVP needs to account for the
Trust Zone region.

BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran. Noted Trust Zone region being accounted for.

Original-Change-Id: Ie0f117ec7a5ff8519c39778d3cdf88c3eee57ea5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208062
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 22f2fa05c009c58f53b99b9ebe1b6d01fdac5ba7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I28506b4401145d366b56126b2eddc4c3d3db7b44
Reviewed-on: http://review.coreboot.org/8639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-12 23:58:56 +01:00
Martin Roth d08057aa20 intel/fsp_baytrail: Add PCI Root Port IRQ Routing
This change generates the ASL tables needed for the PCIe bridge routing.

It generates this ASL (swizzled for each of the 8 functions)
Name(RP1P, Package()
{
	Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
	Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
	Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
	Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
})
Name(RP1A, Package()
{
	Package() {0x0000ffff, 0, 0, 20 },
	Package() {0x0000ffff, 1, 0, 21 },
	Package() {0x0000ffff, 2, 0, 22 },
	Package() {0x0000ffff, 3, 0, 23 },
})
Device(RP01) {
	Name(_ADR, 0x1c0001)
	Name(_PRW, Package() {
		0, 0
	})
	Method(_PRT,0) {
		If(PICM) {
			Return (RP1A)
		} Else {
			Return (RP1P)
		}
	}
}

Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8429
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-12 20:35:49 +01:00
Kyösti Mälkki 48b3dbc748 x86 SMM: Replace weak prototypes with weak function stub
Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7961
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-11 18:15:22 +01:00
Nicolas Reinecke b0922f0183 lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230
Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio.
Verified with schematics.

Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8358
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-10 23:53:17 +01:00
Paul Menzel 60ef456f46 console/Kconfig: Enable CBMEM console by default
Currently on AMD boards no romstage messages can be saved in CBMEM, so
only messages from ramstage on will be stored in CBMEM. Other than
that nothing changes.

Enabling CBMEM console by default does not noticeably decrease boot
time as the messages are directly written to CAR or RAM.

The board status script under `util/board_status/` reads the coreboot
messages from CBMEM, which are then uploaded to the board status
repository. With CBMEM console disabled by default, currently no
coreboot console messages are uploaded to the board status repository,
although it is important to have those.

Enabling CBMEM console by default improves this situation, so that for
all boards at least ramstage messages are stored in the board status
repository.

Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5350
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-03-10 23:42:22 +01:00
Kyösti Mälkki 9e94dbfcd0 ACPI: Get S3 resume state from romstage_handoff
There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.

Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10 23:42:10 +01:00
Kyösti Mälkki a63719407f x86 cache-as-ram: Remove BROKEN_CAR_MIGRATE option
This was added to handle cases of Intel FSP platforms that had
EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM.
These boards were recently fixed.

To support combination of EARLY_CBMEM_INIT without CAR migration was
added maintenance effort with little benefits. You had no CBMEM
console for romstage and the few timestamps you could store were
circulated via PCI scratchpads or CMOS nvram.

Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8636
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10 23:39:41 +01:00
Kyösti Mälkki f48b38b8d7 ARM romstages: Support and fix COLLECT_TIMESTAMPS
Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8021
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-03-10 23:37:08 +01:00
Gabe Black 01fe638010 cbmem console: Allow the cbmem console on non-x86 systems again.
If it's not supported on a particular board, either the build will fail or
checks within the cbmem console itself should detect the problem. There
shouldn't be random memory corruption any more.

BUG=None
TEST=Built with CONSOLE_CBMEM enabled on nyan and saw that it was actually
enabled.
BRANCH=None

Original-Change-Id: Id6c8c7675daafe07aa4878cfcf13faefe576e520
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193167
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 20b486443bfc2d93d72bbc9e496023a00ab9ab30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I39fbcdff61f6d8f520f2e9d7612dee78e97898b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7748
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-10 23:36:23 +01:00
Dave Frodin 180a11427d northbridge/amd/pi: Remove superfluous logic operand
Commit 2e0cf14 corrected this for pi/00730F01/northbridge.c.
This commit fixes it for pi/00630F01/northbridge.c.

Found-by: Clang

Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8289
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-10 16:44:23 +01:00
Bruce Griffith 006364eedd AMD Bald Eagle: Add northbridge files for new AMD processor
Also fix a typo in a config option for SteppeEagle.

Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7247
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-10 16:43:23 +01:00
Aaron Durbin 1a7da5c3ee x86: simplify early_variables.h header
The CAR macros and the associated functions are only employed
under the following conditions:
- chipsets which have CAR
- compilation during romstage
Therefore clean up the build-time conditionals to use those 2
constructs.

Change-Id: I2b923feeb68f2b964c5ac57e11391313d9c8ffc5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8634
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-10 14:26:14 +01:00
Gerd Hoffmann db9d169ddb qemu: 2.1+ smbios tables support
Starting with version 2.1 qemu provides a full set of smbios tables
for the virtual hardware emulated, except type 0 (bios information).

This patch adds support for loading those tables to coreboot.
The code is used by both i440fx and q35.

Change-Id: Id034f0c214e8890194145a92f06354201dee7963
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/8608
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-10 10:44:46 +01:00
Julius Werner dbe0df1992 Add and consistently use wrapper macro for romstage static variables
x86 systems run their romstage as execute-in-place from flash, which
prevents them from having writable data segments. In several code pieces
that get linked into both romstage and ramstage, this has been worked
around by using a local variable and having the 'static' storage class
guarded by #ifndef __PRE_RAM__.

However, x86 is the only architecture using execute-in-place (for now),
so it does not make sense to impose the restriction globally. Rather
than fixing the #ifdef at every occurrence, this should really be
wrapped in a way that makes it easier to modify in a single place. The
chromeos/cros_vpd.c file already had a nice approach for a wrapper
macro, but unfortunately restricted it to one file... this patch moves
it to stddef.h and employs it consistently throughout coreboot.

BRANCH=nyan
BUG=None
TEST=Measured boot time on Nyan_Big before and after, confirmed that it
gained 6ms from caching the FMAP in vboot_loader.c.

Original-Change-Id: Ia53b94ab9c6a303b979db7ff20b79e14bc51f9f8
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203033
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit c8127e4ac9811517f6147cf019ba6a948cdaa4a5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I44dacc10214351992b775aca52d6b776a74ee922
Reviewed-on: http://review.coreboot.org/8055
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-03-09 22:42:28 +01:00
Stefan Reinauer 408ebe6ad0 console: Fix broken early_print.h include guards
Make compilation fail if this is included in non-romcc compiles.
I am a bit surprised that this ever compiled.

Change-Id: I8dfc1229681819d2381821a0195a89b44dd76b6a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8420
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 22:21:31 +01:00
Kyösti Mälkki bf62b2ddb0 AMD fam10: Drop PCI_BUS_SEGN_BITS
All boards in tree use 0.  Looks like this is all work that was
never completed and tested.

We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.

Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.

Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 19:33:08 +01:00
Kyösti Mälkki 991a71d55c AMD fam10: Fix include of conf.c
Change-Id: I982acb0b36f2cef8281ffbac4511f831f08fc89a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8553
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 19:32:54 +01:00
Alexander Couzens 510d1bd3b0 build.h: remove variable for the builduser, -hostname and -domain
They don't contain any useful information and
also block us from having reproducible builds.

Change-Id: Ib03887f6a548230de9f75fb308c73a800e180c48
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8616
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-09 17:53:16 +01:00
Kyösti Mälkki bd29530061 AMD fam10: Remove __PRE_RAM__ from ramstage-only code
Change-Id: I41aba81def13c99671eb609dd1e76a9a45299622
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8552
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 06:00:41 +01:00
Kyösti Mälkki 5ef269b5a3 AMD fam10: Always have AMDMCT
Also drop some more #if UNUSED_CODE.

Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8551
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 06:00:07 +01:00
Kyösti Mälkki c0ee937e92 AMD K8: Fix allocation size for HyperTransport links
There is no requirement that in dev->link_list the last element
would have the highest link->link_num.

Also fix off-by-one error when allocating for more links.

Change-Id: Id8a7db3ffb4111eb31e70ea14fd522b70368dd8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8550
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 05:59:47 +01:00
Kyösti Mälkki 11c79d7fc2 AMD K8: Move the test for connected HyperTransport link
Change-Id: I7f8cbfcae7ec2a49e91ceda1eecdcf76b2137d8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8549
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 05:59:28 +01:00
Paul Menzel e0b6fbde41 google/samus/acpi/mainboard.asl: Correctly align comment
Fix up commit 00aedc5e (samus: add acpi resource for supporting RT5677
codec).

Change-Id: I98b8c6f1a46f9f3bfd79da92bb070cebe8f20dc0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8234
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 03:36:36 +01:00
Paul Menzel bdaeea5396 cpu/Kconfig: Make in-tree microcode generation dependent on BLOBs repository
Since commit ee894357 (cpu/intel (non-FSP): Use microcode from
blobs repository), selecting the option to generate the
microcode from tree fails without allowing to use the BLOBs/
3rdparty repository, which is the default setting.

Therefore, only show the option, if the user has selected the
option to allow the use of the BLOBs repository.

Change-Id: Ide20da0f946aae43dc2c8cdce54941c704d3d288
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8627
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 03:35:33 +01:00
Kane Chen 9604474d4c broadwell: enable PCIe endpoint CLK power management
BUG=chrome-os-partner:31424
BRANCH=none
TEST=build only, due to I don't have broadwell system with wifi to test
     need somebody help me to verify
Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/8448
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 03:33:52 +01:00
Kane Chen 18cb1340f1 device/pciexp: Add support for PCIe CLK power management
Set PCIe "Enable Clock Power Management", if endpoint supports it.

BUG=chrome-os-partner:31424
BRANCH=none
TEST=build and boot on rambi, check Enable Clock Power Management
     in link control register is set properly

Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220742
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
[Edit commit message.]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8447
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 03:33:13 +01:00
Aaron Durbin 2c4aab3fd6 coreboot: fix munged license text
At some point the license text for a file was incorrectly
changed. That license was then copied and pasted. I'm sure it
was myself. Anyhow, fix the bustedness.

Change-Id: I276083d40ea03782e11da7b7518eb708a08ff7cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8620
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-09 02:32:19 +01:00
Stefan Reinauer f69a27bcd3 device: drop i915 specific headers from resource allocator includes
src/include/device/ is the place for include files of the resource
allocator. Hence, drop the i915 include file copies and use the ones
supplied with the i915 driver instead. The only remaining user of this
was the Intel Whitetip Mountain 2 reference board, all other occurences
have been previously fixed already.

Change-Id: Ib9f72df4e8f847597508971e9dbf671f49019767
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8140
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-08 16:16:29 +01:00
Timothy Pearson b6fa61a121 northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later
The BKDG for K10 revision D and later processors recommends a smaller
MCT burst write queue depth when using unganged memory.

TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431
processors.

Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-07 22:50:07 +01:00
Kyösti Mälkki 982473536b AGESA: Move agesawrappers related to HAVE_ACPI_RESUME support
This change brings all agesawrappers in a single file to make it
easier to understand the actual execution flow.

Change-Id: Ifbb2b16e4cccfaa17aaf10887a856797be9b6877
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8605
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:23:13 +01:00
Kyösti Mälkki 82fbda76c9 AGESA: Use same HeapManager for all BiosCallOuts
We do not allow platforms to mess around with memory layout.

Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:22:44 +01:00
Kyösti Mälkki 0127c6c808 AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
Make the build tolerate re-definitions.

Change-Id: Ia7505837c70b1f749262508b26576e95c7865576
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8609
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:22:20 +01:00
Aaron Durbin c13fc15a45 t132: add Kconfig option for MTS microcode directory
In order to make sharing of the location of MTS microcode easier
provide a Kconfig option that is the path to the files.

BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built rush coreboot.

Original-Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207839
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6f1de0e7fd312c1d6798e65d4b43d586f0994337)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I660cb9d8bd13c765c89b54b0807b5b3ee836e807
Reviewed-on: http://review.coreboot.org/8614
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-07 17:52:00 +01:00
Aaron Durbin df324f5a10 tegra132: add preboot MTS to bct generation
The preboot MTS microcode needs to be supplied within the
bct so the BootROM can load it. The size of the bootblock
space in SPI needed to be extended to accomodate the extra
length.

BUG=chrome-os-partner:29059
BUG=chrome-os-partner:29060
BRANCH=None
TEST=Built rush with updated cbootimage with t132 support.

Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204940
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11
Reviewed-on: http://review.coreboot.org/8466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-07 17:51:46 +01:00
Patrick Georgi a425b96091 AMD Fam10h: Only create _PR scope if it is filled in
The former pstates_algorithm() function has two early exit
points now, and so it might never get around to writing
pstates data.

Change-Id: I19ca937375c6d33b78bd5b1859fa5c25473be9b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8610
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-06 22:30:13 +01:00
Patrick Georgi aab66b1dc7 AMD Fam10h: sanity check some CPU data
If a certain register returns crap values, we
determine core_power using an uninitialized variable.
That doesn't sound healthy.

Change-Id: I1e890b78bfcc3bf0255a3d4f6561a783134b1719
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8508
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-05 20:57:33 +01:00
Vadim Bendebury f752d013b0 storm: Provide ability to build ap148 variant
With BOARD_VARIANT_AP148 configuration option enabled the image will
be built for 512MB DRAM instead of 1024MB and the
mainboard_part_number field in the lb_mainboard entry will be set to
"AP148" instead of "Storm".

BUG=chrome-os-partner:30440
TEST=manual
   . built and booted both AP148 and proto0 all the way to reading the
     kernel
   . verified that the config file includes correct part number and
     memory size
   . verified proper machine IDs reportted when starting the kernel

Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207427
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a
Reviewed-on: http://review.coreboot.org/8590
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-03-05 17:33:38 +01:00
Aaron Durbin 30cda7e83f arm64: provide early SoC initialization
Some of the SoC's need an early hook to configure
certain registers. One example of this is on t132
where ramstage is the first thing being ran on the
arm64 core and it is the only entity that can configure
certain registers required for the rest of ramstage.
Therefore, provide the opportunity for the SoC to
implement such requirements.

BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran through coreboot.

Original-Change-Id: Ib352f3788872f888581b398c9b394b7c4e54b02a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208061
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2c50e2b39e75d1383e8e573c576630a5b7313349)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I38df63e46c5c21b2d319fc9eb42053c3a0d61bc8
Reviewed-on: http://review.coreboot.org/8595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05 17:33:11 +01:00
Aaron Durbin 072e0cc899 rush_ryu: Add new mainboard
This is a clone of rush for the time being. All the incompatible
bits can be moved later. Additional patches to follow.

BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built coreboot for rush_ryu board

Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207838
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab
Reviewed-on: http://review.coreboot.org/8594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05 17:32:50 +01:00
Aaron Durbin 5f66b52464 tegra132: add support for TZ carve-out
The TrustZone carve-out needs to be taken into account when
determining the memory layout. However, things are complicated
by the fact that TZ carve-out registers are not accessible by
the AVP.

BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and booted to end of ramstage. Noted that denver cores
     can read TZ registers while AVP doesn't bother.

Original-Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207835
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit a4d792f4ed6a0c39eab09d90f4454d3d5dc3db26)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8fbef03d5ac42d300e1e41aeba9b86c929e01494
Reviewed-on: http://review.coreboot.org/8593
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-03-05 17:32:19 +01:00
Furquan Shaikh 9c8cfc5c25 coreboot arm64: Add proper masks for setting SCTLR and SCR regs to 0 at init
Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.

BUG=None
BRANCH=None
TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.

Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207815
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9
Reviewed-on: http://review.coreboot.org/8592
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-03-05 17:32:08 +01:00
Aaron Durbin f13c567c97 t132: handle carve-outs for addressable memory
The carve-out regions need to be taken into account when
calculating addressable memory because those regions aren't
accessible from the main cpu. The additional exposed functions
are to accommodate adding resources during ramstage resource
reading. The TZ (trust zone) region is empty for now until
more documentation is provided on determining its location.

BUG=None
TEST=Built and booted through attempting payload loading.
     MTS carve-out is taken into account programmatically.

Original-Change-Id: I3301b2a12680ad79047198ada41f32eb1b7fa68b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207585
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 15b9c74dd1ef5bfb1fd7c6dab50624f815658e14)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I46d54dbbb8e102fc70ab34bc4bbd2361ef1ea504
Reviewed-on: http://review.coreboot.org/8591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-05 17:31:42 +01:00
Aaron Durbin eeacf74a7c t132: Enable cbmem console support
Enabled CBMEM support for t132 platforms. Some of the existing
code is moved around to avoid dependencies in the other stages
that need it.

BUG=None
BRANCH=None
TEST=Built and booted a rush with cbmem support.

Original-Change-Id: I78a31b58ab9cc01a7b5d1fffdb6c8ae0c446c7dd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207163
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f552197dbda06c754b5664c3bed4ed361154229a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8fa2919714b467cc976e5bb5c4716e5b7979694b
Reviewed-on: http://review.coreboot.org/8589
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05 17:31:26 +01:00
Aaron Durbin 5626d8f59a t132: bring up 64-bit denver core
The startup sequence for cpu0 is implemented while also
providing a trampoline for transitioning to 64-bit mode because
the denver cores on t132 come out of cold reset in 32-bit mode.
Mainboard callbacks are provided for providing the board-specific
bits of the bringup sequence.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through ramstage.

Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207263
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97
Reviewed-on: http://review.coreboot.org/8586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-05 17:31:04 +01:00
Werner Zeh c42a613ff5 mainboard/siemens/mc_tcu3: Add new mainboard.
This mainboard is based on Intel's Bayleybay
board which uses Bay Trail CPU with Intel FSP.
It has one USB3.0 interface, 4 USB2.0 interfaces,
up to two Ethernet ports and a LVDS connection
for LCD panels. The board is equipped with 512 MB
of DDR3 in a memory down configuration.

This board boots into Ubuntu/Lubuntu 14.10 using SeaBIOS,
but other OSes should work as well (but are not tested).
It has a version.hex file which is needed for
our OS and has no hardware functionality.

Change-Id: I94401bbd1d61ec69703de38ae1bc97969c5d979e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8430
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 14:19:40 +01:00
Werner Zeh 0f9c9de35a fsp_baytrail: Add I2C driver
Add a driver wich can handle the internal I2C controllers
of Baytrail SoC. This driver is not suitable for the
SMBus controller.

Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8401
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 14:19:34 +01:00
Werner Zeh b5a374d58b fsp_baytrail: Add new microcode for Bay Trail M
Add a new microcode for Bay Trail M D0 stepping used
in cpu N2807 silicon.
In addition, a selection of the used CPU type has
been added (I or M/D) which allows to use only the
really needed microcode for a given CPU type.

Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 12:45:10 +01:00
Alexandru Gagniuc fb9d4caf16 mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variable
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8498
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 09:33:47 +01:00
Aaron Durbin bc772c3f3d arm64: Set 16 byte alignment and ramstage start address
To align with arm use the RAMSTAGE_BASE Kconfig option
for start of ramstage. Also, use 16-byte alignment for the
start and end of the sections. 4 bytes were previously used, but
it definitely seems more appropriate to at least have the heap
handing out 16-byte aligned pointers.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through attempting to load payload

Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207432
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550
Reviewed-on: http://review.coreboot.org/8588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04 20:04:46 +01:00
Aaron Durbin 00263d0d8e arm64: remove assembly code string functions
Inconsistent progress was observed running ramstage.
It was determined that the hand-coded assembly functions
were causing issues. Some of the comments seems suspect about
the hardware taking care of alignment. The prudent thing to do
is to use the C ones. Optimization can come later after maturity.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted to attempting to payload

Original-Change-Id: I4137adf9b36b638ed207e4efd57adaac64c6a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207431
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2762e478c6b59dd30c59aa87a922d0f78c00c0c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id3196b0c2bf41a21db31f999ba437d118875a236
Reviewed-on: http://review.coreboot.org/8587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-03-04 20:04:18 +01:00
Aaron Durbin 0df877a65a arm64: use one stage_entry for all stages
Ramstage needs an assembly entry point for setting up
the initial state of the CPU. Therefore, a function is
provided, arm64_el3_startup(), that bootstraps the state
of the processor, initializes the stack pointer, and
branches to a defined entry symbol. To make this work
without adding too much preprocessor macro conditions
provide _stack and _estack for all the stages.

Currently the entry point after initialization is 'main',
however it can be changed/extended to do more work such
as seeding the stack contents with tombstones, etc.

It should be noted that romstage and bootblock weren't
tested. Only ramstage is known to work.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Brought up 64-bit ramstage on rush.

Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207262
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949
Reviewed-on: http://review.coreboot.org/8585
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 20:00:18 +01:00
Aaron Durbin 6ba1b628ee arm64: ensure vital sections aren't garbage collected
The driver structures live in special sections which have no
direct reference to the symbols. Therefore, when garbage
collecting sections in the linker the drivers are tossed out
resulting in no drivers being linked into ramstage. Fix this
by adding the KEEP() directive to those special sections.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and noted console starts working in ramstage.

Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207261
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4
Reviewed-on: http://review.coreboot.org/8584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04 19:59:46 +01:00
Furquan Shaikh e5d014c29a coreboot t132: Stack init re-work
1) In order to avoid stack from overflowing during ramstage decompression,
initialize stack right at the beginning of romstage.
2) Declare different Kconfig options for stack at each stage.
3) Provide a macro that does stack seeding if required and calls appropriate
function.

BUG=None
BRANCH=None
TEST=Compiles and runs successfully on rush.

Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206880
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd
Reviewed-on: http://review.coreboot.org/8583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 19:58:30 +01:00
Tom Warren dfe7ea2b4e rush: PMIC: initial AS3722 PMIC writes for Rush
Still waiting on VDD_CPU value, etc. from board guys, but this is a start.

BUG=None
BRANCH=None
TEST=Built and flashed rush, saw 'PMIC init done' string OK.

Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206412
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2
Reviewed-on: http://review.coreboot.org/8582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 19:56:26 +01:00
Aaron Durbin d2907c1e02 t132: kick off core complex after loading MTS microcode
Once the MTS microcode is loaded the core complex can be
directed to decode the MTS and start running. The cores,
however, won't start executing until instructed to do so.

BUG=chrome-os-partner:29222
BRANCH=None
TEST=Built, booted, ran. Noted it took about 920ms for the
     core complex to decode and handshake back.

Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206075
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e
Reviewed-on: http://review.coreboot.org/8581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04 19:55:56 +01:00
Furquan Shaikh 196ee2b029 coreboot memrange: Two changes for zero size or empty memrange
1) Add check for zero size in memrange.
2) Add public memrange_init_empty function to allow initializing only the
memrange structure without filling in device resources

BUG=None
BRANCH=None
TEST=Compiles and runs succesfully for rush MMU memranges.

Original-Change-Id: I8e4d864cbc9a770cd208f8a9f83f509dc7ace894
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208957
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5c42301c2a51a1a2a29ef58012f210d03bd37f94)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8d63abb15efda74270ef6fa3c0df55c05659595d
Reviewed-on: http://review.coreboot.org/8597
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-04 19:55:19 +01:00
Aaron Durbin 3aca2cdced t132: load MTS microcode
The armv8 cores need to have microcode loaded before they can
be taken out of reset. Locate and load the MTS microcode at the
fixed address of 0x82000000. The ccplex, once enabled, will
decode and transfer the microcode to the carveout region.

BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and ran. Confirmed dump of MTS region after loading code.

Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df
Reviewed-on: http://review.coreboot.org/8580
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04 19:51:42 +01:00
Stefan Reinauer 73307e0917 Add stage information to coreboot banner
As a convenience, print the actual stage name when entering a stage.
Also unify the banner between bootblock / romstage and ramstage. No
reason for two different occurences.

Instead of this:

coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...

you will see this:

coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting...

Roughly based on: https://chromium-review.googlesource.com/199671

Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8578
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-04 19:46:25 +01:00
Aaron Durbin 8ddc1f328a rush: enable 128MiB MTS carveout below top of DRAM
The recommended settings for the size of the MTS region is 128MiB.
Therefore, provide this region 128MiB below the top of DRAM for
each configuration.

BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and noted MTS carveout region at expected location.

Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206291
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I369a3897e31f3126d031d3582f52f9892350f658
Reviewed-on: http://review.coreboot.org/8579
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:25:52 +01:00
Marc Jones 0e69639909 t132: Replace fallback with CONFIG_CBFS_PREFIX
Use the Kconfig value to load the name of the stage instead of the
hard-coded fallback stage.

(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b
Reviewed-on: http://review.coreboot.org/8576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:25:18 +01:00
Aaron Durbin 1ac4e591bf t132: Add shared romstage
There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.

BUG=None
BRANCH=None
TEST=Built and booted to same place as before.

Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:24:18 +01:00
Furquan Shaikh 650d11ce94 coreboot rush: Add dram init code
Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.

BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5

Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:23:46 +01:00
Furquan Shaikh d42b3fc6a9 coreboot rush: Add support for basic romstage
Add basic romstage support for rush. Since, dram init needs to be done before we
can jump to armv8 core, romstage will run on armv4 core as well. Thus,
correcting the compiler selection options.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Prints romstage banner and initial printk

Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205763
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a
Reviewed-on: http://review.coreboot.org/8573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04 18:23:11 +01:00
Furquan Shaikh b68cb9e8ae coreboot t132: Enable loading of romstage from CBFS media
Add proper Kconfig options and initialize cbfs media to enable loading of
romstage

BUG=None
BRANCH=None
TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer
for romstage

Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205762
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78
Reviewed-on: http://review.coreboot.org/8572
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:16:27 +01:00
Furquan Shaikh f0d150e0ba coreboot t132: Remove init pllx for now
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source
for the CPU cluster). So, remove the init call for pllx. This needs to be added
later when required. Also, add a few more printks to display the progress.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Print messages seen on serial console.

Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205680
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81
Reviewed-on: http://review.coreboot.org/8571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:16:09 +01:00
Furquan Shaikh 84bbab9226 coreboot t132,rush: Add mainboard specific bootblock_init
Pull in mainboard specific bootblock_init function from nyan into
rush. Additionally, pull in all files required for proper compilation of rush
after adding the bootblock_init function

BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205583
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795
Reviewed-on: http://review.coreboot.org/8570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:15:44 +01:00
Timothy Pearson a89accd74f cpu/amd/model_10xxx: Documentation update
Change-Id: Ic29009be42ef77261a3b535327cf5c12761023c1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:16:22 +01:00
Timothy Pearson ead8751367 cpu/amd/model_10xxx: Refactor model detection to reduce code duplication
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.

Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:15:55 +01:00
Furquan Shaikh 29c1afce62 coreboot t132: Add clock.c to all three stages of coreboot
Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code
for enabling armv8 core is not included yet. clock_init added to bootblock.c

BUG=None
BRANCH=None
TEST=Compiles successfully for rush.

Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205581
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I688e1e1373dea26557a84507a8e92d3055862801
Reviewed-on: http://review.coreboot.org/8569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-03 18:53:10 +01:00
Timothy Pearson 226fc941af northbridge/amd/amdmct: Add revision D to K10 revision mask list
Change-Id: Ib5f87bdc50c0bca370a636218d3b5d4cc9157c12
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8501
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-03 06:36:14 +01:00
Furquan Shaikh 67b0374649 coreboot arm64: Correct cache function names
Correct function names to make them consistent with generic calling name

BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205582
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 16668529527224fca3086ee88955d29e3a268516)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317
Reviewed-on: http://review.coreboot.org/8469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02 22:19:56 +01:00
Furquan Shaikh d653ae8960 coreboot arm: Define function for setting cntfrq register
Define functions for setting cntfrq register in arm and arm64 arch. This allows
SoCs to set this register independently of the architecture being used.

BUG=None
BRANCH=None
TEST=Compiles successfully for nyan and rush

Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205580
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6)

armv8: GPL license armv8 lib

BUG=None
BRANCH=None
TEST=Compiles successfully.

Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)

Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a
Reviewed-on: http://review.coreboot.org/8468
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02 22:19:46 +01:00
Furquan Shaikh 732b83ed36 tegra132: Enable bootblock support in tegra132 including UART support
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203143
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3)

This cherry-pick was modified to match the tegra124 uart.c, which
uses the idx and base address calculations instead of Kconfig settings.
This driver could use the 8250MEM driver when the ARM vs x86 IO
calling convention is worked out.

Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8517
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02 21:17:21 +01:00
Kyösti Mälkki 280a29d5bb devicetree: Drop redundant scan_bus() ops
Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8533
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:55:22 +01:00
Kyösti Mälkki 85756c14e9 devicetree: Drop dummy root_dev ops
This is just dead code.

Should we decide that we want some of these calls made, they would
be implemented in the mainboard context.

Change-Id: I1f097c8da722f3afab9aa1c80b96590c7ca457d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8532
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:53:58 +01:00
Kyösti Mälkki 976d91c07e AGESA fam16: Drop HyperTransport scan
Already done for fam15tn/rl.

Change-Id: Id74ca13610a4ef407c866a4419139287413078a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:48:11 +01:00
Alexandru Gagniuc 5818da262d cpu/intel: (non-FSP) Remove microcode updates from tree
Now that we use the microcode updates in the blobs repository, remove
them from the main repo. Since the microcode updates are blobs, it
makes more sense to ship them in the blobs repo rather than the main
one.

The update-microcodes.sh script is also deleted, as a more current
version resides in 3rdparty.

Change-Id: Iee74a3ede3b5eb684ef0386d270120e70173c1b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4531
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28 08:21:15 +01:00
Alexandru Gagniuc ee89435798 cpu/intel (non-FSP): Use microcode from blobs repository
Now that microcode has been added to blobs, use that one instead of
the one included in the tree. Microcode from the tree will be
removed in a subsequent patch. Since the microcode updates are blobs,
they belong in the blobs repository.

This change may introduce a build failure if the "Generate from tree"
microcode option is selected, but the blobs repository is not
enabled. We have to live with this for now, until microcode is moved
to blobs for all CPUs, at which point we may adjust Kconfig
accordingly.

Leave the FSP  cpu alone for now, as that will need approval from
SAGE.

Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28 00:14:49 +01:00
Kevin Paul Herbert 4104e6cd30 x86: Fix pointer arithmetic regressions from MMIO changes
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).

Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.

Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-27 18:15:33 +01:00
Timothy Pearson c684d05b0f mainboard/asus/kfsn4-dre: Enable W83793 fan controller
The Winbond W83793 fan controller is not automatically
configured correctly on power application, leading to
abnormal, and in some cases random, fan behaviour.

This commit enables the controller and sets sane default
values.

TEST: Booted mainboard and verified that the correct number
of fan speed sensors were visible from hwmon under Linux.
Also verified that, unlike before, the CPU fans were running
at a high enough speed to properly cool the CPUs.  Verified
the 8 fan outputs under direct control of the W83793 device.
Verified voltage and temperature sensors and limits via output
of the 'sensors' command.

Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8503
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-26 06:22:49 +01:00
Timothy Pearson d3e31be8c5 drivers/i2c/w83793: Use devicetree.cb to set additional values
This allows devicetree.cb to set:
Minimum PWM values
Temperature sensor source
Voltage sensor high/low limits
Fan pin routing
Default PWM values
Manual PWM values per-fan

Change-Id: I3a321406a26ae01a121289d24b41c9f988dd6f30
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8502
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-26 06:20:07 +01:00
Aaron Durbin a63da6f97e rush: Correct version field to match t132
The version field for t132 cpus is 0x00130001. Update it to
the correct version.

BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and was able to see serial with subsequent changes.

Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205435
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a
Reviewed-on: http://review.coreboot.org/8467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25 20:08:23 +01:00
Furquan Shaikh 26a8747cca coreboot arm64: Add library for system access
Add support for library functions required to access different system registers:
1) PSTATE and special purpose registers
2) System control registers
3) Cache-related registers
4) TLB maintenance registers
5) Misc barrier related functions

BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203490
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb)

armv8: GPL license armv8 lib

BUG=None
BRANCH=None
TEST=Compiles successfully.

Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)

Get the library and the GPL license in a single commit.

Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d
Reviewed-on: http://review.coreboot.org/8465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-25 20:01:44 +01:00
Marc Jones 595a40cfc9 tegra124: Clean up ARM UART driver build
CONFIG_CONSOLE_SERIAL_UART has been updated to
CONFIG_DRIVER_UART. The UART may be used for more than serial console.

Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8516
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25 19:48:51 +01:00
Marc Jones d8ea0ba5a8 arm64: Remove early_console.c
The early_console.c file isn't used or built. It has been replaced
by the generic uart and console drivers.

Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25 19:42:00 +01:00
Paul Menzel 21a530981d soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`
Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which
selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already
selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`).

Therefore remove the explicit selection of that Kconfig option.

Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25 16:21:23 +01:00
Patrick Georgi f3a235e977 intel/broadwell: free local heap object
No real harm done (thanks to our free() implementation),
but let's do it right.

Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8511
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-25 14:05:45 +01:00
Patrick Georgi bdd185a355 amd/sb600: Fix NULL test after use issue
Change-Id: Icecbcc1dee837ecfe0dd52bade3b83fdcdd15bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8513
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-25 14:05:42 +01:00
Kyösti Mälkki 9b5f137823 Intel ibexpeak: Fix SATA configuration
It got broken with commit bde6d309.

Change-Id: I0d7180b1659da45bf87d4de46b7b387cbc73cd0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24 11:49:32 +01:00
Werner Zeh 63693dca06 drivers/intel/i210: Add new driver for Intel i210 MACPHY
Add a new driver for Intel i210 MACPHY with the goal to
update the MAC address in i210 if it is found
during PCI scan.

Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8404
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-24 07:08:11 +01:00
Alexandru Gagniuc 5b4b024af2 (bakersport|bayleybay)_fsp: Do not force a default loglevel
DEFAULT_CONSOLE_LOGLEVEL_* is supposed to be selected by the user, and
should not be overriden by any other part of the tree. As such, remove
the selection of DEFAULT_CONSOLE_LOGLEVEL_7 from these two boards.

Change-Id: I194a71b371b184e81a16fec2bd21f1b0deb4ebbf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24 06:41:31 +01:00
Alexandru Gagniuc 1896996589 mainboard: Do not redefine CONSOLE_POST Kconfig variable
This option is already defined in console/Kconfig, and is intended
to be controlled by the user. Only six boards in the entire tree
redefined it, so remove the definition from those boards.

Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8457
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24 06:41:16 +01:00
Alexandru Gagniuc eb73a21882 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables
SUPPORT_CPU_UCODE_IN_CBFS is a deprecated option now that all CPUs
with updateable microcode (except AGESA) load microcode from CBFS.
CPU_MICROCODE_ADDED_DURING_BUILD is a state variable that is set
based on user's choice in the microcode menu and should not be changed
directly.

Eliminate INCLUDE_MICROCODE_IN_BUILD variable, whose use directly
interferes with the microcode mechanism, remove selection of
CPU_MICROCODE_ADDED_DURING_BUILD, and do not depend
SUPPORT_CPU_UCODE_IN_CBFS on anything. This makes usage of the
microcode mechanism consistent with other CPUs in the tree.

This incorrect usage of the Kconfig variables was hiding the fact that
some of the microcode files present in fsp_baytrail/microcode_blob.c
were not present in the tree.

Change-Id: I71cb3f834c22c0363a20bd469797a9f51c215371
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24 06:41:05 +01:00
Kyösti Mälkki b5a8a13bde pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.

Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.

Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:36:21 +01:00
Kyösti Mälkki 07354235df pcengines/apu1: Fix and clean up devicetree
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware.

Disable 0:14.1 IDE controller, as it would only be used with SATA ports
4 and 5 that are not populated with connectors in the hardware.

Disable 0:14.2 HD audio, as it is not implemented in the hardware

Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller
are not populated in the hardware.

Fix some alignment and whitespace.

To my knowledge these changes are not included with SAGE release
pcengines.apu_139_osp.tar.gz, but that tarball does not contain
either devicetree.cb or a pre-compiled static.c file so I cannot tell
for sure.

Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:35:48 +01:00
Kyösti Mälkki 5d899c4217 pcengines/apu1: Fix PCI device 16 interrupts
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed
in PIC mode. The only affected peripheral was the SD card reader.

This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz.

Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8327
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-02-23 21:35:17 +01:00
Kyösti Mälkki 780935687d pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.

As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.

Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:34:55 +01:00
Kyösti Mälkki 8c190f3518 pcengines/apu1: New board PC Engines APU1
While we cannot recreate exact copies of PC Engines APU1 firmware images,
I shall upstream the vital changes for coreboot from the following tarballs
SAGE has published to meet GPL:

SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz
md5sum: ce5f54723e4fe3b63a1a3e35586728d4

pcengines.apu_139_osp.tar.gz
md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef

The patch here adds Kconfig, Makefile.inc and devicetree.cb files to
match 2014/04/05 release tarball config.h and static.c files.

Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:34:21 +01:00
Kyösti Mälkki f09e6d47b8 pcengines/apu1: Fork of amd/persimmon
Drop persimmon customization for superio, azalia, PCI-e reset etc.

Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:34:05 +01:00
Kyösti Mälkki 0b87bb7726 AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins
Some GPIO pins are shared with PCI bridge 0:14.4.

As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.

Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2015-02-23 21:33:55 +01:00
Patrick Georgi 477b4c539a AMD Fam10h: Don't write uninitialized data into ACPI
The goto statement skipped all the code that is necessary
to fill in the data structures that are read right after
the jump.

Since there doesn't seem to be useful data, why write these
ACPI objects in the first place?

Change-Id: I1d06c11a7a31517b81e54159355d5c27e3cc3735
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 20:33:45 +01:00
Patrick Georgi b4ad5d0a93 drivers/xgi: Avoid double-free
xgifb_probe() doesn't own the object it tries to free
in its error code path, potentially leading to a
double-free in xgi_z9s_init().

Since we don't actually implement free, it doesn't matter
too much, but let's keep things proper.

Change-Id: I70c8f395fd59584664040ca6e07be56e046c80fc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8506
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-23 20:33:38 +01:00
Dave Frodin 1f565b4023 Remove */cpu/amd/agesa/* from excluded illegal globals file
The change in commit 5636237 allows */cpu/amd/agesa/* to be removed.

TEST: Booted the amd/parmer board.

Change-Id: I8d2d2639f8e5f3b1dd58be96be98db0eff7b268f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8505
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-23 10:39:43 +01:00
Dave Frodin b85656f285 cpu/amd/agesa: Use alloc_cbmem() only in ramstage
This copies a change made in commit 1cc3338 that allows alloc_cbmem()
to be called only in ramstage. This will allow the */cpu/amd/agesa/*
field to be removed from the list of illegal_globals EXCLUDE_FILEs.

TEST: Booted the amd/parmer board.

Change-Id: I2d4b5352815aae090ffce7b83e487f7c0a4d0c88
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-23 10:39:39 +01:00
Patrick Georgi d3f3df3c6d drivers/xgi: terminate file with newline
That's just how we roll.

Change-Id: I47ef62476703fdf2544d9cd77c30ae12452afeae
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8514
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 09:46:10 +01:00
Werner Zeh a8b03da4a8 drivers/pc80/mc146818rtc: Enable RTC reset on power loss
If function cmos_init() was called with parameter invalid
set, this indicates, that the caller has found a power
loss event in the RTC registers. In this case, we need to
load the default date and time because it can be corrupted.

Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8373
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-23 09:09:25 +01:00
Timothy Pearson bc1abb12a9 drivers/i2c/w83793: Remove incorrect zeroing of PWM values
Fan 2 and Fan 3 were inexplicably set to zero after device
setup.

Change-Id: I37945745dbfaf33eb28808d85cdf75dca401e44b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8520
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-23 08:32:45 +01:00
Dave Frodin 1cc3338c1d cpu/amd/pi: Use alloc_cbmem() only in ramstage
Without this change the builder would fail with the complaint
that there was a global static variable in romstage. alloc_cbmem()
is only called in ramstage. The alternative was to add
*/cpu/amd/pi/*.romstage.o to the list of illegal_globals
EXCLUDE_FILEs in arch/x86/init/romstage.ld.

TEST: Booted the amd/lamar board.

Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21 00:27:17 +01:00
Bruce Griffith fa0ab8cfc2 AMD Bald Eagle: Add CPU subdirectory files for new AMD processor
This adds the AMD Family 15h model 30 CPU.
S3 suspend/resume currently is not supported.

Tested on the amd/lamar platform.

Change-Id: Ifef55747a5d715b17937fc75ab9d35945b59f0e6
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21 00:24:44 +01:00
Alexandru Gagniuc e5ccbfd290 cpu/allwinner/a10/twi.c: Refactor I²C handler to use i2c_seg API
The coreboot I²C API was completely reworked in commit
* cdb61a6 i2c: Replace the i2c API.

For the allwinner I²C driver, wrappers to the old API were provided
on a "best guess" basis. Replace these wrappers with proper
transaction handling based on the i2c_seg API.

Change-Id: Ibdda3b022ce4876deb2906e17a5a0ca9e939aada
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8431
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-20 23:24:17 +01:00
Alexandru Gagniuc 1959abd790 drivers/xpowers/axp209: Adapt to new I²C API
Originally, axp209_(read|write) accessors relied on i2c_(read|write)
to return the number of bytes transferred. This was changed in
* cdb61a6 i2c: Replace the i2c API.
to return an error code or 0 on success. This caused the AXP209 check
to fail. Fix the accessors to account for this new behavior.

Change-Id: Ib0f492bd52260d224d87f8e8f2d3c1244d1507df
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8432
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-20 23:20:56 +01:00
Kyösti Mälkki c5163ed83b AMD binaryPI: Drop HT3_SUPPORT
Kconfig variable is not implemented.

Also fix broken abuild.

Change-Id: I569f44e97abc570158472ddbd0f890315233f8a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8494
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-20 07:56:09 +01:00
Kyösti Mälkki 7255062ea7 AMD fam10: Refactor variables in scan_chain
We only need one of devx and dev. This function should be called
with dev already adjusted if link_num > 3.

Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8351
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:06:12 +01:00
Kyösti Mälkki e40beb1f79 AMD fam10: Move the test for connected HyperTransport link
Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8350
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:05:38 +01:00
Kyösti Mälkki 26c664759b AMD K8 fam10: Refactor offset_unitid configuration
Change-Id: I198f2ad321e1a8b6d932f5624b129e312e36a309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8349
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:04:00 +01:00
Kyösti Mälkki f5e7fa22e7 AMD amdfam10: Always have HT3_SUPPORT
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:43 +01:00
Kyösti Mälkki 260a6db7ec AMD K8 fam10: Drop link_num from scan_chain parameters
Change-Id: Id8fc1d7d8a23238e6848cd2cf4270d782e90a7d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8347
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:25 +01:00
Kyösti Mälkki fe57eeb5bf AMD K8 fam10: Remove some excessive preprocessor use
Change-Id: Iee51c51b662d1f5e3d918d1e5b961f06c6b99df6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8346
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:12 +01:00
Vladimir Serbinenko d15bddab57 sandybridge: Try lower frequency if PLL didn't lock.
Change-Id: I2c2d586fc572b78b5019f8ef2714959799a8d2a9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8480
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-19 00:21:31 +01:00
Dave Frodin 891f71a541 amd/00730F01: Move SteppeEagle specific settings to northbridge
These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.

Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-18 18:55:56 +01:00
Alexander Couzens 452efc23b9 cpu/intel/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1
They seem to have been copy-pasted during the backport from sandybridge.

Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8295
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-18 12:40:31 +01:00
Timothy Pearson a2f79d5971 cpu/amd/model_10xxx: Add monotonic timer support
Change-Id: Idf37d51c6b53ae85dc96fb609531ceda06ec948c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8470
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-18 01:26:51 +01:00
Patrick Georgi d6e40a5942 tegra132: Postprocess bootblock properly
It's not very useful to try to link a host tool into
the bootblock image.

Change-Id: Id3b6496c061d41184fbb516d56746855b455b0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/8473
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-17 18:11:01 +01:00
Alexandru Gagniuc 8b2c8f1c10 sandybridge/raminit: Get max mem clock from devicetree
Note that the limit is not set in the devicetree.cb which use native
sandybridge raminit, as it is not needed. When that isn't set, it's
automatically set to zero, and when we find that, we automatically
return the default limit. Thus behavior isn't changed for any board.

Change-Id: I447399eea71355612b654710a56f3a0077c2f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8476
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17 17:38:50 +01:00
Alexandru Gagniuc fe951d899d sandybridge/raminit: Do not die() if timC calibration fails
We can successfully bring up systems if timC calibration fails, as has
been demonstrated with google/butterfly. As a result, do not die(),
but simply print a message and continue in the hope that we may be
able to boot.

Change-Id: I49ec80324f63b2d45ae8f61c5c26454acb9c232f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8475
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17 17:37:37 +01:00
Furquan Shaikh f0990dac1e tegra132: Add BCT support in tegra132 soc
Builds with cbootimage.

BUG=None
BRANCH=None
TEST=build test

Original-Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203145
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 4778ae4d08a25306407f0fd2fe47976d63463f9d)

Increase the bootblock area for the larger BCT that is generated by
the coreboot version of the cbootimage tool.

Change-Id: I42b8208504bf4936a9fa14f820d665590f6a3754
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8413
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-17 05:25:59 +01:00
Furquan Shaikh d6ba1541ec google/rush: Add BCT support in mainboard rush
Changes might be required for .bct files as we get to know more.
Pulling in files from mainboard nyan for now

BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/203144
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d3633f8cf8c01a07b54ceef2dd7bf7a64afd7c76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8412
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-17 05:25:40 +01:00
Yen Lin ba118cc3a9 T124: perform ram_repair when CPU rail is powered on in warmboot
This patch is to perform software triggered RAM re-repair in
the warm boot path.

"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.

Also, note that this file isn't built in coreboot proper, but is a
companion binary for kernel. It resides here for safe keeping.

BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run suspend_stress_test on nyan.

Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I540f8afbffa323d1e378cb6ba6a20be4afd08339
Original-Reviewed-on: https://chromium-review.googlesource.com/207422
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit f06c413c42819f8f75d9b0fecde02b82583f1d2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I151ce943ce8623e46cc55f890bbd6fc641cc2b98
Reviewed-on: http://review.coreboot.org/8416
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-17 01:16:55 +01:00
Yen Lin 5840626cec T124: perform ram_repair when CPU rail is powered on in coldboot
This patch is to perform software triggered RAM re-repair in
the cold boot path.

"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.

BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run cold reboot test on nyan.

Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I87869431e80e7bc66948a7f67f35e5b907993765
Original-Reviewed-on: https://chromium-review.googlesource.com/207362
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit d999f5ecc31d90c8dce1dd91533bc34ffd3c03f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iaee1d7f9fa8856f26d7ead70eaeeff9d80dbb181
Reviewed-on: http://review.coreboot.org/8415
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-17 01:16:47 +01:00
Jimmy Zhang b365530bb6 tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIME
Based on TRM, cpu clock enabling and reset vector setting should
all be done properly before ungating cpu power partition. Otherwise,
with current code, a race condition could occur where cpu starts but
reset vector has not been set.

BUG=chrome-os-partner:30064
BRANCH=none
TEST=run nyan_big reboot test. No issue is experienced.

Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I571e128693bb2763ee673bd183b8cf60921dc475
Original-Reviewed-on: https://chromium-review.googlesource.com/206682
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 106480ff32406c899a24544fdfab858db5afd1d9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I3da6018dd68e4c15d2c58db566a9745b0b26c365
Reviewed-on: http://review.coreboot.org/8414
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-17 01:16:34 +01:00
Kyösti Mälkki b4fa3fd2ae nvidia/ck804: Minor cleanup on dead code
Change-Id: I07f4190ab73ec3468e3738be14d64468e2a05720
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8340
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:14:18 +01:00
Kyösti Mälkki 413e3da8c0 nvidia/ck804: Fix redundant configuration defines
All code must agree on PCI enumeration for the CK804 device,
define these only once. The definition in enable_usbdebug.c was
different and was assumed incorrect.

Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:14:02 +01:00
Kyösti Mälkki facf0b9361 Revert "nvidia/ck804: Add ability to override CK804 base unit ID"
This reverts commit b871687991.

Use of #ifndef here makes it error-prone and hides errors.

Change-Id: I13a999250c80adedb6b3fd4963a862ff106750f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:13:50 +01:00
Timothy Pearson 2af1e4402b mainboard/asus/kfsn4-dre: Add HT speed limit to NVRAM
Change-Id: Ia4829447835dd26381185c586eaac210dc0591d9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8463
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 21:05:27 +01:00
Timothy Pearson 03259a8794 northbridge/amd/amdht: Get maximum HT link frequency from NVRAM
This patch allows the user to set a maximum HT link frequency in
NVRAM, paralleling a similar option available in the proprietary
BIOS on some mainboards.

Change-Id: Iba3789262eefa52421e76533cbf14d9da2ef1de8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8462
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 21:04:55 +01:00
Timothy Pearson 033bb4bc8d acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9.  The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.

The modified code will function with up to 99 cores.

Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16 21:02:30 +01:00
Timothy Pearson 4f731f2eab northbridge/amd/amdfam10: Remove HT link frequency from Kconfig menu
Change-Id: I48d2cda330d8e8f1e58bc670e4e898479216e576
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8461
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 20:35:19 +01:00
Timothy Pearson 94efd19517 mainboard/cmos: Kill off unused boot_* parameters
Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8460
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:24:14 +01:00
Timothy Pearson c0ae684d16 mainboard/cmos: Move ECC variables out of fallback mechanism byte
Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8458
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:23:44 +01:00
Timothy Pearson 9b68f05fc8 mainboard/cmos: Delete obsolete commented parameters
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8459
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-16 09:23:02 +01:00
Timothy Pearson c5ca13758f mainboard/amd/amdfam10: Update AMD K10 socket F NVRAM layout files
This removes spurious K8 options and adds appropriate K10 options.
File content taken from the functional K10 ASUS KFSN4-DRE board.

Change-Id: I237bb139056f39f21416268cb52d24c5bc5f111d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8456
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:13:09 +01:00
Timothy Pearson 83b556884f mainboard/asus/kfsn4-dre: Remove hard-coded ECC scrub rate
Change-Id: I6ccf44645dabf8ac3674f40d3c5cbcf694aa6237
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8441
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:11:59 +01:00
Timothy Pearson 2b1bcc1253 northbridge/amd/amdfam10: Remove Kconfig memory controller options
All settable memory controller options are now controlled by NVRAM,
making the Kconfig options irrelevant.

Change-Id: I9b2c8798d830e5c41bb9a108514e60d784d2ebc5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:11:32 +01:00
Timothy Pearson 3c206781f2 northbridge/amd/amdfam10: Fold back memory frequency based on MCT load
K10 processors cannot operate at full memory speeds when more than a
certain number of DIMMs are installed on a specific channel.  The
allowed DIMM numbers and speeds are listed in the BKDG; this patch
implements the appropriate frequency reduction to ensure stability.

Change-Id: I8ac5b508915e423d262ad36c49de1fe696df2ecd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:08:12 +01:00
Timothy Pearson a70093611f mainboard/asus/kfsn4-dre: Add memory interleave options to NVRAM
These values were originally hard-coded in the AMD MCT wrapper.

Change-Id: I12056d38d5348e70a44c192385e22e715e207792
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8454
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:05:33 +01:00
Timothy Pearson c936624433 mainboard/asus/kfsn4-dre: Add ECC redirection to NVRAM
Change-Id: Ie7a73a5962e61585ebc427005e72715c8da4e0ac
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8451
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:03:50 +01:00
Timothy Pearson e23d5b0d59 mainboard/asus/kfsn4-dre: Add ECC scrub rate to NVRAM
Change-Id: Iaece709f521aaf6689b71bc0c71606847c3e1e4e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8439
Tested-by: build bot (Jenkins)
2015-02-16 09:02:59 +01:00
Timothy Pearson f20c6e81fe nvram: Add option to reset NVRAM to default parameters on every boot
In specific configurations, such as homogeneous supercomputing systems,
changeable NVRAM parameters are more of a liability than a useful tool.
This patch allows a coreboot image to be compiled that will always set
the NVRAM parameters to their default values, reducing maintainance
overhead on large clusters.

Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 08:36:37 +01:00
Timothy Pearson 5fc1ad101c mainboard/asus/kfsn4-dre: Add default NVRAM settings
Change-Id: Ic86104d6e7811b0bda9279411db84f464324994a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8450
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 08:27:08 +01:00
Timothy Pearson 68c4475df3 mainboard/asus/kfsn4-dre: Fix invalid CMOS enums
Change-Id: Id837445f346e9ab0218ccca12794b519a8a71c0d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8449
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 08:07:34 +01:00
Timothy Pearson 2012b8127b northbridge/amd/amdmct: Fix FTBFS with node interleaving enabled
This fixes errors of the form:
error: 'Dct0MemSize' may be used uninitialized in this function

Change-Id: Ifc853aea9050994f5641c57a081aa0667331c995
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8455
Tested-by: build bot (Jenkins)
2015-02-15 19:27:35 +01:00
Alexandru Gagniuc b93dcec9f4 hp/pavilion_m6_1035dx: Provide CMOS defaults
TEST: Boot with corrupted CMOS and make sure console level defaults
to SPEW, instead of 0, and that cbmem console is not empty.

Change-Id: I8ab2423e99bbe116f52ad27f4b20427d8557f6ff
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8379
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-15 18:15:06 +01:00
Timothy Pearson 068ca9c8fc northbridge/amd/amdmct: Allow override of memory settings via NVRAM
This patch allows the following memory controller settings to be overridden in NVRAM:
Memory frequency limit
ECC enable
ECC scrub rate

Change-Id: Ibfde3d888b0f81a29a14af2d142171510b87655e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8438
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15 17:54:35 +01:00
Paul Menzel eb605d72b2 device/device_util.c: Add space after ellipse for better legibility
Currently the coreboot console log contains messages in the following
form.

	Show all devs...Before device enumeration.
	[…]
	Show all devs...After init.

Add a space after the ellipse, so it’s better readable and it does not
look like a newline is missing.

	Show all devs... Before device enumeration.
	[…]
	Show all devs... After init.

Change-Id: Ifa2a37b8d60c433c219df7533a79fced03b6271a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-15 09:21:09 +01:00
Kevin Paul Herbert bde6d309df x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
2015-02-15 08:50:22 +01:00
Alexandru Gagniuc 4b10dec1a6 cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM
The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions

However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.

Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.

Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 22:54:01 +01:00
Kyösti Mälkki 24501cae52 AMD cimx/sb800: Initially enable all GPP ports
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().

Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:59 +01:00
Kyösti Mälkki 41cd047cd2 AMD cimx/sb800: Move cimx init for ramstage
This has nothing to do with SATA controller. We only need to
fill the table with defaults before we parse devicetree for
changes to device configuration.

Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:44 +01:00
Kyösti Mälkki 8dba709a06 AMD cimx/sb800: Disable unused GPP ports
If devicetree.cb has GPP port off, really disable it before even
trying to do link training.

Change-Id: I810945da28d86768e88249dc4d29a50ad9f9959b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8385
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:33 +01:00
Kyösti Mälkki 486c05f4bf AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration
A set of pins can be configured for GPIO or (parallel) PCI bridge use.

When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.

When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.

As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.

Drop related dead code.

Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:23 +01:00
Kyösti Mälkki 11f9c35bd2 AMD cimx/sb800: Fix console output
These sb800_enable() messages without newline mess up the log.

Change-Id: I1689b68702e08e2a287083835f310f52f495c451
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8384
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:15 +01:00
Kyösti Mälkki 2a2d6135a4 AGESA fam15tn fam15rl fam16kb: Drop HT3_SUPPORT
Kconfig variable is not implemented.

Change-Id: I546a1001847e7b1002f96baf49ed3301852a6894
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8345
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:48:42 +01:00
Kyösti Mälkki 225da645ad AGESA fam10 fam12 fam15: Always have HT3_SUPPORT
Keep the slower HyperTransport configuration for a possible reference
in fam15 boards.

Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8344
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:48:05 +01:00
Paul Menzel ddea94259a arch/x86/boot/tables.c: Remove unused variable assignment to `rom_table_end`
Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:13:37 +01:00
Alexandru Gagniuc 23804fc6e5 drivers/xpowers/axp209: Print a message when probing fails
Probing is done by reading the ID register and comparing it to a known
value. When there is a mismatch, print an error.

Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 19:03:04 +01:00
Dave Frodin a0edc78523 superio/fintek/f81216h: Add the correct unlock key values
The actual key values were not added in commit 17ace8255.
TEST: amd/lamar shows the correct result.

Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8375
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:53:26 +01:00
Furquan Shaikh a02c265e3f arm64: Cleanup arch io header files
BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203142
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48
Reviewed-on: http://review.coreboot.org/8410
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:34:37 +01:00
Dave Frodin 4675c598a4 southbridge/amd/pi: Combine and correct the IRQ text strings
This combines the Avalon and Bolton tables of text descriptions
of the IRQ assignments. It also corrects the text string for
the SD controller on Bolton.

Test: This was verified on amd/lamar.

Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8374
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:31:06 +01:00
Marc Jones f5b65a34fd tegra132: Fix build for verstage
Verstage isn't included yet, but we need to have
the Kconfig option for toolchain.inc to pass.

Change-Id: I7fae73cd3b77fd347398221489caf745274701eb
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8409
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-13 22:34:14 +01:00
Timothy Pearson b32bf54c31 northbridge/amd/amdfam10: Move K10 specific menu to proper Kconfig file
Change-Id: Ib83ec5c397fdef5aa9e3376f1c0072cfa2f74fa6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8425
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-13 09:30:15 +01:00
Werner Zeh 2a84445748 fsp_baytrail: Add macros to define 20K pull-up and down
Add two macros to gpio.h which allow to setup 20K
pull-up or pull-down resistor for a given GPIO.

Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8402
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-13 09:29:28 +01:00
Stefan Reinauer 1e9336e89c Fix source code permissions
Two source files were accidently marked executable. Switch them back to
mode 644 (rw-r---r--)

Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9
Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8426
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-13 01:48:23 +01:00
Timothy Pearson 7a4454f9ce drivers/xgi: Fix user-visible typo in printk
Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-12 04:41:53 +01:00
Timothy Pearson adb5908dc8 payloads/seabios: Enable SeaVGABIOS option if native text init supported
SeaVGABIOS supports both the coreboot linear framebuffer and native EGA
text mode.  To use SeaBIOS interactively on standard VGA hardware a VBIOS
is needed; SeaVGABIOS is one such option.

TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS.  Was able to
interact with SeaBIOS and comboot menu, then booted Linux successfully.
VGA display was continuously usable from power on to Linux login.

Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8368
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-12 04:41:39 +01:00
Paul Menzel 4549e5a665 AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly
Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5101
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-12 02:27:07 +01:00
Nicolas Reinecke 0908839323 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id
Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8355
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:44 +01:00
Timothy Pearson 6fdb4d5d3c amd/amdfam10: Fix incorrect core count identification
The core count identification code in the PowerNow! _PSS
ACPI object generation code was incorrectly copied from the
model_fxx code.  This code has been rewritten to properly
return the number of cores installed in the system.

Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8421
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:10 +01:00
Nicolas Reinecke 2f5bb6548d asus/m4a785/Kconfig: Add vgabios PCI id
The PCI id defaults to 1106,3230 -> via chrome 9 ...
Tested on the board.

Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:43:21 +01:00
Nicolas Reinecke fa0b3c8cdd cpu/amd/model_10xxx: update microcode
microcode updates are extracted from: www.amd64.org/microcode.html
Mircocode versions of 1020h and 1022h are more recent in coreboot
than inside the AMD archive.

Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8354
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:41:33 +01:00
Timothy Pearson f73179d4be mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID
This resolves an issue on Shanghai dual CPU configurations where
the APs on node 0 would not start.  Single CPU configurations are
unaffected by this issue.

TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified
proper BSP/AP start and microcode patch levels.

Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8397
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 07:16:47 +01:00
Alexander Couzens f251a6d7d4 cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.

Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:58:06 +01:00
Kyösti Mälkki 754fac4346 PCI subsystem: Remove AGP bridge type
There is no auto-detection for AGP type and we have no hardware that
selects this. Furthermore, we treat AGP bridges just like PCI bridges,
there is no optimisation for higher bandwidth.

Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8367
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:38:32 +01:00
Werner Zeh b474abee84 Baytrail_fsp: Make ME path configurable in menuconfig
By adding a description to ME_PATH it becomes visible
and editable in menuconfig.

Change-Id: I8c2f6a30c10f16b19f3667263db02c93688c9f8f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8398
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:26:52 +01:00
Michał Masłowski 208a53527a lenovo/x200: Increase default CBFS_SIZE to 2 MiB
The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB
flash variants.  Let's allow using the whole region instead of the
gm45 default of 1 MiB.

Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/8392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-10 07:27:06 +01:00
Timothy Pearson c1f47c1460 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
Fix a mistake that led to an invalid 0ms latency in the automatically
generated PowerNow! ACPI _PSS objects.

TEST: Booted FreeBSD and Linux and verified correct latency values.

Found-by: Coverity Scan
Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8376
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-10 07:26:32 +01:00
Martin Roth 2213843ae8 fsp_baytrail: Get FSP reserved memory from the FSP HOB list
Because the pointer to the FSP HOB list is now being saved, we can
use that to find the top of usable memory.  This eliminates the need
to hardcode the size of the FSP reserved memory area.

Tested on minnowboard max for baytrail.

The HOB structure used does not seem to be present for the rangeley
or ivybridge/pantherpoint FSPs.  At the very least, the GUID is not
documented in the integration guides.

Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8308
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-09 17:44:31 +01:00
Martin Roth ad4fa21705 Get rid of .car.global_data warnings for GCC build
The "used" attribute was added in commit 27cf2472 which caused these
warnings to start appearing when using the standard coreboot GCC
toolchain:

{standard input}: Assembler messages:
{standard input}:96: Warning: ignoring changed section type for .car.global_data
{standard input}:96: Warning: ignoring changed section attributes for
.car.global_data

The # at the end of the section name causes the assembler to
ignore everything following the name. I verified that the resulting
binaries are the same with and without the #.		

Change-Id: Iaac8042533842ed887f33895f083b613a18f496a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8301
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-09 17:44:02 +01:00
Kyösti Mälkki cd02ef19e5 Intel FSP platforms: Fix timestamps
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.

Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-09 11:41:34 +01:00
Nicolas Reinecke 29d358e6a1 lenovo/t430s: Add new port.
The port is based on the x230 / t530.
Tested - is in active use.

Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8359
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-08 09:26:46 +01:00
Alexandru Gagniuc b5669ba579 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
cmos_init() had layers of preprocessor directives, which resulted in
a complete mess. Refactor it to make use of the IS_ENABLED() macro.
This improves readability significantly.

One of the changes is to remove in inline stub declaration of
(get|set)_option. Although that provided the ability for the compiler
to optimize out code when USE_OPTION_TABLE is not selected, there is
no evidence that such savings are measureable.

Change-Id: I07f00084d809adbb55031b2079f71136ade3028e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8306
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 23:56:04 +01:00
Alexandru Gagniuc a4d784eeab include/types.h: Provide BIT() macro
This macro is controversial for arches where the bits are numbered
MSb first, though we don't support such an arch. We've seen this macro
creep into our tree in different places, so provide it in one place.

Change-Id: I86cd8a16420f34ef31b615aec4e0f7bd3191ca35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8280
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-02-06 19:25:57 +01:00
Timothy Pearson da8fcf0afe mainboards/asus/kfsn4-dre: Indicate native text mode init support
Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8369
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06 19:22:56 +01:00
Timothy Pearson 08c15ed266 drivers/xgi: Fix legacy VGA text mode initialization
TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s
Initial text from coreboot appeared, and the Linux
console was displayed immediately at the start of
kernel initialization.  After boot was complete
the text mode console continued to behave normally.

SeaBIOS does not currently make use of the legacy
VGA text-mode display.

Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8360
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06 19:22:36 +01:00
York Yang 114baa0a0a intel/fsp_rangeley: Indent '#define' consistently
The indentations of #define are not consistent in chip.h. Update to make 
all #define indentations being aligned and put them after the variable 
declaration.

Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8333
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2015-02-06 00:58:50 +01:00
Martin Roth 582b2aee0f FSP & CBMEM: Fix broken cbmem CAR transition.
1) Save the pointer to the FSP HOB list to low memory at address 0x614.

This is the same location as CBMEM_RESUME_BACKUP - the two aren't used
in the same platform, so overlapping should be OK.  I didn't see any
documentation that actually said that this location was free to use, and
didn't need to be restored after use in S3 resume, but it looks like
the DOS boot vector gets loaded juat above this location, so it SHOULD
be ok.  The alternative is to copy the memory out and store it in cbmem
until we're ready to restore it.

2) When a request for the pointer to a CAR variable comes in, pass back
the location inside the FSP hob structure.

3) Skip the memcopy of the CAR Data.   The CAR variables do not
get transitioned back into cbmem, but used out of the HOB structure.

4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.

Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8196
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 00:53:13 +01:00
Kyösti Mälkki 0490f74d78 TPM: Fix whitespace
Change-Id: I2d00a2964b16436356c5e02764897e37ef610efc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8343
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-06 00:25:59 +01:00
Timothy Pearson 67085e0c09 mainboards/asus/kfsn4-dre: Enable native VGA initialization
Change-Id: I953ced7d34af9ec0923fa6df93b9ad4270196c77
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8332
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:37:17 +01:00
Timothy Pearson c522fc8f38 drivers/xgi/z9s: Port Linux framebuffer initialization to coreboot
Add native XGI Z9s framebuffer support to coreboot
XGI initialization code largely taken from Linux 3.18.5

TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS
with SeaVGABIOS enabled.  Text appeared correctly on screen
and interaction with graphical comboot menu was successful.
However, Linux cleared the framebuffer on boot, rendering the
screen useless until Linux loaded its native xgifb driver.

Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8331
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:37:05 +01:00
Dave Frodin 5c015f045d southbridge/amd/pi: write_hpet requires additional config option
This copies what was done in southbridge/amd/agesa in:
commit 56f46d8 agesa/family15tn: Switch to per-device ACPI

TEST: amd/lamar.

Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8288
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:34:05 +01:00
Dave Frodin ef9a4e6aec southbridge/amd/pi: Update Kconfig and makefiles for bolton
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8287
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:33:42 +01:00
Dave Frodin 9cfa742a26 southbridge/amd/pi: Add the bolton definitions
This adds the PCI and interrupt related definitions
for the bolton specific features.

Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-05 17:33:00 +01:00
Kyösti Mälkki c3f6bb086b AMD HyperTransport: Drop unused link optimisation
Change-Id: Ia4398f6eb013c69838487bdd02d094f97d7224b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8342
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 16:11:43 +01:00
Kyösti Mälkki 08e39c572f AMD K8: Remove some excessive preprocessor use
Tests on CPUID are valid regardless of revision.

Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:20:42 +01:00
Kyösti Mälkki 9bc83888ad newisys/khepri broadcom/blast: Drop duplicate entry in Kconfig
Keep the value that is listed first, it also the one with a more
recent change.

Change-Id: I0336c962544d75f94512563c08f280aa43c7a175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8336
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:18:06 +01:00
Kyösti Mälkki 09b5e4d005 AMD8131: Remove obsolete directory
Change-Id: I875384e55a4a71d1a5c962d128d13356f3befa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8335
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:17:42 +01:00
Dave Frodin 17ace82552 superio/fintek: Add required changes so F81216H can be used
The amd/lamar mainboard is the first mainboard to use the f81216h.
These changes are needed to fix up commit 27a63d77 so the
Super I/O builds and functions correctly.
  - Wrong #include name
  - Removed global variable in romstage
  - Missing "case" in switch()

Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8255
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-04 15:45:39 +01:00
Kyösti Mälkki 1608f3651f cpu/amd (non-AGESA): Remove terminator from microcode blob
Change-Id: I6370e971922dee5e8d476a883c5f0f32fbbc8911
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:52:12 +01:00
Kyösti Mälkki d15cb519ad amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selection
Include microcode updates in CBFS for every CPU revision the platform
can support, as changing to different CPU revision should not require
a coreboot rebuild.

This increases CBFS usage from 2 kB to 14 kB.

Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4521
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-02-03 04:52:00 +01:00
Kyösti Mälkki 5fe1fb7a5f cpu/amd (non-AGESA): Load microcode updates from CBFS
Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4502
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:52 +01:00
Alexandru Gagniuc 893b81f79f cpu/amd/model_10xxx: Remove UPDATE_CPU_MICROCODE option
This option is now deperecated by loading microcode updates from cbfs.
Remove this option in anticipation of implementing CBFS loading for
AMD cpus. Removing it beforehand results in less patch overhead.

Change-Id: Ibdef7843db686734e2b6b1568692720fb543b240
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:43 +01:00
Jonathan A. Kollasch 30c34c0751 nvidia/ck804: make Message Signaled Interrupts work
Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable
HT MSI Mapping so that MSIs work.  Prior to this change PCIe devices
downstream of the CK804 with MSI enabled would fail to actually assert
their interrupt.  Tested on msi/ms7135 and winent/mb6047 running Debian
GNU/Linux 7.0 (wheezy).

Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8276
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-03 00:47:26 +01:00
Alexandru Gagniuc a583924252 src/arch/*/include/stdint.h: Provide definitions for bool type
Although bool normally belongs in stdbool.h, for our use cases,
providing these definitions in stdint.h is acceptable.

Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8279
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-02 20:29:23 +01:00
Jonathan A. Kollasch e299ae673c winent/mb6047: switch to CAR version of ck804 early_setup.c
Change-Id: I9b45b7fbd862a5600ead7ad4e623a8a87ae364aa
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8319
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:48:36 +01:00
Jonathan A. Kollasch bdebb07d2f winent/mb6047: clean up includes in acpi_tables.c
Change-Id: I63bdc856fa4232cd66ff2e48e39c2cdb97bb88d3
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8316
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:45:43 +01:00
Jonathan A. Kollasch 679efee2d7 winent/mb6047: use correct ACPI SCI interrupt trigger
Change-Id: I245c0afb66f3a29b5acb40e8d949d8b1aa08cd73
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8315
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-01 16:43:39 +01:00
Jonathan A. Kollasch fcf5988cf6 winent/mb6047: drop inaccurate comment in acpi_tables.c
Change-Id: Ib0bb8bed32b96a5f7fd48407bd111972f89e7907
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8314
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:11:17 +01:00
Vladimir Serbinenko ac1b6def75 lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports.
Fixes USB3 ports degraded to USB2 speeds.

Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8313
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-01 10:12:12 +01:00
Vladimir Serbinenko b26156ec65 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8312
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 08:22:40 +01:00
York Yang e1e11e63af intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
by UPD input. Update UPD_DATA_REGION structure for matching up this
FSP change.

PcdCustomerRevision is a debugging aid that will be output to debug
message in FSP. When needed, it can be customized by BCT tool for tracking
BCT configurations.

Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-31 23:09:26 +01:00
Martin Roth 9cd155334b FSP platforms: Clear area in CAR for cbmem
This patch clears the CAR area. The FSP loads the entire CAR area with a
pattern instead of clearing it.  At least the cbmem area needs to be
cleared or cbmem will not use it.

Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8195
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 22:30:03 +01:00
Timothy Pearson 4e6f0c289b asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devices
Test:
Single Opteron 2419 with 1GB RAM in slot A1
Booted Ubuntu Linux 14.04 and verified all 6 cores were visible
Brief stress test of all 6 cores simultaneously
Verified proper ACPI power states for all 6 cores

Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8311
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-31 21:33:20 +01:00
Timothy Pearson 9c8106696e cpu/amd (non-AGESA): Fix AP crash during microcode version lookup
Move mapping tables to struct and prevent OOB array
access that was crashing the APs during CAR initialization.

Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-31 21:33:10 +01:00
Timothy Pearson 0d7f8d0b79 amd/amdfam10: Update name table with Opteron 2400/8400 series codes
Change-Id: I52587c0c0dffd814d39087475b8f14c500a68933
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8309
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-31 21:32:25 +01:00
Nicolas Reinecke 86393bb64b vendorcode/amd/agesa/f14: update microcode
05000028 -> 05000029 tested on asrock E350M1
05000101 -> 05000119

Change-Id: Iccb096eb55a4a789c1e810f68c8c8eacfd5f8a0b
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8296
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:23:35 +01:00
Nicolas Reinecke cb6cfbdc06 mainboard/lenovo/t420s/Kconfig: select NO_UART_ON_SUPERIO
same as 37130ebdab

Change-Id: I73feed3a077dfcc61634147775df1e05fdb97e8b
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8278
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:21:43 +01:00
Nicolas Reinecke 5e03170541 intel/model_2065x: update microcode
Change-Id: I6c13518d2217bc823d409ab800bca011e76e9f25
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8277
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:21:15 +01:00
Nicolas Reinecke 6d1158f3a9 southbridge/intel/bd82x6x native usb init: replace some magic values
Some magic numbers are documented in the PCH datasheet so use them.

Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8307
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:20:15 +01:00
Nicolas Reinecke 266971c1cd lenovo/t530/romstage.c: add usb port description and missing oc config
OC2 at port 4 was missing. Verified with RCBA dump.

Change-Id: Ide5701d53aeee28619204c7ac408662626aa11e4
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8304
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:19:42 +01:00
Nicolas Reinecke 5ecc6bc7d6 lenovo/t5x0: Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.

same as http://review.coreboot.org/4650 /
63acd22dc5

Change-Id: I82d7a2b9f2ec56557b3a9c26d1af57ed39e31850
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8302
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:18:46 +01:00
Kyösti Mälkki 9664345586 devicetree: Search PnP device node from the tree by path
Copied from device_util.c with added ROMSTAGE_CONST.

Change-Id: If872631ed96a79b9a0b15e09382d6f81098c8db3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8297
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-30 16:58:27 +01:00
Timothy Pearson 20c2c4b277 asus/kfsn4-dre/Kconfig: Enable power on after power fail by default
Change-Id: I655843c78d31cc69a007ddaf9b51cde063c48c79
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8299
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-29 15:39:19 +01:00
Martin Roth 5fc32bf5e6 drivers/intel/fsp: Add find_saved_temp_mem()
Add a function to retrieve the location of the CAR temporary memory
that was saved by the FSP into the HOB structure.

Change-Id: I2635de5207cd699740721d333a7706425b837651
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8194
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-29 04:33:53 +01:00
Timothy Pearson 8057285119 mainboards: Add support for the Asus KFSN4-DRE series of motherboards
Status:
Tested with KFSN4-DRE PCB v1.04G
Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work.
Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank).
Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1.
AMD PowerNow! functions correctly via ACPI.
Video, network, USB, SATA, and serial have received thorough testing.
Tested with KFSN4-DRE PCB v1.05G
Single Opteron 2419 CPU tested with 1GB RAM in slot A1.
Booted to PXE configuration menu; not tested further.

Known issues:
RAM initialization is a bit flaky with multiple high-density modules;
this could be a generic MCT training issue but is probably bad hardware.
The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device
works after Linux boots and initializes the device.
Suspend/resume functions at the S1 level but sometimes hangs on resume.
Wake on LAN can be flaky; the strap(s) needed to have WoL work on power
application were not physically installed by ASUS so the board needs to
boot at least once after power application before it will work.

Change-Id: I0709f822eea8ed877f55db9443143028a5400472
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8270
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 22:12:06 +01:00
Timothy Pearson a6f669e183 amd/amdfam10: Allocate the lower DRAM region up to TOM
This fixes the resource allocator locating the PCI register
space below 0xe0000000 thereby causing corruption with more
than ~3.5GB physical RAM on AMD Family 10h systems.

Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8261
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 22:11:48 +01:00
Timothy Pearson 7f3ae39640 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects
Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8285
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 20:58:10 +01:00
Timothy Pearson b871687991 nvidia/ck804: Add ability to override CK804 base unit ID
Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8273
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-01-28 20:00:17 +01:00
Timothy Pearson 6300b03414 amd/amdfam10: Add runtime ACPI _PSS generation
Skeleton and ACPI generator interface taken from
model_fxx powernow_acpi.c
Small portions of FIDVID MSR code taken from
model_10xxx fidvid.c

Nearly completely rewritten for the P-state-based K10 CPU

TEST: KFSN4-DRE with dual Opteron 8356 CPUs
Verified CPU per-core dynamic state change with system load
Verified reported P-state count and frequencies
Stress-tested each CPU (all cores simultaneously) to verify
proper P0 transition and configuration.

Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8284
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:58:36 +01:00
Timothy Pearson e916201004 nvidia/ck804: Fix FTBFS with AMD Family 10h systems
The build failure stems from a missing function being called via a chain
including setup_ss_table(), set_ht_link_ck804(), and
st_ht_link_buffer_counts_chain(); the latter function is only available
in the AMD K8 code.

It appears that a bunch of K8-specific code snuck into the CK804 and MCP55
southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0.

Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8269
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:56:15 +01:00
Timothy Pearson 02112bd280 nvidia/ck804: Add ability to enable/disable PCIe PME# wake events
Change-Id: Ie2937dd220464e3b168aa8a50a57c03b6258c189
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8283
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:03:39 +01:00
Timothy Pearson 684fda5964 nvidia/ck804: Fix cosmetics in Kconfig
Change-Id: Ic675911f534f07516c838b52c9463e89448d4353
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8291
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 18:59:20 +01:00
Timothy Pearson e1cc3abb02 nvidia/ck804: Add ability to bypass register 0x78 initialization
On the ASUS KFSN4-DRE initializing CK804 0x78 causes an almost
immediate soft reset.  Leaving the register at its power-on
default value appears to have no ill effect on that same board.

Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8272
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 05:26:14 +01:00
Timothy Pearson 82982a130c amd/amdfam10: Enhance resource debugging when enabled
Change-Id: Ie39652bded9a42d1d816ca5198db59a83e5c083a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8266
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-28 04:40:39 +01:00
Timothy Pearson c139c42f3f northbridge/amd/amdht: Initialize variable `currentBUID`
Fix uninitialized variable when manual non-coherent BUID
selection is used.

Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8267
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 01:03:44 +01:00
Timothy Pearson 8d9492e536 amd/amdfam10: Serialize mutable ASL methods
Fix three IASL warnings in ASL utility code by making the
methods `GWBM`, `GWEM` and `GIOR` serialized.

TEST: Built and booted on ASUS KFSN4-DRE.

Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8264
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 00:53:35 +01:00
Timothy Pearson e538daeaec amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM
Remove declaration of unused variable `io`.

Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8265
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-27 23:33:34 +01:00