Commit Graph

9831 Commits

Author SHA1 Message Date
Werner Zeh 0f9c9de35a fsp_baytrail: Add I2C driver
Add a driver wich can handle the internal I2C controllers
of Baytrail SoC. This driver is not suitable for the
SMBus controller.

Change-Id: I841c3991a2fb0f8b92b8e59ec02d62f5866f5bdf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8401
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 14:19:34 +01:00
Werner Zeh b5a374d58b fsp_baytrail: Add new microcode for Bay Trail M
Add a new microcode for Bay Trail M D0 stepping used
in cpu N2807 silicon.
In addition, a selection of the used CPU type has
been added (I or M/D) which allows to use only the
really needed microcode for a given CPU type.

Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 12:45:10 +01:00
Alexandru Gagniuc fb9d4caf16 mainboard: Do not redefine DRIVERS_PS2_KEYBOARD Kconfig variable
Change-Id: Icc603dfe92360d978221a25ad28517da43942bea
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8498
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05 09:33:47 +01:00
Aaron Durbin bc772c3f3d arm64: Set 16 byte alignment and ramstage start address
To align with arm use the RAMSTAGE_BASE Kconfig option
for start of ramstage. Also, use 16-byte alignment for the
start and end of the sections. 4 bytes were previously used, but
it definitely seems more appropriate to at least have the heap
handing out 16-byte aligned pointers.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through attempting to load payload

Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207432
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550
Reviewed-on: http://review.coreboot.org/8588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04 20:04:46 +01:00
Aaron Durbin 00263d0d8e arm64: remove assembly code string functions
Inconsistent progress was observed running ramstage.
It was determined that the hand-coded assembly functions
were causing issues. Some of the comments seems suspect about
the hardware taking care of alignment. The prudent thing to do
is to use the C ones. Optimization can come later after maturity.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted to attempting to payload

Original-Change-Id: I4137adf9b36b638ed207e4efd57adaac64c6a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207431
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2762e478c6b59dd30c59aa87a922d0f78c00c0c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id3196b0c2bf41a21db31f999ba437d118875a236
Reviewed-on: http://review.coreboot.org/8587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-03-04 20:04:18 +01:00
Aaron Durbin 0df877a65a arm64: use one stage_entry for all stages
Ramstage needs an assembly entry point for setting up
the initial state of the CPU. Therefore, a function is
provided, arm64_el3_startup(), that bootstraps the state
of the processor, initializes the stack pointer, and
branches to a defined entry symbol. To make this work
without adding too much preprocessor macro conditions
provide _stack and _estack for all the stages.

Currently the entry point after initialization is 'main',
however it can be changed/extended to do more work such
as seeding the stack contents with tombstones, etc.

It should be noted that romstage and bootblock weren't
tested. Only ramstage is known to work.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Brought up 64-bit ramstage on rush.

Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207262
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949
Reviewed-on: http://review.coreboot.org/8585
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 20:00:18 +01:00
Aaron Durbin 6ba1b628ee arm64: ensure vital sections aren't garbage collected
The driver structures live in special sections which have no
direct reference to the symbols. Therefore, when garbage
collecting sections in the linker the drivers are tossed out
resulting in no drivers being linked into ramstage. Fix this
by adding the KEEP() directive to those special sections.

BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and noted console starts working in ramstage.

Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207261
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4
Reviewed-on: http://review.coreboot.org/8584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04 19:59:46 +01:00
Furquan Shaikh e5d014c29a coreboot t132: Stack init re-work
1) In order to avoid stack from overflowing during ramstage decompression,
initialize stack right at the beginning of romstage.
2) Declare different Kconfig options for stack at each stage.
3) Provide a macro that does stack seeding if required and calls appropriate
function.

BUG=None
BRANCH=None
TEST=Compiles and runs successfully on rush.

Original-Change-Id: I55d6ce59ea91affba3e86d68406921497c83fb52
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206880
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5e32d73803a2a9d222fcc4ca5f58efd3abe95d34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib833a1badb170a33cbf20d232019425b59db60cd
Reviewed-on: http://review.coreboot.org/8583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 19:58:30 +01:00
Tom Warren dfe7ea2b4e rush: PMIC: initial AS3722 PMIC writes for Rush
Still waiting on VDD_CPU value, etc. from board guys, but this is a start.

BUG=None
BRANCH=None
TEST=Built and flashed rush, saw 'PMIC init done' string OK.

Original-Change-Id: I6f8b16c4ebf1e9c159f8175d59262119ef0e498f
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206412
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 96a9ff8f632c2b9bf3f81f5b8fc4f3b6784a02bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9d3d7ff55f2d6ca88ebdcc8ad1d7de135f5136d2
Reviewed-on: http://review.coreboot.org/8582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 19:56:26 +01:00
Aaron Durbin d2907c1e02 t132: kick off core complex after loading MTS microcode
Once the MTS microcode is loaded the core complex can be
directed to decode the MTS and start running. The cores,
however, won't start executing until instructed to do so.

BUG=chrome-os-partner:29222
BRANCH=None
TEST=Built, booted, ran. Noted it took about 920ms for the
     core complex to decode and handshake back.

Original-Change-Id: I0a9ed53e596eb65801461b2769d133710a92a48a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206075
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 6edb6e21a69d84ba5b23137e9e390954159e7887)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I179e561bb3a34b206620eecde6781a1c05a3744e
Reviewed-on: http://review.coreboot.org/8581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04 19:55:56 +01:00
Furquan Shaikh 196ee2b029 coreboot memrange: Two changes for zero size or empty memrange
1) Add check for zero size in memrange.
2) Add public memrange_init_empty function to allow initializing only the
memrange structure without filling in device resources

BUG=None
BRANCH=None
TEST=Compiles and runs succesfully for rush MMU memranges.

Original-Change-Id: I8e4d864cbc9a770cd208f8a9f83f509dc7ace894
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208957
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5c42301c2a51a1a2a29ef58012f210d03bd37f94)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8d63abb15efda74270ef6fa3c0df55c05659595d
Reviewed-on: http://review.coreboot.org/8597
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-04 19:55:19 +01:00
Aaron Durbin 3aca2cdced t132: load MTS microcode
The armv8 cores need to have microcode loaded before they can
be taken out of reset. Locate and load the MTS microcode at the
fixed address of 0x82000000. The ccplex, once enabled, will
decode and transfer the microcode to the carveout region.

BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and ran. Confirmed dump of MTS region after loading code.

Original-Change-Id: Ie5ab72e5363cbdb251d169356f718020d375fce6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6726d8862c08b155b9218aa5e2e39428a105089e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I425c2e2fd1eaec49d81bef1ff4bf4f36da9296df
Reviewed-on: http://review.coreboot.org/8580
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-04 19:51:42 +01:00
Stefan Reinauer 73307e0917 Add stage information to coreboot banner
As a convenience, print the actual stage name when entering a stage.
Also unify the banner between bootblock / romstage and ramstage. No
reason for two different occurences.

Instead of this:

coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...

you will see this:

coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting...

Roughly based on: https://chromium-review.googlesource.com/199671

Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8578
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-04 19:46:25 +01:00
Aaron Durbin 8ddc1f328a rush: enable 128MiB MTS carveout below top of DRAM
The recommended settings for the size of the MTS region is 128MiB.
Therefore, provide this region 128MiB below the top of DRAM for
each configuration.

BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and noted MTS carveout region at expected location.

Original-Change-Id: Iac17f210dfef8e8a36617c7b3dceba8c2134ee9b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206291
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit f1758c74330afe9dd7eaa8ff1fef5e4d18ed14ad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I369a3897e31f3126d031d3582f52f9892350f658
Reviewed-on: http://review.coreboot.org/8579
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:25:52 +01:00
Marc Jones 0e69639909 t132: Replace fallback with CONFIG_CBFS_PREFIX
Use the Kconfig value to load the name of the stage instead of the
hard-coded fallback stage.

(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1ac707efe38e29f109dbbe206de74fbfe7cb7b0b
Reviewed-on: http://review.coreboot.org/8576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:25:18 +01:00
Aaron Durbin 1ac4e591bf t132: Add shared romstage
There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.

BUG=None
BRANCH=None
TEST=Built and booted to same place as before.

Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:24:18 +01:00
Furquan Shaikh 650d11ce94 coreboot rush: Add dram init code
Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.

BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5

Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:23:46 +01:00
Furquan Shaikh d42b3fc6a9 coreboot rush: Add support for basic romstage
Add basic romstage support for rush. Since, dram init needs to be done before we
can jump to armv8 core, romstage will run on armv4 core as well. Thus,
correcting the compiler selection options.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Prints romstage banner and initial printk

Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205763
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a
Reviewed-on: http://review.coreboot.org/8573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-04 18:23:11 +01:00
Furquan Shaikh b68cb9e8ae coreboot t132: Enable loading of romstage from CBFS media
Add proper Kconfig options and initialize cbfs media to enable loading of
romstage

BUG=None
BRANCH=None
TEST=Compiles successfully for rush and cbfs_load_stage returns entry pointer
for romstage

Original-Change-Id: If62edcdc0496d89d30003ffd7b827b77835910fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205762
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c89c05bc86fd6c1e49fbed5e0730659b64bffc6c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I68c10171424c85605b5065a19634d3c5dd639b78
Reviewed-on: http://review.coreboot.org/8572
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:16:27 +01:00
Furquan Shaikh f0d150e0ba coreboot t132: Remove init pllx for now
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source
for the CPU cluster). So, remove the init call for pllx. This needs to be added
later when required. Also, add a few more printks to display the progress.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Print messages seen on serial console.

Original-Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205680
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit d557d99edb855fbf7b32231c6746c676041bf62a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iaf56f2d587708c6e9fb01d4ced2edb5931075a81
Reviewed-on: http://review.coreboot.org/8571
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:16:09 +01:00
Furquan Shaikh 84bbab9226 coreboot t132,rush: Add mainboard specific bootblock_init
Pull in mainboard specific bootblock_init function from nyan into
rush. Additionally, pull in all files required for proper compilation of rush
after adding the bootblock_init function

BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205583
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit e7aac547026717d7380f71593010e3ea34ecea51)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie26f91f8caaa06af3b195246febcdc70b9fe9795
Reviewed-on: http://review.coreboot.org/8570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-04 18:15:44 +01:00
Timothy Pearson a89accd74f cpu/amd/model_10xxx: Documentation update
Change-Id: Ic29009be42ef77261a3b535327cf5c12761023c1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:16:22 +01:00
Timothy Pearson ead8751367 cpu/amd/model_10xxx: Refactor model detection to reduce code duplication
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.

Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:15:55 +01:00
Furquan Shaikh 29c1afce62 coreboot t132: Add clock.c to all three stages of coreboot
Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code
for enabling armv8 core is not included yet. clock_init added to bootblock.c

BUG=None
BRANCH=None
TEST=Compiles successfully for rush.

Original-Change-Id: I858c41a83d665da2c406707586b5e35a732177d4
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205581
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 61dbf1db72307815c4abdc218799479c334a4882)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I688e1e1373dea26557a84507a8e92d3055862801
Reviewed-on: http://review.coreboot.org/8569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-03 18:53:10 +01:00
Timothy Pearson 226fc941af northbridge/amd/amdmct: Add revision D to K10 revision mask list
Change-Id: Ib5f87bdc50c0bca370a636218d3b5d4cc9157c12
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8501
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-03 06:36:14 +01:00
Furquan Shaikh 67b0374649 coreboot arm64: Correct cache function names
Correct function names to make them consistent with generic calling name

BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205582
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 16668529527224fca3086ee88955d29e3a268516)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317
Reviewed-on: http://review.coreboot.org/8469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02 22:19:56 +01:00
Furquan Shaikh d653ae8960 coreboot arm: Define function for setting cntfrq register
Define functions for setting cntfrq register in arm and arm64 arch. This allows
SoCs to set this register independently of the architecture being used.

BUG=None
BRANCH=None
TEST=Compiles successfully for nyan and rush

Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205580
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6)

armv8: GPL license armv8 lib

BUG=None
BRANCH=None
TEST=Compiles successfully.

Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)

Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a
Reviewed-on: http://review.coreboot.org/8468
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02 22:19:46 +01:00
Furquan Shaikh 732b83ed36 tegra132: Enable bootblock support in tegra132 including UART support
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: Ia9420cfec5333dd5477f04cf080bdad8a37db025
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203143
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a1037f203c6a07cb116eeb1632cb7200ad022cd3)

This cherry-pick was modified to match the tegra124 uart.c, which
uses the idx and base address calculations instead of Kconfig settings.
This driver could use the 8250MEM driver when the ARM vs x86 IO
calling convention is worked out.

Change-Id: I6e439359b8bb541db4679ac144c519cf251ffed6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8517
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-02 21:17:21 +01:00
Kyösti Mälkki 280a29d5bb devicetree: Drop redundant scan_bus() ops
Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8533
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:55:22 +01:00
Kyösti Mälkki 85756c14e9 devicetree: Drop dummy root_dev ops
This is just dead code.

Should we decide that we want some of these calls made, they would
be implemented in the mainboard context.

Change-Id: I1f097c8da722f3afab9aa1c80b96590c7ca457d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8532
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:53:58 +01:00
Kyösti Mälkki 976d91c07e AGESA fam16: Drop HyperTransport scan
Already done for fam15tn/rl.

Change-Id: Id74ca13610a4ef407c866a4419139287413078a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:48:11 +01:00
Alexandru Gagniuc 5818da262d cpu/intel: (non-FSP) Remove microcode updates from tree
Now that we use the microcode updates in the blobs repository, remove
them from the main repo. Since the microcode updates are blobs, it
makes more sense to ship them in the blobs repo rather than the main
one.

The update-microcodes.sh script is also deleted, as a more current
version resides in 3rdparty.

Change-Id: Iee74a3ede3b5eb684ef0386d270120e70173c1b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4531
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28 08:21:15 +01:00
Alexandru Gagniuc ee89435798 cpu/intel (non-FSP): Use microcode from blobs repository
Now that microcode has been added to blobs, use that one instead of
the one included in the tree. Microcode from the tree will be
removed in a subsequent patch. Since the microcode updates are blobs,
they belong in the blobs repository.

This change may introduce a build failure if the "Generate from tree"
microcode option is selected, but the blobs repository is not
enabled. We have to live with this for now, until microcode is moved
to blobs for all CPUs, at which point we may adjust Kconfig
accordingly.

Leave the FSP  cpu alone for now, as that will need approval from
SAGE.

Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-28 00:14:49 +01:00
Kevin Paul Herbert 4104e6cd30 x86: Fix pointer arithmetic regressions from MMIO changes
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).

Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.

Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-27 18:15:33 +01:00
Timothy Pearson c684d05b0f mainboard/asus/kfsn4-dre: Enable W83793 fan controller
The Winbond W83793 fan controller is not automatically
configured correctly on power application, leading to
abnormal, and in some cases random, fan behaviour.

This commit enables the controller and sets sane default
values.

TEST: Booted mainboard and verified that the correct number
of fan speed sensors were visible from hwmon under Linux.
Also verified that, unlike before, the CPU fans were running
at a high enough speed to properly cool the CPUs.  Verified
the 8 fan outputs under direct control of the W83793 device.
Verified voltage and temperature sensors and limits via output
of the 'sensors' command.

Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8503
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-26 06:22:49 +01:00
Timothy Pearson d3e31be8c5 drivers/i2c/w83793: Use devicetree.cb to set additional values
This allows devicetree.cb to set:
Minimum PWM values
Temperature sensor source
Voltage sensor high/low limits
Fan pin routing
Default PWM values
Manual PWM values per-fan

Change-Id: I3a321406a26ae01a121289d24b41c9f988dd6f30
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8502
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-26 06:20:07 +01:00
Aaron Durbin a63da6f97e rush: Correct version field to match t132
The version field for t132 cpus is 0x00130001. Update it to
the correct version.

BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and was able to see serial with subsequent changes.

Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205435
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a
Reviewed-on: http://review.coreboot.org/8467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-25 20:08:23 +01:00
Furquan Shaikh 26a8747cca coreboot arm64: Add library for system access
Add support for library functions required to access different system registers:
1) PSTATE and special purpose registers
2) System control registers
3) Cache-related registers
4) TLB maintenance registers
5) Misc barrier related functions

BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203490
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb)

armv8: GPL license armv8 lib

BUG=None
BRANCH=None
TEST=Compiles successfully.

Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)

Get the library and the GPL license in a single commit.

Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d
Reviewed-on: http://review.coreboot.org/8465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-25 20:01:44 +01:00
Marc Jones 595a40cfc9 tegra124: Clean up ARM UART driver build
CONFIG_CONSOLE_SERIAL_UART has been updated to
CONFIG_DRIVER_UART. The UART may be used for more than serial console.

Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8516
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25 19:48:51 +01:00
Marc Jones d8ea0ba5a8 arm64: Remove early_console.c
The early_console.c file isn't used or built. It has been replaced
by the generic uart and console drivers.

Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-25 19:42:00 +01:00
Paul Menzel 21a530981d soc/intel/baytrail/Kconfig: Remove explicit `HAVE_MONOTONIC_TIMER`
Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which
selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already
selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`).

Therefore remove the explicit selection of that Kconfig option.

Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-25 16:21:23 +01:00
Patrick Georgi f3a235e977 intel/broadwell: free local heap object
No real harm done (thanks to our free() implementation),
but let's do it right.

Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8511
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-25 14:05:45 +01:00
Patrick Georgi bdd185a355 amd/sb600: Fix NULL test after use issue
Change-Id: Icecbcc1dee837ecfe0dd52bade3b83fdcdd15bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8513
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-25 14:05:42 +01:00
Kyösti Mälkki 9b5f137823 Intel ibexpeak: Fix SATA configuration
It got broken with commit bde6d309.

Change-Id: I0d7180b1659da45bf87d4de46b7b387cbc73cd0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24 11:49:32 +01:00
Werner Zeh 63693dca06 drivers/intel/i210: Add new driver for Intel i210 MACPHY
Add a new driver for Intel i210 MACPHY with the goal to
update the MAC address in i210 if it is found
during PCI scan.

Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8404
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-24 07:08:11 +01:00
Alexandru Gagniuc 5b4b024af2 (bakersport|bayleybay)_fsp: Do not force a default loglevel
DEFAULT_CONSOLE_LOGLEVEL_* is supposed to be selected by the user, and
should not be overriden by any other part of the tree. As such, remove
the selection of DEFAULT_CONSOLE_LOGLEVEL_7 from these two boards.

Change-Id: I194a71b371b184e81a16fec2bd21f1b0deb4ebbf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24 06:41:31 +01:00
Alexandru Gagniuc 1896996589 mainboard: Do not redefine CONSOLE_POST Kconfig variable
This option is already defined in console/Kconfig, and is intended
to be controlled by the user. Only six boards in the entire tree
redefined it, so remove the definition from those boards.

Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8457
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24 06:41:16 +01:00
Alexandru Gagniuc eb73a21882 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables
SUPPORT_CPU_UCODE_IN_CBFS is a deprecated option now that all CPUs
with updateable microcode (except AGESA) load microcode from CBFS.
CPU_MICROCODE_ADDED_DURING_BUILD is a state variable that is set
based on user's choice in the microcode menu and should not be changed
directly.

Eliminate INCLUDE_MICROCODE_IN_BUILD variable, whose use directly
interferes with the microcode mechanism, remove selection of
CPU_MICROCODE_ADDED_DURING_BUILD, and do not depend
SUPPORT_CPU_UCODE_IN_CBFS on anything. This makes usage of the
microcode mechanism consistent with other CPUs in the tree.

This incorrect usage of the Kconfig variables was hiding the fact that
some of the microcode files present in fsp_baytrail/microcode_blob.c
were not present in the tree.

Change-Id: I71cb3f834c22c0363a20bd469797a9f51c215371
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-24 06:41:05 +01:00
Kyösti Mälkki b5a8a13bde pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.

Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.

Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:36:21 +01:00
Kyösti Mälkki 07354235df pcengines/apu1: Fix and clean up devicetree
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware.

Disable 0:14.1 IDE controller, as it would only be used with SATA ports
4 and 5 that are not populated with connectors in the hardware.

Disable 0:14.2 HD audio, as it is not implemented in the hardware

Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller
are not populated in the hardware.

Fix some alignment and whitespace.

To my knowledge these changes are not included with SAGE release
pcengines.apu_139_osp.tar.gz, but that tarball does not contain
either devicetree.cb or a pre-compiled static.c file so I cannot tell
for sure.

Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:35:48 +01:00
Kyösti Mälkki 5d899c4217 pcengines/apu1: Fix PCI device 16 interrupts
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed
in PIC mode. The only affected peripheral was the SD card reader.

This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz.

Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8327
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-02-23 21:35:17 +01:00
Kyösti Mälkki 780935687d pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.

As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.

Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:34:55 +01:00
Kyösti Mälkki 8c190f3518 pcengines/apu1: New board PC Engines APU1
While we cannot recreate exact copies of PC Engines APU1 firmware images,
I shall upstream the vital changes for coreboot from the following tarballs
SAGE has published to meet GPL:

SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz
md5sum: ce5f54723e4fe3b63a1a3e35586728d4

pcengines.apu_139_osp.tar.gz
md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef

The patch here adds Kconfig, Makefile.inc and devicetree.cb files to
match 2014/04/05 release tarball config.h and static.c files.

Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:34:21 +01:00
Kyösti Mälkki f09e6d47b8 pcengines/apu1: Fork of amd/persimmon
Drop persimmon customization for superio, azalia, PCI-e reset etc.

Change-Id: I35f49ca67e6cc2df826f24e5a4bb3db5bb6f711e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:34:05 +01:00
Kyösti Mälkki 0b87bb7726 AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins
Some GPIO pins are shared with PCI bridge 0:14.4.

As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.

Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2015-02-23 21:33:55 +01:00
Patrick Georgi 477b4c539a AMD Fam10h: Don't write uninitialized data into ACPI
The goto statement skipped all the code that is necessary
to fill in the data structures that are read right after
the jump.

Since there doesn't seem to be useful data, why write these
ACPI objects in the first place?

Change-Id: I1d06c11a7a31517b81e54159355d5c27e3cc3735
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 20:33:45 +01:00
Patrick Georgi b4ad5d0a93 drivers/xgi: Avoid double-free
xgifb_probe() doesn't own the object it tries to free
in its error code path, potentially leading to a
double-free in xgi_z9s_init().

Since we don't actually implement free, it doesn't matter
too much, but let's keep things proper.

Change-Id: I70c8f395fd59584664040ca6e07be56e046c80fc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8506
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-23 20:33:38 +01:00
Dave Frodin 1f565b4023 Remove */cpu/amd/agesa/* from excluded illegal globals file
The change in commit 5636237 allows */cpu/amd/agesa/* to be removed.

TEST: Booted the amd/parmer board.

Change-Id: I8d2d2639f8e5f3b1dd58be96be98db0eff7b268f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8505
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-23 10:39:43 +01:00
Dave Frodin b85656f285 cpu/amd/agesa: Use alloc_cbmem() only in ramstage
This copies a change made in commit 1cc3338 that allows alloc_cbmem()
to be called only in ramstage. This will allow the */cpu/amd/agesa/*
field to be removed from the list of illegal_globals EXCLUDE_FILEs.

TEST: Booted the amd/parmer board.

Change-Id: I2d4b5352815aae090ffce7b83e487f7c0a4d0c88
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-23 10:39:39 +01:00
Patrick Georgi d3f3df3c6d drivers/xgi: terminate file with newline
That's just how we roll.

Change-Id: I47ef62476703fdf2544d9cd77c30ae12452afeae
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8514
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 09:46:10 +01:00
Werner Zeh a8b03da4a8 drivers/pc80/mc146818rtc: Enable RTC reset on power loss
If function cmos_init() was called with parameter invalid
set, this indicates, that the caller has found a power
loss event in the RTC registers. In this case, we need to
load the default date and time because it can be corrupted.

Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8373
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-23 09:09:25 +01:00
Timothy Pearson bc1abb12a9 drivers/i2c/w83793: Remove incorrect zeroing of PWM values
Fan 2 and Fan 3 were inexplicably set to zero after device
setup.

Change-Id: I37945745dbfaf33eb28808d85cdf75dca401e44b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8520
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-23 08:32:45 +01:00
Dave Frodin 1cc3338c1d cpu/amd/pi: Use alloc_cbmem() only in ramstage
Without this change the builder would fail with the complaint
that there was a global static variable in romstage. alloc_cbmem()
is only called in ramstage. The alternative was to add
*/cpu/amd/pi/*.romstage.o to the list of illegal_globals
EXCLUDE_FILEs in arch/x86/init/romstage.ld.

TEST: Booted the amd/lamar board.

Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21 00:27:17 +01:00
Bruce Griffith fa0ab8cfc2 AMD Bald Eagle: Add CPU subdirectory files for new AMD processor
This adds the AMD Family 15h model 30 CPU.
S3 suspend/resume currently is not supported.

Tested on the amd/lamar platform.

Change-Id: Ifef55747a5d715b17937fc75ab9d35945b59f0e6
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-21 00:24:44 +01:00
Alexandru Gagniuc e5ccbfd290 cpu/allwinner/a10/twi.c: Refactor I²C handler to use i2c_seg API
The coreboot I²C API was completely reworked in commit
* cdb61a6 i2c: Replace the i2c API.

For the allwinner I²C driver, wrappers to the old API were provided
on a "best guess" basis. Replace these wrappers with proper
transaction handling based on the i2c_seg API.

Change-Id: Ibdda3b022ce4876deb2906e17a5a0ca9e939aada
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8431
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-20 23:24:17 +01:00
Alexandru Gagniuc 1959abd790 drivers/xpowers/axp209: Adapt to new I²C API
Originally, axp209_(read|write) accessors relied on i2c_(read|write)
to return the number of bytes transferred. This was changed in
* cdb61a6 i2c: Replace the i2c API.
to return an error code or 0 on success. This caused the AXP209 check
to fail. Fix the accessors to account for this new behavior.

Change-Id: Ib0f492bd52260d224d87f8e8f2d3c1244d1507df
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8432
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-20 23:20:56 +01:00
Kyösti Mälkki c5163ed83b AMD binaryPI: Drop HT3_SUPPORT
Kconfig variable is not implemented.

Also fix broken abuild.

Change-Id: I569f44e97abc570158472ddbd0f890315233f8a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8494
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-20 07:56:09 +01:00
Kyösti Mälkki 7255062ea7 AMD fam10: Refactor variables in scan_chain
We only need one of devx and dev. This function should be called
with dev already adjusted if link_num > 3.

Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8351
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:06:12 +01:00
Kyösti Mälkki e40beb1f79 AMD fam10: Move the test for connected HyperTransport link
Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8350
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:05:38 +01:00
Kyösti Mälkki 26c664759b AMD K8 fam10: Refactor offset_unitid configuration
Change-Id: I198f2ad321e1a8b6d932f5624b129e312e36a309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8349
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:04:00 +01:00
Kyösti Mälkki f5e7fa22e7 AMD amdfam10: Always have HT3_SUPPORT
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:43 +01:00
Kyösti Mälkki 260a6db7ec AMD K8 fam10: Drop link_num from scan_chain parameters
Change-Id: Id8fc1d7d8a23238e6848cd2cf4270d782e90a7d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8347
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:25 +01:00
Kyösti Mälkki fe57eeb5bf AMD K8 fam10: Remove some excessive preprocessor use
Change-Id: Iee51c51b662d1f5e3d918d1e5b961f06c6b99df6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8346
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:12 +01:00
Vladimir Serbinenko d15bddab57 sandybridge: Try lower frequency if PLL didn't lock.
Change-Id: I2c2d586fc572b78b5019f8ef2714959799a8d2a9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8480
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-19 00:21:31 +01:00
Dave Frodin 891f71a541 amd/00730F01: Move SteppeEagle specific settings to northbridge
These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.

Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-18 18:55:56 +01:00
Alexander Couzens 452efc23b9 cpu/intel/model_2065x|nehalem: remove unsupported MSR_PP0/MSR_PP1
They seem to have been copy-pasted during the backport from sandybridge.

Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8295
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-18 12:40:31 +01:00
Timothy Pearson a2f79d5971 cpu/amd/model_10xxx: Add monotonic timer support
Change-Id: Idf37d51c6b53ae85dc96fb609531ceda06ec948c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8470
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-18 01:26:51 +01:00
Patrick Georgi d6e40a5942 tegra132: Postprocess bootblock properly
It's not very useful to try to link a host tool into
the bootblock image.

Change-Id: Id3b6496c061d41184fbb516d56746855b455b0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/8473
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-17 18:11:01 +01:00
Alexandru Gagniuc 8b2c8f1c10 sandybridge/raminit: Get max mem clock from devicetree
Note that the limit is not set in the devicetree.cb which use native
sandybridge raminit, as it is not needed. When that isn't set, it's
automatically set to zero, and when we find that, we automatically
return the default limit. Thus behavior isn't changed for any board.

Change-Id: I447399eea71355612b654710a56f3a0077c2f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8476
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17 17:38:50 +01:00
Alexandru Gagniuc fe951d899d sandybridge/raminit: Do not die() if timC calibration fails
We can successfully bring up systems if timC calibration fails, as has
been demonstrated with google/butterfly. As a result, do not die(),
but simply print a message and continue in the hope that we may be
able to boot.

Change-Id: I49ec80324f63b2d45ae8f61c5c26454acb9c232f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8475
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17 17:37:37 +01:00
Furquan Shaikh f0990dac1e tegra132: Add BCT support in tegra132 soc
Builds with cbootimage.

BUG=None
BRANCH=None
TEST=build test

Original-Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203145
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 4778ae4d08a25306407f0fd2fe47976d63463f9d)

Increase the bootblock area for the larger BCT that is generated by
the coreboot version of the cbootimage tool.

Change-Id: I42b8208504bf4936a9fa14f820d665590f6a3754
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8413
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-17 05:25:59 +01:00
Furquan Shaikh d6ba1541ec google/rush: Add BCT support in mainboard rush
Changes might be required for .bct files as we get to know more.
Pulling in files from mainboard nyan for now

BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/203144
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d3633f8cf8c01a07b54ceef2dd7bf7a64afd7c76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8412
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-17 05:25:40 +01:00
Yen Lin ba118cc3a9 T124: perform ram_repair when CPU rail is powered on in warmboot
This patch is to perform software triggered RAM re-repair in
the warm boot path.

"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.

Also, note that this file isn't built in coreboot proper, but is a
companion binary for kernel. It resides here for safe keeping.

BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run suspend_stress_test on nyan.

Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I540f8afbffa323d1e378cb6ba6a20be4afd08339
Original-Reviewed-on: https://chromium-review.googlesource.com/207422
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit f06c413c42819f8f75d9b0fecde02b82583f1d2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I151ce943ce8623e46cc55f890bbd6fc641cc2b98
Reviewed-on: http://review.coreboot.org/8416
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-17 01:16:55 +01:00
Yen Lin 5840626cec T124: perform ram_repair when CPU rail is powered on in coldboot
This patch is to perform software triggered RAM re-repair in
the cold boot path.

"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.

BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run cold reboot test on nyan.

Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I87869431e80e7bc66948a7f67f35e5b907993765
Original-Reviewed-on: https://chromium-review.googlesource.com/207362
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit d999f5ecc31d90c8dce1dd91533bc34ffd3c03f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iaee1d7f9fa8856f26d7ead70eaeeff9d80dbb181
Reviewed-on: http://review.coreboot.org/8415
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-17 01:16:47 +01:00
Jimmy Zhang b365530bb6 tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIME
Based on TRM, cpu clock enabling and reset vector setting should
all be done properly before ungating cpu power partition. Otherwise,
with current code, a race condition could occur where cpu starts but
reset vector has not been set.

BUG=chrome-os-partner:30064
BRANCH=none
TEST=run nyan_big reboot test. No issue is experienced.

Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I571e128693bb2763ee673bd183b8cf60921dc475
Original-Reviewed-on: https://chromium-review.googlesource.com/206682
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 106480ff32406c899a24544fdfab858db5afd1d9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I3da6018dd68e4c15d2c58db566a9745b0b26c365
Reviewed-on: http://review.coreboot.org/8414
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-02-17 01:16:34 +01:00
Kyösti Mälkki b4fa3fd2ae nvidia/ck804: Minor cleanup on dead code
Change-Id: I07f4190ab73ec3468e3738be14d64468e2a05720
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8340
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:14:18 +01:00
Kyösti Mälkki 413e3da8c0 nvidia/ck804: Fix redundant configuration defines
All code must agree on PCI enumeration for the CK804 device,
define these only once. The definition in enable_usbdebug.c was
different and was assumed incorrect.

Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:14:02 +01:00
Kyösti Mälkki facf0b9361 Revert "nvidia/ck804: Add ability to override CK804 base unit ID"
This reverts commit b871687991.

Use of #ifndef here makes it error-prone and hides errors.

Change-Id: I13a999250c80adedb6b3fd4963a862ff106750f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:13:50 +01:00
Timothy Pearson 2af1e4402b mainboard/asus/kfsn4-dre: Add HT speed limit to NVRAM
Change-Id: Ia4829447835dd26381185c586eaac210dc0591d9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8463
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 21:05:27 +01:00
Timothy Pearson 03259a8794 northbridge/amd/amdht: Get maximum HT link frequency from NVRAM
This patch allows the user to set a maximum HT link frequency in
NVRAM, paralleling a similar option available in the proprietary
BIOS on some mainboards.

Change-Id: Iba3789262eefa52421e76533cbf14d9da2ef1de8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8462
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 21:04:55 +01:00
Timothy Pearson 033bb4bc8d acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9.  The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.

The modified code will function with up to 99 cores.

Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16 21:02:30 +01:00
Timothy Pearson 4f731f2eab northbridge/amd/amdfam10: Remove HT link frequency from Kconfig menu
Change-Id: I48d2cda330d8e8f1e58bc670e4e898479216e576
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8461
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 20:35:19 +01:00
Timothy Pearson 94efd19517 mainboard/cmos: Kill off unused boot_* parameters
Change-Id: I19d6b56e3ac5e6e7946648b97c86a223b748e3bd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8460
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:24:14 +01:00
Timothy Pearson c0ae684d16 mainboard/cmos: Move ECC variables out of fallback mechanism byte
Change-Id: Icebc12d8f83494150a7bdd3adcc168d7b48b2e68
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8458
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:23:44 +01:00
Timothy Pearson 9b68f05fc8 mainboard/cmos: Delete obsolete commented parameters
Change-Id: Iccad79c142a7fcf89dd0fbebe8c07ad9ef019e91
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8459
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-16 09:23:02 +01:00
Timothy Pearson c5ca13758f mainboard/amd/amdfam10: Update AMD K10 socket F NVRAM layout files
This removes spurious K8 options and adds appropriate K10 options.
File content taken from the functional K10 ASUS KFSN4-DRE board.

Change-Id: I237bb139056f39f21416268cb52d24c5bc5f111d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8456
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:13:09 +01:00
Timothy Pearson 83b556884f mainboard/asus/kfsn4-dre: Remove hard-coded ECC scrub rate
Change-Id: I6ccf44645dabf8ac3674f40d3c5cbcf694aa6237
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8441
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:11:59 +01:00
Timothy Pearson 2b1bcc1253 northbridge/amd/amdfam10: Remove Kconfig memory controller options
All settable memory controller options are now controlled by NVRAM,
making the Kconfig options irrelevant.

Change-Id: I9b2c8798d830e5c41bb9a108514e60d784d2ebc5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:11:32 +01:00
Timothy Pearson 3c206781f2 northbridge/amd/amdfam10: Fold back memory frequency based on MCT load
K10 processors cannot operate at full memory speeds when more than a
certain number of DIMMs are installed on a specific channel.  The
allowed DIMM numbers and speeds are listed in the BKDG; this patch
implements the appropriate frequency reduction to ensure stability.

Change-Id: I8ac5b508915e423d262ad36c49de1fe696df2ecd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:08:12 +01:00
Timothy Pearson a70093611f mainboard/asus/kfsn4-dre: Add memory interleave options to NVRAM
These values were originally hard-coded in the AMD MCT wrapper.

Change-Id: I12056d38d5348e70a44c192385e22e715e207792
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8454
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:05:33 +01:00
Timothy Pearson c936624433 mainboard/asus/kfsn4-dre: Add ECC redirection to NVRAM
Change-Id: Ie7a73a5962e61585ebc427005e72715c8da4e0ac
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8451
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:03:50 +01:00
Timothy Pearson e23d5b0d59 mainboard/asus/kfsn4-dre: Add ECC scrub rate to NVRAM
Change-Id: Iaece709f521aaf6689b71bc0c71606847c3e1e4e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8439
Tested-by: build bot (Jenkins)
2015-02-16 09:02:59 +01:00
Timothy Pearson f20c6e81fe nvram: Add option to reset NVRAM to default parameters on every boot
In specific configurations, such as homogeneous supercomputing systems,
changeable NVRAM parameters are more of a liability than a useful tool.
This patch allows a coreboot image to be compiled that will always set
the NVRAM parameters to their default values, reducing maintainance
overhead on large clusters.

Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 08:36:37 +01:00
Timothy Pearson 5fc1ad101c mainboard/asus/kfsn4-dre: Add default NVRAM settings
Change-Id: Ic86104d6e7811b0bda9279411db84f464324994a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8450
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 08:27:08 +01:00
Timothy Pearson 68c4475df3 mainboard/asus/kfsn4-dre: Fix invalid CMOS enums
Change-Id: Id837445f346e9ab0218ccca12794b519a8a71c0d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8449
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 08:07:34 +01:00
Timothy Pearson 2012b8127b northbridge/amd/amdmct: Fix FTBFS with node interleaving enabled
This fixes errors of the form:
error: 'Dct0MemSize' may be used uninitialized in this function

Change-Id: Ifc853aea9050994f5641c57a081aa0667331c995
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8455
Tested-by: build bot (Jenkins)
2015-02-15 19:27:35 +01:00
Alexandru Gagniuc b93dcec9f4 hp/pavilion_m6_1035dx: Provide CMOS defaults
TEST: Boot with corrupted CMOS and make sure console level defaults
to SPEW, instead of 0, and that cbmem console is not empty.

Change-Id: I8ab2423e99bbe116f52ad27f4b20427d8557f6ff
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8379
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-15 18:15:06 +01:00
Timothy Pearson 068ca9c8fc northbridge/amd/amdmct: Allow override of memory settings via NVRAM
This patch allows the following memory controller settings to be overridden in NVRAM:
Memory frequency limit
ECC enable
ECC scrub rate

Change-Id: Ibfde3d888b0f81a29a14af2d142171510b87655e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8438
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15 17:54:35 +01:00
Paul Menzel eb605d72b2 device/device_util.c: Add space after ellipse for better legibility
Currently the coreboot console log contains messages in the following
form.

	Show all devs...Before device enumeration.
	[…]
	Show all devs...After init.

Add a space after the ellipse, so it’s better readable and it does not
look like a newline is missing.

	Show all devs... Before device enumeration.
	[…]
	Show all devs... After init.

Change-Id: Ifa2a37b8d60c433c219df7533a79fced03b6271a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-15 09:21:09 +01:00
Kevin Paul Herbert bde6d309df x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
2015-02-15 08:50:22 +01:00
Alexandru Gagniuc 4b10dec1a6 cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM
The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions

However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.

Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.

Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 22:54:01 +01:00
Kyösti Mälkki 24501cae52 AMD cimx/sb800: Initially enable all GPP ports
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().

Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:59 +01:00
Kyösti Mälkki 41cd047cd2 AMD cimx/sb800: Move cimx init for ramstage
This has nothing to do with SATA controller. We only need to
fill the table with defaults before we parse devicetree for
changes to device configuration.

Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:44 +01:00
Kyösti Mälkki 8dba709a06 AMD cimx/sb800: Disable unused GPP ports
If devicetree.cb has GPP port off, really disable it before even
trying to do link training.

Change-Id: I810945da28d86768e88249dc4d29a50ad9f9959b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8385
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:33 +01:00
Kyösti Mälkki 486c05f4bf AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration
A set of pins can be configured for GPIO or (parallel) PCI bridge use.

When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.

When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.

As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.

Drop related dead code.

Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:23 +01:00
Kyösti Mälkki 11f9c35bd2 AMD cimx/sb800: Fix console output
These sb800_enable() messages without newline mess up the log.

Change-Id: I1689b68702e08e2a287083835f310f52f495c451
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8384
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:15 +01:00
Kyösti Mälkki 2a2d6135a4 AGESA fam15tn fam15rl fam16kb: Drop HT3_SUPPORT
Kconfig variable is not implemented.

Change-Id: I546a1001847e7b1002f96baf49ed3301852a6894
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8345
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:48:42 +01:00
Kyösti Mälkki 225da645ad AGESA fam10 fam12 fam15: Always have HT3_SUPPORT
Keep the slower HyperTransport configuration for a possible reference
in fam15 boards.

Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8344
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:48:05 +01:00
Paul Menzel ddea94259a arch/x86/boot/tables.c: Remove unused variable assignment to `rom_table_end`
Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:13:37 +01:00
Alexandru Gagniuc 23804fc6e5 drivers/xpowers/axp209: Print a message when probing fails
Probing is done by reading the ID register and comparing it to a known
value. When there is a mismatch, print an error.

Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 19:03:04 +01:00
Dave Frodin a0edc78523 superio/fintek/f81216h: Add the correct unlock key values
The actual key values were not added in commit 17ace8255.
TEST: amd/lamar shows the correct result.

Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8375
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:53:26 +01:00
Furquan Shaikh a02c265e3f arm64: Cleanup arch io header files
BUG=None
BRANCH=None
TEST=Compiles successfully for rush

Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203142
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48
Reviewed-on: http://review.coreboot.org/8410
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:34:37 +01:00
Dave Frodin 4675c598a4 southbridge/amd/pi: Combine and correct the IRQ text strings
This combines the Avalon and Bolton tables of text descriptions
of the IRQ assignments. It also corrects the text string for
the SD controller on Bolton.

Test: This was verified on amd/lamar.

Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8374
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:31:06 +01:00
Marc Jones f5b65a34fd tegra132: Fix build for verstage
Verstage isn't included yet, but we need to have
the Kconfig option for toolchain.inc to pass.

Change-Id: I7fae73cd3b77fd347398221489caf745274701eb
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8409
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-13 22:34:14 +01:00
Timothy Pearson b32bf54c31 northbridge/amd/amdfam10: Move K10 specific menu to proper Kconfig file
Change-Id: Ib83ec5c397fdef5aa9e3376f1c0072cfa2f74fa6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8425
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-13 09:30:15 +01:00
Werner Zeh 2a84445748 fsp_baytrail: Add macros to define 20K pull-up and down
Add two macros to gpio.h which allow to setup 20K
pull-up or pull-down resistor for a given GPIO.

Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8402
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-13 09:29:28 +01:00
Stefan Reinauer 1e9336e89c Fix source code permissions
Two source files were accidently marked executable. Switch them back to
mode 644 (rw-r---r--)

Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9
Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8426
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-13 01:48:23 +01:00
Timothy Pearson 7a4454f9ce drivers/xgi: Fix user-visible typo in printk
Change-Id: I1e4c5c807d4a78844a40083178b6f96ffeb3659e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-12 04:41:53 +01:00
Timothy Pearson adb5908dc8 payloads/seabios: Enable SeaVGABIOS option if native text init supported
SeaVGABIOS supports both the coreboot linear framebuffer and native EGA
text mode.  To use SeaBIOS interactively on standard VGA hardware a VBIOS
is needed; SeaVGABIOS is one such option.

TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS.  Was able to
interact with SeaBIOS and comboot menu, then booted Linux successfully.
VGA display was continuously usable from power on to Linux login.

Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8368
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-12 04:41:39 +01:00
Paul Menzel 4549e5a665 AMD K8 boards’ `romstage.c`: Spell sync*hr*onize correctly
Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5101
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-12 02:27:07 +01:00
Nicolas Reinecke 0908839323 cpu/amd/model_10xxx: add Propus (00100F52h BL-C2) equivalent id
Change-Id: I32eccfb4eae176e0155c53efaf463258653eefc2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8355
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:44 +01:00
Timothy Pearson 6fdb4d5d3c amd/amdfam10: Fix incorrect core count identification
The core count identification code in the PowerNow! _PSS
ACPI object generation code was incorrectly copied from the
model_fxx code.  This code has been rewritten to properly
return the number of cores installed in the system.

Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8421
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-11 23:10:10 +01:00
Nicolas Reinecke 2f5bb6548d asus/m4a785/Kconfig: Add vgabios PCI id
The PCI id defaults to 1106,3230 -> via chrome 9 ...
Tested on the board.

Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:43:21 +01:00
Nicolas Reinecke fa0b3c8cdd cpu/amd/model_10xxx: update microcode
microcode updates are extracted from: www.amd64.org/microcode.html
Mircocode versions of 1020h and 1022h are more recent in coreboot
than inside the AMD archive.

Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8354
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 22:41:33 +01:00
Timothy Pearson f73179d4be mainboards/asus/kfsn4-dre: Run BSP FIDVID before AP FIDVID
This resolves an issue on Shanghai dual CPU configurations where
the APs on node 0 would not start.  Single CPU configurations are
unaffected by this issue.

TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified
proper BSP/AP start and microcode patch levels.

Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8397
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-11 07:16:47 +01:00
Alexander Couzens f251a6d7d4 cpu/intel: >= nehalem: add comments to msr finalize's
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.

Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-02-11 02:58:06 +01:00
Kyösti Mälkki 754fac4346 PCI subsystem: Remove AGP bridge type
There is no auto-detection for AGP type and we have no hardware that
selects this. Furthermore, we treat AGP bridges just like PCI bridges,
there is no optimisation for higher bandwidth.

Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8367
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:38:32 +01:00
Werner Zeh b474abee84 Baytrail_fsp: Make ME path configurable in menuconfig
By adding a description to ME_PATH it becomes visible
and editable in menuconfig.

Change-Id: I8c2f6a30c10f16b19f3667263db02c93688c9f8f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8398
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-10 09:26:52 +01:00
Michał Masłowski 208a53527a lenovo/x200: Increase default CBFS_SIZE to 2 MiB
The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB
flash variants.  Let's allow using the whole region instead of the
gm45 default of 1 MiB.

Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/8392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-10 07:27:06 +01:00
Timothy Pearson c1f47c1460 amd/amdfam10: Fix invalid transition latency in PowerNow! _PSS objects
Fix a mistake that led to an invalid 0ms latency in the automatically
generated PowerNow! ACPI _PSS objects.

TEST: Booted FreeBSD and Linux and verified correct latency values.

Found-by: Coverity Scan
Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8376
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-10 07:26:32 +01:00
Martin Roth 2213843ae8 fsp_baytrail: Get FSP reserved memory from the FSP HOB list
Because the pointer to the FSP HOB list is now being saved, we can
use that to find the top of usable memory.  This eliminates the need
to hardcode the size of the FSP reserved memory area.

Tested on minnowboard max for baytrail.

The HOB structure used does not seem to be present for the rangeley
or ivybridge/pantherpoint FSPs.  At the very least, the GUID is not
documented in the integration guides.

Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8308
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-09 17:44:31 +01:00
Martin Roth ad4fa21705 Get rid of .car.global_data warnings for GCC build
The "used" attribute was added in commit 27cf2472 which caused these
warnings to start appearing when using the standard coreboot GCC
toolchain:

{standard input}: Assembler messages:
{standard input}:96: Warning: ignoring changed section type for .car.global_data
{standard input}:96: Warning: ignoring changed section attributes for
.car.global_data

The # at the end of the section name causes the assembler to
ignore everything following the name. I verified that the resulting
binaries are the same with and without the #.		

Change-Id: Iaac8042533842ed887f33895f083b613a18f496a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8301
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-02-09 17:44:02 +01:00
Kyösti Mälkki cd02ef19e5 Intel FSP platforms: Fix timestamps
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.

Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-09 11:41:34 +01:00
Nicolas Reinecke 29d358e6a1 lenovo/t430s: Add new port.
The port is based on the x230 / t530.
Tested - is in active use.

Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8359
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-08 09:26:46 +01:00
Alexandru Gagniuc b5669ba579 drivers/pc80/mc146818rtc: Reduce superfluous preprocessor use
cmos_init() had layers of preprocessor directives, which resulted in
a complete mess. Refactor it to make use of the IS_ENABLED() macro.
This improves readability significantly.

One of the changes is to remove in inline stub declaration of
(get|set)_option. Although that provided the ability for the compiler
to optimize out code when USE_OPTION_TABLE is not selected, there is
no evidence that such savings are measureable.

Change-Id: I07f00084d809adbb55031b2079f71136ade3028e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8306
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 23:56:04 +01:00
Alexandru Gagniuc a4d784eeab include/types.h: Provide BIT() macro
This macro is controversial for arches where the bits are numbered
MSb first, though we don't support such an arch. We've seen this macro
creep into our tree in different places, so provide it in one place.

Change-Id: I86cd8a16420f34ef31b615aec4e0f7bd3191ca35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8280
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-02-06 19:25:57 +01:00
Timothy Pearson da8fcf0afe mainboards/asus/kfsn4-dre: Indicate native text mode init support
Change-Id: Ib00ecdcad17fa5c0300d22378837e36d0918f9db
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8369
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06 19:22:56 +01:00
Timothy Pearson 08c15ed266 drivers/xgi: Fix legacy VGA text mode initialization
TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s
Initial text from coreboot appeared, and the Linux
console was displayed immediately at the start of
kernel initialization.  After boot was complete
the text mode console continued to behave normally.

SeaBIOS does not currently make use of the legacy
VGA text-mode display.

Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8360
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-06 19:22:36 +01:00
York Yang 114baa0a0a intel/fsp_rangeley: Indent '#define' consistently
The indentations of #define are not consistent in chip.h. Update to make 
all #define indentations being aligned and put them after the variable 
declaration.

Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8333
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2015-02-06 00:58:50 +01:00
Martin Roth 582b2aee0f FSP & CBMEM: Fix broken cbmem CAR transition.
1) Save the pointer to the FSP HOB list to low memory at address 0x614.

This is the same location as CBMEM_RESUME_BACKUP - the two aren't used
in the same platform, so overlapping should be OK.  I didn't see any
documentation that actually said that this location was free to use, and
didn't need to be restored after use in S3 resume, but it looks like
the DOS boot vector gets loaded juat above this location, so it SHOULD
be ok.  The alternative is to copy the memory out and store it in cbmem
until we're ready to restore it.

2) When a request for the pointer to a CAR variable comes in, pass back
the location inside the FSP hob structure.

3) Skip the memcopy of the CAR Data.   The CAR variables do not
get transitioned back into cbmem, but used out of the HOB structure.

4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.

Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8196
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 00:53:13 +01:00
Kyösti Mälkki 0490f74d78 TPM: Fix whitespace
Change-Id: I2d00a2964b16436356c5e02764897e37ef610efc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8343
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-06 00:25:59 +01:00
Timothy Pearson 67085e0c09 mainboards/asus/kfsn4-dre: Enable native VGA initialization
Change-Id: I953ced7d34af9ec0923fa6df93b9ad4270196c77
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8332
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:37:17 +01:00
Timothy Pearson c522fc8f38 drivers/xgi/z9s: Port Linux framebuffer initialization to coreboot
Add native XGI Z9s framebuffer support to coreboot
XGI initialization code largely taken from Linux 3.18.5

TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS
with SeaVGABIOS enabled.  Text appeared correctly on screen
and interaction with graphical comboot menu was successful.
However, Linux cleared the framebuffer on boot, rendering the
screen useless until Linux loaded its native xgifb driver.

Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8331
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:37:05 +01:00
Dave Frodin 5c015f045d southbridge/amd/pi: write_hpet requires additional config option
This copies what was done in southbridge/amd/agesa in:
commit 56f46d8 agesa/family15tn: Switch to per-device ACPI

TEST: amd/lamar.

Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8288
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:34:05 +01:00
Dave Frodin ef9a4e6aec southbridge/amd/pi: Update Kconfig and makefiles for bolton
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8287
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:33:42 +01:00
Dave Frodin 9cfa742a26 southbridge/amd/pi: Add the bolton definitions
This adds the PCI and interrupt related definitions
for the bolton specific features.

Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-05 17:33:00 +01:00
Kyösti Mälkki c3f6bb086b AMD HyperTransport: Drop unused link optimisation
Change-Id: Ia4398f6eb013c69838487bdd02d094f97d7224b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8342
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 16:11:43 +01:00
Kyösti Mälkki 08e39c572f AMD K8: Remove some excessive preprocessor use
Tests on CPUID are valid regardless of revision.

Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:20:42 +01:00
Kyösti Mälkki 9bc83888ad newisys/khepri broadcom/blast: Drop duplicate entry in Kconfig
Keep the value that is listed first, it also the one with a more
recent change.

Change-Id: I0336c962544d75f94512563c08f280aa43c7a175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8336
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:18:06 +01:00
Kyösti Mälkki 09b5e4d005 AMD8131: Remove obsolete directory
Change-Id: I875384e55a4a71d1a5c962d128d13356f3befa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8335
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:17:42 +01:00
Dave Frodin 17ace82552 superio/fintek: Add required changes so F81216H can be used
The amd/lamar mainboard is the first mainboard to use the f81216h.
These changes are needed to fix up commit 27a63d77 so the
Super I/O builds and functions correctly.
  - Wrong #include name
  - Removed global variable in romstage
  - Missing "case" in switch()

Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8255
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-04 15:45:39 +01:00
Kyösti Mälkki 1608f3651f cpu/amd (non-AGESA): Remove terminator from microcode blob
Change-Id: I6370e971922dee5e8d476a883c5f0f32fbbc8911
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:52:12 +01:00
Kyösti Mälkki d15cb519ad amd/model_10xxx: Drop AMD_UCODE_PATCH_FILE selection
Include microcode updates in CBFS for every CPU revision the platform
can support, as changing to different CPU revision should not require
a coreboot rebuild.

This increases CBFS usage from 2 kB to 14 kB.

Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4521
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-02-03 04:52:00 +01:00
Kyösti Mälkki 5fe1fb7a5f cpu/amd (non-AGESA): Load microcode updates from CBFS
Change-Id: Ic67856414ea2fea9a9eb95d72136cb05da9483fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4502
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:52 +01:00
Alexandru Gagniuc 893b81f79f cpu/amd/model_10xxx: Remove UPDATE_CPU_MICROCODE option
This option is now deperecated by loading microcode updates from cbfs.
Remove this option in anticipation of implementing CBFS loading for
AMD cpus. Removing it beforehand results in less patch overhead.

Change-Id: Ibdef7843db686734e2b6b1568692720fb543b240
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-02-03 04:51:43 +01:00
Jonathan A. Kollasch 30c34c0751 nvidia/ck804: make Message Signaled Interrupts work
Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable
HT MSI Mapping so that MSIs work.  Prior to this change PCIe devices
downstream of the CK804 with MSI enabled would fail to actually assert
their interrupt.  Tested on msi/ms7135 and winent/mb6047 running Debian
GNU/Linux 7.0 (wheezy).

Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8276
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-03 00:47:26 +01:00
Alexandru Gagniuc a583924252 src/arch/*/include/stdint.h: Provide definitions for bool type
Although bool normally belongs in stdbool.h, for our use cases,
providing these definitions in stdint.h is acceptable.

Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8279
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2015-02-02 20:29:23 +01:00
Jonathan A. Kollasch e299ae673c winent/mb6047: switch to CAR version of ck804 early_setup.c
Change-Id: I9b45b7fbd862a5600ead7ad4e623a8a87ae364aa
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8319
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:48:36 +01:00
Jonathan A. Kollasch bdebb07d2f winent/mb6047: clean up includes in acpi_tables.c
Change-Id: I63bdc856fa4232cd66ff2e48e39c2cdb97bb88d3
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8316
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:45:43 +01:00
Jonathan A. Kollasch 679efee2d7 winent/mb6047: use correct ACPI SCI interrupt trigger
Change-Id: I245c0afb66f3a29b5acb40e8d949d8b1aa08cd73
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8315
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-01 16:43:39 +01:00
Jonathan A. Kollasch fcf5988cf6 winent/mb6047: drop inaccurate comment in acpi_tables.c
Change-Id: Ib0bb8bed32b96a5f7fd48407bd111972f89e7907
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8314
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 16:11:17 +01:00
Vladimir Serbinenko ac1b6def75 lenovo/x230: Set xhci_switchable_ports and superspeed_capable_ports.
Fixes USB3 ports degraded to USB2 speeds.

Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8313
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-01 10:12:12 +01:00
Vladimir Serbinenko b26156ec65 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8312
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 08:22:40 +01:00
York Yang e1e11e63af intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
by UPD input. Update UPD_DATA_REGION structure for matching up this
FSP change.

PcdCustomerRevision is a debugging aid that will be output to debug
message in FSP. When needed, it can be customized by BCT tool for tracking
BCT configurations.

Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-31 23:09:26 +01:00
Martin Roth 9cd155334b FSP platforms: Clear area in CAR for cbmem
This patch clears the CAR area. The FSP loads the entire CAR area with a
pattern instead of clearing it.  At least the cbmem area needs to be
cleared or cbmem will not use it.

Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8195
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 22:30:03 +01:00
Timothy Pearson 4e6f0c289b asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devices
Test:
Single Opteron 2419 with 1GB RAM in slot A1
Booted Ubuntu Linux 14.04 and verified all 6 cores were visible
Brief stress test of all 6 cores simultaneously
Verified proper ACPI power states for all 6 cores

Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8311
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-31 21:33:20 +01:00
Timothy Pearson 9c8106696e cpu/amd (non-AGESA): Fix AP crash during microcode version lookup
Move mapping tables to struct and prevent OOB array
access that was crashing the APs during CAR initialization.

Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-31 21:33:10 +01:00
Timothy Pearson 0d7f8d0b79 amd/amdfam10: Update name table with Opteron 2400/8400 series codes
Change-Id: I52587c0c0dffd814d39087475b8f14c500a68933
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8309
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-31 21:32:25 +01:00
Nicolas Reinecke 86393bb64b vendorcode/amd/agesa/f14: update microcode
05000028 -> 05000029 tested on asrock E350M1
05000101 -> 05000119

Change-Id: Iccb096eb55a4a789c1e810f68c8c8eacfd5f8a0b
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8296
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:23:35 +01:00
Nicolas Reinecke cb6cfbdc06 mainboard/lenovo/t420s/Kconfig: select NO_UART_ON_SUPERIO
same as 37130ebdab

Change-Id: I73feed3a077dfcc61634147775df1e05fdb97e8b
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8278
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:21:43 +01:00
Nicolas Reinecke 5e03170541 intel/model_2065x: update microcode
Change-Id: I6c13518d2217bc823d409ab800bca011e76e9f25
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8277
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:21:15 +01:00
Nicolas Reinecke 6d1158f3a9 southbridge/intel/bd82x6x native usb init: replace some magic values
Some magic numbers are documented in the PCH datasheet so use them.

Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8307
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:20:15 +01:00
Nicolas Reinecke 266971c1cd lenovo/t530/romstage.c: add usb port description and missing oc config
OC2 at port 4 was missing. Verified with RCBA dump.

Change-Id: Ide5701d53aeee28619204c7ac408662626aa11e4
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8304
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:19:42 +01:00
Nicolas Reinecke 5ecc6bc7d6 lenovo/t5x0: Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.

same as http://review.coreboot.org/4650 /
63acd22dc5

Change-Id: I82d7a2b9f2ec56557b3a9c26d1af57ed39e31850
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8302
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:18:46 +01:00
Kyösti Mälkki 9664345586 devicetree: Search PnP device node from the tree by path
Copied from device_util.c with added ROMSTAGE_CONST.

Change-Id: If872631ed96a79b9a0b15e09382d6f81098c8db3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8297
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-30 16:58:27 +01:00
Timothy Pearson 20c2c4b277 asus/kfsn4-dre/Kconfig: Enable power on after power fail by default
Change-Id: I655843c78d31cc69a007ddaf9b51cde063c48c79
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8299
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-29 15:39:19 +01:00
Martin Roth 5fc32bf5e6 drivers/intel/fsp: Add find_saved_temp_mem()
Add a function to retrieve the location of the CAR temporary memory
that was saved by the FSP into the HOB structure.

Change-Id: I2635de5207cd699740721d333a7706425b837651
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8194
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-29 04:33:53 +01:00
Timothy Pearson 8057285119 mainboards: Add support for the Asus KFSN4-DRE series of motherboards
Status:
Tested with KFSN4-DRE PCB v1.04G
Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work.
Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank).
Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1.
AMD PowerNow! functions correctly via ACPI.
Video, network, USB, SATA, and serial have received thorough testing.
Tested with KFSN4-DRE PCB v1.05G
Single Opteron 2419 CPU tested with 1GB RAM in slot A1.
Booted to PXE configuration menu; not tested further.

Known issues:
RAM initialization is a bit flaky with multiple high-density modules;
this could be a generic MCT training issue but is probably bad hardware.
The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device
works after Linux boots and initializes the device.
Suspend/resume functions at the S1 level but sometimes hangs on resume.
Wake on LAN can be flaky; the strap(s) needed to have WoL work on power
application were not physically installed by ASUS so the board needs to
boot at least once after power application before it will work.

Change-Id: I0709f822eea8ed877f55db9443143028a5400472
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8270
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 22:12:06 +01:00
Timothy Pearson a6f669e183 amd/amdfam10: Allocate the lower DRAM region up to TOM
This fixes the resource allocator locating the PCI register
space below 0xe0000000 thereby causing corruption with more
than ~3.5GB physical RAM on AMD Family 10h systems.

Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8261
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 22:11:48 +01:00
Timothy Pearson 7f3ae39640 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects
Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8285
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 20:58:10 +01:00
Timothy Pearson b871687991 nvidia/ck804: Add ability to override CK804 base unit ID
Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8273
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-01-28 20:00:17 +01:00
Timothy Pearson 6300b03414 amd/amdfam10: Add runtime ACPI _PSS generation
Skeleton and ACPI generator interface taken from
model_fxx powernow_acpi.c
Small portions of FIDVID MSR code taken from
model_10xxx fidvid.c

Nearly completely rewritten for the P-state-based K10 CPU

TEST: KFSN4-DRE with dual Opteron 8356 CPUs
Verified CPU per-core dynamic state change with system load
Verified reported P-state count and frequencies
Stress-tested each CPU (all cores simultaneously) to verify
proper P0 transition and configuration.

Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8284
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:58:36 +01:00
Timothy Pearson e916201004 nvidia/ck804: Fix FTBFS with AMD Family 10h systems
The build failure stems from a missing function being called via a chain
including setup_ss_table(), set_ht_link_ck804(), and
st_ht_link_buffer_counts_chain(); the latter function is only available
in the AMD K8 code.

It appears that a bunch of K8-specific code snuck into the CK804 and MCP55
southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0.

Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8269
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:56:15 +01:00
Timothy Pearson 02112bd280 nvidia/ck804: Add ability to enable/disable PCIe PME# wake events
Change-Id: Ie2937dd220464e3b168aa8a50a57c03b6258c189
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8283
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:03:39 +01:00
Timothy Pearson 684fda5964 nvidia/ck804: Fix cosmetics in Kconfig
Change-Id: Ic675911f534f07516c838b52c9463e89448d4353
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8291
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 18:59:20 +01:00
Timothy Pearson e1cc3abb02 nvidia/ck804: Add ability to bypass register 0x78 initialization
On the ASUS KFSN4-DRE initializing CK804 0x78 causes an almost
immediate soft reset.  Leaving the register at its power-on
default value appears to have no ill effect on that same board.

Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8272
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 05:26:14 +01:00
Timothy Pearson 82982a130c amd/amdfam10: Enhance resource debugging when enabled
Change-Id: Ie39652bded9a42d1d816ca5198db59a83e5c083a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8266
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-28 04:40:39 +01:00
Timothy Pearson c139c42f3f northbridge/amd/amdht: Initialize variable `currentBUID`
Fix uninitialized variable when manual non-coherent BUID
selection is used.

Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8267
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 01:03:44 +01:00
Timothy Pearson 8d9492e536 amd/amdfam10: Serialize mutable ASL methods
Fix three IASL warnings in ASL utility code by making the
methods `GWBM`, `GWEM` and `GIOR` serialized.

TEST: Built and booted on ASUS KFSN4-DRE.

Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8264
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 00:53:35 +01:00
Timothy Pearson e538daeaec amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM
Remove declaration of unused variable `io`.

Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8265
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-27 23:33:34 +01:00
Kyösti Mälkki ae98e83eb2 CBMEM: Always use DYNAMIC_CBMEM
Drop the implementation of statically allocated high memory
region for CBMEM. There is no longer the need to explicitly
select DYNAMIC_CBMEM, it is the only remaining choice.

Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:54:32 +01:00
Kyösti Mälkki 2fb6b40ed0 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT
We can now create CBMEM with dynamic allocation even if CBMEM
location is resolved late in ramstage.

Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7861
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:50:14 +01:00
Kyösti Mälkki 02aebb67b3 CBMEM: Change some types to uintptr_t
Change-Id: Ib2158c866067f9e2e9bfcf4b117eb8b7a2a819c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8191
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:48:43 +01:00
Kyösti Mälkki f1e3c763b3 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.

TODO: Check TSEG alignment, it used for MTRR programming.

Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:48:06 +01:00
Kyösti Mälkki 91fac61240 CBMEM: Tidy up CAR migration
Move the  CAR migration call to arch -specific part of CBMEM init,
it is truly a x86 specific thing.

Change-Id: I715417e54f197b8745e0670d6b900a5660178141
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7860
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:47:35 +01:00
Kyösti Mälkki 3bf3854847 CBMEM: Tag chipsets with LATE_CBMEM_INIT
In preparation to remove the static CBMEM allocator, tag the chipsets
that still do not implement get_top_of_ram() for romstage.

LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE.

Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7850
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:47:00 +01:00
Kyösti Mälkki 8659e4072e CBMEM console: Fix and enhance pre-RAM support
Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can
do CBMEM console in bootblock and romstage. Kconfig forces it to zero
if _BASE is unset or we cannot do CAR migration on x86.

Add CBMEM console to bootblock, except for x86. Only one of bootblock
and romstage clears the pre-RAM buffer.

To start with empty console log on S3 wakeup, ramstage now clears
previous contents of CBMEM buffer if there was no pre-RAM buffer.

Unify Kconfig variable naming.

TODO: ARM configurations do not define PRERAM_BUFFER_BASE values.

Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:44:17 +01:00
Kyösti Mälkki 4d10750d13 CBMEM: Add timestamp_reinit()
This avoids the need for separate timestamp_reinit() calls made
via CAR_MIGRATE() that is not implemented for ARM.

Change-Id: Ia683162f3cb5d3cb3d4b7983a4b7e13306b0cfc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8033
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:43:24 +01:00
Kyösti Mälkki 0a11a61395 CBMEM: Move cbmemc_reinit()
This replaces need for separate cbmemc_reinit() calls made
via CAR_MIGRATE() and in ramstage.

Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7859
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:42:23 +01:00
Kyösti Mälkki e45542580c CBMEM console: Fix CAR migration step
With the change it becomes irrelevant if memcpy() car.global_data or
cbmemc_reinit() is done first.

Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8032
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:42:10 +01:00
Kyösti Mälkki 823edda98e CBMEM: Implement cbmem_run_init_hooks() stub
Until we completely can unify early_variables, use these to
handle CBMEM update hooks for both romstage and ramstage.

For x86, CAR_MIGRATE serves the purpose of romstage hooks.

Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7876
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:41:23 +01:00
Kyösti Mälkki 05369de639 intel: Drop romstage handoff via scratchpad
If HAVE_ACPI_RESUME ever gets implemented, use CBMEM handoff instead.

Change-Id: I77463988fa5324c729579902f4796be4da15d551
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8182
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:10:48 +01:00
Martin Roth 7b132deb80 drivers/intel/fsp: Add HOB tools to work with GUIDs
Add new functions to:
- Compare two GUIDs
- Find a hob based on its GUID
- Print information about GUID_EXTENSION type HOBs
- Print a GUID's address and value

Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27 19:40:24 +01:00
Dave Frodin fedd8e382a southbridge/amd/pi: Clean up whitespace in Kconfig
Change-Id: I4dbccc7d132a14a71107f24124814d30d93d6ece
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8252
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:08:52 +01:00
Dave Frodin bc21a41e1c southbridge/amd/pi: Rename Avalon to Hudson
To maintain consistancy with southbridge/amd/agesa/hudson rename
pi/avalon to pi/hudson in advance of adding support for the
base hudson southbridge.

Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:07:45 +01:00
Dave Frodin bd1d1580d3 northbridge/amd/pi: Correct the path to an #include
Change-Id: Ibf0bd494b2022272cb2d5c4ddb1bdf82ea70ca50
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8250
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:05:22 +01:00
Dave Frodin fa2ec5e4a3 southbridge/amd/pi: Correct several path names
Change-Id: I247c17516cd06970185e271eccb78528a8de01c1
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8249
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:04:37 +01:00
Dave Frodin 6b31431411 southbridge/amd/pi: Correct several yangtze/avalon typos
These were probably accidentally missed when the move
from southbridge/amd/agesa/hudson to amd/pi/avalon occured.

Change-Id: I4cf6e2f8b25899d6d342452cb1b15e694dae35c8
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:03:07 +01:00
Bruce Griffith 98e8253b4f AMD Bald Eagle: Add binary PI vendorcode files
Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB.  This includes the gcc makefiles,
some Kconfig, and the AGESA standard library functions.

Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.

This fix changes the makefile so that the AGESA dispatcher is
built using its own rules rather than generic library generation
rules in coreboot/Makefile and coreboot/Makefile.inc.  The AGESA
source files are initially copied from whereever they live into
coreboot/build/agesa.  They are compiled from there.  The binary
PI directory now has a mandatory structure that places the AGESA
BLOB into the same directory as the support headers.  These will
nominally be placed in the amd directory in SageBIOS or the
3rdparty directory in coreboot.org.

Change-Id: I56788cd197159939b64c7d16c1d32418f8cc2197
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:02:06 +01:00
Timothy Pearson 88d213a63b amd/amdht: Compile in multiprocessor support when selected
Fix multiprocessor support not being compiled in when selected
via Kconfig on AMD systems.

Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8268
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-27 08:04:26 +01:00
Timothy Pearson 367fe8cac1 ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Change-Id: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9
Reviewed-on: http://review.coreboot.org/8259
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-27 06:23:04 +01:00
Furquan Shaikh ae9cd01460 rmodule: Correct the typecast with proper parenthesis
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I67801f96ec63a3150263ce3d6a4a7556092c6be5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209505
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 71cd62740e150cb5b5adc1b20c7f13fa8c51b7e3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0c3f5f10a3af7028728dadca539681a081d858e0
Reviewed-on: http://review.coreboot.org/8237
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-27 01:44:12 +01:00
Daisuke Nojiri efb5cde87f vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integration
vboot2 abtracts tpm storage as some 'secure' space. Thus, it's firmware's
responsibility to handle vboot specific operations with tpm. This CL just copies
related files from vboot_reference so that we can see how code was modified in
the next CL. Note rollback_index.c/h were renamed to antirollback.c/h.

TEST=none
BUG=none
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I1792a622058f70a8fcd3c4037547539ad2870420
Original-Reviewed-on: https://chromium-review.googlesource.com/206462
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 2ae188b29242bf09c5e79e31f98b330a30bf7b93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5fa5a636003e8472127194e961fea4309489b1d9
Reviewed-on: http://review.coreboot.org/8164
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-27 01:43:57 +01:00
Kevin Cheng 3c21e4687b vboot_wrapper: handling VBERROR_TPM_REBOOT_REQUIRED from VbInit().
Doing reset while VBERROR_TPM_REBOOT_REQUIRED occured.

BUG=chromium:389568
TEST=Manual force VBERROR_TPM_REBOOT_REQUIRED returned from VbInit()
     and system will reboot.

Original-Change-Id: I9d7c4b3a380a931a728f792b4013b3b9bf65dfae
Original-Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206337
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 32728dd9fc43a95d6f763a85f9cc7a660a66b175)
Original-Reviewed-on: https://chromium-review.googlesource.com/206948
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 1ea5e233386d236ce20f3d1695fac3a1bc49d4bd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib93fdf7b22918f563d3e29207a75fc831bee186a
Reviewed-on: http://review.coreboot.org/8163
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-27 01:43:48 +01:00
Daisuke Nojiri 224f922604 vboot2: read dev and recovery switch
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=none
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: Ia5353018a0db3dae2e0432b7e6a34d46f81b0ffa
Original-Reviewed-on: https://chromium-review.googlesource.com/206064
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit b420451c71c86bc27784d920f53870ee56ddc0f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I30c9f0ac44de0a5816b5b8d0ded2dc7d7e77c7a1
Reviewed-on: http://review.coreboot.org/8162
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-27 01:43:31 +01:00
Daisuke Nojiri 1989a53ade vboot2: implement vb2ex_read_resource
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I633f9dddbf8b2f25797aacc246bcebaafb02bea4
Original-Reviewed-on: https://chromium-review.googlesource.com/206063
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 1f215672de31847cc647e83d2c04633b7f8dfa33)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I57f449b052132b300f7bca4351871c539a7a8694
Reviewed-on: http://review.coreboot.org/8161
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-27 01:43:17 +01:00
Daisuke Nojiri bcc1d422a2 vboot2: implement select_firmware for pre-romstage verification
This patch has a basic structure of vboot2 integration. It supports only Nyans,
which have bootblock architecture and romstage architecture are
compatible from linker's perspective.

TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa
Original-Reviewed-on: https://chromium-review.googlesource.com/204522
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001
Reviewed-on: http://review.coreboot.org/8160
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-27 01:43:01 +01:00
Stefan Reinauer 77b1655d9b vboot2: add verstage
This reverts the revert commit 5780d6f387
and fixes the build issue that cuased it to be reverted.

Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains,
compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the
boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with
verstage_.

TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none

Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>

(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf
Reviewed-on: http://review.coreboot.org/8224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27 01:41:40 +01:00
Timothy Pearson 40ce5d90b8 nvidia/ck804/lpc.c: Fix power restoration control
Control bits located by changing tristate power
restoration value in proprietary BIOS, booting into
Linux, dumping the entire CK804 configuration space,
then comparing values against those dumped earlier.
"Last state" control bit(s) are unknown at this time.

TEST: Boot ASUS KFSN4-DRE with both coreboot power on
and power off after power failure settings, then
pull power plug / reinsert power plug and verify
mainboard behaviour matches setting.

Change-Id: I737bdd35632fe786968a1cb8458e56c785363cfa
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8258
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-01-27 01:39:25 +01:00
Furquan Shaikh 5c4a5105d8 rush: Add support for rush board
Add basic support for rush board

BUG=None
BRANCH=None
TEST=Compiles successfully with soc tegra132 and armv8 arch selected for
romstage and ramstage

Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197399
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ica57c68d230e4e0e9916729752395843de188733
Reviewed-on: http://review.coreboot.org/8041
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-26 11:41:26 +01:00
Furquan Shaikh 4208e0c834 tegra132: Add support for tegra132 soc
Add basic support for tegra132 soc.

BUG=None
BRANCH=None
TEST=Compiles successfully for rush board using tegra132 soc

Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197398
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63
Reviewed-on: http://review.coreboot.org/8040
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-26 11:41:17 +01:00
Marc Jones 17b9c198e0 arm64: Prepare ARM64 for building
There were a number of issues with the ARM64 build files. This
patch ports the following changes from ARMV4/V7 to ARMV8:

  - make armv8 Kconfig options consistent with armv4/v7
  - fix build include issues in boot.c, tables.c,
    and early_variables.h by matching armv4/v7.

    Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iacd95d336559c45458784d1da67bde62a0956620
Reviewed-on: http://review.coreboot.org/8236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-26 11:41:06 +01:00
Timothy Pearson 5ec1153200 northbridge/amd: Add Kconfig options for ECC redirection
Change-Id: I83e7605650b13e82a2e6c2822cbd237b4e473b5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8271
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-25 20:32:22 +01:00
Timothy Pearson 6f2caa0ffa northbridge/amd: Add Kconfig options for ECC scrub rate
Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8263
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-25 20:31:55 +01:00
Timothy Pearson d0c1dd0205 device/hypertransport.c: Fix typo in comment
Change-Id: Ib63a8b6e7f4663926104426992f6dea9ee3510b0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8262
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-24 23:04:31 +01:00
Zhuo-Hao Lee 29445dc44e device/oprom/realmode/x86: Fix memory corruption
The length of the memcpy is incorrect and this will cause the
destination buffer to corrupt the following 2 bytes of data.

BUG=none
BRANCH=All
TEST=build and boot on rambi, system boot up without error

Change-Id: I96adf2555b01aa35bb38a2e0f221fc2b2e87a41b
Signed-off-by: Zhuo-Hao Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/237510
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
[Remove usage of macro `FIELD_SIZEOF(t, f)`.]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8227
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-20 14:14:08 +01:00
Randall Spangler 7e72abef1b samus: Update indices of ramstage and refcode blobs
This must be committed at the same time as the corresponding
depthcharge change which updates the fmap.

BUG=chrome-os-partner:30079
BRANCH=none
TEST=Build samus firmware.
     dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and
       PD_MAIN_B sections.
     Boot samus.  'crossystem mainfw_act' -> A
     As root, 'crossystem fwb_tries=1'
     Reboot samus.  'crossystem mainfw_act' -> B
CQ-DEPEND=CL:208984,CL:*169850,CL:208989

Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e
Original-Signed-off-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208899
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837
Reviewed-on: http://review.coreboot.org/8219
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-19 22:17:30 +01:00
Duncan Laurie 808a254c3f samus: Delay bringing SSD out of reset
In order to ensure that we meet timing requirements for the SSD
power sequencing delay bringing the SSD out of reset until after
memory training.

BUG=chrome-os-partner:29914
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208155
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317
Reviewed-on: http://review.coreboot.org/8215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-19 22:17:16 +01:00
Duncan Laurie 6a342cb699 samus: Disable self refresh and MRC cache on broadwell
Add workarounds for power and/or lpddr3 issues on Broadwell SKU.

BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208154
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c3ee57114315320b542f53645ffb168ad654b756)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie28f3ad65000a627ba64486e0f16493e8101cef3
Reviewed-on: http://review.coreboot.org/8214
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-19 22:17:02 +01:00
Duncan Laurie 515d3d2e2c samus: Enable keyboard backlight
- Turn on keyboard backlight early in boot (not resume) path
as a sign of life for the system
- Add ACPI device for keyboard backlight so the kernel can find
and make use of it

BUG=chrome-os-partner:30586
BRANCH=None
TEST=build and boot on samus

Original-Change-Id: Iecaef0ec5c814774e19d7c4a14cb92dc236cfee3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208152
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e166f76f9bd167468c7637dcce2b9eabf7dce8f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I47927d97c1586ec09310d014d8fba7d7a3d773c4
Reviewed-on: http://review.coreboot.org/8213
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-19 01:54:00 +01:00
Kane Chen 00aedc5e1a samus: add acpi resource for supporting RT5677 codec
Add codec acpi resource for supporting RT5667 codec.

BUG=chrome-os-partner:29649
TEST=emerge-coreboot successfully
     checked codec device is probed

Original-Change-Id: I739c0dbfdbfa221b06f99c3d934825b640096c6b
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207707
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit f9698c45a47efe7fd2a1f5432640f3db5e4bd3f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib14b27421613d747e02037ecd2311d9966a5d813
Reviewed-on: http://review.coreboot.org/8212
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-19 01:53:43 +01:00
Kyösti Mälkki 2e3bdcf76e asrock/e350m1: Fix PCIe slot for x4 cards
Configuration for GNB GPP was incorrect, only PCIe x1 cards worked.

Change-Id: I369bf6382080e6034ff138ac664c76b03280ca69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8229
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-17 16:40:25 +01:00
Kane Chen 374f27bc02 baytrail: there is a chance that USBPHY_COMPBG is set to 0
Due to some projects don't have the correct settings in devicetree.cb
so put this change in case those projects without are setting in devicetree.cb

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly
     even there is no setting in devicetree

Original-Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209051
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 713f809952a2d8da434d619d48cb7ddce1991925)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I86f9b77e703d2b844fa636678499c47ffaffeede
Reviewed-on: http://review.coreboot.org/8218
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16 20:50:40 +01:00
Kane Chen e381544292 rambi: configure USBPHY_COMPBG by the setting in devicetree.cb
USBPHY_COMPBG needs to be configured by project

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly
CQ-DEPEND=CL:208557

Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208731
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75
Reviewed-on: http://review.coreboot.org/8217
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16 20:50:32 +01:00
Kane Chen 314c4c3ed6 baytrail: use the setting in devicetree.cb to config USBPHY_COMPBG
USBPHY_COMPBG needs to be configured by project

BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
     checked the USBPHY_COMPBG is configured properly

Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208557
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 20a9c0ab7ab180596821751110f0c0a35d3ff3a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795
Reviewed-on: http://review.coreboot.org/8216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-16 20:50:21 +01:00
Furquan Shaikh 7a3c349eb1 rmodule: Fix 64-bit related typecast errors
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I5687c24fcecd26e7656317eb8dde0f1f798e49fc
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209335
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 707cb3e274aa7eabc8e1792fc09d05b4c9e95913)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I2a40acbb14a5ba5c6e4d552b67a331256567d5b4
Reviewed-on: http://review.coreboot.org/8220
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-16 20:50:06 +01:00
Furquan Shaikh 251eef1926 coreboot tpm: Fix printk format specifiers
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I828776724dce287d9a7eb732f2c9ecccf8d68229
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209336
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit b50c9441ddaeabc5aa039f2141853ed7ba7a9d5b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6e81312609448c531345e592ee371ea53dc0916c
Reviewed-on: http://review.coreboot.org/8221
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-01-16 20:49:55 +01:00
Furquan Shaikh c1f5a2e364 fmap: Fix pointer related casts
BUG=None
BRANCH=None
TEST=Compiles

Original-Change-Id: I3a747cb562e7390bb81eca874d6c5aaa54b81e6e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209337
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5d3aef321a9313719308909ec40fdad0ec631a9f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia8edf54f65947be12a7ae69f6825545fb2aed0f1
Reviewed-on: http://review.coreboot.org/8222
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-01-16 20:49:29 +01:00
Edward O'Callaghan 660ec7cfdf drivers/i2c/w83795: Fix tautology from wrong return type
The correct type-signature of 'do_smbus_write_byte' is:

 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)

and so storing the return type in a 'u32' is inappropriate, leading
to a tautological compare of 'ret < 0' and 'err < 0'.

Change-Id: I65486df7156c70af84fa00c336142d9a45998620
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8209
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-15 17:12:13 +01:00
Edward O'Callaghan b0a00c996d mainboard/tyan/s2882/irq_tables.c: Remove dead code under #if 0
Silence unused variable warning.

Change-Id: I2671e0843a60e5bd857b233a45ea68715461f187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8202
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-15 13:13:10 +01:00
Stefan Reinauer 4417deb76f Move container_of() macro to stddef.h
It's not a SPI related macro, hence move it to stddef.h where
other similar macros live.

Change-Id: I1008894af7a272f1bc36d3ae6cee3881132b6ba9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8109
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-14 21:23:29 +01:00
Kyösti Mälkki 41759274fe baytrail broadwell: Use timestamps internal stash
No reason to carry timestamps on CAR stack, as implementation
of timestamps internally stashes on CAR_GLOBAL table and migrates
those to CBMEM.

Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8022
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-14 19:45:36 +01:00
Paul Menzel 5780d6f387 Revert "vboot2: add verstage"
This reverts commit 320647abda, because it
introduced the following regression.

	$ LANG=C make V=1
	Warning: no suitable GCC for arm.
	Warning: no suitable GCC for aarch64.
	Warning: no suitable GCC for riscv.
	/bin/sh: --: invalid option
	Usage: /bin/sh [GNU long option] [option] ...
	/bin/sh [GNU long option] [option] script-file ...
	GNU long options:
	--debug
	--debugger
	--dump-po-strings
	--dump-strings
	--help
	--init-file
	--login
	--noediting
	--noprofile
	--norc
	--posix
	--rcfile
	--restricted
	--verbose
	--version
	Shell options:
	-ilrsD or -c command or -O shopt_option (invocation only)
	-abefhkmnptuvxBCHP or -o option
	make: -print-libgcc-file-name: Command not found

It also introduced trailing whitespace.

Change-Id: I50ec00a38e24c854fa926357cd24f9286bf4f66f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8223
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-14 19:28:19 +01:00
Edward O'Callaghan 3bde659445 vendorcode/amd/agesa: Remove UCODE_VS_FLAG() macro unused variable
Remove useless AGESA microcode macro that leads to unused variable
warnings.

Change-Id: Ia21bfc758f81e349bdd0bfd185df75e8b1898336
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8200
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-01-14 05:58:24 +01:00
Edward O'Callaghan b4d176bb71 northbridge/via/vx800/lpc.c: Remove unused variables
Change-Id: I1f94171173d0b3d672aebeb0dd901dd292028711
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8199
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-14 05:05:39 +01:00
Daisuke Nojiri 320647abda vboot2: add verstage
Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains, compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with verstage_.

TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none

Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>

(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0
Reviewed-on: http://review.coreboot.org/8159
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-13 21:33:57 +01:00
Aaron Durbin b3e0202fd4 cbfs: add cbfs_read()
Allow for reading from cbfs media without having a handle
to a non-CBFS_DEFAULT_MEDIA cbfs_media. In conjunction with
cbfs_locate_file() one can locate and cbfs_read() a file
without bringing the entire file through a potentially
temporary buffer (non-memory-mappable cbfs media platforms).

BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built.

Original-Change-Id: Ib5d965334bce1267650fc23c9e9f496675cf8450
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205991
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 85200f28863e5ea8888322f5787dc6de9a2999f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I25e3221beefd0155305ad63da6be9f47e756f7d0
Reviewed-on: http://review.coreboot.org/8181
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-13 21:30:14 +01:00
Aaron Durbin b312b7f466 cbfs: add cbfs_locate_file()
cbfs_locate_file() can be used to locate the data within the
cbfs file. Based on the offset and length of the file it can
then be read into any address without bringing the contents
into another buffer (platforms without memory-mapped access
to entire contents of cbfs at once).

BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and booted rush into romstage (stage load still works).

Original-Change-Id: I2932f66478c74511ec1c876b09794d9a22a526b3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206000
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 56c958facd379ca0eeebe1b689e3b80d5e692699)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0c4964132af615a069258c0eb37153bd84fbbfae
Reviewed-on: http://review.coreboot.org/8180
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-01-13 21:29:53 +01:00
Martin Roth fa6bd71bdd vendorcode/intel: remove DebugDeadLoop() from fsptypes.h
When included for the CAR transition, this was causing the error:
error: invalid storage class for function 'DebugDeadLoop'

Change-Id: Idf37a8104b4468b40c29c8cbe9a40f7a357a4f17
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8193
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-13 18:19:08 +01:00
Edward O'Callaghan 735e10a0d5 soc/intel/fsp_baytrail/gpio.c: Silence unused variable warning
Put functions in appropriate pre-processor sections to avoid
false-positive 'unused function' compiler warnings.

Change-Id: Ia83d721827ad9924807c0ca5ebd681060af49a82
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8203
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-13 02:52:50 +01:00
Edward O'Callaghan b50921e5bd mainboard/lenovo/x220/gpio.c: Remove unused struct
Change-Id: I25bdee38cedbe38cd447483d3e8b3bdc3f646a62
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8201
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-13 02:51:32 +01:00
Martin Roth 98b698c94f src/device: Doxygen fixes
- Add missing parameters
- add missing @param commands

Change-Id: I029b5dafde94bd250800b06c0e9bd2118f10ef48
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8173
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-12 21:29:38 +01:00
Edward O'Callaghan 97ccefdaf3 southbridge/intel/lynxpoint/me_9.x.c: Avoid unused func warn
Put functions in appropriate pre-processor sections to avoid
false-positive 'unused function' compiler warnings.

Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8157
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-01-12 20:16:53 +01:00
Edward O'Callaghan 8cc5dc1dd2 soc/intel/broadwell/me.c: Prevent unused function warning
Put function under same guard as its call site so that the
compiler does not emit a warn about unused functions upon
a false branch of the guard.

Change-Id: I899d539ec5fbb87e7469415cc8d15837ba8e63f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8156
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-01-12 19:05:46 +01:00
Edward O'Callaghan dd191a2a7d soc/intel/broadwell/spi_loading.c: Remove dead code
I would appear from commit a6354a1 that this is now dead code.

Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-12 18:55:49 +01:00
Edward O'Callaghan 37130ebdab mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO
These boards don't have Super I/O's, rather they use Embedded
Controllers instead. No need to confuse with Super I/O related
stuff showing up in menuconfig.

Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7986
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-01-12 15:50:08 +01:00
Edward O'Callaghan fc13352f2f mainboard/lenovo/x201/romstage.c: Remove unused function
Function was orginally used for reverse engineering.

Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8158
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-11 08:28:31 +01:00
Kyösti Mälkki 78c5d584a0 ACPI: Add acpi_is_wakeup_s3() for romstage
This replaces acpi_is_wakeup_early().

Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8187
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10 13:53:51 +01:00
Kyösti Mälkki 2320cbebc6 AMD binaryPI: Drop ramtop via nvram
If HAVE_ACPI_RESUME gets implemented, EARLY_CBMEM_INIT is
required too.

Change-Id: I8c7932297e0938eff629d1e46081ccf3e7690aea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8185
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10 13:52:31 +01:00
Kyösti Mälkki 7a846e7acc ACPI: Prepare for HAVE_ACPI_RESUME changes
Change-Id: I71d522b135dff8b3c287699cc649caece9e4342c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8186
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10 13:52:10 +01:00
David Hendricks 054c83ac72 Fix mainboard names for daisy and peach_pit
This just fixes name members of mainboard_ops for daisy and
peach_pit, which were never officially supported but used for
development and proof-of-concept.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96
Reviewed-on: http://review.coreboot.org/8184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-10 09:20:34 +01:00
Kyösti Mälkki 2fcf6f1caf haswell: Fix MRC cache to use CBFS
Place the mrc.cache file at top of CBFS. There is no real requirement
for it to have a fixed location though.

Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-10 09:19:40 +01:00
Axel Holewa 1682b8d97a macbook21: Add CST entries
Due to the CST entries the machine uses less power running
GNU/Linux-libre. This can be seen by monitoring CPU temperature
and time left the machine can run on battery. CPU temperature
measurements have been done with lm_sensors, battery querying
with acpi. Tests have been done before applying this patch and
after. In both cases the battery was fully loaded and the machine
powered up on battery, without AC. In both tests the machine was
idleing for more than 1 hour.

Without this patch battery was predicted to last 01:52:30 hours,
CPU temperature first measurement showed 38 degrees. After 15 min
idle, temperature has reached its maximum value in this test of
61 and 62 degrees (Core 0 and 1). Fan speed begins to increase
shortly after 15 min. From its minimal value 1800 rpm it reaches
3100 rpm after 40 min. CPU temperature did not increase any further.
After 60 min idle, the battery was predicted to still last 57 min.

With this patch battery was predicted to last 02:22:40 hours. That
is plus 30 min. CPU temperature begins at 35 degrees. After 15 min
temperature has reached 45 degrees; after 30 min it has reached
the maximal temperature during this test of about 50 degrees.
That is 10 degrees improvement. The fan stayed at minimal speed.
After 60 min idle, the battery was predicted to still last 01:22:48
hours; a 25 minute improvement.

Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13
Signed-off-by: Axel Holewa <mono@posteo.de>
Reviewed-on: http://review.coreboot.org/7923
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-10 08:45:15 +01:00
David Hendricks 560c643e32 Primitive memory test
This adds a generic primitive memory test. We should look into
using tests in src/lib/ramtest.c, but they seem to rely too heavily
on x86 asm and this test has been useful on multiple ARM platforms.

BUG=none
BRANCH=none
TEST=builds and runs on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: Ia0fb4e12bc59bf708be13faf63c346b531eb3aed
Original-Reviewed-on: https://chromium-review.googlesource.com/186309
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e7625c15415eaf6053ce32b67d9d6ab18d776f5f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Conflicts:
	src/lib/Makefile.inc

Change-Id: I34e7aedfd167199fd5db4cd4a766b2b80ddda79b
Reviewed-on: http://review.coreboot.org/8150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09 16:50:55 +01:00
Tom Warren 4a810ba2d6 nyan*: I2C: Fix bus clear BC_TERMINATE naming.
In the original fix for the 'Lost arb' we were seeing on
Nyan* during reboot stress testing, I had the name of
BC_TERMINATE's bit setting wrong. Fix this to use the
IMMEDIATE (1) setting. The setting didn't change, just
the name. According to Julius this is the optimal
setting for bus clear in this instance. Also widened
the SCLK_THRESHOLD mask to 8 bits as per spec.

BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.

Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206409
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff
Reviewed-on: http://review.coreboot.org/8152
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-09 16:50:37 +01:00
Joseph Lo 749559b1fb tegra124: fix and fine tune the warm boot code
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same
as PLLP. But that is incorrect, BootROM had switched it to pllp_out2
with the rate 204MHz. So actually the warm boot procedure was running at
the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz.

And the CPU complex power on sequences were different with what we used
in kernel and Coreboot. Fix up the sequence as below.
* enable CPU clk
* power on CPU complex
* remove I/O clamps
* remove CPU reset

Update the time of the CPU complex power on function for record.
* power_on_partition(PARTID_CRAIL): 528 uSec
* power_on_partition(PARTID_CONC): 0 uSec
* power_on_partition(PARTID_CE0): 4 uSec

Finally, removing the redundant routine of a flow controller event with
(20 | MSEC_EVENT | MODE_STOP).

BUG=chrome-os-partner:29394
BRANCH=none
TEST=manually test LP0 with lid switch quickly and make sure the last
write to restore register successfully

Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205901
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: If21d17dc888b2c289970163e4f695423173ca03d
Reviewed-on: http://review.coreboot.org/8151
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-09 16:50:23 +01:00
Kyösti Mälkki 0b5b541373 AMD binaryPI 00730F01: Switch to per-device ACPI
Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7583
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09 11:02:01 +01:00
Kyösti Mälkki dc357566ea cpu/amd/pi: Use acpi_is_wakeup()
Propagate commit 9107e53 from amd/agesa and fix some
related #includes under cpu/amd/pi.

Change test to return true on S2 wakeup too. In S2 CPU would
have been powered down so MTRR recovery is required.

Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8171
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09 11:01:19 +01:00
Edward O'Callaghan 6d28b91d38 amd/agesa/family12/northbridge.c: Indent (tab) fix
Trivial; Use tab over space for indent.

Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8015
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 10:41:21 +01:00
Jimmy Zhang f4ef77e844 tegra: i2c: re-init i2c controller after reset
This serves as supplemental patch to CL:197732. After clearing bus, we
should also redo controller init (because controller has been reset
before bus clear). On the upper layer, upon receiving error return status,
it should just retry instead of simply call cpu_reset().

BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Built and tested on nyan and nyan_big.

Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202784
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984
Reviewed-on: http://review.coreboot.org/8145
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-09 08:19:36 +01:00
David Hendricks 6a29e6c6b6 elog: Add ELOG_TYPE_BOOT event using fake boot count if necessary
This makes it so that we always log the generic "system boot" event.
If boot count support has not been implemented, fake it.

BUG=chrome-os-partner:28772
BRANCH=nyan
TEST=booted on Big, ran "mosys eventlog list" and saw
"System boot" event logged with boot count == 0

Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204525
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351
Reviewed-on: http://review.coreboot.org/8142
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:46:56 +01:00
Duncan Laurie c25318938f samus: Updates from P2 build
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26

BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards

Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d
Reviewed-on: http://review.coreboot.org/8135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:45:32 +01:00
David Hendricks bb0d5ef97a x86: Initialize drivers in SMM context if needed
This adds a block in the SMI handler to call init functions for
drivers which may be used in SMM. A static variable is used to
ensure the init functions are only called once.

BUG=chrome-os-partner:29580
BRANCH=mccloud
TEST=Built and booted on mccloud, system no longer hangs when
pressing power button at the dev mode screen. Also tested on parrot.

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee
Original-Reviewed-on: https://chromium-review.googlesource.com/204764
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861
Reviewed-on: http://review.coreboot.org/8134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:44:57 +01:00
Duncan Laurie 990a592c1d samus: Enable EC ALS device
Enable the ACPI Device for the EC ALS.

BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw

Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203744
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d
Reviewed-on: http://review.coreboot.org/8133
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:44:27 +01:00
Duncan Laurie 612163ebaa chrome ec: Add ACPI Device for ALS if enabled
The EC can export ALS information if the sensor is attached
to it directly rather than to the host.  This adds a basic
ACPI ALS device and implements the required information.

The kernel does not use the _ALR tuple set but it is required
by the ACPI spec so this just adds the sample two point
response curve defined in ACPI 5.0 section 9.2.5.

The EC does not currently send events for lux value changes so
a polling interval of 1 second is defined.

BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw

Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f
Reviewed-on: http://review.coreboot.org/8132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:43:34 +01:00
Duncan Laurie a416f212dc samus: Updates for P2 board
- RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66
- LTE_POWER_ON connection removed

BUG=chrome-os-partner:29502
BRANCH=None
TEST=none yet, preparing for new board

Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203186
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314
Reviewed-on: http://review.coreboot.org/8131
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:43:21 +01:00
David Hendricks 2445274347 storm: Reserve memory from 0x4000_0000-0x414f_ffff
This marks the bottom chunk of memory, which is used by various IP
blocks, as reserved so that Depthcharge does not attempt to wipe it.

BUG=chrome-os-partner:30067
BRANCH=storm
TEST=Built and booted for storm, depthcharge shows:
Wipe memory regions:
        [0x00000041500000, 0x00000051000000)
        [0x000000510006a0, 0x00000053000000)
        [0x00000054141260, 0x0000007fffd000)

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77
Original-Reviewed-on: https://chromium-review.googlesource.com/206516
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a
Reviewed-on: http://review.coreboot.org/8149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09 06:21:08 +01:00
David Hendricks 0c0767c238 storm: Increase DRAM size to 1024MB
BUG=chrome-os-partner:29871
BRANCH=storm
TEST=builds and boots (sort of)

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I82e1792152d17d689e129c9941e8972221bde366
Original-Reviewed-on: https://chromium-review.googlesource.com/206011
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 8995fde9bdfb8af8fb86525fd67a61614881f78e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ice4a5382903b0ab6e085c39d05c46601373080eb
Reviewed-on: http://review.coreboot.org/8148
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09 06:20:44 +01:00
Vadim Bendebury f6ad8320dd storm: USB fixes for proto0
The actual storm device has a single USB interface, which needs to be
explicitly turned on using GPIO51.

BUG=chrome-os-partner:29871
TEST=verified that depthcharge finds and boots a kernel from USB stick

Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205329
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7
Reviewed-on: http://review.coreboot.org/8147
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-01-09 06:20:10 +01:00
Vadim Bendebury 22fa0e0e0c spi: Add Spansion flash S25FL128P
Storm devices use more recent Spansion flash, add its description to
the table of supported devices.

BUG=chrome-os-partner:29871
TEST=the updated firmware boots all the way to depthcharge

Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205182
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f
Reviewed-on: http://review.coreboot.org/8146
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09 06:19:32 +01:00
Stefan Reinauer d6865222c8 misc: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*.

Back in the day, like more than half a decade ago, we migrated a lot
of boards to printk, but we never cleaned up the existing code to be
consistent. Instead, we worked around the problem with a very messy
console.h (nowadays the mess is hidden in romstage_console.c and
early_print.h)

This patch cleans up the generic code pieces to use printk() on all
non-ROMCC boards.

Our two remaining ROMCC boards are fixed up in this commit:
bifferos/bifferboard and dmp/vortex86ex.

Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8115
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 06:12:22 +01:00
Martin Roth c62ee70b6e src/mainboard: Doxygen fixes
- Remove @param command for #define - this isn't valid.
- Rename duplicate @section names - All of the renamed @sections
have other @section names in the same file.
- Remove blank @brief and @param commands - Doxygen seems to REALLY
dislike this...
- Add a missing @param name.

Change-Id: Iba99ec68b37bbb5c375b7256363d16228031d771
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8175
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 06:05:19 +01:00
Martin Roth 2507820bd9 src/include: Doxygen fixes
- Join doxygen file command with the file description
- Give extended file location so doxygen knows which early_sbmus.h
the file is.  (I don't get this either, but it fixes the warning)

Change-Id: Ia91fb1ac1e9687e1a5a5cb5234696b3c24d4cd24
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8174
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 06:04:55 +01:00
Edward O'Callaghan 08079eca29 mainboard/packardbell/ms2290/romstage.c: Comment unused func
Take unused reverse eng function out of build by wrapping in #if 0.

Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8167
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 05:35:56 +01:00
Edward O'Callaghan 5e06850c0f northbridge/intel/nehalem/raminit.c: Remove redundant function
Remove 'read_mchbar8_bypass()' as 'read_mchbar8()' does the same
thing and 'read_mchbar8_bypass()' is unused.

Change-Id: I0dc2325e6205c38b63e5200c408ece65e4f938dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8166
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 05:35:11 +01:00
Stefan Reinauer 199b581f5c Drop duplicate API from spi_flash.h
This convenience API was never used.

Change-Id: If2a99967e7f8c02e9029f7766aeef1e1a1f3dd16
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8108
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 05:32:36 +01:00
Nicolas Reinecke 9c2aa69725 asrock/e350m1, lenovo/x2x0 Kconfig: fix indentation
Change-Id: Ide09e129fd9400eb20f9b7bb3cd0e5d6d271e372
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 05:30:29 +01:00
Kyösti Mälkki 1d7f5c5c37 macbook21 lenovo/xx: Fix inw() in SMI handlers
Missing base may have enabled SMI for all GPI inputs.

Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8169
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 05:23:57 +01:00
Martin Roth 543888d582 northbridg/via/vx900: Doxygen fixes
- @todo has to be lowercase for doxygen
- Fix some parameters that had changed in the code.
- The @file entries needed to be more specific.

Change-Id: Icdce08735f581609cd25cce41e986c71435368a4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8154
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-08 21:59:42 +01:00
Martin Roth f4cb4128ad northbridge/amd: Doxygen fixes
- Add missing parameter names in several files
- remove parameter types in several files
- remove lines from doxygen documentation.  These should be outside the
doxygen comments.
- Some of the comments shouldn't have been doxygen style.  Turn these
into regular non-doxygen comments.

Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8153
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-08 21:58:45 +01:00
Edward O'Callaghan 9739846469 northbridge/amd/agesa/family1{4,5}: Remove cruft from dimmSpd.c
Remove useless comment pretaining to abusing pragma's for old
GCC/GDB interaction issues.

Change-Id: Ic83a0285ac947a23699a81a82b89de08a47ab052
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8017
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-07 11:31:27 +01:00
Kyösti Mälkki de53bdf569 CBMEM: Rename utility file
This file will have CBMEM init hooks API one day.

Change-Id: I0c31495d4217a5eb235b13e6d8e8c99a87a3b840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-07 06:09:42 +01:00
Stefan Reinauer 069f4766a0 mainboard: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the mainboard code to use printk() on all non-ROMCC
boards.

Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8111
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:16:47 +01:00
Stefan Reinauer 5491ca23fc cpu: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the cpu code to use printk() on all non-ROMCC
boards.

Change-Id: I233c53300f9a74bce4b828fc4074501a77f7b593
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8114
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:16:20 +01:00
Stefan Reinauer 5ab52ddc3d southbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the southbridge code to use printk() on all non-ROMCC
boards.

Change-Id: I312406257e66bbdc3940e206b5256460559a2c98
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8110
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:15:20 +01:00
Stefan Reinauer 65b72ab55d northbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.

Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:15:02 +01:00
Stefan Reinauer d42c9dae85 superio: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the superio code to use printk() on all non-ROMCC
boards.

Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:14:19 +01:00
Stefan Reinauer 0d3cde9062 superio/smsc/lpc47n217: Drop dead code
This code is unused, and the same functionality is in superiotool
already.

Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06 18:24:56 +01:00
Stefan Reinauer d548e5c6d9 broadwell: Use correct include file for console functions
console_tx_byte() is defined in stream.h, not console.h. This will cause
problems later, when untangling more ROMCC and console code. Hence, fix
the issue beforehand.

Change-Id: If4e04bd6c69b630912414676950157d06c364d74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8121
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06 18:23:29 +01:00
Stefan Reinauer 8de452da2e Drop VIA VT8235 southbridge
It's unused.

Change-Id: Iad3e7aa0f777392c9d65b9fcdd3c1666af31723a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7883
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06 18:20:32 +01:00
Kyösti Mälkki 9b29aad526 Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"
This reverts commit 9270553fff.

Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8138
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06 11:19:28 +01:00
Martin Roth 6355cbff51 AMD platforms: fix callout_entry doxygen errors
Somewhere along the line, the sb_cfg parameter name was changed to
config, but this wasn't carried into the documentation or the function
prototypes everywhere.

Change-Id: Iccb0829c2f50370dddb70af915a6759316c4727a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8098
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 06:34:18 +01:00
Martin Roth d30746ab6b AMD Mainboards - rd890_cfg.h: fix Doxygen errors.
Doxygen gives an error when processing #defines inside doxygen comments.
Normal comments are ignored.  The choice for this fix was to make this
a standard comment starting with '/*' instead of '/**', or to make the
comment not a #define.

Change-Id: I97fbbcea6f045d80ec7c0ab5e196d57e5da16d86
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8099
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 06:33:52 +01:00
Martin Roth 5f066b29ce doxygen fixes: change @var to @param var
These files were trying to document the parameters, but didn't have
the syntax quite right.  Change the comments from @varname to
@param varname as required by doxygen.

Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8100
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:33:25 +01:00
Martin Roth d63dbe8ef9 AMD Mainboards - rd890_cfg.c: Fix doxygen warnings
Remove variable types from the param declaration.

Change-Id: Ia6a3d36fcf01d7a52bb1a31cfdb47d88bf612d79
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8097
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 06:33:01 +01:00
Martin Roth 32bc6b6b84 doxygen fixes: fix parameter names to match the functions
The doxygen parameter names in the comments no longer matched the
functions they were attached to.  Doxygen complains about extra
parameter comments and uncommented parameters in the functions.

Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8101
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:32:37 +01:00
Martin Roth 0b2c4ece7d Remove AMD's "Release Content" doxygen from coreboot files
These comments are left over and are not relevent in the coreboot
code, but created a new section titled "Release Content" in the
doxygen documentation produced by the coreboot code.  In an effort
to clean up the output, I'm removing these doxygen comments.

Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8069
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:31:15 +01:00
Martin Roth fc34750c88 drivers/intel/fsp: split the UEFI HOB functions into hob.c
The FSP uses a lot of UEFI HOB (Hand Off Block) functions for reporting
and passing information to coreboot.  These seem to me like they should
be in their own file, so I'm splitting them out of fsp_util.c.  I'll
be adding a couple more functions in the next patch.

These functions should all be compliant to the Hand Off Block spec.

Change-Id: Ie8bbc0a9277b9484f13dd077b3a52e424a8600fe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8065
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:28:50 +01:00
Edward O'Callaghan 9270553fff Re-factor 'to_flash_offset()' into 'spi_flash.h'
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by
Clang complaining that the function 'to_flash_offset' is unused.

Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06 04:56:14 +01:00
Edward O'Callaghan 089a510292 northbridge/intel: Do not define include guard as 1
As `#ifndef` and not `#if` is used in the check for
include guards, setting it to 1 is not needed.

Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8103
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-01-06 04:17:47 +01:00
Edward O'Callaghan ebe3a7aea3 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion
Use 'delay.h' header rather than directly including 'delay.c'
source. N.B. Some amdfam10 and K8 boards are not included in
this changeset since unrelated issues are woven in there.

Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8086
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 01:52:07 +01:00
Edward O'Callaghan 77757c22b9 mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.

Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 01:51:42 +01:00
Edward O'Callaghan d76ac6349d superio/smsc/lpc47n207: Hook into build system
Provide proper Makefile and Kconfig components so
that this superio is built as object code. Select
superio component in mainboard Kconfig's to bring
in the link-time symbols and thereby removing the
need for .c inclusion.

N.B. The LPC47N207 Super I/O does not physically exist
on these boards. The Super I/O is found on external LPC
debug card hardware and so should really be made selectable.
However, this is beyond the scope of this specific fix, that
rids us of .c inclusions in romstage.c

Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8084
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-06 01:23:31 +01:00
Stefan Reinauer 3a6550d989 timestamps: Switch from tsc_t to uint64_t
Cherry-pick from chromium and adjusted for added boards
and changed directory layout for arch/arm.

Timestamp implementation for ARMv7

Abstract the use of rdtsc() and make the timestamps
uint64_t in the generic code.

The ARM implementation uses the monotonic timer.

Original-Signed-off-by: Stefan Reinauer <reinauer@google.com>

BRANCH=none
BUG=chrome-os-partner:18637
TEST=See cbmem print timestamps

Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62
Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793
(cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c)

Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8020
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-05 22:21:49 +01:00
Dave Frodin 83405a1241 hp/abm: Add new mainboard
The hp/abm board is used in network/server applications.

Notes:
- The hp/abm board is headless and therefore does not define
  CONFIG_GFXUMA, and does not require a video bios.
- The micro USB connector on the board edge is connected to COM4
  (i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3.
- If you are using SeaBIOS it would also need to be configured to
  use the UART at I/O=2E8h.
- This board has been tested with headless installed versions of
  Ubuntu 12.10 and Fedora 19.

Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6116
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-01-05 17:02:36 +01:00
Kyösti Mälkki e75deb69cc Copy asrock/ibm-a180 to hp/abm
Change-Id: I8dcb3912976d7381421dc41ee30e7c7652e6c28a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6115
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-01-05 17:00:36 +01:00
Edward O'Callaghan c800199007 northbridge/via/vx800/examples: Remove rotting source
This is just bit-rotting and its likely this will continue to rot
by the time someone notices it exits it will be too late (i.e., today).

Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8087
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-05 16:03:47 +01:00
Martin Roth c3fde7ef36 AMD Mainboards - romstage.c: Fix doxygen errors
- Remove types from the param declarations.
- list needed to be uppercase.

Change-Id: I8b9ed78908e5d3e1d99e7ba2ea9013be109b8e27
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8072
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-04 21:28:57 +01:00
Martin Roth c226bd6228 AMD Mainboards - PlatformGnbPcie.c: Fix Doxygen errors
Remove PeiServices param for OemInitEarly - it doesn't exist in the
function.

Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8073
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-04 20:28:55 +01:00
Martin Roth 15b6325cd4 AMD Mainboards - platform_cfg.h: Fixes for doxygen
- Move @def BIOS_SIZE description to the next line
- SB_GEN2 changed to SB_GPP_GEN2
- Move the SIO_HWM_BASE_ADDRESS description to the next line

Change-Id: Ia3496b0108484f557627304553461932a100dfa5
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8071
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-04 20:17:48 +01:00
Martin Roth 182e551f2d smihandler.c: Fix doxygen errors in southbridge_smi_handler
Correct the param to match the functions.

Change-Id: Id002c549a6ba6a7be4fa5eee396769eaa2510698
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8074
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-04 20:06:57 +01:00
Martin Roth 24e2e951b9 atomic.h: Fix doxygen errors
- @v & @i need to be @param v & @param i
- add the @file command

Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8075
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-04 20:03:28 +01:00
Martin Roth 6e22225d60 remove vx900_int16 doxygen module/group
This doxygen directive was creating a top level modules section, which
had the vx900_int15 code as its only member.  I do think that breaking
the code into documented sections is a good plan, but in an effort to
clean up the output, I'm removing this for now.

Change-Id: I3f7e2f704136ebbd1961c5946bac4c2edbd6a371
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8070
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-04 20:03:04 +01:00
Edward O'Callaghan 9e687a62b1 superio/smsc/lpc47b272/superio.c: Remove dead code
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.

Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8083
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-04 13:49:01 +01:00
Edward O'Callaghan 520a328e5a src/superio/smsc/lpc47m10x/superio.c: Remove dead code
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.

Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8082
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:48:47 +01:00
Edward O'Callaghan 117849ef4d superio/smsc/lpc47b272: Use link-time symbols over .c inclusion
Change-Id: Id3d5f2a120c0a933c031102f206829305da20f0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8081
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:48:38 +01:00
Edward O'Callaghan c3e77fc953 superio/smsc/lpc47m10x: Use link-time symbols over .c inclusion
Change-Id: I4a3639c05231eacd016ec3873330f9844befd448
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8080
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:48:23 +01:00
Edward O'Callaghan 536a44390d superio/smsc/lpc47b397: Use link-time symbols over .c inclusion
Change-Id: I344f2a8d2ae5f6f3fa04d79773ee1c59de69e425
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8079
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-04 13:48:13 +01:00
Edward O'Callaghan b8f05d4faa superio/nsc/pc87417: Use link-time symbols over .c inclusion
Change-Id: I2efb7ab4b69bcd127b2faf54277dc229c9dcf3ea
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8078
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-04 13:48:03 +01:00
Edward O'Callaghan db1a2fb3df superio/nsc/pc87366: Use link-time symbols over .c inclusion
Change-Id: Id156ca3c9a14c5bcc4d6cdb8434ca8efdac3139a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8077
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:47:53 +01:00
Edward O'Callaghan fc4e8550af superio/nsc/pc97317: Use link-time symbols over .c inclusion
Change-Id: Ia45bc7a880d0dab57c56a0452858cd26626f09df
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8076
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:47:45 +01:00
Edward O'Callaghan e64f5b1bcd superio/intel/i3100: Use link-time symbol over .c includes
Change-Id: I83db9b189e672b0e1f25bc42b73639c375bea3e5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8054
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:47:35 +01:00
Edward O'Callaghan 24fb03e767 superio/nsc/pc87360: Use link-time symbol over .c includes
Change-Id: Id6d9efc93fdaff63dcaab50712ac9be35ccb42a7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8053
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:47:26 +01:00
Edward O'Callaghan 74834e0758 mainboard: Sanitize some superio include paths to be non-local
This brings mainboard up to being consistent tree-wide now for
all superio header path inclusions.

Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8052
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-04 13:47:16 +01:00
David Hendricks cab19911ff ipq806x: Fix casting in cbmem_top() so >=2GB can be used
This explicitly casts CONFIG_SYS_SDRAM_BASE to an unsigned type so
we don't get compilation errors when increasing CONFIG_DRAM_SIZE_MB.

BUG=chrome-os-partner:29871
BRANCH=storm
TEST=compilation no longer fails with DRAM_SIZE set to 1024

Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9717c39d87682d43ec4e7a4042d9b559a1d7eedb
Original-Reviewed-on: https://chromium-review.googlesource.com/206010
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 178db896346ae8cbc5ddec5373a83688f32c62ba)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I68c11d398820684ad928bdfdd74f7a6885247333
Reviewed-on: http://review.coreboot.org/8059
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-04 00:45:22 +01:00
Vadim Bendebury 0b70bd1336 ipq806x: move GPIO definitions to the proper include file
When the IPQ SPI driver was ported to coreboot, a few GPIO related
definitions ended up in a wrong include file. Move them to the proper
place and get rid of duplicated definition of GPIO_OUT.

BUG=chrome-os-partner:27784, chrome-os-partner:29871
TEST=proto0 still boots with the new firmware

Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205328
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4
Reviewed-on: http://review.coreboot.org/8058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-04 00:15:50 +01:00
Vadim Bendebury 6b33286e95 ipq806x: move translation table out of the way
Depthcharge clears up all unused DRAM before starting Linux, and does
not know the translation table location. Instead of adding an
exclusion term to the memory wipe descriptor let's move the table to
the top of IMEM, it is also likely to be a good location in the
future, when EFS is introduced.

BUG=chrome-os-partner:27782
TEST=manual
   . built and ran firmware on ap148

Original-Change-Id: I76546438d243076dda4d0eb3f784e0b5a8a1fa22
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203624
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 4250f8574d6cc0bbec5ba0411f22d801f034afb8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I12cd74e3d318b878e7703414a7ddaaed0812cb7a
Reviewed-on: http://review.coreboot.org/8057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-04 00:15:34 +01:00
Julius Werner 028cba9266 ipq806x: Add USB support
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.

BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).

Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202157
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af
Reviewed-on: http://review.coreboot.org/8056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:15:17 +01:00
Tom Warren 96ef1883a7 nyan_big: Update Hynix BCTs and add Kingston 2GB BCT.
Hynix 2GB/4GB configs have been fine-tuned.
Kingston 2GB config is new, uses RAMCODE 0x6.

BUG=none
TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my
Big 2GB system (PVT1/SKU1) and it booted OK.
BRANCH=nyan_big

Original-Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203305
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit e47d18d8cff50f46d0a14715b6750f7aa6d0da82)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I363db37d6a63d9f5c578e68a0149259657e1ebfd
Reviewed-on: http://review.coreboot.org/8045
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:14:15 +01:00
Vince Hsu 1e3679ddd0 tegra124: configure DP with correct pixel clock
For some panels, the plld can't provide the pixel clock that
the panels wants, so we give it a good enough one. And we
should calculate the dp/dc settings by the real pixel clock.

BRANCH=nyan
BUG=chrome-os-partner:29489
TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big).
No screen flicker is observed. No sor dp fifo underflow found.

Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203358
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac
Reviewed-on: http://review.coreboot.org/8044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:14:03 +01:00
Jimmy Zhang c1f7cbe49f arm: lpae: Set XN and PXN bits for noncacheable regions
Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.

BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>

Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Original-Reviewed-on: https://chromium-review.googlesource.com/203447
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe
Reviewed-on: http://review.coreboot.org/8043
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:13:28 +01:00
Todd Broch cb2351ea1f nyan: Ignore the recovery GPIO.
CrOS devices with Chromeos EC need only use hostevent to communicate
recovery assertion to the BIOS.  This CL removes wired GPIO from
determining recovery as it appears under certain conditions (cold
reset) the internal PU on the AP isn't strong enough and therefore the
value is sometimes seen as asserted.

BRANCH=none
BUG=chrome-os-partner:29333
TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot.

Original-Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2
Original-Signed-off-by: Todd Broch <tbroch@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202996
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit d9927bcd67b0fb069fde231314e654d727092282)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6e086cbabc884f18deb2791a0f897e332b31032f
Reviewed-on: http://review.coreboot.org/8042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:12:55 +01:00
Duncan Laurie 5106b9dbb7 samus: Minor fixes for P1.9 boards
- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix

BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus

Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203185
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
Reviewed-on: http://review.coreboot.org/8048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:05:44 +01:00
Duncan Laurie ef57a22163 wtm2: Fix issues with USB in firmware
XHCI driver was not enabled in libpayload and some ports were
disabled that should be enabled.

The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to
properly indicate unused so crossystem does not attempt to
export GPIO number 255 in the kernel and trigger a warning.

BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2

Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/203184
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 328362469b00c9467908a7d18a031fee73753def)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434
Reviewed-on: http://review.coreboot.org/8047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-04 00:05:23 +01:00
Duncan Laurie 502c38f9df samus: Enable DDI2 hotplug
Both DDI ports may be used on this board so it needs to be
able to detect a device on either port.

BUG=chrome-os-partner:28234
TEST=None (needs hardware)

Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099
Reviewed-on: http://review.coreboot.org/8046
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-04 00:04:15 +01:00
Duncan Laurie 25c6f75bb2 samus: Update for board revision 1.9
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU

BUG=chrome-os-partner:28234
TEST=Boot on P1.9

Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:03:54 +01:00
Duncan Laurie fe8b788a12 samus: Move SPD related information to spd directory
Put all the SPD related information in one place including
the onboard SPD sources and the board specific parsing.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus

Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201082
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123
Reviewed-on: http://review.coreboot.org/8006
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:03:40 +01:00
Duncan Laurie 0aa06cbf18 wtm2: Convert to use soc/intel/broadwell
Convert wtm2 board to use the broadwell soc chipset.

BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226

Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201070
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda
Reviewed-on: http://review.coreboot.org/8001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-04 00:03:17 +01:00
Nicolas Reinecke dafa12adfc intel/model_206ax: update microcode
tested on ivy and sandy (t520/t420s & t530)

Change-Id: Ie527e8c4804821764ecc42f7495573eff67828f7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7976
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-03 20:11:32 +01:00
Vadim Bendebury 24a53dddb9 ipq806x: clean up UART driver tx_byte function
The driver as it was copied from u-boot provided a function to
transmit multiple characters in one invocation. This feature was not
ported to coreboot, there is no need to maintain the complexity when
only one character at a time is transmitted. It is also very desirable
to get rid of a 1024 byte array allocated on the stack.

The array was necessary to allow to convert multiple newline
characters in the transmit data flow into two character sequences
CRLF. Now just a single word is enough to keep one or two characters
to transmit.

[EDIT km: newline translation is now part of printk]

BUG=chrome-os-partner:27784
TEST=verified that coreboot with the new code prints generates console
     output.

Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201782
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8011
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-03 20:02:37 +01:00
Kyösti Mälkki 3ae558f5a1 ARM64: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: Ibe4e172bb654f6414949bd11787c9407d091a858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8028
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-03 06:25:52 +01:00
Kyösti Mälkki a38d1b2795 ARMv7: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:07:22 +01:00
Vadim Bendebury 96c9686407 storm: Put the page table at a correct address
The recently introduced page table location value is wrong, it
overlaps with other areas of the code. This patch fixes the location,
a more robust scheme is needed for memory layout management.

BUG=none
TEST=manual
  . occasional random failures disappear after this patch is applied

Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202641
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7afcab42db259e53541fb991b36d680fc2186304
Reviewed-on: http://review.coreboot.org/8019
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-03 05:02:36 +01:00
Vadim Bendebury 1485c3040b storm: modify memory layout
This is an interim change (before EFS is enabled), align ROM and RAM
stages so that they have enough room and do not step over each other.

BUG=chrome-os-partner:27784
TEST=manual
   . booted coreboot successfully on ap148

Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202046
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481
Reviewed-on: http://review.coreboot.org/8012
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-03 05:02:07 +01:00
Deepa Dinamani 2c04117eac mainboard/storm: setup mmu in storm mainboard_init
enable protection of zero page access, provide for uncached device memory range,
and protect against access outside of DRAM except to device registers.

BUG=chrome-os-partner:28467
TEST=verified mmu.pagetable.list output:

_______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________|
     C:00000000--000FFFFF| | | | | | | | |
     C:00100000--3FFFFFFF| A:00:00100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered |
     C:40000000--428FFFFF| A:00:40000000--428FFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc |
     C:42900000--43CFFFFF| A:00:42900000--43CFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered |
     C:43D00000--5FFFFFFF| A:00:43D00000--5FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc |

Original-Change-Id: If9beb10938841aead5105d662f0aef741995d708
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200341
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 09dd137453d8c6f1b60692b01226498e22f34fb2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Conflicts:
	src/mainboard/google/storm/mainboard.c

Change-Id: Idff7e3f0bc5903933e9f1b980f595666380696d1
Reviewed-on: http://review.coreboot.org/8010
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:01:08 +01:00
Deepa Dinamani 4d2d6ca79a soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
Define a base address for page table entries. Place it 64KB below the
bootblock loading address.

BUG=chrome-os-partner:28467
TEST=verified that the page tables are being populated at this
     address. Also observed that the SPI driver takes 900 ns to
     process a byte as opposed to 1.5 us in case caching is not
     enabled.

Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200332
(cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068
Reviewed-on: http://review.coreboot.org/8009
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03 05:00:08 +01:00
Vadim Bendebury 41a5d0df58 ipq8064: add SOC initialization skeleton
The main benefit of adding this skeleton is the addition of the
correct memory map to CBMEM. Attempts to load depthcharge do not fail
because of unavailability of the bounce buffer.

BUG=chrome-os-partner:27784
TEST=boot updated firmware on AP148, observe

   CPU: Qualcomm 8064

  in the ramstage console output as well as not failing to load
  depthcharge any more.

Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199675
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013
Reviewed-on: http://review.coreboot.org/8000
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-03 04:59:50 +01:00
Vadim Bendebury 1ea5685862 storm: enable early console
Include the required modules in romstage and enable early console.

BUG=chrome-os-partner:27784
TEST=observe the romstage prompt in the console output:
   coreboot-4.0 romstage Tue May 13 17:08:58 PDT 2014 starting...

Original-Change-Id: Ie3853b9afc53246e6eb997f279ccd4dbb08f748b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199673
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 6e643d3425ee226b3ebfbf329b35e7017f83d0c3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibdc695da634356988b3e551b0a9e4be2e129ccb4
Reviewed-on: http://review.coreboot.org/7997
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 04:59:39 +01:00
Vadim Bendebury 15c98b0217 storm/ipq8064: add dynamic CBMEM support
Squashed the correction patch with the original to avoid confusion in
coreboot.org review.

All what's needed apart from configuring the feature is to provide a
function which would report the top of DRAM address.

BUG=chrome-os-partner:27784
TEST=manual
  . with all other patches applied, the image proceeds all the way to
    trying to download 'fallback/payload'.

Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3
Original-Reviewed-on: https://chromium-review.googlesource.com/197897
(cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

storm: initialize dynamic cbmem properly

Dynamic cbmem support has been enabled on storm, but the proper
initialization at romstage is missing.

Proper DRAM base address definition is also necessary so that CBMEM is
placed in the correct address range (presently at the top of DRAM).

BUG=chrome-os-partner:27784

TEST=build boot coreboot on ap148, observe the following in the
     console output:

  Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
  coreboot table: 256 bytes.
  CBMEM ROOT  0. 5ffff000 00001000
  COREBOOT    1. 5fffd000 00002000

Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74
Reviewed-on: http://review.coreboot.org/7996
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 04:59:27 +01:00
Vadim Bendebury f3254348a1 ipq8064: Configure storm bootblock to run
This adds necessary configuration options to enable bootblock on Storm
to read the rombase image from the SPI flash.

BUG=chrome-os-partner:27784
TEST=manual
   . after this change is applied, the AP148 boots coreboot from the
     Spansion SPI flash device:

   coreboot-4.0 Thu May  1 14:25:34 PDT 2014 starting...
   Exception handlers installed.
   SF: Detected S25FL128S_256K with page size 10000, total 2000000
   CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001
   coreboot-4.0 Thu May  1 14:25:34 PDT 2014 booting...
   Exception handlers installed.
...

Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197801
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 73d72df228e3c6154d8836b0af6d94df91c88bf4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67
Reviewed-on: http://review.coreboot.org/7995
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 04:59:10 +01:00
Nicolas Reinecke 572795bf08 lenovo/t420s: Add new port.
This is based on x220 and t520. Tested on i7 model with usb3.
There is no support for nvidia gpu and optimus.

Change-Id: I6ca9436ccec3024095d02078e5e450147841e463
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-01-03 04:14:28 +01:00
Neil Chen c619c41890 blaze: change ramcode 1000/1001/1010 to use 792MHz bct
This change updates the cfg file for Hynix/Micron/Samsung 4GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.

BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.

Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202059
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c
Reviewed-on: http://review.coreboot.org/8008
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2015-01-03 00:56:17 +01:00
Vadim Bendebury 0e2d9b63d7 storm: ipq8064: enable CBFS SPI wrapper
This change forces storm platform to use the common CBFS SPI wrapper,
which makes the SOC specific CBFS code unnecessary and requires
including SPI controller support in all coreboot stages.

BUG=chrome-os-partner:27784
TEST=manual
  . with this change and the rest of the patches coreboot on AP148
    comes up all the way to attempting to boot the payload (reading
    earlier stages from the SPI flash along the way).

Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197932
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2
Reviewed-on: http://review.coreboot.org/7994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 00:27:37 +01:00
Vadim Bendebury 20d3d53433 ipq8084: provide monotonic us timer
This service is required by various coreboot code modules. It looks
like the 8064 SOC does not provide anything better than a 32 KHz free
running counter (it is used in u-boot for us timer as well). Let's use
this for now.

BUG=chrome-os-partner:27784
TEST=manual
   . with the rest of the patches applied AP148 boots all the way to
     trying to start the payload.

Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197896
(cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id37ed21193db67ceee11a795713c34ef26383380
Reviewed-on: http://review.coreboot.org/7993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03 00:27:09 +01:00
Julius Werner 989e12bb63 arm: Fix stored PC value when handling exceptions
ARM processors save the PC value in the Link Register when they handle
and exception, but they store it with an added offset (depending on the
exception type). In order to make crashes easier to read and correctly
support more complicated handlers in libpayload, this patch adjusts the
saved PC value on exception entry to correct for that offset.

(Note: The value that we now store is what ARM calls the "preferred
return address". For most exceptions this is the faulting instruction,
but for software interrupts (SWI) it is the instruction after that. This
is the way most programs like GDB expect the stored PC address to work,
so let's leave it at that.)

Numbers taken from the Architecture Reference Manual at the end of
section B1.8.3.

BRANCH=none
BUG=chrome-os-partner:18390
TEST=Provoked a data abort and an undefined instruction in both coreboot
and depthcharge, confirmed that the PC address was spot on.

Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199844
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6
Reviewed-on: http://review.coreboot.org/7992
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-03 00:26:18 +01:00
David Hendricks 739e6a84aa elog: Add function to log boot reason in ChromeOS case
This adds a generic helper function for adding boot reason in the
ChromeOS case. If vboot is enabled, it will use information passed
in via the vboot handoff table in cbmem to determine mode and
reason in the case of recovery.

BUG=chromium:373467
BRANCH=nyan
TEST=built along with follow-up CL and booted on Big under various
modes, verified entry was added to eventlog with "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b
Original-Reviewed-on: https://chromium-review.googlesource.com/199690
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75
Reviewed-on: http://review.coreboot.org/7991
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-03 00:25:27 +01:00
Kyösti Mälkki 22261c387e allwinner/a10: Always has DYNAMIC_CBMEM
The static allocator only worked for x86 anyway.

Change-Id: Iadaab225fea04b455c559c25b918a2a842b9faca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8029
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-02 21:52:15 +01:00
Ronald G. Minnich 6d8228599b Allow RISCV to be compiled with ANY_TOOLCHAIN
Change-Id: I9210241c902ad8a88980a7c9cdb0d52c460b2541
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8025
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-01-02 18:44:57 +01:00
Ronald G. Minnich e8897c45a8 soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.
riscv builds again.

Change-Id: I4caaee49c3eaa948540a916f684dd4e1ed9c9011
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8026
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-01 18:07:14 +01:00
Ronald G. Minnich 922b3ca8e5 ARM: Fix ARM_LPAE to not be selectable as a menu item.
It was showing up as a menu item and it should not.

Change-Id: I448f683fbf4187b11821381332f971b1daea29f8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-01 17:40:57 +01:00
Edward O'Callaghan 149ea15f7e mainboard/lenovo/t530/Kconfig: Enable VMX by default
Fix a trivial tab/space indent inconsistency while here.

Change-Id: I819d85293e1a070817cd13349a220ba85ba89951
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7984
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-01 05:35:19 +01:00
Duncan Laurie 2663a55caf samus: Combine mainboard patches to build soc/intel/broadwell
Combine four patches dependencies. These will not build
individually, so combine them for coreboot.org upstream.

samus: Move SPD handling to separate file

The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.

It relies on the updated pei_data structure from broadwell instead
of the haswell interface.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Move PEI data structure init to separate file

This needs to be executed in both romstage and ramstage
for the different PEI binary stages.

It uses the broadwell interface now instead of haswell.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199921
(cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Convert mainboard to use soc/intel/broadwell

Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.

- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook

BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199922

(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

samus: Add some code to print basic info from SPD

The handling of LPDDR is a bit messy in Intel platforms.  There
is no traditional SPD so instead one is created by hand from the
provided datasheets.

These have varying (and sometimes unexpected) geometry and it can
be important during bringup to know what configuration is being
passed to the memory training code.

This could in theory be put in a more generic location, but for now
this is the only board with LPDDR3 where I have found it valuable.

BUG=chrome-os-partner:28234
TEST=Build and boot on samus, look for SPD details on the console.
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751

Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199923
(cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
Reviewed-on: http://review.coreboot.org/7943
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 21:24:48 +01:00
Duncan Laurie 229958e0b9 broadwell: Hook into the build system
Hook the soc/intel/broadwell directory into the configuration
and build system so it can be used by mainboards.

BUG=chrome-os-partner:28234
TEST=build and boot on wtm2

Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b
Reviewed-on: http://review.coreboot.org/7940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 21:23:09 +01:00
Marc Jones a6354a1aca broadwell: Preparations for building
Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.

- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic

Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-12-31 21:22:24 +01:00
Vadim Bendebury dffd892e47 ipq8064: modify SPI controller driver to work in coreboot
A typical SPI operation consists of two phases - command and data
transfers. Command transfer is always from the host to the chip (i.e.
is going in the 'write' direction), data transfer could be either read
or write.

We don't want the receive FIFO to be operating while the command phase
is in progress. A simple way to keep the receive FIFO shut down is to
not to enable it until the command phase is completed.

Selective control of the receive FIFO allows to consolidate the
receive and transmit functions in a single spi_xfer() function, as it
happens in other SPI controller drivers.

The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the
next byte can be written or received, respectively. While data is
being received the 0xFF bytes are transmitted per each received byte,
to keep the SPI bus clocking.

The data structure describing the three GSBI ports is moved from the
.h file into .c file. A version of the clrsetbits macro is added to
work with integer addresses instead of pointers.

BUG=chrome-os-partner:27784
TEST=not yet, but with the res of the changes the bootblock loads and
     starts the rombase section successfully.

Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197779
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f
Reviewed-on: http://review.coreboot.org/7983
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2014-12-31 21:05:50 +01:00
Vadim Bendebury 11c4c92d91 ipq8064/storm: UART enable and various fixes
The original patch from chromium was  a bit of a mishmash.
Between that, rebasing and using the coreboot.org UART infrastructure,
the patch has changed a bit from the original. It seems reasonable to
keep these changes together.
- build in the ipq UART and turn on bootblock console
- sets LPAE and ROM header address
- adds cpd.c to storm

The original commit:
ipq8064: make UART driver work in bootblock

This patch it the last one in the chain adapting the ipq9064 UART
driver for use in coreboot. A new config option
(CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of
the driver.

The previously introduced uart_wrapper.c is now included in the build
to provide the console driver structure used by ramstage.

Necessary configuration options are added to allow use of UART in the
bootblock.

BUG=chrome-os-partner:27784

TEST=with this change the coreboot image on AP148 prints a banner on
   start up:

coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting...

Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196663
(cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91
Reviewed-on: http://review.coreboot.org/7875
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-31 21:04:54 +01:00
Edward O'Callaghan a40901bf01 vendorcode/amd/cimx/sbX00: Make SBPort.c filename consistent
Change-Id: I41ba4cffa545a31c1e0845ec44c8a433bda9f99d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7886
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31 09:52:55 +01:00
Kyösti Mälkki bae775a4f4 arch/x86: Declare GDT symbols and move_gdt()
We relocate GDT to CBMEM, this can be done late in ramstage.
Note: We currently do this for BSP CPU only.

Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-31 09:51:50 +01:00
Kyösti Mälkki a91e1e6cc1 Fix Kconfig whitespace
Change-Id: Iad64d018edda3064a77bfbcd41cfea5275a2e737
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8013
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31 09:46:00 +01:00
Kane Chen d816a0251e baytrail: add more gpio init macros
GPIO init marcos are not enough to initialize different gpio attributes

BUG=none
TEST=emerge-rambi coreboot works well

Original-Change-Id: I193fa7b3e22632cacb555e726e3dd3991f4f4faa
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200531
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5e0fcbcd7cefcfccb5b565003336d197bb29e4cc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6bf4db9397733a003dfdedc6eb63b82127917851
Reviewed-on: http://review.coreboot.org/7953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31 05:28:45 +01:00
Ken Chang a859aa3df5 nyan*: Set GEN2 I2C pads to open-drain mode
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external
pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus
the pinmux E_OD bit of these two pins needs to be set to
ensure GEN2 I2C pads work fine on 3.3V.

BRANCH=nyan
BUG=none
TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c
on blaze w/o this change. the waveform looks good on both
scl/sda pins w/ this change.

Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200996
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea
Reviewed-on: http://review.coreboot.org/7952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31 05:26:51 +01:00
Vadim Bendebury 9e208bc357 Print segment clean up information only when required.
Eliminate duplicated printout and if needed, print only changed
information.

BUG=none
TEST=verified that the 'New segment dstaddr...' message is not
     duplicated anymore

Original-Change-Id: Ia13593394fccbb225f2bd9ab2b9228bac29d50fb
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199672
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit aadf018821ebfa63d6ac9d2429ae1fb483dd6cb3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7544bddc4026191395cfe3b8ac66256ec223391e
Reviewed-on: http://review.coreboot.org/7937
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-31 05:26:27 +01:00
Shawn Nematbakhsh 0dadb767a0 rambi: Add _PRW for LID0 ACPI Device
The kernel will not track wakeup events for devices unless they have
a defined _PRW.  There is no EC output of the lid signal coming to
a GPIO and instead it pulses PCH_WAKE#.

BUG=chrome-os-partner:27631
TEST=Manual on Rambi.
- Run lidclose + lidopen on EC console, verify that wakeup_count
  increments.
- Run lidclose + lidopen in rapid succession, verify that suspend
  request is aborted.
BRANCH=Rambi.

Original-Change-Id: I8d4c58a7bb37d7e474ec094fe96e46e1bfd980de
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200289
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 08c6b42f1ed1af7fff6217e6b71469edd7ff4b2e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Iee813ed6f39cd3d5e0a2bdd395c740f82a1cf01a
Reviewed-on: http://review.coreboot.org/7945
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31 05:26:01 +01:00
Sheng-Liang Song 8c7e62202d rambi: Unconditionally clear the EC recovery request
Implement Rambi clear_recovery_mode_switch()

BUG=chromium:279607
BRANCH=TOT
TEST=Verified recovery sequences on Rambi.

Original-Change-Id: I481329d0f49584ad0314bd982b80bbc86112c2c0
Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Sheng-liang Song <ssl@google.com>
Original-Tested-by: Sheng-liang Song <ssl@google.com>
(cherry picked from commit 77e60a039f3d8328694a743e7cd15cce71b02f5d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I837151551b8aa68cf86b6fa1dd39b7b673d6a4d9
Reviewed-on: http://review.coreboot.org/7896
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2014-12-31 05:25:44 +01:00
Sheng-Liang Song 1d6560fc60 chromeos: Unconditionally clear the EC recovery request
Add the empty weak function clear_recovery_mode_switch().

Problem:
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set,
the following will happen:

1. Boot device in recovery mode with Esc + F3 + Pwr.
2. Turn device off with Pwr button.
3. Turn device on with Pwr button.

Device still boots to recovery screen with
recovery_reason:0x02 recovery button pressed.

If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the
device off and on again  with the Pwr button does a normal boot.

Solution:
Unconditionally clear the recovery flag.

BUG=chromium:279607
BRANCH=TOT
TEST=Compile OK.

Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf
Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197780
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Sheng-liang Song <ssl@google.com>
Original-Tested-by: Sheng-liang Song <ssl@google.com>
(cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae
Reviewed-on: http://review.coreboot.org/7895
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-30 23:30:52 +01:00
Daisuke Nojiri afde961adf vboot: Convert response_length from uint32_t to size_t in VbExTpmSendReceive
Length arguments for VbExTpmSendReceive have type uint32_t but it calls function
which expects size_t. This change converts uint32_t to size_t on call and
size_t to uint32_t on return.

BUG=None
BRANCH=None
TEST=Booted Nyan Big to Linux

Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I1971488baae2d060c0cddec7749461c91602a4f9
Original-Reviewed-on: https://chromium-review.googlesource.com/198016
(cherry picked from commit 6830747eb47568f2a2b494624522d37d8945c030)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I20741759e7bbd60dd7044c532287d6b55047e19a
Reviewed-on: http://review.coreboot.org/7894
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:44:24 +01:00
Kein Yuan 704c006479 Rambi: Set SOC_DISP_ON as GPIO to avoid LCD_VCC glitch
To avoid LCD_VCC glitch on cold reset, set SOC_DISP_ON as GPIO output high.
After gfx initialize is done, set it to native function 2.

BUG=chrome-os-partner:25159
BRANCH=firmware-rambi-5216.B
TEST=Tested on Rambi and squawks, no LCD_VCC glitch anymore.

Original-Change-Id: If16af498e910a8da1d77a9a66456eb767286a61a
Original-Change-Id: Icf62588fa0338f89fafb3fe9246c26f16bcdaa60
Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197985
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 6f7d621678f22133c9825565fedc77d19198b08c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibaf547b8d1c27811a1bec9fa3254d559c505a361
Reviewed-on: http://review.coreboot.org/7893
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-30 22:44:09 +01:00
Duncan Laurie 4397aa1347 vboot: Add a new post code for TPM failure
If the kernel does not properly handle the TPM and send it a
TPM_SaveState command before suspend then it will not be in
the correct state on resume.  In order to easily detect this
case add a new post code for TPM failure and use it in the
vboot resume path.

BUG=chromium:371105
TEST=Build and boot on wtm2.

Original-Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199371
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ff2f0dc56c1a783295710f81567af02729fe1da2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I5baf894fd72922acd79d191e5485ae8ef7e0d559
Reviewed-on: http://review.coreboot.org/7936
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:13:30 +01:00
Gabe Black a4c4b1c69c elog: Use the RTC driver interface instead of reading CMOS directly.
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.

BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan

Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197798
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4fad296ecfeff8987e4a18054661190239245f32
Reviewed-on: http://review.coreboot.org/7891
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:11:54 +01:00
Gabe Black abb001a2fe rtc: Add an RTC driver for the AS3722 PMIC.
The AS3722 PMIC, like many PMICs, has an RTC built into it. This change adds a
driver for it which implements the new RTC API.

BUG=None
TEST=Built and booted with the event log code modified to use this interface.
Verified that events had accurate timestamps.
BRANCH=nyan

Original-Change-Id: I400adccbf84221dcba8d520276bb91b389f72268
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197796
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 011e49beba3a99abbd122866891e3c20bf1188d2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibc1d342062c7853a30d195496c077e37a02b35b0
Reviewed-on: http://review.coreboot.org/7890
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:11:18 +01:00