Commit Graph

573 Commits

Author SHA1 Message Date
Martin Roth 9cd155334b FSP platforms: Clear area in CAR for cbmem
This patch clears the CAR area. The FSP loads the entire CAR area with a
pattern instead of clearing it.  At least the cbmem area needs to be
cleared or cbmem will not use it.

Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8195
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 22:30:03 +01:00
Martin Roth 5fc32bf5e6 drivers/intel/fsp: Add find_saved_temp_mem()
Add a function to retrieve the location of the CAR temporary memory
that was saved by the FSP into the HOB structure.

Change-Id: I2635de5207cd699740721d333a7706425b837651
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8194
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-29 04:33:53 +01:00
Martin Roth 7b132deb80 drivers/intel/fsp: Add HOB tools to work with GUIDs
Add new functions to:
- Compare two GUIDs
- Find a hob based on its GUID
- Print information about GUID_EXTENSION type HOBs
- Print a GUID's address and value

Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-27 19:40:24 +01:00
Furquan Shaikh 251eef1926 coreboot tpm: Fix printk format specifiers
BUG=None
BRANCH=None
TEST=Compiles successfully

Original-Change-Id: I828776724dce287d9a7eb732f2c9ecccf8d68229
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209336
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit b50c9441ddaeabc5aa039f2141853ed7ba7a9d5b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I6e81312609448c531345e592ee371ea53dc0916c
Reviewed-on: http://review.coreboot.org/8221
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-01-16 20:49:55 +01:00
Edward O'Callaghan 660ec7cfdf drivers/i2c/w83795: Fix tautology from wrong return type
The correct type-signature of 'do_smbus_write_byte' is:

 int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)

and so storing the return type in a 'u32' is inappropriate, leading
to a tautological compare of 'ret < 0' and 'err < 0'.

Change-Id: I65486df7156c70af84fa00c336142d9a45998620
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8209
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-15 17:12:13 +01:00
David Hendricks 6a29e6c6b6 elog: Add ELOG_TYPE_BOOT event using fake boot count if necessary
This makes it so that we always log the generic "system boot" event.
If boot count support has not been implemented, fake it.

BUG=chrome-os-partner:28772
BRANCH=nyan
TEST=booted on Big, ran "mosys eventlog list" and saw
"System boot" event logged with boot count == 0

Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204525
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351
Reviewed-on: http://review.coreboot.org/8142
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-09 07:46:56 +01:00
Vadim Bendebury 22fa0e0e0c spi: Add Spansion flash S25FL128P
Storm devices use more recent Spansion flash, add its description to
the table of supported devices.

BUG=chrome-os-partner:29871
TEST=the updated firmware boots all the way to depthcharge

Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205182
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f
Reviewed-on: http://review.coreboot.org/8146
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09 06:19:32 +01:00
Kyösti Mälkki 9b29aad526 Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"
This reverts commit 9270553fff.

Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8138
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06 11:19:28 +01:00
Martin Roth 5f066b29ce doxygen fixes: change @var to @param var
These files were trying to document the parameters, but didn't have
the syntax quite right.  Change the comments from @varname to
@param varname as required by doxygen.

Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8100
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:33:25 +01:00
Martin Roth fc34750c88 drivers/intel/fsp: split the UEFI HOB functions into hob.c
The FSP uses a lot of UEFI HOB (Hand Off Block) functions for reporting
and passing information to coreboot.  These seem to me like they should
be in their own file, so I'm splitting them out of fsp_util.c.  I'll
be adding a couple more functions in the next patch.

These functions should all be compliant to the Hand Off Block spec.

Change-Id: Ie8bbc0a9277b9484f13dd077b3a52e424a8600fe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8065
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-06 06:28:50 +01:00
Edward O'Callaghan 9270553fff Re-factor 'to_flash_offset()' into 'spi_flash.h'
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by
Clang complaining that the function 'to_flash_offset' is unused.

Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06 04:56:14 +01:00
Gabe Black a4c4b1c69c elog: Use the RTC driver interface instead of reading CMOS directly.
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.

BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan

Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197798
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4fad296ecfeff8987e4a18054661190239245f32
Reviewed-on: http://review.coreboot.org/7891
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:11:54 +01:00
Gabe Black abb001a2fe rtc: Add an RTC driver for the AS3722 PMIC.
The AS3722 PMIC, like many PMICs, has an RTC built into it. This change adds a
driver for it which implements the new RTC API.

BUG=None
TEST=Built and booted with the event log code modified to use this interface.
Verified that events had accurate timestamps.
BRANCH=nyan

Original-Change-Id: I400adccbf84221dcba8d520276bb91b389f72268
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197796
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 011e49beba3a99abbd122866891e3c20bf1188d2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ibc1d342062c7853a30d195496c077e37a02b35b0
Reviewed-on: http://review.coreboot.org/7890
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 22:11:18 +01:00
Gabe Black 03abaee219 drivers/pc80/mc146818rtc: Assume we always have ALTCENTURY
This patch has a rather twisted history. It was originally split off
from a chromium patch, which moved ALTCENTURY to Kconfig. However,
since we have no user without ALTCENTURY, we've agreed that the best
way to proceed is to eliminate the non-ALTCENTURY case entirely.

The old commit message and identifiers are kept below for reference:

The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.

BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan

Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>

This is the second half the following patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7987
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-30 22:10:41 +01:00
Marc Jones 0658d2348d SPI: Add Eon EN25S64 support.
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.

Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d
Original-Reviewed-on: https://chromium-review.googlesource.com/198324
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e
Reviewed-on: http://review.coreboot.org/7935
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-12-30 19:31:00 +01:00
Marc Jones 79f60a5c9d SPI: Fix Eon support
The Eon SPI25 code had a number of issues:
 - fix page write calculation
 - fix erase segment
 - fix id check
 - fix sector size
 - make commands EN25 generic
This makes the code similar to other SPI25 devices used in coreboot.

BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.

Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198323
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8917e778cd62f3745189336d23c0c6118887d893
Reviewed-on: http://review.coreboot.org/7934
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 19:30:28 +01:00
Vadim Bendebury 8e64388210 drivers/spi: Prepare Spansion driver for use in CBFS wrapper
Since the same driver is going to be used at all coreboot stages, it
can not use malloc() anymore. Replace it with static allocation of the
driver container structure.

The read interface is changed to spi_flash_cmd_read_slow(), because of
the problems with spi_flash_cmd_read_fast() implementation. In fact
there is no performance difference in the way the two interface
functions are implemented.

BUG=chrome-os-partner:27784
TEST=manual
  . with all patches applied coreboot proceeds to attempting to load
    the payload.

Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197931
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2
Reviewed-on: http://review.coreboot.org/7933
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 19:30:09 +01:00
Vadim Bendebury adcb095e9e Provide a common CBFS wrapper for SPI storage
Coreboot has all necessary infrastructure to use the proper SPI flash
interface in bootblock for CBFS. This patch creates a common CBFS
wrapper which can be enabled on different platforms as required.

COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the
common CBFS interface and prevents default inclusion of all SPI chip
drivers, only explicitly configured ones will be included when the new
feature is enabled. Since the wrapper uses the same driver at all
stages, enabling the new feature will also make it necessary to
include the SPI chip drivers in bootblock and romstage images.

init_default_cbfs_media() can now be common for different platforms,
and as such is defined in the library.

BUG=none
TEST=manual
   . with this change and the rest of the patches coreboot on AP148
     comes up all the way to attempting to boot the payload (reading
     earlier stages from the SPI flash along the way).

Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197800
Original-Tested-by: Vadim Bendebury <vbendeb@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41
Reviewed-on: http://review.coreboot.org/7932
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 19:29:47 +01:00
Vadim Bendebury b1528838f6 drivers/spi: add support for another Spansion chip
Add the device ID definitions and properties for the SPI chip used on
the AP148 board (Google Storm).

BUG=chrome-os-partner:27784
TEST=manual
   . with the rest of the patches applied AP148 boots all the way to
     trying to read the payload.

Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197895
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b
Reviewed-on: http://review.coreboot.org/7931
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-30 19:29:23 +01:00
Marc Jones 3cc685fd3e rtc: Add an RTC API, and implement it for x86.
This CL adds an API for RTC drivers, and implements its two functions,
rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the
CMOS as lost state now uses the RTC driver instead of accessing the those
registers directly.

BUG=None
TEST=Built and booted on Link with the event log code modified to use
the RTC interface. Verified that the event times were accurate.
BRANCH=nyan

Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>

This is the first half of the patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883
Reviewed-on: http://review.coreboot.org/7889
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-30 19:28:27 +01:00
Kyösti Mälkki 99c4955338 TPM: Fix i2c driver dependency
Change-Id: I59545ef734dff41ba55dcddd541c54b17b0855bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7914
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-23 04:13:32 +01:00
Marc Jones 455fcaf146 elog: Fix chromium merge issue
This cleans up a mis-merge in elog.c and puts the following
change back:

drivers/elog: Unmangle header include out of pre-proc cond
commit a3119e5835

Change-Id: Iafbbd381efdb103717022d2a3c342da376a9428f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 20:51:21 +01:00
Marc Jones 127ad41f64 Revert "elog: Use the RTC driver interface instead of reading CMOS directly."
This reverts commit 474313d1b6.

This reverted commit was applied out of sequence and there are a number
of dependencies that need to be in place prior to adding it. Remove it
for now.

Change-Id: If80c40867098dee2feff2b9a1d824558f4d7028d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 20:47:46 +01:00
David Hendricks 032c843817 spi_flash: Move (de-)assertion of /CS to single location
This consolidates all calls to spi_claim_bus() and spi_release_bus()
to a single location where spi_xfer() is called. This avoids confusing
(and potentially redundant) calls that were being done throughout the
generic spi_flash.c functions and chip-specific functions.

I don't think the current approach could even work since many chip
drivers assert /CS once and then issue multiple commands such as page
program followed by reading the status register. I suspect the reason
we didn't notice it on x86 is because the ICH/PCH handled each
individual command correctly (spi_claim_bus() and spi_release_bus()
are noops) in spite of the broken code.

BUG=none
BRANCH=none
TEST=tested on nyan and link
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I3257e2f6a2820834f4c9018069f90fcf2bab05f6
Original-Reviewed-on: https://chromium-review.googlesource.com/194510
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d3394d34fb49e9e252f67371674d5b3aa220bc9e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ieb62309b18090d8f974f91a6e448af3d65dd3d1d
Reviewed-on: http://review.coreboot.org/7829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 04:51:28 +01:00
David Hendricks f101bbe4f0 spi_flash: Differentiate between atomic/manual sequencing
This adds a wrapper function and a Kconfig variable to differentiate
between SPI controllers which use atomic cycle sequencing versus
those where the transaction sequence is controlled manually. Currently
this boils down to x86 vs. non-x86.

Yes, it's hideous. The current API only worked because, for better or
worse, x86 platforms have been homogeneous in this regard since they
started using SPI as an alternative to FWH for boot flash. Now that
we have non-x86 platforms which use general purpose SPI controllers,
we should overhaul the entire SPI infrastructure to be more adaptable.

BUG=none
BRANCH=none
TEST=tested on nyan and link
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: If8ccc9400a9d04772a195941a42bc82d5ecc1958
Original-Reviewed-on: https://chromium-review.googlesource.com/195283
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4170c59d06206667755402712083452da9fcd941)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I54e2d3d9f9a0153a56f7a51b80f6ee6d997ad358
Reviewed-on: http://review.coreboot.org/7828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 04:51:21 +01:00
Gabe Black 474313d1b6 elog: Use the RTC driver interface instead of reading CMOS directly.
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.

BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan

Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197798
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I8481adde86d836b5f0b019c815bada6d232a4186
Reviewed-on: http://review.coreboot.org/7833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 02:12:17 +01:00
David Hendricks 259e49a2c7 elog: Isolate some x86-isms
This attempts to isolate/fix some x86-isms:
- Translate flash offset to memory-mapped address only on x86.
- Guard ACPI-dependent line of code
- Use a Kconfig variable for SPI bus when probing the flash rather
  than assuming the bus is always on bus 0.
- Zero-out timestamp on non-x86 until we have a better abstraction.

(note: this is based off of some of Gabe's earlier work)

BUG=none
BRANCH=none
TEST=needs testing
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I887576d8bcabe374d8684aa5588f738b36170ef7
Original-Reviewed-on: https://chromium-review.googlesource.com/191203
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1fc7a75f8c072098e017104788418aeed0705e93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ida4b211cf21ecdde9745d4dbef6a63ffb9fbba8d
Reviewed-on: http://review.coreboot.org/7832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 02:12:09 +01:00
David Hendricks 9acbd6ff99 elog: Do not attempt to init SPI
This severs a dependency the eventlog code has on initializing
chipset/SoC SPI controller. Currently elog_init() calls spi_init()
as a catch-all. This worked for x86 since the SPI controller is only
used for one thing on existing platforms. As we add eventlogging
support to non-x86 platforms we need to consider the more generalized
case where the assumptions about how SPI works on x86 are no longer
valid.

BUG=none
BRANCH=none
Signed-off-by: David Hendricks <dhendrix@chromium.org>
TEST=built and booted on Link, Beltino and Rambi. See below for
"mosys eventlog list" output on Link showing boot and suspend/resume
events (including lid close/open) added successfully.

localhost ~ # mosys eventlog list
0 | 2014-04-14 13:52:44 | Log area cleared | 4096
1 | 2014-04-14 13:52:44 | System boot | 50
2 | 2014-04-14 13:52:44 | EC Event | Power Button
3 | 2014-04-14 13:52:44 | SUS Power Fail
4 | 2014-04-14 13:52:44 | System Reset
5 | 2014-04-14 13:52:44 | ACPI Wake | S5
6 | 2014-04-14 13:53:25 | ACPI Enter | S3
7 | 2014-04-14 13:53:35 | ACPI Wake | S3
8 | 2014-04-14 13:53:35 | Wake Source | RTC Alarm | 0
9 | 2014-04-14 13:53:49 | ACPI Enter | S3
10 | 2014-04-14 13:54:00 | EC Event | Lid Open
11 | 2014-04-14 13:54:00 | ACPI Wake | S3
12 | 2014-04-14 13:54:00 | Wake Source | GPIO | 15

Original-Change-Id: I26e25c0a856f7b8db5ab6b8e7e1acae291d2eadc
Original-Reviewed-on: https://chromium-review.googlesource.com/194526
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2971d20b6ebdd9803b05ccbbaeefe1bde1a21af4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia5f2913fd8e4fee6e741e6d1e39d32bb86525cb3
Reviewed-on: http://review.coreboot.org/7831
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-17 02:12:03 +01:00
David Hendricks 43e925252a spi: Add support for Winbond W25Q32DW
Similar to the W25Q64DW, the W25Q32DW has basically the same
attributes as the earlier W25Q32 parts but with a different
value in the MSB of the ID.

BUG=none
BRANCH=none
TEST=tested on nyan, now SPI flash commands actually work.
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I697768a443c98515d893f9cf8f8b4258ae0f159d
Original-Reviewed-on: https://chromium-review.googlesource.com/191205
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 35f03f4f4f21c470d172ce7cce257517b959346d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I73606737835e4f8ea00d2c331ca37957e4abd953
Reviewed-on: http://review.coreboot.org/7755
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-12-16 23:32:15 +01:00
David Hendricks b598bb332c spi: Make idcode debug print more useful
The old print simply said "Got idcode". This makes it actually
display what it got.

BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I8f1c8fde6e4ac00b12e74f925b7bcff83d1f69f3
Original-Reviewed-on: https://chromium-review.googlesource.com/191204
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 5f13789be77d038d3c1602037afe29a0351f72ee)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I65d0d51c17b3bda62351532aac1756b630433ea3
Reviewed-on: http://review.coreboot.org/7754
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-16 23:32:08 +01:00
Gabe Black cdb61a6f5d i2c: Replace the i2c API.
The new API is in use in depthcharge and is based around the "i2c_transfer"
function instead of i2c_read and i2c_write. The new function takes an array of
i2c_seg structures which represent each portion of the transfer after a start
bit and before the stop bit. If there's more than one segment, they're
seperated by repeated starts.

Some wrapper functions have also been added which make certain common
operations easy. These include reading or writing a byte from a register or
reading or writing a blob of raw data. The i2c device drivers generally use
these wrappers but can call the i2c_transfer function directly if the need
something different.

The tegra i2c driver was very similar to the one in depthcharge and was simple
to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and
replace the ones in coreboot. The Exynos 5420 driver was ported from the high
speed portion of the one in coreboot and was straightforward to port back. The
low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot
and were replaced with the depthcharge implementation.

BUG=None
TEST=Built and booted on nyan with and without EFS. Built and booted on, pit
and daisy.
BRANCH=None

Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193561
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe)

This cherry-pick required additional changes to the following:
src/cpu/allwinner/a10/twi.c
src/drivers/xpowers/axp209/axp209.c

Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7
Reviewed-on: http://review.coreboot.org/7751
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-16 00:02:43 +01:00
David Hendricks c94702481b elog: Probe for SPI flash on bus indicated by Kconfig variable
This replaces a hard-coded bus number of 0 with a Kconfig variable,
CONFIG_BOOT_MEDIA_SPI_BUS. This removes an assumption made for x86
where this value is always 0 and makes it easy to add support for
other platforms where the bus number for the backing SPI flash is
more arbitrary.

BUG=none
BRANCH=none
TEST=tested on Nyan (bus=4) and Link (bus=0)
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I1e878a1628af7f4ccc2f39a70b2190192767e536
Original-Reviewed-on: https://chromium-review.googlesource.com/194854
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 371c6c14d8d4b98004eebce7049a88a219682bc4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie105b4654e028098f2137c96e4309b8d85f096df
Reviewed-on: http://review.coreboot.org/7753
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-15 23:58:34 +01:00
Kyösti Mälkki 164ac0a429 uart8250mem: Add wrapper for MMIO register access
For some UART hardware registers are 32 bits wide, so we will need
base_port + reg << 2 instead. Prepare for that change and unification of
MMIO between ARM and x86.

Change-Id: I5fa2c2f7ee4872499a01754c1ba872a8addf499c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7793
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-15 20:00:28 +01:00
Aaron Durbin 30974bc2f5 vboot: allow for non-memory-mapped VBOOT regions
Depending on the platform the underlying regions vboot requires
may not be accessible through a memory-mapped interface. Allow
for non-memory-mapped regions by providing a region request
abstraction. There is then only a few touch points in the code to
provide compile-time decision making no how to obtain a region.

For the vblocks a temporary area is allocated from cbmem. They
are then read from the SPI into the temporarily buffer.

BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built and booted a rambi with vboot verification.

Original-Change-Id: I828a7c36387a8eb573c5a0dd020fe9abad03d902
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190924
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit aee0280bbfe110eae88aa297b433c1038c6fe8a3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia020d1eebad753da950342656cd11b84e9a85376
Reviewed-on: http://review.coreboot.org/7709
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-09 18:41:00 +01:00
Dave Frodin 018560667a spi/macronix: Add support for MX25L3239E
Also update comment for the MX25L3236D part.

Change-Id: Ifaeeb71e7672a8db55bbb66e6ce7316e2893478d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7631
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-09 18:28:48 +01:00
Edward O'Callaghan 7c0ee48510 drivers/intel/fsp/fsp_util.c: Remove attribute,optimize("O0")
This is not actually required. Tested on 'minnow max' hardware as
well as compared the asm of the optimized and non-optimized. Thanks Martin!

Change-Id: I06e71876c3a3a15101013623797c2ebbf449756d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Found-by: Clang
Reviewed-on: http://review.coreboot.org/7694
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-08 18:27:21 +01:00
Martin Roth e10108a669 FSP platform microcode: Update to remove Kconfig variable
Move the Kconfig variable into a .h file - this does not need to be
in Kconfig.

Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7646
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05 21:40:12 +01:00
Martin Roth 09dd70ebb8 drivers/intel/fsp: add upd macros and #defines
Add macros and #defines for working with the UPD data.  This makes
the code look much cleaner.

Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include
the fsp_values header instead.  This fixes a conflict.

Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7487
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05 16:19:45 +01:00
Kyösti Mälkki 96d92765e1 SPI: Add vendor Atmel
Change-Id: I60e578003b857f5dcabb2e9bc75aa46acddb62b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7433
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 05:29:04 +01:00
Kyösti Mälkki 3f382c7c08 SPI: Add Macronix part MX25U12835F
Change-Id: I82482419afdf536a19b99c79131fa5844aaaec07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7432
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-12-03 05:20:34 +01:00
Edward O'Callaghan 1ab41db0e3 drivers/i2c/at24rf08c/lenovo_serials.c: Use NULL over '0'
Change-Id: I7d8922d1812814ea2ebd72aaf5b5e28dc592bfb3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7590
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-28 04:53:15 +01:00
Edward O'Callaghan 07d89a0e0d drivers/i2c/at24rf08c/lenovo_serials.c: Upper-case'ify
Thereby making consistent with other i2c drivers

Change-Id: I5ddc9d98fbbc1db68a933e3b9a6b92f309b72c41
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7589
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-28 04:53:02 +01:00
Kyösti Mälkki 9e999d6a14 usbdebug: Some fix for dongle compatibility
Not sure what this is about.

Required for BeagleBone (not Black) with HUB in the middle, also
old FX2 senses extra reset if we do this.

Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3868
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-23 20:36:53 +01:00
Kyösti Mälkki b8ef4c9a84 usbdebug: Reduce bus reset delays
According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.

Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3863
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2014-11-23 20:36:16 +01:00
Kyösti Mälkki 46249be267 usbdebug: Refactor descriptor probing of dongle
Organized such that it is easy to support devices that do not
export special Debug Descriptor. Some of these can still work
in a fixed configuration and/or require additional initialisation
for UART clocks etc.

Change-Id: Id07fd6b69007332d67d9e9a456f58fdbca1999cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7209
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2014-11-23 20:35:51 +01:00
Kyösti Mälkki 83fe6d7fd2 usbdebug: Move initialisation of the optional hub
Add new file for device-specific initialisation transactions.

Change-Id: I339df400a41675f178c7af613f03b2b44c826189
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2014-11-23 20:35:03 +01:00
Kyösti Mälkki 7bb4f86d07 usbdebug: Refactor on EHCI memory space
We only reference with ehci_caps and ehci_regs during initialisation,
no need to carry those around.

When EHCI BAR is relocated during PCI allocation, record the changed
address even if usbdebug is not enabled. Use the DBGP_EP_VALID flags
to determine if endpoints have been configured or not.

Change-Id: Idfd52edf7c2fc25b1b225985462ac488264e4c6d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7207
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2014-11-23 20:34:53 +01:00
Kyösti Mälkki 618d179bfe usbdebug: Fix migration to ramstage
On entry to ramstage CBMEM is looked for a copy of an already initialized
EHCI debug dongle state. If a copy is found, it contained the state before
CAR migration and the USB protocol data toggle can be out of sync. It's an
even/odd kind of a parity check, so roughly every other build would
show the problem as invalid first line: 'ug found in CBMEM.'

After CAR migration, re-direct the state changes to correct CBMEM table.

Change-Id: I7c54e76ce29af5c8ee5e9ce6fd3dc6bdf700dcf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7206
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-23 20:34:42 +01:00
Edward O'Callaghan 20a41ae80b drivers/net/ne2k.c: Fix regression
Provide dummy ramstage symbol to keep the linker happy. Borked
in commit fd95624

Change-Id: I2c49e82fec8eb936390cc3b30698f1bf73968c99
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7548
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-11-22 15:25:09 +01:00
Kyösti Mälkki c36af7b00a Replace includes of build.h with version.h
As build.h is an auto-generated file it was necessary to add it as
an explicit prerequisite in the Makefiles. When this was forgotten
abuild would sometimes fail with following error:

   fatal error: build.h: No such file or directory

Fix this error by compiling version.c into all stages.

Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7510
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20 07:28:37 +01:00
Vladimir Serbinenko 9acc1e8dfc acpigen: Use implicit length patching in acpigen_write_resourcetemplate_footer
Change-Id: Ic177720b074fed13a17454dcb6765ac298365624
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19 20:56:59 +01:00
Vladimir Serbinenko 663be6e9f2 acpigen: Add and use acpigen_write_device.
The sequence of bytes to create a method is used several times in codebase.
Put it into a function with logical arguments rather than duplicating magic
bytes everywhere.

Change-Id: I2c33fa403832eb1cfadfbf8d9adef5b63fb9cb24
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7348
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-19 19:51:30 +01:00
Vladimir Serbinenko 80fb8edaea acpigen: Add and use acpigen_write_method.
The sequence of bytes to create a method is used several times in codebase.
Put it into a function with logical arguments rather than duplicating magic
bytes everywhere.

Change-Id: I0e55d8dc7d5e8e92a521c7a83117c470d0614008
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7347
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19 19:50:51 +01:00
Edward O'Callaghan a955fefd14 drivers/intel/gma/intel_dp.c: Fix printf type-specifier
'%02hx' is unsigned short, where as the argument is typed as
uint8_t and so '%02hhx' is actually correct here.

Found-by: Clang
Change-Id: I40c48dcecf12845f4708e511236184908e90fb56
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7428
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2014-11-11 14:42:18 +01:00
Vladimir Serbinenko bcb3abe130 lenovo/wacom: Move to implicit length patching
Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7331
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-09 02:03:08 +01:00
Edward O'Callaghan 0d84a2c03e drivers/ioapic: DEVICE_NOOP some stub function callbacks
Just when you thought you found them all..
Reduces loc and makes NOP's explicit.

Change-Id: I416e0468b7f2f462c940daae695d67fb409aa4c6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7350
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07 12:50:22 +01:00
Edward O'Callaghan 2014111786 drivers/net/ne2k.c: Collect headers and defines to top of file
Change-Id: I2ffb0dd9fe400132f6d430f115f962b5f8578efa
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7292
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-07 12:49:35 +01:00
Vladimir Serbinenko 41f55b734f intel_wifi: Export the SMBIOS structure required by intel driver.
Change-Id: I22984a1bc7ca3be6593143af4fce8d5bfe469837
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7295
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-02 23:09:15 +01:00
Edward O'Callaghan 524625d4e0 drivers: Use DEVICE_NOOP macro over dummy symbol
Change-Id: I931bd9c89bce6ac8f8e9e482a7876e2004abfb38
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7284
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01 21:14:07 +01:00
Edward O'Callaghan 2c9d2cf75c {arch,cpu,drivers,ec}: Don't hide pointers behind typedefs
Change-Id: Id88bb4367d6045f6fbf185f0562ac72c04ee5f84
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/7146
Tested-by: build bot (Jenkins)
2014-10-27 23:40:05 +01:00
Idwer Vollering 06413ff513 drivers/spi: add Macronix MX25U6435F and MX25L6495F support
Contributed by MXIC: http://www.coreboot.org/pipermail/coreboot/2014-October/078835.html

Change-Id: I07f872a5cbb2b0ea63794edb8fbca40d7856ce10
Author: Alex Lu <alexlu6@mxic.com.tw>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/7194
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-10-27 13:53:51 +01:00
Vladimir Serbinenko 795f96e2b9 lenovo/x2[23]0: Handle Ricoh SD cardreader
Change-Id: Id0aecbd3e45bdf9661168ebd0e55f17dc6febaaa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7203
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-10-27 10:36:13 +01:00
Gabe Black b3f08c61f1 cmos: Rename the CMOS related functions.
Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.

This CL also opportunistically cleans up some style problems in this file.

Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)

Removed the addition of stdint.h to mc146818rtc.h since
types.h is now included. Changed rtc_init to cmos_init for
fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.

Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22 03:55:14 +02:00
Gabe Black 3f5644593d tpm: i2c: When probing the TPM, write a 0 into the TPM access register.
Not doing so makes it fail when run at high frequency.

Change-Id: I1cfb69c55f03cb90f66f437289803d897a1aad5c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191812
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 04452441d2bfe2cacd3e0b6990c0e9261b5350d1)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/7007
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22 03:52:42 +02:00
Kyösti Mälkki 1729cd8574 x86 romstage: Move stack just below RAMTOP
Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.

Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19 06:14:05 +02:00
Scott Radcliffe f5fcedfbc4 drivers/spi: Add support for Micron N25Q128
Support added for Micron N25Q128 SPI flash, which has
the same manufacturer id as ST Micro. Jedec ID =
0x20 0xBB 0x18. Since existing stmicro.c only compares
the last device id byte, this flash is mistakenly
identified as M25P128, which has ID = 0x20 0x20 0x18.

To handle this situation and avoid breaking code for
existing devices, a two byte .id member is added.
New devices should be added to the beginning of the
flash table array with .idcode = STM_ID_USE_ALT_ID and
.id = the two byte jedec device id.

A 4KB subsector erase capability is added and used for
this new device. It requires using a different SPI
op-code supported by adding .op_erase member. Previous
devices defined in stmicro.c are assigned their original
op-code for 64KB sector erase.

N25Q128 is now working on a custom designed Bayley Bay
based board. Tested by verifying the MRC fastboot cache
is successfully (re)written. Note that previous devices
were not retested.

Change-Id: Ic63d86958bf8d301898a157b435f549a0dd9893c
Signed-off-by: Scott Radcliffe <sradcliffe@microind.com>
Reviewed-on: http://review.coreboot.org/7077
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-10-17 11:27:07 +02:00
Ronald G. Minnich 2adb297cf9 uarts: 32/64 cleanup
We had lots of casts that caused warnings when compiling on RISCV.
Clean them up.

Change-Id: I46fcb33147ad6bf75e49ebfdfa05990e8c7ae4eb
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7066
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-16 17:41:14 +02:00
Mohan D'Costa ed0c83877f intel/fsp_baytrail: Add S3 suspend/resume Support
This adds S3 Suspend / Resume support to Intel's Bay Trail FSP

It is based on the "src/soc/intel/baytrail/romstage/romstage.c"
implementation.

Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008
Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp>
Reviewed-on: http://review.coreboot.org/6937
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
2014-09-29 19:35:57 +02:00
Mohan D'Costa bdae9bedcd spi: Add support for Winbond W25Q128FW
The W25Q128FW spi part is programatically equivalent
to the other W25Q128 parts except it operates at 1.8V.
Just add a new entry with the appropriate ID.

Tested on a modified MinnowMax Board.

Change-Id: Id6a426418a7f785a9d959b02a9e3d2ffc421804f
Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp>
Reviewed-on: http://review.coreboot.org/6971
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
2014-09-29 19:34:53 +02:00
David Hendricks 1101a71219 spi: add Kconfig variable for dual-output read enable
Add a Kconfig variable so that driver code knows whether
or not to use dual-output reads.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5
Reviewed-on: https://chromium-review.googlesource.com/177834
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8)

tegra124: implement x2 mode for SPI transfers on CBFS media

This implements x2 mode when reading CBFS media over SPI.

In theory this effectively doubles our throughput, though the initial
results were almost negligibly better. Using a logic analyzer we see
a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we
want to see further gains here then we'll probably need to tune AHB
arbitration and utilization to eliminate bubbles/stalls when copying
from APB DMA.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e
Reviewed-on: https://chromium-review.googlesource.com/177835
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc)

nyan: turn on dual-output reads for SPI flash

Nyan's SPI chip is capable of dual-output reads, so let's use it.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df
Reviewed-on: https://chromium-review.googlesource.com/177836
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c)

Squashed three commits to enable dual output spi reads for nyan.
Also fixed the spi_xfer interface that has been updated to use bytes
instead of bits.

Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6909
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-09-17 19:56:16 +02:00
Vladimir Serbinenko a71bdc3181 intel/gma: consolidate vbt code
Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6800
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-13 14:27:03 +02:00
Vladimir Serbinenko 35c0f439fc Move nehalem/sandy/ivy to per-device acpi
Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6802
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-09-11 21:53:33 +02:00
Stefan Reinauer d518c7a2d7 tpm: Clean up I2C TPM driver
Drop a lot of u-boot-isms and share common TIS API
between I2C driver and LPC driver.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e
Reviewed-on: https://chromium-review.googlesource.com/175670
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 3fc8515b9dcef66998658e1aa5c020d22509810c)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6855
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-10 19:37:49 +02:00
Ronald G. Minnich 3a75e5e864 Haswell/falco/peppy/slippy: continue to clean up FUI.
As a first step towards removing hardcodes from the FUI support,
change the haswell call to i915_lightup to panel_lightup, and pass the
intel_dp * as a parameter. Get rid of the scalar arguments and make
them part of intel_dp. Get rid of file-scope variables and use the
ones in the intel_dp struct. In falco, use functions that peppy
uses. Drop slippy support for FUI, it's a dead board; if this is ok
I'll remove the files next.

And, incidentally, fix the broken RGBX constant and change it to BGRX.

Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174932
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6833
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-09-08 22:56:11 +02:00
Gabe Black 51edd54738 ARM: Generalize armv7 as arm.
There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.

Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>

ARM: Split out ARMv7 code and make it possible to have other arch versions.

We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.

The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.

Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)

Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.

Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
2014-09-08 18:59:23 +02:00
Vladimir Serbinenko a2a906e47a Consolidate intel vga int15 hooks
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6820
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-05 22:48:49 +02:00
Ronald G. Minnich e231de2134 drivers/gma: remove unused code
We had brought this code in from the kernel but found it best to
use mainboard- or chipset specific versions. Firmware should
strive to be as non-generic as possible.

Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172625
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 7dba0dfd25bf9e367f9e5128b15edb018e958c3a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6779
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-04 01:31:26 +02:00
Vladimir Serbinenko ed74dcd7f0 lenovo: Read mainboard version from AT24RF08C.
Tablets have different mainboard version than laptop variants.

Change-Id: I77a1e2b50d30dcf3fa064e0c378ceca7ccf96e89
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6785
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-08-30 19:26:33 +02:00
Gerd Hoffmann 2177f1bcb5 qemu: fix cirrus build
commit 9518b56 (intel/gma: Clarify code and use dedicated init for
Google Peppy) changed "struct edid" and thereby broke the build.
Adapt drivers/emulation/qemu/bochs.c to the changes to fix this.

Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y.

Change-Id: I2d3cecde21d495e9b99ff8d2f741f8a462c75a4d
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/6771
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28 07:50:53 +02:00
Gerd Hoffmann 4f62732858 qemu: fix bochs build
commit 9518b56 (intel/gma: Clarify code and use dedicated init for
Google Peppy) changed "struct edid" and thereby broke the build.
Adapt drivers/emulation/qemu/bochs.c to the changes to fix this.

Build failure triggers with CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y.

Change-Id: Ic295c6d31284555e1463af5bca673231b8722d54
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/6769
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-28 07:50:34 +02:00
Ronald G. Minnich 74fade43ee Peppy/Haswell: move more support functions from mainboard to the intel i915 driver
Move (and rename to make it clearer) the function that computes display
parameters from the dpcd and edid.

Change-Id: Idfbb56fd312b23c742c52abca1a34ae117a8fece
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171366
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
(cherry picked from commit 8f2b3bafee7cb05db8fae1c52fc9e1ee64e5e35d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6768
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-28 01:00:47 +02:00
Ronald G. Minnich 9518b56ab0 intel/gma: Clarify code and use dedicated init for Google Peppy
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.

Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.

The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c.  I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.

The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works.  To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.

Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.

Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.

Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh@gmail.com>
(cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)

snow: Fix a typo in devicetree.cb that was breaking the snow build.

A typo in a recent change broke the snow build.

Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171014
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 154876c126a6690930141df178485658533096d2)

Squashed a fix into the initial patch and updated nehalem/gma.c
to have a non-static gtt_poll.

Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6657
Tested-by: build bot (Jenkins)
2014-08-25 22:36:03 +02:00
Gabe Black 77ffa0d3ad UART 8250: Unconditionally provide register constants and use UART8250 prefix.
The register indexes and bitfield masks were guarded by the UART8250 config
options, but it might be (is) necessary to use them in a driver that is
UART8250 like without actually using the 8250 driver itself. To avoid any name
collision with other drivers, also change the constant prefix from UART_ to
UART8250_.

Change-Id: Ie606d9e0329132961c3004688176204a829569dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171336
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit a93900be8d8a8260db49e30737608f9161fbf249)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6715
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-25 19:07:04 +02:00
Furquan Shaikh 77f48cdead Falco/Slippy: Patch to refactor haswell/gma.c and mainboard/google/slippy/i915io.c
A large portion of documented registers have been initialized using macros. Only a few
undocumented registers are left out. i915io.c looks lot more cleaner by removing redundant
calls. However, some more work is required to correctly identify which calls are not required.

All the io_writes are replaced by gtt_writes.

Change-Id: I077a235652c7d5eb90346cd6e15cc48b5161e969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66204
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 39f3289f68b527575b0a120960ff67f78415815e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6600
Tested-by: build bot (Jenkins)
2014-08-13 19:32:11 +02:00
Stefan Reinauer 7cb01e0bcf drivers: Add I2C TPM driver to coreboot
On ARM platforms the TPM is not attached through LPC but through I2C.
This patch adds an I2C TPM driver that supports the following chips:
 * Infineon SLB9635
 * Infineon SLB9645
In order to select the correct TPM implementation cleanly, CONFIG_TPM
is moved to src/Kconfig and does the correct choice.

Old-Change-Id: I2def0e0f86a869d6fcf56fc4ccab0bc935de2bf1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/167543
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit b4049a0e96f6335a93877e1e884f9a440487c421)

i2c tpm: Remove mostly useless delay code/tables.

I assume from the code in the TPM driver that the TPM spec defines
different types of delays and timeouts which each have a particular
duration, and that the TPM can tell you how long each type is if you ask
it. There was a large table, some members of a data structure, and a
function or two which managed the timeouts and figured their value for
different operations.  The timeout values for the various "ordinals"
were never set in the vendor specific data structure, however, and
always defaulted to 2 minutes.  Similarly the timeouts a, b, c, and d
were never overridden from their defaults.  This change gets rid of all
the timeout management code and makes the "ordinal" timeout 2 minutes
and the a, b, c, and d timeouts 2 seconds, the larger of the two default
values.

This is a port from depthcharge to coreboot, original change:
https://chromium-review.googlesource.com/#/c/168363/

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Old-Change-Id: I79696d6329184ca07f6a1be4f6ca85e1655a7aaf
Reviewed-on: https://chromium-review.googlesource.com/168583
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit b22395a73f361c38626911808332a3706b2334fe)

TPM: Stop requesting/releasing the TPM locality.

The locality is requested when the TPM is initialized and released when
it's cleaned up. There's no reason to set it to the same thing again and
restore it back to the same value before and after every transaction.

forward ported from https://chromium-review.googlesource.com/#/c/168400

Old-Change-Id: I291d1f86f220ef0eff6809c6cb00459bf95aa5e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168584
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit cc866c20c6f936f349d2f1773dd492dca9bbf0c1)

Squashed three commits for the i2c tpm driver.

Change-Id: Ie7a50c50fda8ee986c02de7fe27551666998229d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6519
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10 22:25:48 +02:00
Vladimir Serbinenko f2e206a7fd x230: Deploy VBT
Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5396
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-07-29 01:34:09 +02:00
Elyes HAOUAS e34a6275ee src/drivers: Remove a trailing whitespace
Change-Id: If357da5d84a255e0bdf8784d559ee0941045bbd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6309
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-21 22:28:51 +02:00
Vladimir Serbinenko f2b3cd63cf lenovo/x60: Support digitizer on X60t and X201t.
Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5239
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-07-19 14:24:29 +02:00
Edward O'Callaghan c4561e24bb drivers/spi: Sanitize headers from preprocessor abuse
Continuing on from the rational given in:

a173a62 Remove guarding #includes by CONFIG_FOO combinations

Change-Id: I35c636ee7c0b106323b3e4b90629f7262750f8bd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6114
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17 20:21:30 +02:00
Edward O'Callaghan 4fc32be152 drivers,Makefile.inc: Trivial - drop trailing blank lines at EOF
Change-Id: I2d1f6a571166924c929452fd0f70192670904220
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6285
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17 02:19:46 +02:00
Edward O'Callaghan 8f3de28af3 drivers/intel/fsp/fsp_util: 'long unsigned int' is 'unsigned long'
This is a bit of strange way to write 'unsigned long', fix that.

Change-Id: I17caf971dac840e0f35f883dacfbd5c94d8c03d6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6196
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-15 15:20:18 +02:00
Kyösti Mälkki 1110495de9 SPI: Split writes using spi_crop_chunk()
SPI controllers in Intel and AMD bridges have a slightly different
restriction on how long transactions they can handle.

Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6163
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:42:49 +02:00
Kyösti Mälkki 77d1280d0c SPI flash: Fix alignment checks in Page Program commands
There are two separate restrictions to take into account:

  Page Program command must not cross address boundaries defined by the
  flash part's page size.

  Total number of bytes for any command sent to flash part is restricted
  by the SPI controller capabilities.

Consider

  CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4.
  This write would be split at offset 64 for no reason.

Consider

  CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4.
  This write would not be split at page boundary as required.

We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT
is a misnomer for the maximum payload length supported by the SPI controller
and is removed in a followup.

Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6162
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:42:27 +02:00
Edward O'Callaghan 1bd01663f5 drivers: Trivial - drop trailing blank lines at EOF
Change-Id: Ie80c87c614a536cc6b0bdbf196c280b64547d3b7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6203
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:51:47 +02:00
Gabe Black 93d9f92cfb spi: Change spi_xfer to work in units of bytes instead of bits.
Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.

BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None

Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6175
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:36:20 +02:00
Gabe Black 1e187356e8 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.
The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.

BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None

Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6174
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:36:11 +02:00
Kyösti Mälkki ab60510818 spi flash: Organise options list
Change-Id: I21e4e2384d9b8bbd34f652e99af11dee993fb41c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6173
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:35:53 +02:00
Dave Frodin c50c0ab456 drivers/spi: Reduce the per loop delay of spi_flash_cmd_poll_bit()
At the end of some SPI operations the SPI device needs to be polled
to determine if it is done with the operation. For SPI data writes
the predicted time of that operation could be less than 10us.
The current per loop delay of 500us is adding too much delay.
This change replaces the delay(x) in the do-while loop with a
timer so that the actual timeout value won't be lengthened by the
delay of reading the SPI device.

Change-Id: Ia8b00879135f926c402bbd9d08953c77a2dcc84e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5973
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05 00:38:46 +02:00
Kyösti Mälkki 931c1dcec0 stdlib: Drop duplicates of min() and max()
Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6161
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-01 10:15:26 +02:00
Edward O'Callaghan ec79d7a66e drivers/pc80/mc146818rtc_early.c: Silence unused func complaints
Clang complains these functions are unused since they find their way
into the bootblock of ROMCC boards by #including the .c file. These
static inlines should probably be moved into a header in reality.

Change-Id: I9d82a6befb0ac99afab6265f9d3649e419f2887d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6122
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-29 15:03:49 +02:00
Edward O'Callaghan b0cbb2cd17 drivers/intel/gma: Uninitialized var before if condition
The variable 'wait' is used uninitialized whenever 'if' condition is false
                if (val & DDI_BUF_CTL_ENABLE) {
                    ^~~~~~~~~~~~~~~~~~~~~~~~

Leading to an uninitialized use occurs here:
                if (wait)
                    ^~~~

Change-Id: I7d96bf1e33b9c4312d4a0ba8276e83d17d6cd070
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-25 11:38:33 +02:00
Edward O'Callaghan a3119e5835 drivers/elog: Unmangle header include out of pre-proc cond
Change-Id: Ic4905d8a6908a30602382f5846f1dc2c0dbe2431
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6068
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 11:34:32 +02:00
Kyösti Mälkki 9d9eb1ec8d PC80 RTC: Use acpi_is_wakeup_s3()
Change-Id: Idc4c47f3802019c2853ec71f8e9c057c3ab8d3ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6074
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:54 +02:00
Kyösti Mälkki 6202aea922 PS2 keyboard: Use acpi_is_wakeup_s3()
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6073
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:54 +02:00
Kyösti Mälkki c3c4a38c95 Misc: Use acpi_is_wakeup_s3()
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6072
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:53 +02:00
Edward O'Callaghan 669cb2f0c4 drivers/intel/gma: Equality comparison with extraneous parentheses
Spotted by Clang.

Change-Id: I3e612c0fa050a09fa7e5b1cb643935b84eb2b957
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6053
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-20 07:36:31 +02:00
Mike Loptien ce740c474c PIC i8259: Move #defines and functions to i8259.h
The PIC i8259.c file has a lot of #defines and function
definitions in it.  I am moving these to the i8259.h file
and also adding a few functions to update the PIC IRQ mask
register.  The PIC default configuration has all of its
interrupts masked off except for IRQ2.  IRQ2 is where
the Slave PIC is cascaded from the Master PIC.

Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5950
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-11 17:07:38 +02:00
Vladimir Serbinenko 4c81a9e142 i915_reg: Declare LVDS register values.
Change-Id: If8b3578c4fa31bf9f09c0053a5cac7ebc993b634
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5319
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 01:57:12 +02:00
Martin Roth 2a9b2ed3ff drivers/intel/fsp: update enable_mrc_cache with fast boot
When going from a configuration with fast boot disabled to one with
it enabled, ENABLE_MRC_CACHE was not being enabled properly.  This
forces it on with ENABLE_FSP_FAST_BOOT.

Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-29 23:09:26 +02:00
Martin Roth 7312c54dc6 add rtc_init() to romstage
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory.  Because of this, we need to initialize
the RTC in romstage instead of ramstage.

Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5735
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-29 23:09:12 +02:00
Vladimir Serbinenko a31a838cdb lenovo: Add lenovo_mainboard_partnumber.
Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5246
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 15:59:19 +02:00
Patrick Georgi e9e99e976e drivers/pc80/Kconfig: Revert PS/2 initialization defaults
Remove the inconsistent behaviour based on unrelated
configuration: PS/2 init is now always enabled.
This can change once we find a better approach.

Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5634
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2014-05-23 19:28:22 +02:00
Edward O'Callaghan fb8df3240f drivers: Drop GbE stub drivers
These NIC stub drivers were to initialize the Gigabit Ethernet adapters
just enough to keep coreboot from trying to execute an option ROM.
However this is no longer required as non-VGA option roms are not ran;
See:

b32816e Remove PCI_ROM_RUN option

Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5777
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-20 13:46:35 +02:00
Edward O'Callaghan 9c8532b350 drivers/spi/sst.c: Remove unused func to_sst_spi_flash()
Trips up clang builds with a warn treated as error.

Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5779
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-18 18:05:42 +02:00
Patrick Georgi 58f73a69cd build: separate CPPFLAGS from CFLAGS
There are a couple of places where CPPFLAGS are
pasted into CFLAGS, eliminate them.

Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5765
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:29 +02:00
Patrick Georgi 98f49d2823 build: CPPFLAGS is more common than INCLUDES
Rename INCLUDES to CPPFLAGS since the latter is more
commonly used for preprocessor options.

Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5764
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:24 +02:00
Patrick Georgi 1ec065bffa drivers/pc80/Kconfig: simplify PS/2 selection rules
There's no need to state the dependency twice.

Change-Id: Ia241d441211c6f476d0a6ed7589b038f7a220265
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5633
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-05-15 10:08:38 +02:00
Edward O'Callaghan def00be41d src/drivers/pc80: Remove empty struct keyboard
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.

Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-13 10:03:51 +02:00
Martin Roth a6427161c2 Intel FSP: add a shared set of functions for the FSP
- Move the non chipset-specific fsp pieces out of the chipset into a
shared area.  This is used by northbridge / southbrige / SOC code.  It
pulls in pieces from Kconfig, Makefile and FSP specific code.
- Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP"

Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5635
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:35:56 +02:00
Paul Menzel 2d9725e763 drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payload
If the user selects GRUB 2 as the payload in Kconfig, coreboot does
not need to initialize the PS/2 keyboard as GRUB 2 is going to do it.

Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 15:05:07 +02:00
Paul Menzel 4fdc680efc drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payload
As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is
able to initialize the PS/2 keyboard itself, so it is not necessary to
let coreboot do it.

SeaBIOS is also able to do it faster as discussed in a thread on the
coreboot mailing list from October 2010 [1]. In that thread it was
also proposed to not let coreboot initialize the PS/2 coreboot when
SeaBIOS is used as a payload.

[1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310
    subject: [coreboot] coreboot+seabios timings

Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 15:04:58 +02:00
Paul Menzel 7ac7627546 drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboard
Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 15:03:57 +02:00
Kyösti Mälkki 48713a1bf7 console: Drop EARLY_CONSOLE option
We have means to easily disable a specific console in romstage if
necessary, so this global option makes little sense.

The option was initially introduced as a work-around for build issues
around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.

Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5607
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:20 +02:00
Kyösti Mälkki 70342a7f51 uart: Support multiple ports
The port for console remains to be a compile time constant.
The Kconfig option is changed to select an UART port with index
to avoid putting map of UART base addresses in Kconfigs.

With this change it is possible to have other than debug console
on different UART port.

Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5342
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:05 +02:00
Kyösti Mälkki 88e518f4bc SPI: Use common dependency in Kconfig
Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-29 17:31:03 +02:00
Kyösti Mälkki 4566d2e7cd uart8250io: Fix build with DEBUG_SMI
Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-26 15:09:07 +02:00
Furquan Shaikh 817149643c Get rid of HAVE_INIT_TIMER config option
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use a stub for init_timer in
places where we do not have any init_timer defined. Thus, remove the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include a stub_timer if required.

Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 13:25:28 +02:00
Kyösti Mälkki d6060b7142 usbdebug: Add BeagleBone Black
Avoid some confusion as the selection of "BeagleBone" is not compatible
with the product "BeagleBone Black".

Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4289
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-22 15:49:26 +02:00
Kyösti Mälkki 147f703aa9 Drop drivers/generic/debug
Not very popular nor useful nowadays.

Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4554
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-22 13:42:48 +02:00
Kyösti Mälkki fd95624dae console: Drop driver list in ramstage
This framework was only available in ramstage. So we had to define
console output functions separately for bootblock, romstage and SMM.
Follow-up patches will re-enable all the consoles removed here,
in a more flexible fashion, and with less lines-of-code and copy-paste.

Also the driver list is not in a well-defined order and some of the
loops could exit without visiting all drivers.

NOTE: This build has no console in ramstage.

Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5337
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:09 +02:00
Kyösti Mälkki d53d96dddd OxPCIe uart: Move under drivers/uart
This driver is only a thin shell for uart8250mem and we could extend it
with further compatible PCI IDs from other vendors/brands.

Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:30:53 +02:00
Kyösti Mälkki 4c686f2106 OxPCIe uart: Split PCI bridge control
None of the PCI bridge management here is specific to the PCI UART
device/function. Also the Kconfig variable defaults are not globally
valid, fill samsung/lumpy with working values.

Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5237
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:29:45 +02:00
Kyösti Mälkki afa7b13b93 uart: Redefine Kconfig options
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.

Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.

Removes:
  CONSOLE_SERIAL_UART
  HAVE_UART_IO_MAPPED
  HAVE_UART_MEMORY_MAPPED

Renames:
  CONSOLE_SERIAL8250     ->  DRIVERS_UART_8250IO
  CONSOLE_SERIAL8250MEM  ->  DRIVERS_UART_8250MEM

Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:24:43 +02:00
Kyösti Mälkki bbf6f3d384 console uart: Fill coreboot table entries
Also fixes the reported baudrate to take get_option() into account.

Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5310
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:19:27 +02:00
Kyösti Mälkki c2610a4a18 uart: Prepare to support multiple base addresses
Prepare low-level register access to take UART base address as a
parameter. This is done to support a list of base addresses defined
in the platform.

Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5309
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:13:03 +02:00
Chris Douglass b34739b4b0 drivers/spi: Add support for adesto SPI flash parts
Adds support for the following Adesto Technologies
SPI Flash parts.

AT25DF081
AT25DF321
AT25DF641

It has been tested on an Orion VPX7654 board populated
with an AT25DF321A part. The "08" and "64" densities have not
been tested.

These parts are the successors of the Atmel AT26DF line that
was spun out or purchased by Adesto.

In this patch, adesto.c is identical to winbond.c with part
entries for the Adesto parts. The datasheet for the AT25DF parts
includes a "100MHz" programming command in addition to the "85MHz"
command that is currently used but this patch does not add support
for that enhanced programming mode.

Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5225
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-12 01:03:31 +01:00
Vladimir Serbinenko afc62a7631 intel/gma: Remove MCH register declarations.
i915_reg.h re-declares some of MCH registers as seen through MCHBAR mirror.
It's not currently used and we don't want any MCH registers in GFX.

Change-Id: I5fa4711fee60d64316696b7ed713013de8759b54
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5318
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 21:22:15 +01:00
Kyösti Mälkki 0567c91b22 console: Use single driver entry for UARTs
UARTs now have unified prototypes and can use a single entry
in the list of drivers for ramstage.

Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5308
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:40:34 +01:00
Kyösti Mälkki ab94bbf072 usbdebug: Move Kconfig under drivers/usb
This menu may become a bit more complicated with addition of
new USB hardware so move it out of console/.

Change-Id: Ieb330675b9227a3e53d093f7c2b5a65e3842dc82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5307
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 15:38:12 +01:00
Kyösti Mälkki 9c479c9a3e SMM: Only have console with DEBUG_SMI
Existing code compiled serial communication and printk() for SMM
even when DEBUG_SMI was not selected.

Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5142
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-04 15:36:27 +01:00
Kyösti Mälkki bea6bf07df uart8250: Move under drivers/uart
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5236
Tested-by: build bot (Jenkins)
2014-03-04 15:34:27 +01:00
Kyösti Mälkki 2b95da01e6 uart8250mem: Unify calls with generic UART
NOTE: UART base for SMM continues to be broken, as it does not use
the address resource allocator has assigned.

Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:28:41 +01:00
Kyösti Mälkki 1d7541feeb console: Fix includes
Do not pull in console hw-specific prototypes everywhere
with console.h as those are not needed for higher levels.

Move prototypes for UARTs next to other consoles.

Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5232
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:26:08 +01:00
Kyösti Mälkki 7e75f20477 pl011 UART: Move under drivers/uart
Currently this is only a minimal stub to get console on qemu-armv7.

Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5162
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:25:15 +01:00
Kyösti Mälkki 919923def3 option: Add arch-agnostic get_option()
We should not have pc80/ includes in console/.

Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5157
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:23:10 +01:00
Kyösti Mälkki 3ee1668ab4 uart8250: Fix and unify baudrate divisor calculation
Divisor is a function of requested baudrate, platform-specific
reference clock and amount of oversampling done on the UART reference.
Calculate this parameter with divisor rounded to nearest integer.

When building without option_table or when there is no entry for
baud_rate, CONFIG_TTYS0_BAUD is used for default baudrate.

For OxPCIe use of 4 MHz for reference was arbitrary giving correct
divisor for 115200 but somewhat inaccurate for lower baudrates.
Actual hardware is 62500000 with 16 times oversampling.

FIXME: Field for baudrate in lb_tables is still incorrect.

Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5229
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:22:08 +01:00
Vladimir Serbinenko 131573056f nehalem: Replace video init.
Old video init just replayed the sequence.
This one actually computes the values.

Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5270
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 00:41:05 +01:00
Vladimir Serbinenko 1b12ef1ac3 drivers/intel/gma: Add EDID retrieving functions.
Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5278
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-04 00:40:50 +01:00
Vladimir Serbinenko db7d04d1b7 qemu: Support textmode gfx init.
Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5283
Tested-by: build bot (Jenkins)
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 23:14:04 +01:00
Chris Douglass f0e025a386 drivers/spi: Sort SPI flash files
Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967
Signed-off-by: Christopher Douglass <cdouglass.orion@gmail.com>
Reviewed-on: http://review.coreboot.org/5260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-28 21:13:47 +01:00
Kyösti Mälkki ea6736a2d0 usbdebug: Unify console API
Struct dbgp_pipe would not be suitable for use with xHCI.
Just use an index, it is easy to setup in Kconfig if our
future debug setup has separate pipes for console
output and debugging/traceings.

Change-Id: Icbbd28f03113b208016f80217ab801d598d443a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-20 23:29:12 +01:00
Kyösti Mälkki 970ad70763 console: Add drivers/uart
Also move UART related Kconfig options from top-level file.

Change-Id: I4e407977cff6f6506f991600c98d6d264676d3f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5230
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-17 20:45:27 +01:00
Idwer Vollering 73a1018ce3 src/drivers/spi: introduce AMIC support
Add support for the AMIC A25L032 flash chip.

Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5252
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-17 10:21:48 +01:00
Kyösti Mälkki 6f6a249a75 usbdebug: Remove EHCI_DEBUG_OFFSET
Read this variable from PCI configuration capabilities list instead.

Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5176
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-16 20:10:54 +01:00
Kyösti Mälkki 8cde852ecf usbdebug: Split to USB host/device
Top-level interface to console over USB mut not require low-level
details of ECHI debug port internals.

Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5197
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-12 21:55:56 +01:00
Kyösti Mälkki cb141bce35 usbdebug: Split PCI EHCI part
There are EHCI compatible host controllers on ARM without PCI bus
architecture. Currently we have not come across one with the debug
capability though.

Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5175
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:34:20 +01:00
Kyösti Mälkki 48e899d2d5 usbdebug: Fix data toggle on receive
USB device end toggles data PID when we ACK'd the zero-length data
packet. As USB host we need to toggle data PID too or the next data
received would get discarded.

Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4775
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:33:45 +01:00
Kyösti Mälkki 0108bf5157 usbdebug: Improve receive speed
Read from USB endpoint_in 8 bytes at a time, the maximum what
EHCI debug port capability has to offer.

Change-Id: I3d012d758a24b24f894e587b301f620933331407
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10 19:33:04 +01:00
Kyösti Mälkki 03731d776c QEMU debugcon: Move under drivers/emulation/qemu
Also prepare this console for use in romstage.

Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5136
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2014-02-06 11:16:26 +01:00
Kyösti Mälkki 207379db12 ne2k: Move under drivers/net
Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5135
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-06 11:14:50 +01:00
Kyösti Mälkki 5148642c56 spkmodem: Move under drivers/pc80
Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5134
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06 11:14:24 +01:00
Kyösti Mälkki e2227a23a7 usbdebug: Move under drivers/usb
Also relocate and split header files, there is some interest
for EHCI debug support without PCI.

Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5129
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06 11:13:57 +01:00
Paul Menzel 25fc8d181f drivers/i2c/at24rf08c/lenovo_serials.c: Remove trailing whitespace
The trailing whitespace breaks the Git commit hook
`util/lint/lint-stable-003-wihitespace`. So remove it.

Change-Id: I70e4ac71529884a9a4fabf2aa9a4ea6e0323b9d4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5092
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-02 12:26:08 +01:00
Vladimir Serbinenko 62adc4c610 lenovo: Handle EEPROM/RFID chip.
EEPROM/RFID chip present in thinkpad should be locked in a way to avoid
any potential RFID access.

Read serial number, UUID and P/N from EEPROM.

This info is stored on AT24RF08 chip acessible through SMBUS.

Change-Id: Ia3e766d90a094f63c8c854cd37e165221ccd8acd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4774
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-01 18:48:16 +01:00
Aaron Durbin 16000c883e spi: Add support for Winbod W25Q64DW
The W25Q64DW spi part is programatically equivalent
to the other W25Q64 parts except it operates at 1.8V.
Just add a new entry with the appropriate ID.

BUG=chrome-os-partner:22292
BRANCH=None
TEST=SPI controller can program the part.

Change-Id: I65b0261223a9fefcb07477a43b6a3edb8228dd03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170011
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5077
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-28 22:24:06 +01:00
Vladimir Serbinenko 63e35f207c pc80/keyboard: Ignore interface test failure.
On Asus A8N-E this test fails but if failure is ignored keyboard works.

Change-Id: Ifeeff2f41537b35bc90a679f956fea830b94292c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4816
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 17:39:42 +01:00
Vladimir Serbinenko e23bd0e3c4 SPI: Add API for programmer-specific flashing.
Change-Id: I7a2f5b9ae74458b5ed6271b1c27842c61546dcd2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4712
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-23 20:42:08 +01:00
Andrew Wu e33d6cac96 keyboard.c: fix coding style with indent
Change-Id: Ie8efa9fb9bdc65bf8015eec197f44c432e87d907
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3986
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-23 20:41:44 +01:00
Alexandru Gagniuc abe9b81e83 xpowers/axp209: Add helper to set voltages from devicetree config
Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4638
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 06:24:54 +01:00
Alexandru Gagniuc 4d3a89d72a xpowers/axp209: Allow voltages to be sepecified in devicetree.cb
This allows system voltages to be specified uniformly, rather than
hardcoding them for each board. This will be used by cubieboard in an
upcoming patch.

Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4637
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:02:12 +01:00
Alexandru Gagniuc 428eeff923 drivers: Add support for X-Powers AXP209 PMU
Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4591
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:01:48 +01:00
Vladimir Serbinenko 066dcec2fe drivers/spi/eon: Add EN25Q64
chip found in X230 if not using hardware sequencing.

Change-Id: I6ded10d35bfdbbe3d54c4170dd7846c7833f5ff7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4616
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12 18:07:02 +01:00
Vladimir Serbinenko 0af61b6c82 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4659
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:02 +01:00
Idwer Vollering d26da9c8f0 Coding style: punctuation cleanup [1/2].
Clean up superfluous line terminators.

Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4562
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-23 02:12:51 +01:00
David Hendricks ea3a463460 max77802: update header
This adds #defines for BUCK2DVS1_1_2625V and BOOSTCTRL_OFF.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I363c73ff4a645da53973767fa4bfa2c120394af6
Reviewed-on: https://gerrit.chromium.org/gerrit/64303
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4426
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:29:42 +01:00
Furquan Shaikh 997be3d2ee Refactor code containing aux calls
Moved a lot of code from i915io.c to intel_dp.c with specific function calls

Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc
Reviewed-on: https://gerrit.chromium.org/gerrit/63950
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:27:03 +01:00
Furquan Shaikh 771c3aca70 Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flags
Depending upon the values decoded from edid, the function decides the appropriate bits to
be set in flags parameter (Important for fastboot to work correctly in kernel)

Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856
Reviewed-on: https://gerrit.chromium.org/gerrit/64265
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4423
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:26:59 +01:00
Furquan Shaikh db3157cfee Add cpu transcoder attribute to intel dp
Also, used this attribute in the calculation of htotal and other registers
Added intel_dp_* functions for m,n registers and dimension register calculations

Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a
Reviewed-on: https://gerrit.chromium.org/gerrit/64001
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4422
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:26:55 +01:00
Furquan Shaikh d0a81f7534 Calculate transcoder flags based on pipe config
Works fine with all three panels with the change of 6 bits per color.

Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e
Reviewed-on: https://gerrit.chromium.org/gerrit/63762
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 13:26:51 +01:00
Aaron Durbin c422002b5f tpm: provide explicit tpm register access
An issue was observed using a specific vendor's TPM in that it
chokes on access to registers that are not explicitly defined in the
PC client specification. The previous driver used generic access
functions for reading and writing registers. However, issues come
to play when reading from the status register. It read it as a 32-bit
value, but that read address 0x1b which is not defined in the spec.

Instead of using generic access functions for the tpm registers
provide explicit ones. To that end provide more high level wrapper
functions to perform the semantic access required.

Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63243
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4388
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:11 +01:00
Aaron Durbin ebad176554 rtd2132: implement full configuration
It has been disseminated that the RTD2132 chip
needs to be fully programmed for settings to take affect.
Most of the settings are note documented very well and
present themselves as magic values. Also, the wait time
for starting the sequence needs to be bumped from 2ms to 60ms.
Lastly, expose all the known settings through devicetree.

Change-Id: I9eeea9c4a13ec20b8ce1c5297e43c4dd793d90e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65857
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:55:54 +01:00
Martin Roth 08637d3c9e Remove PS/2 keyboard initialization on resume from S3
When we go through the resume path, there shouldn't ever be a need to
initialize the PS/2 keyboard.  The OS is going to reinitialize it
anyway, and it just slows the resume.

Verified Code flow in normal boot/S3 resume with print statements.
Verified Keyboard was correctly disabled and flushed by booting
to recovery mode screen while pressing keys on the integrated
keyboard.

Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4396
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:30:07 +01:00
Ronald G. Minnich c0872f26d7 Pit: move parade writes to mainboard.c
What gets written into the parade is highly mainboard-dependent.
So the parade_writes array needs to be there.

Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61486
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:06:52 +01:00
Furquan Shaikh 6b19071ffb FUI: Fill in link_m and link_n values
... based on the EDID detailed timing values for
pixel_clock and link_clock.

Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n
respectively.  Other two undocumented registers 0x6f030 and 0x6f034 correspond
to data_m and data_n respectively.

Calculations are based on the intel_link_compute_m_n from linux kernel.

Currently, the value for 0x6f030 does not come up right with our calculations.
Hence, set to hard-coded value.

Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/4381
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 08:04:10 +01:00
Ronald G. Minnich 45df5962c7 SLIPPY: final changes for FUI
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back
that we need.

There are two new files for slippy annotated with comments about how it needs to evolve.

That said, this code has been tested on 3 different panels. Both dev and non-dev usages work.

physbase initialization to static value removed.

Moved spin calls to intel_dp_*

Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61136
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4370
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:51 +01:00
Duncan Laurie 0cf0d1499a rtd2132: Add driver for Realtek RTD2132 LVDS bridge
This driver allows the mainboard to enable spread spectrum
clocking at 0.5%, 1.0%, and 1.5% with devicetree settings.

Change-Id: I59c61e67aa8e951fd9904ad951deb6d0ba29669e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61894
Reviewed-on: http://review.coreboot.org/4365
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 07:28:17 +01:00
Vladimir Serbinenko dd9945bdc7 qemu/videoinit: Set required fields in fake EDID
x_resolution, y_resolution and bytes_per_line were not inited. Without them
coreboot sweared that screen is 1108630x1142817 and payload tried to draw on
such a big screen.

Change-Id: I0d0277a20c7e1976c27af4a57651ab2be0f9c5d7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4535
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-16 23:57:43 +01:00
Vladimir Serbinenko ad3bd9d5f2 drivers/pc80: Add ACPI description.
AT controller needs an ACPI node, otherwise FreeBSD doesn't detect keyboard
and mouse. Currently each SuperIO adds its own description. This one should
be used in the future instead.

Change-Id: Iaad5ed3846c6d9f467a02a286a1e6f60a3607af5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-14 18:24:53 +01:00
Ronald G. Minnich 01ab2d14be Add kernel-derived support functions for DDI.
Newer mainboards that use haswell -- and, presumably, chipsets to come -- need
some support functions. Add them in the drivers/intel/gma directory.
Currently, this is one file: intel_ddi.c, but more may come.

Compilation of this file is controlled by INTEL_DDI, defined
in the Kconfig as default n and used in the Makefile.inc

Change-Id: I501ee291c0d4589925ed3e478f67106337fcad31
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60612
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4337
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 03:42:55 +01:00
Aaron Durbin 10a070b447 elog: handle ROM_SIZE differences from detected flash size
The elog code calculates flash offsets and their equivalent
addresses in the memory address space. However, it assumes
the detected flash size is entirely mapped into the address
space. This can lead to incorrect calculations. Add code
to allow ROM_SIZE to be less than detected flash size. The
underlying assumption is that the first ROM_SIZE bytes are
programmed into the larger device.

Change-Id: Id848f136515289b40594b7d3762e26e3e55da62f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60501
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4332
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-07 03:27:44 +01:00
Ronald G. Minnich 4623b20e5a Add in the Makefile bits for the new intel gma driver
The Intel GMA driver is in, this CL splices in the Makefile bits.

Change-Id: Icf42a537575b8cc90a679ec1fc15b09294630611
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60346
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4331
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-06 00:33:58 +01:00
Ronald G. Minnich 99451b174a FUI: add intel_dp driver derived from kernel functions
These functions are not all used yet, but do compile and are partially used
in the FUI testing.

They were extracted from the 3.4 kernel using coccinnelle filters. The .c files
are only compiled in if CONFIG_INTEL_DP is set.

Change-Id: Id95622a75aa02b496c9ea4717cb143394a8332e3
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60245
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:24:03 +01:00
Ronald G. Minnich 5bcca7e982 haswell: pull in the init code for FUI
Removed two unnecessary register sets, and did the power well a bit
more correctly. Also, added a register definition include file so we can
used constants instead of magic numbers.

We also set registers to common initialized values that are
needed for FUI, VBIOS, and kernel. This set of registers
appears to be an absolute bare minimum. Since we're hoping to use
FUI for all chipsets from this one forward, we unconditionally do the
setting here.

Signed-off-by: Ronald G. Minnich <rminnich@google.com>

Change-Id: Ife3f661ba010214d92b646b336f2b06645119f17
Reviewed-on: https://gerrit.chromium.org/gerrit/59988
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4328
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-05 20:23:23 +01:00
Gabe Black 0bf1febed8 elog: Get rid of the descriptor type and some unnecessary wrappers
There was always exactly one elog descriptor declared and initialized, but its
contents were being accessed through a pointer that was passed back and forth
between functions instead of being accessed directly. This made the code more
verbose than it needed to be and harder to follow. To address this the
descriptor type was eliminated, its contents were turned into individual
global variables, and various functions were adjusted to no longer take the
descriptor as an argument.

Similarly, the code was more verbose and complicated than it needed to be
because of several wrapper functions which wrapped a single line of code which
called an underlying function with particular arguments and were only used
once. This makes it harder to tell what the code is doing because the call to
the real function you may already be familiar with is obscured behind a
new function you've never seen before. It also adds one more text to the file
as a whole while providing at best a marginal benefit. Those functions were
removed and their callers now call their contents directly.

Built and booted on Link. Ran mosys eventlog list. Cleared the event log
and ran mosys eventlog list again. Added 2000 events and ran mosys eventlog
list. Cleared the log again and ran mosys eventlog list.

Change-Id: I4f5f6b9f4f508548077b7f5a92f4322db99e01ca
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49310
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4245
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:18:06 +01:00
Gabe Black 84a93d1bc3 elog: Stream line the elog driver.
The elog driver's design was a bit more elaborate than it really needed to be
since it no longer had to keep track of multiple copies of the log in flash
and also in memory. This change streamlines it by removing unnecessary
compartmentalization of some bits of code, and some variables which tracked
the last entry added which were never used.

Built and booted on Link. Ran mosys eventlog list. Added 2000 events to
the event log and ran mosys eventlog list again. Cleared the log by echoing 1
into /sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list.

Change-Id: I7d4cdebf2f5b1f6bb1fc70e65eca18f71b124b18
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49309
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4244
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:17:53 +01:00
Gabe Black 455c68ed0d elog: Merge elog_validate_and_fill into elog_init_descriptor.
elog_validate_and_fill was called in exactly one place, in
elog_init_descriptor. It didn't actually do what its name implied since the
data in the event log was already "filled" by elog_init_descriptor. Likewise
elog_init_descriptor was delegating an important part of its own job, scanning
through the list of events, to elog_validate_and_fill.

Since one function was basically just a displaced part of the other which
couldn't really stand on its own, this change merges them together.

Built and booted on Link. Ran mosys eventlog list. Added 2000 events with
the SMI handler and ran mosys eventlog list again.

Change-Id: Ic899eeb18146d0f127d0dded207d37d63cbc716f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49308
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4243
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:17:46 +01:00
Gabe Black 42cb7090c5 elog: Get rid of elog_reinit_descriptor.
This function was just a wrapper around elog_init_descriptor, and all it did
was pass the current backing store location and size back in so it would be
reused. Those values, which never change, are now set in
elog_setup_descriptors, eliminating those parameters to init and eliminating
the need for _reinit_.

Built and booted on Link. Ran mosys eventlog list. Added 2000 events to
the log and ran mosys eventlog list again.

Change-Id: I133768aa798dfc10f32e14db95235a88666890c3
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49307
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4242
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:17:37 +01:00
Gabe Black 331eb084bb elog: Eliminate the second in memory copy of the event log.
The event log driver keeps two copies of the event log in memory, one to
take the place of the historically memory mapped image of flash which is now
read and written manually, and one originally intended to be an in memory
cache of flash. Since both are now just copies in memory, there's no value in
having them both and keeping them in sync.

Built and booted on Link. Ran mosys eventlog list. Added 2000 events to
the log and ran mosys eventlog list again. Cleared the log by echoing a 1 into
/sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list again.

Change-Id: Ibed62a10c78884849726aa15ec795ab2914afc35
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49306
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4241
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:16:44 +01:00
Gabe Black bfae4aa768 Make elog_shrink not depend on having seperate memory/flash descriptors.
The way elog_shrink currently works is that it completely clears the data in
the flash/flash descriptor and then recreates it using the part of the log
it's going to keep as stored in the memory descriptor. That scheme depends on
there being to independent copies of the log.

This change reworks elog_shrink so that it moves the data it wants to keep
within a single descriptor and then propogates it to the other and to flash
intact. This way, when one of the descriptors goes away, all we have to do is
remove the code that would update it.

Built and booted into ChromeOS on Link. Ran mosys eventlog list. Added
2000 events to the log and ran mosys eventlog list again. Echoed a 1 into
/sys/firmware/gsmi/clear_eventlog and ran mosys eventlog list.
BRANCH=None

Change-Id: I50d77a4f00ea3c6b3e0ec8996dab1a3b31580205
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49305
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4240
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:16:31 +01:00
Gabe Black e62e0369d5 elog: Get rid of the staging_header variable.
The header is at the start of the log. There's no reason to either keep a
seperate pointer to it, or to keep a copy of it in some other bit of memory.

Built and booted on Link and used 'mosys eventlog list' to list the
contents of the log. Ran

for x in $(seq 1 2000); do
  cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog;
done

And ran mosys eventlog list again to verify that the log had been shrunk
correctly.

Change-Id: I2afcd52c0ce5bbb662ac56f2895cdbea28d5c2ce
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49304
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4239
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02 15:16:15 +01:00
Gerd Hoffmann 748a6b1068 qemu: minor bochs cleanups
Add a comment, tweak spacing a bit, addr variable
doesn't need to be global any more.

Change-Id: Id8d8a7babce671243351074f7ac52a5c8c264de5
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4274
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-26 09:14:57 +01:00
Alexandru Gagniuc d7134e06b1 pc80/mc146818rtc: Return an error code rather than an integer
Do not return hardcoded numerical values to communicate succes/failure, but
instead use an enumeration.

Change-Id: I742b08796adf136dce5984b702533f91640846dd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4265
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:59:59 +01:00
Stefan Reinauer 86ce7f9273 RTC: Skip rtc_init() in S3 resume path
In addition to not clearing the pending interrupts, we also
don't want to reset the RTC control register when booting
with an S3 resume.

On most new systems, when the RTC well is losing power, we
will also lose state that is required to perform a resume,
so we end up in a normal boot anyways. Hence don't do any
RTC initialization in the S3 resume path.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I73b486082faa741e9dccd15f2b8e3a8399c98f80
Reviewed-on: https://gerrit.chromium.org/gerrit/56826
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4206
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:41:23 +01:00
Duncan Laurie 032be82a11 elog: Check for successful flash erase in elog_shrink
A parrot device with a bad flash part has been seen to hang
in the elog_shrink code becuase the flash was not successfully
erased and it gets stuck in a loop trying to shrink the log
and then add an event.

Change-Id: I8bb13dbadd293f9d892f322e213c9255c8e9acb3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56405
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4186
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:38:04 +01:00
Gabe Black 8f4baece7a elog: Make sure the elog data structures are initialized in elog_clear.
If elog_clear is called before other elog functions, for instance if it's
called through an SMI immediately after the system boots, then the elog data
structures won't have been set up and the system will go off the deep end.
This change adds a call to elog_init to elog_clear to make sure things things
are always initialized before we start using them.

Before this change, this command would cause
the system to lock up if run immediately after boot:

echo 1 > /sys/firmware/gsmi/clear_eventlog

After this change, that results in the log being cleared correctly.

Change-Id: I45027f0dbfa40ca8c581954a93b14b4fedce91ed
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/49303
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4144
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:06:28 +01:00
Vladimir Serbinenko 7905f9254e qemu: cirrus native video init
Recent commit proposal by Ron Minnich proposes to move to native gfx init for
qemu. Unfortunately we didn't have native init for default qemu video (cirrus)
Here is one extracted from GRUB one which I wrote couple of years ago.

Change-Id: Icb89cf918ef5d276bcc703c48c568e7b9c1be756
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4270
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 20:40:58 +01:00
Ronald G. Minnich cae09e0bbe bochs: add support for native graphics
Per our discussions with Gerd, qemu will now always do native graphics
on coreboot. The VGA BIOS capability is not needed and will no longer
be supported. Attempts to build without native graphics will result in
an error.

This code builds for both x86 emulation targets. I'm hitting an issue
testing that is unrelated to coreboot; if someone can test, that
would be helpful. Be sure to start qemu with -vga std.

We also add a test for the PCI BAR being zero and return silently if it
is.

Change-Id: I66188f61e1bac7ad93c989cc10f3e0b55140e148
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4258
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2013-11-25 18:31:25 +01:00
Stefan Reinauer fd4f4136e8 Rename cpu/x86/car.h to arch/early_variables.h
and add an ARMv7 version.

Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
Signed-off-by: Stefan Reinauer <reinauer@google.com>
[km: rebased fa004acf8 from chromium git]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-10-13 12:47:05 +02:00
Kyösti Mälkki ecd8424919 Fix whitespace leaked into tree
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.

Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 21:04:35 +02:00
Kyösti Mälkki 1cf85774da SPI: Support STMicro partial page write
Ported from spi/winbond.c.

Fixes this error:
   ICH SPI: Too much to write.
   Does your SPI chip driver use CONTROLLER_PAGE_LIMIT?

Change-Id: I50db8fd1104d3b7d319b278b14f97e3ff9cb6404
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3877
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-08-23 05:07:11 +02:00
Gabe Black 2ddc9ea0c8 parade: Add a driver for the parade ps8625.
This driver is basically the same as the one in U-Boot but without the device
tree stuff. That driver is, in turn, a straightforward implementation of the
sequence of register writes described in the data sheet. Comments were added
in U-Boot which helpfully describe what the register writes are actually
doing and are kept.

Change-Id: I64ba6b373478853bb2120f0553a43de901170d02
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/3753
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:20:39 +02:00
David Hendricks 90a42d83cf max77802: add header for max77802 PMIC
This adds register offsets and important values for the Maxim
MAX77802 PMIC.

Change-Id: I3724b82bcb235b6684d2b976876f628f1ffbed3f
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3747
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:35:26 +02:00
Martin Roth 5688979fbd drivers: Fix spelling
Change-Id: Ib0d98e3ab5b2943c36f88765587e8963a4f49604
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3754
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:18:15 +02:00
Stefan Reinauer 08dc357146 ARMv7: De-uboot-ify Exynos5250 code
When starting the Exynos5250 port, a lot of unneeded u-boot code
was imported. This is an attempt to get rid of a lot of unneeded
code before the port is used as a basis for further ARM ports.

There is a lot more that can be done, including cleaning up the
5250's Kconfig file.

Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3642
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:15 +02:00
Denis 'GNUtoo' Carikli bc2c9efd56 ELOG: Fix warning to fix the compilation.
Without that fix we have:
  src/drivers/elog/elog.c: In function 'elog_is_header_valid':
  src/drivers/elog/elog.c:213:3: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format]

Change-Id: I71b80a94c03a04eedb688ae107d92c05a878315e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3551
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-28 11:04:44 +02:00
Gerd Hoffmann 414b947851 qemu: complete bochs dispi interface vga driver.
Ditch unused fb*.h files.
Rename init.c (name is _way_ to generic) to bochs.c.
Add proper bochs dispi interface detection and mode setup.
Hook up coreboot framebuffer table initialization.

Change-Id: I7154b1593902e7d42606b64819217872eee10683
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3500
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 02:00:08 +02:00
Aaron Durbin cb997d3710 pc80/tpm: allow for cache-as-ram migration
As the TPM driver can be accessed in romstage after
cache-as-ram is torn down use the cache-as-ram migration
API to dynamically determine the global variable address.

Change-Id: I149d7c130bc3677ed52282095670c07a76c34439
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:29:59 +02:00
Paul Menzel ac75bc682b x86 I/O APIC: Make functions `io_apic_{read,write}()` public
Some LPC initialiation can save some lines of code when being able
to use the functions `io_apic_read()` and `io_apic_write()`.

As these two functions are now public, remove them from the generic
driver as otherwise we get a build errors like the following.

    […]
    Building roda/rk9; i386: ok, using i386-elf-gcc
    Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
      Creating config file... (blobs, ccache) ok;  Compiling image on 4 cpus in parallel .. FAILED after 12s!
    Log excerpt:
    coreboot-builds/roda_rk9/arch/x86/lib/ramstage.o: In function `io_apic_write':
    /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/arch/x86/lib/ioapic.c:32: multiple definition of `io_apic_write'
    coreboot-builds/roda_rk9/drivers/generic/ioapic/ramstage.o:/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/drivers/generic/ioapic/ioapic.c:22: first defined here
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/roda_rk9/generated/coreboot_ram.o] Error 1
    make: *** Waiting for unfinished jobs....
    […]

Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3180
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-07 22:40:10 +02:00
David Hendricks 765ff76d8f [2/2] tps65090: re-factor for coreboot
This does basic re-factoring to fit the driver into coreboot.

Change-Id: Id5f8c12a73ec37ddd545d50b3e8e9b3012657db1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3061
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:34:19 +02:00
David Hendricks 6e877ec63e [1/2] initial import of TI TPS65090
This imports TPS65090 PMIC from u-boot and adds/updates Makefiles
and Kconfig files. The follow-up patch will re-factor the code.

Change-Id: Ic9e43b9665ddf7f55feae8fa17fbf3d2d5f4756d
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3060
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:33:13 +02:00
David Hendricks b959fbb87a exynos5: Re-factor I2C code
This re-factors the Exynos5 I2C code to be simpler and use the
new API, and updates users accordingly.

- i2c_read() and i2c_write() functions updated to take bus number
  as an argument.

- Get rid of the EEPROM_ADDR_OVERFLOW stuff in i2c_read() and
  i2c_write(). If a chip needs special handling we should take care
  of it elsewhere, not in every low-level i2c driver.

- All the confusing bus config functions eliminated. No more
  i2c_set_early_config() or i2c_set_bus() or i2c_get_bus(). All this
  is handled automatically when the caller does a transaction and
  specifies the desired bus number.

- i2c_probe() eliminated. We're not a command-line utility.

- Let the compiler place static variables automatically. We don't need
  any of this fancy manual data placement.

- Remove dead code while we're at it. This stuff was ported early on
  and much of it was left commented out in case we needed it. Some
  also includes nested macros which caused gcc to complain.

- Clean up #includes (no more common.h, woohoo!), replace debug() with
  printk().

Change-Id: I8e1f974ea4c6c7db9f33b77bbc4fb16008ed0d2a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3044
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 00:01:02 +02:00
David Hendricks cfb73607be replace device/i2c.h with simpler version
The existing header was imported along with the Exynos code and left
mostly unchanged. This is the first patch in a series intended to
replace the imported u-boot I2C API with a much simpler and cleaner
interface:

- We only need to expose i2c_read() and i2c_write() in our public API.
  Everything else is board/chip-dependent and should remain hidden
  away.

- i2c_read and i2c_write functions will take bus number as an arg
  and we'll eliminate i2c_get_bus and i2c_set_bus. Those are prone to
  error and end up cluttering the code since the user needs to save
  the old bus number, set the new one, do the read/write, and restore
  the old value (3 added steps to do a simple transaction).

- Stop setting default values for board-specific things like SPD
  and RTC bus numbers (as if we always have an SPD or RTC on I2C).

- Death to all the trivial inline wrappers. And in case there was any
  doubt, we really don't care about the MPC8xx. Though if we did then
  we would not pollute the public API with its idiosyncrasies.

Change-Id: I4410a3c82ed5a6b2e80e3d8c0163464a9ca7c3b0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3043
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-09 23:59:34 +02:00
Stefan Reinauer 24d1d4b472 x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22 00:00:09 +01:00
Paul Menzel a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Paul Menzel a8ae1c66f9 Whitespace: Replace tab character in license text with two spaces
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].

    $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[        ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'

[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt

Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20 23:30:45 +01:00
Dave Frodin 832452a7ea RTC: Use the correct index when setting the default month
Change-Id: I947a8b7ccd6141f164d1e63f7b8f524efa6c00f2
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2442
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-19 00:59:50 +01:00
Zheng Bao 600784e8b9 spi.h: Rename the spi.h to spi-generic.h
Since there are and will be other files in nb/sb folders, we change
the general spi.h to a file name which is not easy to be duplicated.

Change-Id: I6548a81206caa608369be044747bde31e2b08d1a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2309
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-02-11 21:01:47 +01:00
Hung-Te Lin 77608b21d3 armv7/snow: Remove power_init from bootblock.
The power_init is not required on Exynos 5250 (snow) in bootblock stage. To get
a cleaner and faster bootblock, we can remove it.

Note, power_init internally calls max77686 and s3c24x0_i2c, so both files are
also removed.

Verified to boot on armv7/snow.

Change-Id: I5b15dfe5ac7bf4650565fea0afefc94a228ece29
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07 18:15:26 +01:00
Hung-Te Lin 5f83f6cb7a armv7: Clean up arm/snow bootblock build process.
Remove duplicated / testing code and share more driver for bootblock, romstage
and ramstage.

The __PRE_RAM__ is now also defined in bootblock build stage, since bootblock is
executed before RAM is initialized.

Change-Id: I4f5469b1545631eee1cf9f2f5df93cbe3a58268b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2282
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-07 06:10:09 +01:00
Hung-Te Lin 6fe0cab205 Extend CBFS to support arbitrary ROM source media.
Summary:
	Isolate CBFS underlying I/O to board/arch-specific implementations as
	"media stream", to allow loading and booting romstage on non-x86.

	CBFS functions now all take a new "media source" parameter; use
	CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
	API Changes:
		cbfs_find => cbfs_get_file.
		cbfs_find_file => cbfs_get_file_content.
		cbfs_get_file => cbfs_get_file_content with correct type.

CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
the ROM may come from USB, UART, or SPI -- any serial devices and not available
for memory mapping.

To support these devices (and allowing CBFS to read from multiple source
at the same time), CBFS operations are now virtual-ized into "cbfs_media".  To
simplify porting existing code, every media source must support both "reading
into pre-allocated memory (read)" and "read and return an allocated buffer
(map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
provides simple memory mapping simulation.

Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
is defined for CBFS functions to automatically initialize a per-board default
media (CBFS will internally calls init_default_cbfs_media).  Also revised CBFS
function names relying on memory mapped backend (ex, "cbfs_find" => actually
loads files). Now we only have two getters:
	struct cbfs_file *entry = cbfs_get_file(media, name);
	void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);

Test results:
 - Verified to work on x86/qemu.
 - Compiles on ARM, and follow up commit will provide working SPI driver.

Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:58:32 +01:00
David Hendricks 4868a1179d snow: add max77686 driver in romstage and ramstage
Change-Id: Id3e20b1ab5d85cfd22e2dae2750f32007b7f8f74
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2123
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 05:57:06 +01:00
David Hendricks 1d5390ecc8 size optimizations for max77686
This contains some size optimizations for the Maxim MAX77686 driver:
- change max77686_para.vol_{min,div} from u32 to u16 (currently their
  max value is 50000 so it should be fine)
- remove max77686_para.regnum which takes 4 bytes for each and is not
  used

(Patch was originally written by Hung-Te Lin, I'm just uploading it)

Change-Id: I24044427c49467e99380d1f60ebc59e69c285b22
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2124
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-10 05:54:53 +01:00
David Hendricks e293440faa corrections for MAX77686 config variable
Fix some minor discrepancies which prevented the MAX77676 from
getting compiled in properly.

Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2076
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-29 15:33:53 +01:00
Martin Roth 3316cf2ff8 Claim the SPI bus before writes if the IMC ROM is present
The SB800 and Hudson now support adding the IMC ROM which runs from the same
chip as coreboot.  When the IMC is running, write or erase commands sent to
the spi bus will fail, and the IMC will die.  To fix this, we send a request
to the IMC to stop fetching from the SPI rom while we write to it. This
process (in one form or another) is required for writes to the SPI bus while
the IMC is running.

Because the IMC can take up to 500ms to respond every time we claim the
bus, this patch tries to keep the number of times we need to do that to a
minimum.  We only need to claim the bus on writes, and using a counter for
the semaphore allows us to call in once to claim the bus at the beginning
of a number of transactions and it will stay claimed until we release it
at the end of the transactions.

Claim() - takes up to 500ms hit
    claim() - no delay
        erase()
    release()
    claim() - no delay
        write()
    release()
Release()

Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-12-12 22:34:16 +01:00
Stefan Reinauer 0cc9f41f46 Fix maxim max77686 driver
With driver-y going away, the current driver code didn't get
compiled in with upstream.

Change-Id: I9bff45a35c995888a482bdc22a1573f6bfb88211
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2027
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-12 06:03:26 +01:00
Stefan Reinauer de48f0fd42 Fix up Maxim MAX77686 driver
... to fit into the naming convention

Change-Id: I4a7d81c4d6674d001fc831df863bd2343f6c636f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2020
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-12-12 00:27:04 +01:00
Marc Jones 747127d505 Limit SPI device debug prints with CONFIG_DEBUG_SPI_FLASH
Fix debug printks which were not using CONFIG_DEBUG_SPI_FLASH,
which would cause long delays durring boot when SPI devices
were written.

Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 06:47:28 +01:00
Zheng Bao c269a9b51c driver/spi: Add support of MX25L3235D
Tested on Thatcher.

Change-Id: I648171ba0d03be1e984c182f6d0f082241e3f51c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1971
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-06 06:17:52 +01:00
Stefan Reinauer 3d6eb29099 Only compile PC80 drivers when CONFIG_PC80_SYSTEM is set
Change-Id: Iac2f3ebf68c9c1df296fc81d10ee97053a9d5469
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1956
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30 21:33:18 +01:00
Patrick Georgi 7f934f5ee0 build system: Treat cmos.default as text file
It's a more easily maintainable format than a 128 byte binary blob

Change-Id: Ic9b9f53cd025b5f89a21971930fabf6592f95d67
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1867
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-30 21:24:57 +01:00
Ronald G. Minnich f2e13b0b19 Add the maxim MAX77686 power controller.
Create a new directory in drivers for power controllers.
Add the MAXIM MAX77686 power control support.

Accessing this controller requires I2C support.
Note that this will not build until the I2C usage is changed for
coreboot. I'm putting it in mainly because we need it soon
and I want to see if the new directory is acceptable.

Change-Id: I6c2a6d2165f33b41d2c8e4813222b21d2385e879
Signed-off-by: David Hendricks <dhendrix@chromium.org>
SIgned-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1938
Tested-by: build bot (Jenkins)
2012-11-29 21:37:08 +01:00
Patrick Georgi 23f38cd05c Get rid of drivers class
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.

These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.

With ramstage.a gone, we can drop this special class, too.

Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 22:00:49 +01:00
Zheng Bao b8117b0622 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
For SST chips, the Write-Status-Register instruction must be
executed immediately after the execution of the
Enable-Write-Status-Register instruction, instead of Write-Enable.

Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-27 11:03:52 +01:00
Stefan Reinauer 95a6396ae3 Clean up Kconfig
- move VGA handling options into devices/Kconfig
- make Devices a top level menu
- move some  options "closer" to the code they control

Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1840
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16 01:13:47 +01:00
Stefan Reinauer 8483344802 Drop Kconfig.deprecated_options
Both remaining options, DRIVERS_PS2_KEYBOARD and ID_SECTION_OFFSET
are not likely to go away any time soon, so let's not keep them
in Kconfig.deprecated_options but move them close to the code they
control.

Change-Id: I310b877c5b3d5a3444056641c4aee07a48c4c4be
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1839
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-16 01:13:40 +01:00
Stefan Reinauer feadfb7776 If cmos is invalid, always set the rtc date and time
If cmos is invalid for any reason, always set the date and time
before marking RTC valid.

Change-Id: Ib9d154802f75221d58bf28ba9c813f2529904596
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1790
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:12:14 +01:00
Marc Jones dd76bc0e01 Remove duplicate defines from mc146818rtc.c
Remove the duplicate #defines and use what is set in mc146818rtc.h.

Change-Id: Ic471e03c68b591d19c0646fdbea78374af11c8b8
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1789
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:12:03 +01:00
Duncan Laurie 215f278563 ELOG: Support for non-memory mapped flash
If the event log is stored in flash that is not memory
mapped then it must use the SPI controller to read from
the flash device instead of relying on memory accesses.

In addition a new CBMEM ID is added to keep an resident
copy of the ELOG around if needed.  The use of CBMEM for
this is guarded by a new CONFIG_ELOG_CBMEM config option.
This CBMEM buffer is created and filled late in the process
when the SMBIOS table is being created because CBMEM is
not functional when ELOG is first initialized.

The downside to using CBMEM is that events added via the
SMI handler at runtime are not reflected in the CBMEM copy
because I don't want to let the SMM handler write to memory
outside the TSEG region.

In reality the only time we add runtime events is at kernel
shutdown so the impact is limited.

Test:
1) Test with CONFIG_ELOG_CBMEM enabled to ensure the event
log is operational and SMBIOS points to address in CBMEM.
The test should involve at least on reboot to ensure that the
kernel is able to write events as well.

> mosys -l smbios info log | grep ^address
address              | 0xacedd000

> mosys eventlog list
0 | 2012-10-10 14:02:46 | Log area cleared | 4096
1 | 2012-10-10 14:02:46 | System boot | 478
2 | 2012-10-10 14:02:46 | System Reset
3 | 2012-10-10 14:03:33 | Kernel Event | Clean Shutdown
4 | 2012-10-10 14:03:34 | System boot | 479
5 | 2012-10-10 14:03:34 | System Reset

2) Test with CONFIG_ELOG_CBMEM disabled to ensure the event
log is operational and SMBIOS points to memory mapped flash.
The test should involve at least on reboot to ensure that the
kernel is able to write events as well.

> mosys -l smbios info log | grep ^address
address              | 0xffbf0000

> mosys eventlog list
0 | 2012-10-10 14:33:17 | Log area cleared | 4096
1 | 2012-10-10 14:33:18 | System boot | 480
2 | 2012-10-10 14:33:18 | System Reset
3 | 2012-10-10 14:33:35 | Kernel Event | Clean Shutdown
4 | 2012-10-10 14:33:36 | System boot | 481
5 | 2012-10-10 14:33:36 | System Reset

Change-Id: I87755d5291ce209c1e647792227c433dc966615d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1776
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:09:39 +01:00
Duncan Laurie 23b0053586 SPI: Fix and enable Fast Read support
- Fix handling of 5-byte Fast Read command in the ICH SPI
driver.  This fix is ported from the U-boot driver.
- Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by
defining a name for the bool in Kconfig and removing the
forced select in southbridge config
- Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers
to use #if instead of #ifdef
- Relocate flash functions in SMM so they are usable.
This really only needs to happen for read function pointer
since it uses a global function rather than a static one from
the chip, but it is good to ensure the rest are set up
correctly as well.

Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1775
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-12 17:09:21 +01:00
Martin Roth bceaf7fea0 Add Gigadevice SPI rom support
Add support for GigaDevice SPI ROMS.
The GD25Q64B device has been tested, the other rom devices added to the
file have not.

Change-Id: If35676ca6b90329f15667ebb32efa0d1a159ae91
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1747
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-09 19:03:35 +01:00