Commit Graph

1796 Commits

Author SHA1 Message Date
Timothy Pearson 620fa5f30f northbridge/amd/amdfam10: Collect DIMM information for ramstage use
1.) Allow MCT information structures to be copied to cbmem.
2.) Retrieve DIMM vendor, model, and serial information.
3.) Allow maximum installable memory to be set via devicetree.

Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9137
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-01 21:14:30 +02:00
Timothy Pearson d5c82afa37 northbridge/amd/amdmct: Pack MCT and DCT info structs
This allows safe access of romstage MCT values from ramstage

Change-Id: I229b19a64f7f148f970ec86dde7f4b6a62469064
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9158
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-01 21:14:08 +02:00
Martin Roth 72a8e5e751 Update hex values to CBFS binary name types in Makefiles
These binaries were being added to CBFS using hexadecimal values instead
of the CBFS binary type names.  The same value was being used in
different places for different things.
For example, the value 0xAB is used for SPDs, MRC & FSP binaries.

This patch uses CBFS type names instead of hex values everywhere a
hex value was previously used.

Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 21:47:15 +02:00
Patrick Georgi ea9f308018 build system: normalize linker script file names
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-28 19:14:47 +01:00
Timothy Pearson b337c1d1f5 northbridge/amd/amdfam10: Properly implement SLIT generation
Change-Id: I973abf2224762bf7a53d71177544ade15db50cba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8856
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-03-27 17:07:06 +01:00
Timothy Pearson 86f4ca5b4b cpu/amd/model_10xxx: Add support for early cbmem
mainboards/amd/fam10: Initialize cbmem area after raminit

When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
When GFXUMA is disabled, CBMEM is placed at TOM
This matches the behaviour present before conversion to early
CBMEM.

The CBMEM location code implicitly assumes TOM does not change
between romstage and ramstage.  TOM is set by romstage raminit,
and is never changed by romstage or ramstage afterward.  As
the CBMEM location is positioned at a specific offset from TOM
that is known to both romstage and ramstage early CBMEM is safe
on Fam10h systems.

TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
tables from romstage and cbmem log tables from ramstage.

Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8489
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19 08:28:43 +01:00
Timothy Pearson e9424c593a northbridge/amd/amdfam10: Unify CBMEM location across UMA and non-UMA
The CBMEM memory segment is always placed at TOM - UMASIZE when GFXUMA
is enabled, however when GFXUMA is disabled an attempt was made to locate
the CBMEM memory segment above the I/O hole in certain rare cases.

Removing this special case does not impact functionality, and paves
the way for early CBMEM support.

Change-Id: I98d29ab9d601a4e20f58e2cd0a66abb13b494e74
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-03-19 05:00:25 +01:00
Aaron Durbin 9ef9d85976 bootstate: use structure pointers for scheduling callbacks
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.

In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.

Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-18 16:41:43 +01:00
Timothy Pearson 4916880511 cpu/amd/model_10xxx: Move GFXUMA size calculation to separate function
This is required for early CBMEM support.

Change-Id: I31d9b6a04ef963a7d3e045d9c5201ae64604218a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8663
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-17 04:33:06 +01:00
Dave Frodin 84c72dedab northbridge/amd/pi: Create common agesawrapper.c
This removes the mainboard agesawrapper.c file from binarypi
based boards and creates a common one.

Change-Id: I900dba914f1c401e4ac732eb93d94b98216e629a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16 21:46:17 +01:00
Dave Frodin 4b45dd3253 cpu/amd/pi: Add amd_initcpuio() and amd_initmmio()
This makes the change to the cpu/amd/pi/00730F01 that was
made for the cpu/amd/agesa based boards in:
    commit 48518f0d
    AGESA: Add amd_initcpuio() and amd_initmmio()
    These are not wrappers for AGESA as they do not enter vendorcode at all.
    We expect most of the added fixme.c file to be written without use of AMDLIB.h
    and parts relocated as northbridge enable_resources().

The equivalent change has already been made for cpu/amd/pi/00630F01.

Change-Id: I591b50ee807436f5a1dee14d2c88a77462024744
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8670
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-16 21:45:49 +01:00
Francis Rowe 71512b2cf6 northbridge/i945/gma: fix build error with native graphics init
Tested on an X60, Native graphics init still works perfectly.

Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8696
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-03-16 06:46:48 +01:00
Timothy Pearson b812d5d92f northbridge/amd/amdht/h3finit.c: Fix boot failure
GIT hash 586d6e introduced a regression that causes boot failure
with an f0011449 AMD stop code.

Change-Id: Ieced9088b79bc89d55117b7240b82a086eff9d21
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8685
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-15 02:45:50 +01:00
Timothy Pearson 586d6e2a88 northbridge/amd/amdht: Allow mainboards to set HT frequency limit
This is useful when the PCB layout of a mainboard does not allow
stable operation at the increased HyperTransport speeds of newer
processors.

Change-Id: Idc93a1294608178ddf38ca72d40e6bad7deb9004
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8464
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-13 21:17:58 +01:00
Alexander Couzens b7b83719bf northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP
This capability means:
FERR messages are sent out on system detected an
unmasked floating point x87 FPU error.

Even though this capability is supported on nehalem it doesn't
make sense to set it in early stage. This MSR
has a core scope which results in an unsync MSR because
it's not set on other cores than the BSP.

Found-by: BITS
Tested-on: lenovo thinkpad x201t

Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13 14:51:42 +01:00
Kyösti Mälkki 9e94dbfcd0 ACPI: Get S3 resume state from romstage_handoff
There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.

Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-10 23:42:10 +01:00
Dave Frodin 180a11427d northbridge/amd/pi: Remove superfluous logic operand
Commit 2e0cf14 corrected this for pi/00730F01/northbridge.c.
This commit fixes it for pi/00630F01/northbridge.c.

Found-by: Clang

Change-Id: I4eb93a07aacf6ffc5a159222117e7c934d85859e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8289
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-10 16:44:23 +01:00
Bruce Griffith 006364eedd AMD Bald Eagle: Add northbridge files for new AMD processor
Also fix a typo in a config option for SteppeEagle.

Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7247
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-10 16:43:23 +01:00
Kyösti Mälkki bf62b2ddb0 AMD fam10: Drop PCI_BUS_SEGN_BITS
All boards in tree use 0.  Looks like this is all work that was
never completed and tested.

We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.

Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.

Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 19:33:08 +01:00
Kyösti Mälkki 991a71d55c AMD fam10: Fix include of conf.c
Change-Id: I982acb0b36f2cef8281ffbac4511f831f08fc89a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8553
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-09 19:32:54 +01:00
Kyösti Mälkki bd29530061 AMD fam10: Remove __PRE_RAM__ from ramstage-only code
Change-Id: I41aba81def13c99671eb609dd1e76a9a45299622
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8552
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 06:00:41 +01:00
Kyösti Mälkki 5ef269b5a3 AMD fam10: Always have AMDMCT
Also drop some more #if UNUSED_CODE.

Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8551
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 06:00:07 +01:00
Kyösti Mälkki c0ee937e92 AMD K8: Fix allocation size for HyperTransport links
There is no requirement that in dev->link_list the last element
would have the highest link->link_num.

Also fix off-by-one error when allocating for more links.

Change-Id: Id8a7db3ffb4111eb31e70ea14fd522b70368dd8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8550
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 05:59:47 +01:00
Kyösti Mälkki 11c79d7fc2 AMD K8: Move the test for connected HyperTransport link
Change-Id: I7f8cbfcae7ec2a49e91ceda1eecdcf76b2137d8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8549
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-09 05:59:28 +01:00
Timothy Pearson b6fa61a121 northbridge/amd/amdmct: Fix burst write depth on K10 rev. D and later
The BKDG for K10 revision D and later processors recommends a smaller
MCT burst write queue depth when using unganged memory.

TEST: Booted ASUS KFSN4-DRE with both Opteron 8356 and Opteron 2431
processors.

Change-Id: I36718d4972c9d2d0bdd3274191503b5fcd803f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-03-07 22:50:07 +01:00
Kyösti Mälkki 982473536b AGESA: Move agesawrappers related to HAVE_ACPI_RESUME support
This change brings all agesawrappers in a single file to make it
easier to understand the actual execution flow.

Change-Id: Ifbb2b16e4cccfaa17aaf10887a856797be9b6877
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8605
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:23:13 +01:00
Kyösti Mälkki 82fbda76c9 AGESA: Use same HeapManager for all BiosCallOuts
We do not allow platforms to mess around with memory layout.

Change-Id: I316ff522c8833fa3b7ad20f2c5a9cae21f4174d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-07 21:22:44 +01:00
Timothy Pearson ead8751367 cpu/amd/model_10xxx: Refactor model detection to reduce code duplication
Moved mctGetLogicalCPUID() to a separate file and made it available in
both romstage and ramstage.

Change-Id: I959c1caa8f796947b627a7b379c37d7307e2898e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-04 06:15:55 +01:00
Timothy Pearson 226fc941af northbridge/amd/amdmct: Add revision D to K10 revision mask list
Change-Id: Ib5f87bdc50c0bca370a636218d3b5d4cc9157c12
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8501
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-03-03 06:36:14 +01:00
Kyösti Mälkki 280a29d5bb devicetree: Drop redundant scan_bus() ops
Change-Id: If96e0843f507b9f1db9977b5d0c47f5ed1c59999
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8533
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:55:22 +01:00
Kyösti Mälkki 976d91c07e AGESA fam16: Drop HyperTransport scan
Already done for fam15tn/rl.

Change-Id: Id74ca13610a4ef407c866a4419139287413078a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-01 21:48:11 +01:00
Kyösti Mälkki c5163ed83b AMD binaryPI: Drop HT3_SUPPORT
Kconfig variable is not implemented.

Also fix broken abuild.

Change-Id: I569f44e97abc570158472ddbd0f890315233f8a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8494
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-02-20 07:56:09 +01:00
Kyösti Mälkki 7255062ea7 AMD fam10: Refactor variables in scan_chain
We only need one of devx and dev. This function should be called
with dev already adjusted if link_num > 3.

Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8351
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:06:12 +01:00
Kyösti Mälkki e40beb1f79 AMD fam10: Move the test for connected HyperTransport link
Change-Id: I9a24f9897115ce37ee11ca41c8b74142c95fc534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8350
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:05:38 +01:00
Kyösti Mälkki 26c664759b AMD K8 fam10: Refactor offset_unitid configuration
Change-Id: I198f2ad321e1a8b6d932f5624b129e312e36a309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8349
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:04:00 +01:00
Kyösti Mälkki f5e7fa22e7 AMD amdfam10: Always have HT3_SUPPORT
Change-Id: I6ce784fd9e7a6876a37c910c503fafa3a17bf96f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:43 +01:00
Kyösti Mälkki 260a6db7ec AMD K8 fam10: Drop link_num from scan_chain parameters
Change-Id: Id8fc1d7d8a23238e6848cd2cf4270d782e90a7d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8347
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:25 +01:00
Kyösti Mälkki fe57eeb5bf AMD K8 fam10: Remove some excessive preprocessor use
Change-Id: Iee51c51b662d1f5e3d918d1e5b961f06c6b99df6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8346
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-20 07:03:12 +01:00
Vladimir Serbinenko d15bddab57 sandybridge: Try lower frequency if PLL didn't lock.
Change-Id: I2c2d586fc572b78b5019f8ef2714959799a8d2a9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8480
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-19 00:21:31 +01:00
Dave Frodin 891f71a541 amd/00730F01: Move SteppeEagle specific settings to northbridge
These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.

Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-18 18:55:56 +01:00
Alexandru Gagniuc 8b2c8f1c10 sandybridge/raminit: Get max mem clock from devicetree
Note that the limit is not set in the devicetree.cb which use native
sandybridge raminit, as it is not needed. When that isn't set, it's
automatically set to zero, and when we find that, we automatically
return the default limit. Thus behavior isn't changed for any board.

Change-Id: I447399eea71355612b654710a56f3a0077c2f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8476
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17 17:38:50 +01:00
Alexandru Gagniuc fe951d899d sandybridge/raminit: Do not die() if timC calibration fails
We can successfully bring up systems if timC calibration fails, as has
been demonstrated with google/butterfly. As a result, do not die(),
but simply print a message and continue in the hope that we may be
able to boot.

Change-Id: I49ec80324f63b2d45ae8f61c5c26454acb9c232f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8475
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-17 17:37:37 +01:00
Timothy Pearson 03259a8794 northbridge/amd/amdht: Get maximum HT link frequency from NVRAM
This patch allows the user to set a maximum HT link frequency in
NVRAM, paralleling a similar option available in the proprietary
BIOS on some mainboards.

Change-Id: Iba3789262eefa52421e76533cbf14d9da2ef1de8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8462
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 21:04:55 +01:00
Timothy Pearson 033bb4bc8d acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9.  The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.

The modified code will function with up to 99 cores.

Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16 21:02:30 +01:00
Timothy Pearson 4f731f2eab northbridge/amd/amdfam10: Remove HT link frequency from Kconfig menu
Change-Id: I48d2cda330d8e8f1e58bc670e4e898479216e576
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8461
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 20:35:19 +01:00
Timothy Pearson 2b1bcc1253 northbridge/amd/amdfam10: Remove Kconfig memory controller options
All settable memory controller options are now controlled by NVRAM,
making the Kconfig options irrelevant.

Change-Id: I9b2c8798d830e5c41bb9a108514e60d784d2ebc5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:11:32 +01:00
Timothy Pearson 3c206781f2 northbridge/amd/amdfam10: Fold back memory frequency based on MCT load
K10 processors cannot operate at full memory speeds when more than a
certain number of DIMMs are installed on a specific channel.  The
allowed DIMM numbers and speeds are listed in the BKDG; this patch
implements the appropriate frequency reduction to ensure stability.

Change-Id: I8ac5b508915e423d262ad36c49de1fe696df2ecd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 09:08:12 +01:00
Timothy Pearson 2012b8127b northbridge/amd/amdmct: Fix FTBFS with node interleaving enabled
This fixes errors of the form:
error: 'Dct0MemSize' may be used uninitialized in this function

Change-Id: Ifc853aea9050994f5641c57a081aa0667331c995
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8455
Tested-by: build bot (Jenkins)
2015-02-15 19:27:35 +01:00
Timothy Pearson 068ca9c8fc northbridge/amd/amdmct: Allow override of memory settings via NVRAM
This patch allows the following memory controller settings to be overridden in NVRAM:
Memory frequency limit
ECC enable
ECC scrub rate

Change-Id: Ibfde3d888b0f81a29a14af2d142171510b87655e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8438
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-15 17:54:35 +01:00
Kevin Paul Herbert bde6d309df x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
2015-02-15 08:50:22 +01:00
Kyösti Mälkki 2a2d6135a4 AGESA fam15tn fam15rl fam16kb: Drop HT3_SUPPORT
Kconfig variable is not implemented.

Change-Id: I546a1001847e7b1002f96baf49ed3301852a6894
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8345
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:48:42 +01:00
Kyösti Mälkki 225da645ad AGESA fam10 fam12 fam15: Always have HT3_SUPPORT
Keep the slower HyperTransport configuration for a possible reference
in fam15 boards.

Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8344
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-14 21:48:05 +01:00
Timothy Pearson b32bf54c31 northbridge/amd/amdfam10: Move K10 specific menu to proper Kconfig file
Change-Id: Ib83ec5c397fdef5aa9e3376f1c0072cfa2f74fa6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8425
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-13 09:30:15 +01:00
Stefan Reinauer 1e9336e89c Fix source code permissions
Two source files were accidently marked executable. Switch them back to
mode 644 (rw-r---r--)

Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9
Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8426
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-13 01:48:23 +01:00
York Yang 114baa0a0a intel/fsp_rangeley: Indent '#define' consistently
The indentations of #define are not consistent in chip.h. Update to make 
all #define indentations being aligned and put them after the variable 
declaration.

Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8333
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2015-02-06 00:58:50 +01:00
Martin Roth 582b2aee0f FSP & CBMEM: Fix broken cbmem CAR transition.
1) Save the pointer to the FSP HOB list to low memory at address 0x614.

This is the same location as CBMEM_RESUME_BACKUP - the two aren't used
in the same platform, so overlapping should be OK.  I didn't see any
documentation that actually said that this location was free to use, and
didn't need to be restored after use in S3 resume, but it looks like
the DOS boot vector gets loaded juat above this location, so it SHOULD
be ok.  The alternative is to copy the memory out and store it in cbmem
until we're ready to restore it.

2) When a request for the pointer to a CAR variable comes in, pass back
the location inside the FSP hob structure.

3) Skip the memcopy of the CAR Data.   The CAR variables do not
get transitioned back into cbmem, but used out of the HOB structure.

4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.

Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8196
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-06 00:53:13 +01:00
York Yang e1e11e63af intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
by UPD input. Update UPD_DATA_REGION structure for matching up this
FSP change.

PcdCustomerRevision is a debugging aid that will be output to debug
message in FSP. When needed, it can be customized by BCT tool for tracking
BCT configurations.

Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-01-31 23:09:26 +01:00
Timothy Pearson a6f669e183 amd/amdfam10: Allocate the lower DRAM region up to TOM
This fixes the resource allocator locating the PCI register
space below 0xe0000000 thereby causing corruption with more
than ~3.5GB physical RAM on AMD Family 10h systems.

Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8261
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 22:11:48 +01:00
Timothy Pearson 82982a130c amd/amdfam10: Enhance resource debugging when enabled
Change-Id: Ie39652bded9a42d1d816ca5198db59a83e5c083a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8266
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-01-28 04:40:39 +01:00
Timothy Pearson c139c42f3f northbridge/amd/amdht: Initialize variable `currentBUID`
Fix uninitialized variable when manual non-coherent BUID
selection is used.

Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8267
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 01:03:44 +01:00
Timothy Pearson 8d9492e536 amd/amdfam10: Serialize mutable ASL methods
Fix three IASL warnings in ASL utility code by making the
methods `GWBM`, `GWEM` and `GIOR` serialized.

TEST: Built and booted on ASUS KFSN4-DRE.

Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8264
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 00:53:35 +01:00
Timothy Pearson e538daeaec amd/amdfam10/northbridge.c: Fix FTBFS with CONFIG_PCI_64BIT_PREF_MEM
Remove declaration of unused variable `io`.

Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8265
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-27 23:33:34 +01:00
Kyösti Mälkki ae98e83eb2 CBMEM: Always use DYNAMIC_CBMEM
Drop the implementation of statically allocated high memory
region for CBMEM. There is no longer the need to explicitly
select DYNAMIC_CBMEM, it is the only remaining choice.

Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:54:32 +01:00
Kyösti Mälkki f1e3c763b3 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.

TODO: Check TSEG alignment, it used for MTRR programming.

Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:48:06 +01:00
Kyösti Mälkki 3bf3854847 CBMEM: Tag chipsets with LATE_CBMEM_INIT
In preparation to remove the static CBMEM allocator, tag the chipsets
that still do not implement get_top_of_ram() for romstage.

LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE.

Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7850
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2015-01-27 22:47:00 +01:00
Kyösti Mälkki 05369de639 intel: Drop romstage handoff via scratchpad
If HAVE_ACPI_RESUME ever gets implemented, use CBMEM handoff instead.

Change-Id: I77463988fa5324c729579902f4796be4da15d551
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8182
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-01-27 22:10:48 +01:00
Dave Frodin bd1d1580d3 northbridge/amd/pi: Correct the path to an #include
Change-Id: Ibf0bd494b2022272cb2d5c4ddb1bdf82ea70ca50
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8250
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-27 15:05:22 +01:00
Timothy Pearson 88d213a63b amd/amdht: Compile in multiprocessor support when selected
Fix multiprocessor support not being compiled in when selected
via Kconfig on AMD systems.

Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8268
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-27 08:04:26 +01:00
Timothy Pearson 367fe8cac1 ACPI: Fix corrupt SSDT table on multiprocessor AMD Family 10h systems
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Change-Id: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9
Reviewed-on: http://review.coreboot.org/8259
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-27 06:23:04 +01:00
Timothy Pearson 5ec1153200 northbridge/amd: Add Kconfig options for ECC redirection
Change-Id: I83e7605650b13e82a2e6c2822cbd237b4e473b5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8271
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-25 20:32:22 +01:00
Timothy Pearson 6f2caa0ffa northbridge/amd: Add Kconfig options for ECC scrub rate
Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8263
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-25 20:31:55 +01:00
Edward O'Callaghan b4d176bb71 northbridge/via/vx800/lpc.c: Remove unused variables
Change-Id: I1f94171173d0b3d672aebeb0dd901dd292028711
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8199
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-01-14 05:05:39 +01:00
Kyösti Mälkki 78c5d584a0 ACPI: Add acpi_is_wakeup_s3() for romstage
This replaces acpi_is_wakeup_early().

Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8187
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-10 13:53:51 +01:00
Kyösti Mälkki 2fcf6f1caf haswell: Fix MRC cache to use CBFS
Place the mrc.cache file at top of CBFS. There is no real requirement
for it to have a fixed location though.

Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-10 09:19:40 +01:00
Kyösti Mälkki 0b5b541373 AMD binaryPI 00730F01: Switch to per-device ACPI
Change-Id: Iad31ae3e511c8ebacc973b2d8a8e3bfca719ee7c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7583
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-09 11:02:01 +01:00
Edward O'Callaghan 6d28b91d38 amd/agesa/family12/northbridge.c: Indent (tab) fix
Trivial; Use tab over space for indent.

Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8015
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 10:41:21 +01:00
Edward O'Callaghan 5e06850c0f northbridge/intel/nehalem/raminit.c: Remove redundant function
Remove 'read_mchbar8_bypass()' as 'read_mchbar8()' does the same
thing and 'read_mchbar8_bypass()' is unused.

Change-Id: I0dc2325e6205c38b63e5200c408ece65e4f938dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8166
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-09 05:35:11 +01:00
Martin Roth 543888d582 northbridg/via/vx900: Doxygen fixes
- @todo has to be lowercase for doxygen
- Fix some parameters that had changed in the code.
- The @file entries needed to be more specific.

Change-Id: Icdce08735f581609cd25cce41e986c71435368a4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8154
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-08 21:59:42 +01:00
Martin Roth f4cb4128ad northbridge/amd: Doxygen fixes
- Add missing parameter names in several files
- remove parameter types in several files
- remove lines from doxygen documentation.  These should be outside the
doxygen comments.
- Some of the comments shouldn't have been doxygen style.  Turn these
into regular non-doxygen comments.

Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8153
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-08 21:58:45 +01:00
Edward O'Callaghan 9739846469 northbridge/amd/agesa/family1{4,5}: Remove cruft from dimmSpd.c
Remove useless comment pretaining to abusing pragma's for old
GCC/GDB interaction issues.

Change-Id: Ic83a0285ac947a23699a81a82b89de08a47ab052
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8017
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-01-07 11:31:27 +01:00
Stefan Reinauer 65b72ab55d northbridge: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.

Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2015-01-06 20:15:02 +01:00
Kyösti Mälkki 9b29aad526 Revert "Re-factor 'to_flash_offset()' into 'spi_flash.h'"
This reverts commit 9270553fff.

Change-Id: I195f721ce7a18aac6c1aa6f4e0f9284455d531b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8138
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-01-06 11:19:28 +01:00
Edward O'Callaghan 9270553fff Re-factor 'to_flash_offset()' into 'spi_flash.h'
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by
Clang complaining that the function 'to_flash_offset' is unused.

Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-06 04:56:14 +01:00
Edward O'Callaghan 089a510292 northbridge/intel: Do not define include guard as 1
As `#ifndef` and not `#if` is used in the check for
include guards, setting it to 1 is not needed.

Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8103
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-01-06 04:17:47 +01:00
Edward O'Callaghan c800199007 northbridge/via/vx800/examples: Remove rotting source
This is just bit-rotting and its likely this will continue to rot
by the time someone notices it exits it will be too late (i.e., today).

Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8087
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-05 16:03:47 +01:00
Martin Roth 6e22225d60 remove vx900_int16 doxygen module/group
This doxygen directive was creating a top level modules section, which
had the vx900_int15 code as its only member.  I do think that breaking
the code into documented sections is a good plan, but in an effort to
clean up the output, I'm removing this for now.

Change-Id: I3f7e2f704136ebbd1961c5946bac4c2edbd6a371
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8070
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-04 20:03:04 +01:00
Alexandru Gagniuc 2e0cf14e14 northbridge/amd/pi/northbridge.c: Remove superfluous logic operand
The "((1ull << (sizeof(modules) * 8)) - 1)" statement evaluates to
0xffffffff, but there's no need to AND with that value, as 'modules'
is already 32-bit. The '&&' is most likely a typo, which meant bitwise
and, as indicated by the structure of thus operation.

Remove this superfluous statement. This also fixes a clang warning.

Change-Id: Ie55bd9f8b0ec5fd41e440f56dcedd40c830bf826
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7965
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-29 04:06:23 +01:00
Kyösti Mälkki e4db49730e AGESA: Use common agesawrapper
Callout FCH_OEM_CONFIG is made during AMD_INIT_RESET, so it was required
to provide GetBiosCallOut here too.

Change-Id: I0eab858677d14536293385ca37daab3e538132e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7826
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:28:12 +01:00
Kyösti Mälkki 296696d697 AGESA fam15tn fam15rl fam16kb: Add OemInitMid()
Change-Id: Icbad42168ec3afb7780c0c2ddc17aa405e08d693
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7825
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:27:15 +01:00
Kyösti Mälkki 6e74b2cbac AGESA: Add OemCustomize hooks structure
We should potentially provide an OEM platform hook to manipulate parameters
around any entry point to AGESA. Use structure for such ops to avoid weak
functions and lots of empty function stubs.

Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7824
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:26:01 +01:00
Kyösti Mälkki 94e796aae6 AGESA fam15: Unify agesawrapper
Disable TSC output for now.

Change-Id: I078b4f0170aaf0ada58e464cf609c234204f8196
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7822
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:24:41 +01:00
Kyösti Mälkki 25c27359d1 AGESA: Common laterunaptask()
Change-Id: I580f975aa987a333074de3d63744ad5f9008377d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7821
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:24:29 +01:00
Kyösti Mälkki 94dd14f035 AGESA: Common agesawrapper_amdinitlate()
Change-Id: I3d532989559ffd7fd0f63e15c2c60bcfe5ec9101
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7820
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:24:00 +01:00
Kyösti Mälkki 83f0139478 AGESA fam15: Ignore AmdCreateStruct() errors
Change-Id: I1b7c95e08d74784e0f144cd5836d46bda64a3596
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7819
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:19:15 +01:00
Kyösti Mälkki 7cfc70b19b AGESA: Use memset() on agesawrappers
Change-Id: Icc8da62c6d1644e16f7db6c634796ad597c755c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7818
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:19:03 +01:00
Kyösti Mälkki 33205f0739 AGESA fam12 fam14: Use lowercase void in agesawrappers
Change-Id: I1755796049c2c3f2090cd6a4b4e28a71b807c7c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7817
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:18:46 +01:00
Kyösti Mälkki 4a08e15086 AGESA fam14: Add amd_initenv()
Not part of wrapper to AGESA, but workaround for enable_resources().
Also remove remains of comments in non-fam14 wrappers.

Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7816
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:18:35 +01:00
Kyösti Mälkki 48518f0d60 AGESA: Add amd_initcpuio() and amd_initmmio()
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().

Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:18:00 +01:00
Kyösti Mälkki 5b7e54306a amd/torpedo: Drop unused code in agesawrapper
Change-Id: I4c7fdfb64689cc8ba7e00bd7966d5c5857baf7c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7814
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:17:48 +01:00
Kyösti Mälkki 24e31e28c4 AGESA fam14: Increase MMCONF region
Increase to max 64 buses, as there are no benefits of limit 16.

NOTE: It appears there is no matching (early) programming of the
region to non-posted MMIO.

Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-20 07:17:40 +01:00
Kyösti Mälkki af87020f0a AGESA fam12: Fix MMCONF region
MMIO for non-posted region used hard-coded setting for 64 buses
while MSR programming was for 256 buses.

Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7812
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-20 07:17:32 +01:00
Kyösti Mälkki 8548a4888a AGESA: Remove redundant redeclaration
Change-Id: I9172769c314850b384abbddf0200d5833e2a8b26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7811
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19 22:36:59 +01:00
Kyösti Mälkki 483bed33a9 AGESA: Only fam14 sets Ontario APU IDs
Change-Id: I3d249a1234599e3820e4ad9b852bbb03a89dd49a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7810
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-19 22:36:36 +01:00
Paul Menzel 9d3e131461 intel/i945: Use define for `BSM`
Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5929
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-12-19 21:14:52 +01:00
Kyösti Mälkki 450335918c AMD amdfam10: Drop EXT_CONF_SUPPORT
Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690.

Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7809
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 19:28:11 +01:00
Kyösti Mälkki ac7402dc11 AGESA fam12 fam14: Drop EXT_CONF_SUPPORT
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped
from other AGESA families.

Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 19:28:00 +01:00
Kyösti Mälkki 2fa088be40 AMD binaryPI: Drop EXT_CONF_SUPPORT
Change-Id: I2ec08df2eb8e65bc759de9917894df9d0c8b1995
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7807
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-19 19:27:50 +01:00
Tobias Diedrich 992066a427 spd_cache debug: Log invalid CRC checksum
"SPD has a invalid or zero-valued CRC" is not a very useful message,
so show the actual and expected values.

Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/7393
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-19 19:26:15 +01:00
Stefan Reinauer 295d9e6569 Drop VIA Epia-N
ROMCC cleanup.

Change-Id: Id72e6fcb89165f28cad8bf3a5b632d3fa094b7dd
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7855
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18 02:14:45 +01:00
Stefan Reinauer 42874ace62 Drop VIA Epia-M series of boards
ROMCC cleanups

Change-Id: Ic4c9d9eb8c7edc506c8a8e8eeeacf759cbaead74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7854
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18 02:14:11 +01:00
Stefan Reinauer e4c73bb5ba Drop VIA Epia mainboard
.. and also drop the northbridge and southbridge used by the board.
This is one of the last boards to not use ROMCC for romstage. Let's
get rid of it.

Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7853
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18 02:13:53 +01:00
Stefan Reinauer 5878bbd935 Drop Intel E7520 and E7525 and related boards
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies

Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-18 02:11:06 +01:00
Stefan Reinauer 61ed48c923 intel/truxton: Un-romcc-ify board
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7852
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-18 02:10:03 +01:00
Stefan Reinauer b59c5de056 Drop GX1, CS5330 and related boards
There is no Cache As Ram for these boards, let's get rid of them.

Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7117
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-16 21:17:36 +01:00
Kyösti Mälkki 13a845acb3 Intel FSP: Move to DYNAMIC_CBMEM
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT
is not enough to disable CBMEM console for romstage on these platforms.

To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy.

Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-12-16 20:40:41 +01:00
Edward O'Callaghan 2d072d415b northbridge/amd/gx2,lx: Treat MSR constant as unsigned long
Clang complains that a signed shift result (0x210000000)
requires 35 bits to represent, but 'int' only has 32 bits.
However, we write the high bits separately and so this is
a spurious warning.

Change-Id: I3e1c57334077feb50004d7b39abff4bd84ca095b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7673
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-12-10 07:06:39 +01:00
Martin Roth a0a71b046a fsp platfoms: add prototype & consolidate main entry-point
- In '-ffreestanding' main() is just as any other function and so
it needs a type-signature. Fixes a clang warning.

- Bay Trail and Rangeley have the updated romstage.c with the code
moved into the chipset, put the prototype in romstage.c.

- The sandybridge code has not been updated, so the prototype
for it goes into chipset_fsp_util.h, next to the prototype for
romstage_main_continue.

- Correct the return value of baytrail main() from void * to void
and remove the unnecessary asmlinkage tag. I'm surprised that this
didn't generate a warning...

Change-Id: I85ac0797d1e55d2b7ffdca039a52820d7827e704
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7724
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-09 03:02:39 +01:00
Dave Frodin 3ff4f85ccd northbridge/amd: Add the audio device to the PCI devices
Change-Id: I826f98e450c9a614930a5e83c7c6bfb4ccdc5984
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7630
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-12-08 18:05:13 +01:00
Vladimir Serbinenko 318e481e55 Kconfig: Remove ACPI_SSDTX_NUM.
Its scope is limited to a single mainboard and is only to go through ifdef.
Kill it and move the value to the code.

Change-Id: I76a87e2790d57dee8f37b51e33d0689fffd3a59d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7135
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07 21:06:34 +01:00
Vladimir Serbinenko 0fa7ac76bd vx800/vga.c: Remove extraneous parentheses.
Change-Id: Ic81b5f66871ec78c72f2adc5723f22fa94a672e8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7682
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 15:51:15 +01:00
Vladimir Serbinenko daf7680805 via/vx900: Plumber registered DIMM to right place.
Currently due to enum mistake DDR3 = 0xb was confused with DIMM type and
interpreted as LRDIMM, considered unregistered and so every RAM was
unregistered.
Registered RAM is rarely used, so I suppose the code was never tested with them.
For unregistered RAM exactly the same codepath is followed.

Change-Id: I02fe8b1fd7be3bd382399ffa0eb513965a2a6d77
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7687
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 15:18:48 +01:00
Vladimir Serbinenko 25fc532838 nehalem/raminit: Add decorations to specify that empty loop is intended so.
Change-Id: I6a05683daa6105e26017d1abf45881a9ef93ea30
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7683
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-07 14:01:43 +01:00
Vladimir Serbinenko 8e688b3d74 vx800: Silence clang warnings.
I have no such board to check the real fixes but this board shouldn't block
benefits for the rest of the tree.

Change-Id: I9e9d4af1b360bcf0099ac2901b08f7fcd7569097
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7681
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-07 14:01:28 +01:00
Edward O'Callaghan 4568f19d1f northbridge/intel/*/acpi/igd.asl: Trivial indent style fix
Change-Id: I26e92645264c69bbc032b0e7e44d7d31de2dfa4d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7665
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-06 10:03:30 +01:00
Martin Roth 09dd70ebb8 drivers/intel/fsp: add upd macros and #defines
Add macros and #defines for working with the UPD data.  This makes
the code look much cleaner.

Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include
the fsp_values header instead.  This fixes a conflict.

Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7487
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-12-05 16:19:45 +01:00
Vladimir Serbinenko 4aad743434 i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages.

For compatibility with old bootblocks also enable it early in romstage.

Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03 21:02:12 +01:00
Kyösti Mälkki 1aa35c6f6c AGESA: Trace execution with AGESA_EVENTLOG()
Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7604
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:11:03 +01:00
Kyösti Mälkki b139b5efcc AGESA: Common agesawrapper for S3 resume
Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7162
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:10:36 +01:00
Kyösti Mälkki 13fdf36ef9 AGESA: Add common eventlog
Change-Id: Ibbf10a53ea671990d336340fdc96dfb37b5defd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7161
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:10:14 +01:00
Kyösti Mälkki 4ee82c69a2 AGESA fam16kb: Move clearing of NoSnoopEnable bit
Originally from commit 4ca72139 move this code now from
cpu/ to northbridge/.

Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7603
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:09:32 +01:00
Kyösti Mälkki 34ad72cd03 AGESA: Remove duplicate OemCustomizeInitEarly declarations
Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7158
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:09:05 +01:00
Kyösti Mälkki 4b5a71179a AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper
Split FCH parts to southbridge/hudson.

Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7159
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:08:39 +01:00
Kyösti Mälkki 8c20a04cae AGESA fam14: Common agesawrapper
Use copy of amd/persimmon.

Change-Id: I7404cb164df9065bcdbaaf5367018870ea675adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7157
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:07:20 +01:00
Kyösti Mälkki 923302ae61 AGESA fam12: Common agesawrapper
Change-Id: Ic44d827323dc0d3c776e79c22088a2f1f654bcf2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7156
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:07:02 +01:00
Kyösti Mälkki e68f4ffb97 AGESA fam15: Common agesawrapper
Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a
common file for now and split eventlog parser to a separate file.

Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7155
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-12-03 08:06:47 +01:00
Kyösti Mälkki 27c4edace6 AGESA: Report events with AGESA_EVENTLOG()
NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may
fall through critical failures.

Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7154
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:04:53 +01:00
Kyösti Mälkki f21c2ac055 AGESA: Use common header for agesawrapper
Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7153
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-12-03 08:04:34 +01:00
Elyes HAOUAS a3ea1e4590 i945: Bit 49 of CAPID0 trivial fix
Change-Id: Ifeb277c375a0685b76fa01174a990a4cd05023bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/7587
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-02 13:58:08 +01:00
Patrick Georgi 546953c0c5 Replace hlt with halt()
There were instances of unneeded arch/hlt.h includes,
various hlt() calls that weren't supposed to exit (but
might have) and various forms of endless loops around
hlt() calls.

All these are sorted out now: unnecessary includes are
dropped, hlt() is uniformly replaced with halt() (except
in assembly, obviously).

Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7608
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-02 10:25:55 +01:00
Patrick Georgi bd79c5eaf1 Replace hlt() loops with halt()
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7606
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:07 +01:00
Patrick Georgi 5f967492e3 intel/sandybridge: make sure to stay in HLT until reboot
It also tells the compiler that we never leave here.

Change-Id: I824569efd46b577588387b29fc7781abf8c42385
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7579
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30 12:20:03 +01:00
Patrick Georgi d3060edce2 i945: make PCIe link wait sensible
Waiting for (a & 4) == 3 to become true proves futile
unless you're searching for defective hardware or
neutrino impact.

While I'm not 100% sure that this is the actual intent
(no data-sheets at hand, and the public ones are unhelpful
as usual), it's the likely correct version and it's also
boot-tested on intel/d945gclf.

While at it, replace register number with the name found
in the public datasheet.

Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6575
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-28 17:56:29 +01:00
Vladimir Serbinenko 8d70e94ae1 Make acpi_fill_dmar into parameter
Change-Id: I5e237cb7acbf47b2c8a4cd725ee8e16e422e3b17
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7371
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-27 20:37:58 +01:00
Edward O'Callaghan 12bb8f97b6 northbridge/amd/agesa/family15rl: Provide Richland support
Provide our current development support for Richland. We
would however like to see a unification of 'northbridge/amd/agesa'
instead of another copy-paste merged.

Change-Id: I88005939844d1132cfd3531a9d47389320026814
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7536
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-27 11:27:45 +01:00
Vladimir Serbinenko d305aa6fc4 i945: Find memory controller by slot instead of by PCIID.
Slot is the same on all model but PCIID varies. Tested on AOA150.

Change-Id: I474548971ea140f25326a68fe8e86698a6725dea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-26 23:19:34 +01:00
Vladimir Serbinenko 46a86f284f agesa/family12: Switch to per-device ACPI
Change-Id: I944e35b04612eca8add80c9f546df99a9a930ac8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7036
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-26 21:33:00 +01:00
Vladimir Serbinenko db09b062ca agesa/family16kb: Switch to per-device ACPI
Change-Id: I7d9cbbd1aeadecc1a4c91816df303c6cb4817fe3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7034
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-26 21:32:40 +01:00
Vladimir Serbinenko 56f46d87d2 agesa/family15tn: Switch to per-device ACPI
Change-Id: Icc2e7b66b3ff5f70b219a3e67494ce3df055c9d5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7033
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-26 21:31:32 +01:00
Vladimir Serbinenko 8be624f1f3 agesa/family15: Switch to per-device ACPI
Change-Id: I3847eb1524a5a816cd4885a31d703b410804c1f0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7032
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-26 21:31:01 +01:00
Kyösti Mälkki 68a83df6df agesa/family14: Fix includes for ACPI
Change-Id: Ic4425840a984a7713088a2568e25bae982e22fc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7582
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-26 21:30:32 +01:00
Vladimir Serbinenko 4ab588b1dd agea/family14: Switch to per-device ACPI
Change-Id: Icc663c28713f2d872bfeb1749303ce92db953bf5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7031
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-25 23:51:06 +01:00
Edward O'Callaghan 66c6532eb6 northbridge/amd/agesa/family16kb: Add MMCONF res to PCI_DOMAIN
This is a port of the following:
commit d5c998be99

  The coreboot resource allocator doesn't respect resources
  claimed in the APIC_CLUSTER. Move the MMCONF resource to the
  PCI_DOMAIN to prevent overlap with PCI devices.

Change-Id: I49167dd3f15d0203a7db8950880ab03171d5c170
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7533
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-25 14:52:52 +01:00
Edward O'Callaghan f0c73ac341 northbridge/amd/agesa/family12/dimmSpd.c: Use ARRAY_SIZE macro
Change-Id: Icf980088c196b152cc4e5e179f7b7e334b695ccc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7574
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-25 12:21:46 +01:00
Edward O'Callaghan 453e4c2e73 northbridge/amd/agesa: Remove useless northbridge.h header
Remove northbridge.h headers which only contain static declaritions
which is silly.

Change-Id: I3e8890a34b4729bb0944bd97a3b9576b841d2354
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7532
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-24 05:38:42 +01:00
Edward O'Callaghan 30b1042020 northbridge/amd/agesa/family15: Remove redudant prototype
Function is static local only and so no need for a static
prototype in header. Sync's header with other fam's also.

Change-Id: I540aeafb8528e229700b6d596d4d8094c22e7625
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7531
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-24 05:38:23 +01:00
Edward O'Callaghan 541ac596a2 northbridge/amd/agesa/family1{2,4}: make get_node_pci() static
Function is local only, as is with other families also.

Change-Id: I1f652be1763a319b2f1c9b0f53e76d6bc44f3450
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7530
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-24 05:38:02 +01:00
Edward O'Callaghan ae5fd3453a northbridge/amd/agesa/family1{4,5,5tn,6kb}: Reduce differences
Lets cut down on whitespace differences, fix some typos and indents.
Also make use of ARRAY_SIZE() macro instead of a local redefinition.

Fix NULL pointer checks ordering and not to use zero.

Change-Id: I93f344d300c04570d795659d848255cb1832e1d8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-24 05:37:50 +01:00
Vladimir Serbinenko 33b535f15d sandy/ivy/nehalem: Remerge interrupt handling
On those chipsets the pins are just a legacy concept. Real interrupts are
messages on corresponding busses or some internal logic of chipset.
Hence interrupt routing isn't anymore board-specific (dependent on layout) but
depends only on configuration.
Rather than attempting to sync real config, ACPI and legacy descriptors, just
use the same interrupt routing per chipset covering all possible devices.

The only part which remains board-specific are LPC and PCI interrupts.

Interrupt balancing may suffer from such merge but:
a) Doesn't seem to be the case of this map on current systems
b) Almost all OS use MSI nowadays bypassing this stuff completely
c) If we want a good balancing we need to take into account that e.g.
   wlan card may be placed in a different slot and so would require complicated
   balancing on runtime. It's difficult to maintain with almost no benefit.

Change-Id: I9f63d1d338c5587ebac7a52093e5b924f6e5ca2d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7130
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-23 17:30:13 +01:00
Vladimir Serbinenko f8457985d8 amdk8: Move to implicit length patching
Change-Id: I8b4c36adaa7ea791ae1a8f7c0d059b9201b08f94
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7332
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-22 16:58:29 +01:00
Vladimir Serbinenko 2a19fb1d76 amdfam10: Move to per-device ACPI
Change-Id: I9ce2333e1ea527843f83d411dea2a669263156c2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7027
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-22 16:57:07 +01:00
Vladimir Serbinenko b67eaee325 i945: Add 27ac to northbridge IDs.
Change-Id: Ie2edf0738d0f27efa696b9f6c17600a97e323117
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7484
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-22 10:50:55 +01:00
Edward O'Callaghan b32e1f4149 northbridge/amd/agesa/Kconfig: Trivial - correct indent
Change-Id: Ia7d9cb77f83afda66a1fe4e1228f2728c94e1c99
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-21 02:36:07 +01:00
Edward O'Callaghan d994ef1932 northbridge/amd/agesa: DEVICE_NOOP some stub functions
Use 'DEVICE_NOOP' over stub functions to reduce loc and
improve formalism.

Change-Id: I9c8d608539647cce22fb1dfbe284a6043d3d23d9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7534
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-21 02:35:59 +01:00
Kyösti Mälkki 023ed1f999 amd/olivehillplus: Share agesawrapper header
This interface is common with AMD PI implementations.

Change-Id: Ifabfce97db749e04aa19e53f62216be78158b282
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7150
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
2014-11-20 19:06:26 +01:00
Kyösti Mälkki e4c17ce803 AMD: Isolate AGESA and PI build environments
To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.

Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.

Change-Id: Ib60861266f8a70666617dde811663f2d5891a9e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7149
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
2014-11-20 19:02:37 +01:00
Kyösti Mälkki c36af7b00a Replace includes of build.h with version.h
As build.h is an auto-generated file it was necessary to add it as
an explicit prerequisite in the Makefiles. When this was forgotten
abuild would sometimes fail with following error:

   fatal error: build.h: No such file or directory

Fix this error by compiling version.c into all stages.

Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7510
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-20 07:28:37 +01:00
Vladimir Serbinenko 10dd0e3171 i945: Add 0x27ae to GMA IDs.
Change-Id: I4c9ccc52a7fe47311761e633c72e280055fb0310
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7485
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-19 21:09:29 +01:00
Edward O'Callaghan bf26243a00 northbridge/amd/amdfam10/conf.c: Remove extraneous parentheses
Remove extraneous parentheses around the comparison. Fix some
style while here.

Found-by: Clang
Change-Id: I882729b8fa9f32a3bb9b1524d4d8829cbb226b7d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7445
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-16 09:41:44 +01:00
Vladimir Serbinenko bf8722aac8 Make set_bios_reset into normal rather than weak function
Change-Id: I2efa254537f83fe689fd07fe6ec80f0446ad5a9d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7370
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-11-15 20:47:33 +01:00
Kyösti Mälkki aaf005eb3d sandy/ivybridge: Use DYNAMIC_CBMEM with native raminit
Change-Id: I76577cc3739f23d392d077db5a5edfdbdbe8fb1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7466
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-15 18:39:21 +01:00
Kyösti Mälkki eaee6e2d95 AMD: Move RAMBASE and RAMTOP
There are no reasons to not load ramstage @ 0x100000.

Boards with HAVE_ACPI_RESUME enabled have performance penalty in using
excessive RAMTOP. For these boards, this change releases 11 MiB of RAM from CBMEM allocation to OS.

Change-Id: Ib71995aba5e9332d0ec1626b3eb3b4ef6a506d1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7094
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-14 15:46:57 +01:00
Vladimir Serbinenko 40412c63e6 gm45: Don't crash if less than 4G of RAM are present.
In such setup there is no resource 5. find_resource die()s if no resource is
present. Use probe_resource instead.

Change-Id: I6eb4a9d8712295c58281ee69ab129276d784ca2e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7438
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-11-12 20:44:25 +01:00
Vladimir Serbinenko 5560188849 i945: consolidate sb & nb early inits
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7062
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-11-09 04:56:11 +01:00
Vladimir Serbinenko 689ddf6832 fsp_rangeley: Switch to per-device ACPI
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7046
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-11-08 20:12:31 +01:00
Edward O'Callaghan 986e85c098 intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-08 08:08:23 +01:00
Edward O'Callaghan 2837ab2cdf northbridge: DEVICE_NOOP some stub function callbacks
Reduces loc and makes NOP's explicit.

Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7344
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-06 22:20:53 +01:00
Edward O'Callaghan 3ec9c95d02 Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7196
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2014-11-05 14:53:56 +01:00
Edward O'Callaghan e408dced63 Redundant addr '&' operator on func ptr's in struct initiator
Bring code inline to be consistent with the rest of coreboot.

See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase,
'expressions that refer to functions get converted to pointers to
those functions'

Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7290
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-04 13:31:36 +01:00
Edward O'Callaghan d2040737a9 northbridge/via: Use DEVICE_NOOP macro over dummy symbol
Change-Id: Ib9d0fae363c5c1fbed3a63cb8aa86716cf1f9ee1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7289
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01 21:16:40 +01:00
Edward O'Callaghan 812d2a47d4 northbridge/amd: Use DEVICE_NOOP macro over dummy symbol
Change-Id: I3fdd2a9f981592112998d74ce4cfe4850d8fab31
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7288
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01 21:16:21 +01:00
Edward O'Callaghan 9f74462790 northbridge/intel: Use DEVICE_NOOP macro over dummy symbol
Change-Id: I9aeed70f72d4df260312df6e53379f1741415b65
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7287
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-11-01 21:15:27 +01:00
Damien Zammit 35170388ed intel/sandybridge: Add PCI ID for northbridge 0x150
Change-Id: I335244b7c39d6ddff6ecb06cb823fee09e35ee26
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7233
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-29 17:03:44 +01:00
Vladimir Serbinenko 7d6b0afdf5 sandybridge: Kill CONFIG_HAVE_MRC_CACHE
Change-Id: I54955fa44d126b7a3d382f57b4aa0dac01688104
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7129
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-24 09:15:12 +02:00
Vladimir Serbinenko fa1d688a78 sandy/ivy native: dedup romstage.c main()
Change-Id: I9909a5b2bdb4b59219db6304fa4332802fe0301c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7127
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-24 09:14:46 +02:00
Damien Zammit a10bde9048 intel/sandybridge: Add VGA pci device ID 0x0162
for Ivy Bridge.  Tested on Gigabyte ga-b75m-d3h.

Change-Id: I7a1b1e8bac38789321960ebbe8c97d68a5aebfe2
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7173
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-23 14:33:12 +02:00
Kyösti Mälkki 30fbb4c23e AGESA boards: Fix early agesawrapper_amdinitmmio()
Regression introduced with commit

   7b23ae0 AGESA: Trace execution with AGESAWRAPPER()

As the call is made before console_init() is called it must
not call any printk(). Debugging Olivehill and Parmer platforms
using a custom FPGA (as these boards have no Super-IO UART) have
been observed to halt and/or delay at early boot.

Change-Id: I3ab4e5378db44aece9046c8636cde1053ce5390d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7059
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
2014-10-22 15:04:32 +02:00
Gabe Black b3f08c61f1 cmos: Rename the CMOS related functions.
Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.

This CL also opportunistically cleans up some style problems in this file.

Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)

Removed the addition of stdint.h to mc146818rtc.h since
types.h is now included. Changed rtc_init to cmos_init for
fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.

Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22 03:55:14 +02:00
Vladimir Serbinenko a3bdbcc11e e7501: Move to perdev ACPI
Change-Id: Ic8472745c2ff0c68fd63b51d1a149a11be1650e9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-19 09:56:54 +02:00
Kyösti Mälkki 26f297e981 AGESA: Drop board and chipset -specific callout headers
Change-Id: If973f28931e65a57cbb8d6739542a57c844f0d66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7115
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19 06:20:58 +02:00
Kyösti Mälkki a1ebbc42ad AGESA fam12 fam14 fam15: Use common agesa_readSpd()
Remove northbridge specific callouts for AGESA_READ_SPD.

Move low-level SMBus code to southbridge.

Change-Id: I5fc91c49d9ef8e0af1c4d8194f857c61ce417d1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19 06:19:44 +02:00
Kyösti Mälkki c5cc9f233c AGESA fam15tn fam16kb 00730f01: Add common agesa_readSpd()
Remove northbridge specific callouts for AGESA_READ_SPD.

Move low-level SMBus code to southbridge.

Change-Id: I3e272389e2a7db542fb48fca8606325af27b65a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7112
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-10-19 06:18:39 +02:00
Kyösti Mälkki 1729cd8574 x86 romstage: Move stack just below RAMTOP
Placement of romstage stack in RAM was vulnerable for getting corrupted
by decompressed ramstage.

Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7096
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19 06:14:05 +02:00
Vladimir Serbinenko b6200969ec via/vt8454c: Migrate to per-device ACPI
Change-Id: Ia3f6691ae7c33b5e22010e25a1f01996a594196e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6943
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18 22:15:32 +02:00
Vladimir Serbinenko 9a0b251680 i3100: Convert to per-device ACPI
Change-Id: Id90db4f6ce1a5fb506c81bc3a6010d85b0aa8c43
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18 22:14:19 +02:00
Vladimir Serbinenko 6c71a684a4 via/vx800: Migrate to collaborative ACPI
Change-Id: I00d0d0e2556d4cd0553a2b3351ace26bf747ff6a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6944
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18 22:06:25 +02:00
Vladimir Serbinenko e7ff9d8839 fsp_sandybridge: Move to per-device ACPI.
Just took combined sandybridge per-device ACPI patch and applied it
on FSP flavour to avoid need of separate tests.

Change-Id: I09838cc01ede504416078edcb1c267a11539e714
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18 22:05:00 +02:00
Vladimir Serbinenko e6e5b5ef55 sch: Switch to per-device ACPI
Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6811
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-18 22:01:18 +02:00
Vladimir Serbinenko c7310d977a e7505: Move to per-device ACPI
Change-Id: I706891b9408cf14b559ef228766c04e98345ff6e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-18 13:54:13 +02:00
Vladimir Serbinenko b752e4f402 acpi_add_ssdt_pstates: Remove function.
Nowhere in database p_state_num is set. So this whole function ends up
being a noop. Moreover the offsets used by it are wrong with any
optimizing iasl. Remove it in preparation of move to per-device ACPI.

Change-Id: I1f1f9743565aa8f0b8fca472ad4cb6d7542fcecb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7012
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2014-10-17 10:04:12 +02:00
Vladimir Serbinenko f21271edb5 Fix mismerge of ACPI patches
Change-Id: I2a9960861465f4686113213d5e5793333b6274b2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7079
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17 09:31:28 +02:00