Commit Graph

1091 Commits

Author SHA1 Message Date
Niels Ole Salscheider 24788351dc flashrom: Add AMD SB700 flash enable
This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 11:58:43 +00:00
Peter Stuge 5a0be5193e flashrom: Fix compilation of r3797 with gcc-4.3.2
Thanks to Niels Ole Salscheider for the problem report.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 11:56:57 +00:00
Peter Stuge b4b56e669b flashrom: Check if erase succeeds and exit with error on failure.
flashrom used to exit 0 even if erase failed. Not anymore.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-05 02:22:30 +00:00
Stefan Reinauer 1162f25a49 Patch to util/inteltool:
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 15:18:20 +00:00
Carl-Daniel Hailfinger fcf9be3b93 Add RDID/REMS IDs for the following flash chips:
SST_25VF512A_REMS
SST_25VF010_REMS
SST_25VF020_REMS
SST_25VF040_REMS
SST_25VF040B_REMS
SST_25VF080_REMS
SST_25VF080B_REMS
SST_25VF032B_REMS
SST_26VF016
SST_26VF032
W_25X16
W_25X32
W_25X64

Straight from the data sheets.

The REMS IDs help in case the RDID opcode is unavailable (due to opcode
lockdown) or unsupported by the chip.

Some day, we need to pair probe functions together with IDs. Multiple
pairs can exist per chip and duplicating chip definitions does not
really make sense.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 00:58:10 +00:00
Peter Stuge fd5a2df876 flashrom: gcc thinks base could be used uninitialized, so shut it up.
Bug from r3791.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 23:36:48 +00:00
Peter Stuge 9602d1e828 flashrom: Fix bug in r3790
If flashbase was set before probe_flash() it would only ever be used once, for
the very first flash chip probe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:39:56 +00:00
Stefan Reinauer d53f3e7546 Replace #ifdefs for sc520 systems by run time probing.
fixes #109

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-03 21:24:40 +00:00
Stefan Reinauer b9b500f456 build_opt_tbl:
make sure the temporary files are created in the same directory as the
target files so they can be rename()d. This fixes a compilation issue on
machines with the build directory living on another partition than /tmp.
Pretty trivial.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-02 12:26:17 +00:00
Stefan Reinauer 7a51e50582 The Winbond Super I/O chips have another indirection of registers. The
hwmon has generic registers and banked registers, mostly temperature
handling, and SMI/GPIO stuff.

Not all LDNs are switched via register offset 0x07, make it a parameter.
  
Add support for dumping the hardware monitor of Winbond W83627THF/THG
parts with the -e option.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 14:18:57 +00:00
Stefan Reinauer b4eb4fb6b0 ok, another attempt to the build_opt_tbl problem:
- create temp files and move them afterwards
- remove dummy option -b
- fix usage
- drop implicit creation of .c file if no --option is specified.

Now let's see if this fixes the issue. :-) We don't want to take 24s
instead of 6s to build an image reliably (Yes, yes, I know Tiano takes
over 20 minutes)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-30 14:52:46 +00:00
Jason WangQingpei.wang 70a1f735a9 Copyright update by Jason Wang for freshly written sb600 code.
Signed-off-by:  Jason Wang<Qingpei.wang@amd.com>
Reviewed-by:    Joe, Bao <Zheng.Bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-29 15:07:15 +00:00
Carl-Daniel Hailfinger 8b30d5d298 Declare special commands to support the Atmel AT25F512A.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:47:55 +00:00
Carl-Daniel Hailfinger f86f1fe961 If a chip has any TEST_BAD_* flag set, we don't even list the
unsupported functions, giving the user the impression that the
unsupported functions are tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 23:45:27 +00:00
Jason Wang f22ce41840 Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.

Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 21:36:51 +00:00
Stefan Reinauer 38bee3c8b6 This patch fixes the ugly race condition created through build_opt_tbl
running twice at the same time, overwriting its output files. This caused
a depending rule to produce an object file with no symbols in it.

This should silence up the regularly happening build failure messages on
the mailing list since we moved to the newer, much faster server.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 11:56:27 +00:00
Jason Wang d95e43cc8f Add SST25VF080B flash chip support.
This is the first chip which uses the infrastructure for alternative
erase commands, namely spi_chip_erase_60_c7().

Signed-off-by:  Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by:   Joe Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 05:40:27 +00:00
Carl-Daniel Hailfinger 6f24cbc083 Flashrom already has the following probe functions:
- probe_spi_rdid with opcode 0x9f, usually 3 bytes ID
- probe_spi_res with opcode 0xab, usually 1 byte ID
We are missing the following probe function:
- probe_spi_rems with opcode 0x90, usually 2 bytes ID

RDID provides best specifity (manufacturer, device class and device) and
RES is supported by quite a few old chips. However, RES only returns one
byte and there are multiple flash chips with different sizes on the
market and all of them have the same RES ID.
REMS is from the same age as RES, but it provides a manufacturer and a
device ID. It is therefore on par with the probing for parallel flash
chips and specific enough.

The order in which chips should be detected is as follows:
1. RDID
2. REMS
3. RES

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-28 01:25:00 +00:00
Carl-Daniel Hailfinger c88733c021 The existing check in probe_spi_res() was right for SPI controllers
which support all commands, but may not exist.
For controllers which support only a subset of commands, it will fail in
unexpected ways. Even if a command is supported by the controller, it
may be unavailable if the controller is locked down.

The new logic checks if RDID could be issued and its return values made
sense (not 0xff 0xff 0xff). In that case, RES probing is not performed.
Otherwise, we try RES.
There is one drawback: If RDID returned unexpected values, we don't
issue a RES probe. However, in that case we should try to match RDID
anyway.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-27 22:48:48 +00:00
Peter Stuge 0924dee124 msrtool: Use libpci to let system and target probes find PCI devices.
And some more notes in TODO.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-25 02:03:16 +00:00
Tero O Peippola ef8ea01c8c Add support for 32Mbit SPI flash SST25VF032B. Tested on gigabyte m57sli.
File util/flashrom/flash.h already had correct ID for that part.

Signed-off-by: Tero O Peippola <xeropp@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-24 20:23:23 +00:00
Peter Stuge cc9db9dfa0 msrtool: Very small fixes I made after sending out the rc1 tarball.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22 18:29:44 +00:00
Peter Stuge dad1e3091f msrtool: Release Candidate 1
msrtool can decode MSRs and print the value of every field in human
readable form. It can also be used to save a set of MSRs to a file,
and at a later time compare the saved values with current values in
hardware.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-22 17:13:36 +00:00
Carl-Daniel Hailfinger 8c0702b89b Currently flashrom assumes every vendor BIOS shares our view about which
SPI opcodes should be placed in which location. Move to a less
optimistic implementation and actually use the generic SPI read
functions. They're useful for abstracting exactly this stuff and that
makes them the preferred choice.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:43:14 +00:00
Carl-Daniel Hailfinger 7cb70d9abd Check for failed SPI command execution in flashrom. Although SPI itself
does not have a mechanism to signal command failure, the SPI host may be
unable to send a given command over the wire due to security or hardware
limitations. The current code ignores these mechanisms completely and
simply assumes almost every command succeeds. Complain if SPI command
execution fails.

Since locked down Intel chipsets (like the one we had problems with
earlier) only allow a small subset of commands, find the common subset
of commands between the chipset and the ROM in the chip erase case. That
is accomplished by the new spi_chip_erase_60_c7() which can be used for
chips supporting both 0x60 and 0xc7 chip erase commands.

Both parts of the patch address problems seen in the real world. The
increased verbosity for the error case will help us diagnose and address
problems better.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Otherwise: Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:41:02 +00:00
Carl-Daniel Hailfinger 9648351d75 Implement read support for the following Atmel chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004

I double-checked the data sheets and am confident this will work.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18 00:36:26 +00:00
Mart Raudsepp b74fbc6122 flashrom: SST39VF020 TEST_OK_ PROBE READ ERASE WRITE
Tested fully on a ThinCan DBE61A

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-17 15:31:56 +00:00
Carl-Daniel Hailfinger ef3f7e38ea The AT25 and AT26 series SPI chips from Atmel are plain EEPROMs.
The AT45 series SPI chips are DataFlash EEPROMs which means they have
odd (non-power-of-two) sector sizes, but some of the DataFlash chips can
be configured or ordered with power-of-two sector sizes.

Add probe support for the following Atmel SPI chips:
AT25DF021
AT25DF041A
AT25DF081
AT25DF161
AT25DF321A
AT25DF641
AT25F512B
AT25FS010
AT25FS040
AT26DF041
AT26DF081A
AT26DF161
AT26DF161A
AT26DF321
AT26F004
AT45CS1282
AT45DB011D
AT45DB021D
AT45DB041D
AT45DB081D
AT45DB161D
AT45DB321C
AT45DB321D
AT45DB642D

Add an explanation why the following chips can't be probed:
AT45BR3214B
AT45D011
AT45D021A
AT45D041A
AT45D081A
AT45D161
AT45DB011
AT45DB011B
AT45DB021A
AT45DB021B
AT45DB041A
AT45DB081A
AT45DB161
AT45DB161B
AT45DB321
AT45DB321B
AT45DB642

Add the ID, but no probing function for this chip:
AT25F512A

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Tested-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-15 13:55:43 +00:00
Uwe Hermann ebb73f2dcf Add detection support for ITE IT8228E, IT8711F, IT8722F, IT8761E,
IT8780F, and Fintek F71863FG.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-12 19:08:58 +00:00
Stefan Reinauer fb9f35d36b cosmetic update for getpir.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10 13:52:14 +00:00
Peter Stuge f27a3eba4d flashrom: SST39SF040 TEST_OK_ PROBE READ ERASE WRITE
Per report from Mario Rogen. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-08 01:39:12 +00:00
Carl-Daniel Hailfinger 176e88e961 The ST M25P16 chip has been confirmed to work fine for probe, read,
erase and write by Stéphan Guilloux.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-05 22:54:36 +00:00
Carl-Daniel Hailfinger aad6502d8a Add support for 8 new chips to flashrom and fix up 2 existing chips
as well.
Replace age-old TODO comments with real explanations.

Fixed chips:
Fujitsu MBM29F400TC (ID definition)
Macronix MX29F002T (chip name)

New chips:
Fujitsu MBM29F004BC
Fujitsu MBM29F004TC
Fujitsu MBM29F400BC
Macronix MX25L512
Macronix MX25L1005
Macronix MX25L2005
Macronix MX25L6405
Macronix MX29F002B

Straight from the data sheets, compile tested only.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-04 12:11:12 +00:00
Carl-Daniel Hailfinger 6f31f11031 Dump ICH8/ICH9/ICH10 SPI registers in flashrom.
This helps a lot if we have to track down configuration weirdnesses.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:20:22 +00:00
Carl-Daniel Hailfinger 6287e2e7aa Add additional SPI sector erase and chip erase command functions to
flashrom. Not all chips support all commands, so allow the implementer
to select the matching function.
Fix a layering violation in ICH SPI code to be less bad. Still not
perfect, but the new code is shorter, more generic and
architecturally
more sound.

TODO (in a separate patch):
- move the generic sector erase code to spi.c
- decide which erase command to use based on info about the chip
- create a generic spi_erase_all_sectors function which calls the
generic sector erase function
  
Thanks to Stefan for reviewing and commenting.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-03 00:02:11 +00:00
Stefan Reinauer d22ef49783 Drop nr/opcode_index parameter from run_opcode and search the opmenu for the opcode instead.
This is slightly slower (ha, ha), but works on boards with a locked opmenu. Tested on ICH7 and works.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 19:51:50 +00:00
Carl-Daniel Hailfinger 8a9e23c586 Add support for the ST M50FW002 chip to flashrom. Identification only,
erase/write are not implemented.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

tested and
Acked-by: Elia Yehuda <z4ziggy@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:25:11 +00:00
Stefan Reinauer 3d9a12f65d inteltool 82945G/GZ/P/PL Support (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 11:11:40 +00:00
Uwe Hermann 50f37b0f9b Move the nvramtool manpage to section 8 (as it's only really usable as root),
as we've done with the superiotool and flashrom manpages, too (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31 05:40:04 +00:00
Andriy Gapon 6a4bf9886a Allow nvramtool to build and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 15:41:39 +00:00
Uwe Hermann b076ced581 Mark two more chips as fully tested (trivial).
- SST SST39SF010A
 - Winbond W29C011

Tested by me on actual hardware, all operations.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-30 03:10:17 +00:00
Stefan Reinauer a69d1db504 Flashrom support for some Numonyx parts (M25PE)
using block erase d8 as discussed with Peter Stuge

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 22:13:20 +00:00
Ed Swierk c6bb6be6d2 Enable SPI boot flash support on EP80579, which has the ICH7 register set
(trivial).

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Ed Swierk <eswierk@aristanetworks.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 14:54:36 +00:00
Andriy Gapon b64aa60f1f Allow superiotool to compile and work on FreeBSD. Tested on FreeBSD 7.
Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28 22:13:38 +00:00
Uwe Hermann c372aa4f77 Mark Winbond W39V040FA" (512 KB) as fully supported, tested by
Martin Stecklum <stecky@gmx.net> (both write and erase).

The tests were done on an MSI MS-7065 board, so that's supported now
too (wiki page will be updated).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28 12:00:59 +00:00
Uwe Hermann 49387739da Add support for the Intel 82371MX (MPIIX) southbridge (trivial).
Untested, but should work just as well as the other *PIIX* southbridges
according to the datasheets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-28 11:50:05 +00:00
Uwe Hermann 045d32d78c Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.
Tested on PIIX3 hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-26 18:40:42 +00:00
Uwe Hermann 4446aa0a29 Add support for the VIA VT82C586A/B chipset, improve documentation.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-25 18:03:50 +00:00
Urja Rannikko 38204a2c18 Add support for the ITE IT8661F/IT8770F, IT8673F, and IT8671F/IT8687R.
They all use a different init sequence than the more modern ITE Super I/Os.

For now we only use 0x370 as config port, but 0x3f0 or 0x3bd would also be
valid. Contrary to other Super I/Os, the config port for these is _not_
hardcoded via hardware, instead it can be programmed by software, i.e.
you get to choose whether you want to use 0x370, 0x3f0, or 0x3bd.

Tested on IT8671F by Uwe Hermann and on IT8770F by Urja Rannikko.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-23 23:33:18 +00:00
Uwe Hermann 1877b5e51d Reduce serial output, otherwise flashing will fail very often (trivial).
This has been tested on hardware by me.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 22:09:02 +00:00
Andriy Gapon c880a369de Add register definitions for W83627HF based on publicly available
specification and local testing.

Also tweak a little bit algorithm for (internal) device ID calculation:
Chips from the W83627HF/F/HG/G family have an ID of 0x52 and a multitude of
revisions (0x1x, 0x3a, 0x41, maybe more), chips from the W83627HF/GF family
have the same device ID but revisions 0xfx.

Please note that the last line of the patch simply fixes the comment
about internal device ID composition (upper half of reg 0x21 is used).
I chose the most conservative way of detecting W83627HF - only if reg
0x21 value matches 0xFx we skip the previous logic and keep using it for
all other revisions.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-19 21:03:41 +00:00
Uwe Hermann 1aa329dcb0 Coding-style fixes for flashrom, partly indent-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18 21:14:13 +00:00
Urja Rannikko 582364d808 flashrom: Allow the SiS 620 chipset to detect and read at least 256kb chips.
Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info
about SiS620.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-18 13:54:30 +00:00
Marc Jones 7528aa6de3 SB600 has four write once LPC ROM protect areas. It is not possible to write
enable that area once the register is set so print a warning.

Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-15 17:50:29 +00:00
Uwe Hermann b0ae976eaf Drop global register 0x07 for all Super I/Os (trivial).
This is useless, as it changes with each access; it doesn't convey any
useful information at all.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-14 16:34:38 +00:00
Josh Profitt b9c6b0e8f7 Add dump support to ITE IT8726F, and add comments and a missing GPIO
register to ITE IT8718F.

Signed-off-by: Josh Profitt <zorn169@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-14 16:28:50 +00:00
Carl-Daniel Hailfinger f4b54b4135 Add ICH10 support to flashrom.
The ICH9 and ICH10 data sheets are identical regarding FWH/SPI flash
interfaces, so this just adds the required PCI IDs.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10 20:54:41 +00:00
Peter Stuge 4e40e46d49 flashrom: Check that a filename was specified also when using force read
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-10 20:43:17 +00:00
Uwe Hermann 0323a2b8f5 Add Fintek F71882FG support (trivial).
Tested on actual hardware, the MSI K9AG Neo2-Digital (MS-7368).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-09 23:56:11 +00:00
Mats Erik Andersson 0994c397a5 Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines,
whereas writing resort to the recent write_en29f002a(),
since also these chips use a byte wise algorithm.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-07 12:21:12 +00:00
Uwe Hermann cfb6ac72d1 Add some more Super I/O IDs/names (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01 20:16:58 +00:00
Marc Jones dc65196f8f Add an abuild command line option for -fno-stack-protect for toolchains that might require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 17:09:44 +00:00
Tim ter Laak 166ad2d7a5 This patch fixes support for the AT49F002N(T) chip in the flashrom tool.
It replaces the write function to one based on write_byte_program_jedec()
instead of write_page_write_jedec(), as this part does not support page
programming.
I have verified the NT variant to fully work now, and adjusted the test
status accordingly. The N variant *should* also work with this patch, but
remains untested.

Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 04:13:32 +00:00
Peter Stuge 5de576c190 flashrom: ST M29F040B status TEST_OK_ PROBE READ ERASE WRITE
Per report from Daniel Lindenaar. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30 04:00:23 +00:00
Peter Stuge b246158f77 flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 21:21:36 +00:00
Uwe Hermann 5f41bf97cb Mark the SyncMOS S29C51002T as working (trivial).
All operations tested by me on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-29 18:48:23 +00:00
Stefan Reinauer a67aab7083 Add string support to nvramtool.
To add a string to your cmos.layout, you need to specify type 's':

#start     len       type    unused   name
416        512       s       0        boot_devices

With this patch you can do

$ nvramtool -w boot_devices="(hd0,0);(hd2,1);(hd3)"

And FILO will attempt to load a menu.lst from any of these devices in that
order.

The patch is not exactly pretty, but a cleaner solution might have resulted in
a complete rewrite of the tool, which I did not want.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-27 10:08:28 +00:00
Mats Erik Andersson ad9bdb4345 Activate proper support for EN29F002(A)(N)[BT].
Fully tested for Probe/Read/Erase/Write on EN29F002NT.
Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()'
are still in use, but a tailored 'write_en29f002a()' is
needed due to a byte wise writing mechanism for this chip.

Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-26 13:19:02 +00:00
Stefan Reinauer 297b91c6cd fix two minor bugs in nvramtool. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-18 14:49:33 +00:00
Peter Stuge eb2b8a282c flashrom: Winbond W49V002A TEST_OK_ PROBE READ ERASE WRITE
Per report from Kevin O'Connor. Thanks Kevin!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3570 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-10 09:55:10 +00:00
Peter Stuge 05e0feece9 flashrom: Debug print actual time base calculated by myusec_calibrate_delay()
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-07 03:14:27 +00:00
Carl-Daniel Hailfinger 00809ebf02 This changes the python generated makefiles
targets/*/*/Makefile
        targets/*/*/normal/Makefile
        targets/*/*/fallback/Makefile

to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.

Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.

The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-04 13:44:00 +00:00
Peter Stuge 12aa5d9acf flashrom: Only find "unknown .. SPI chip" if no other chip was found
This removes the false positive matches we've been seeing, and also removes
the true positive match in case there is more than one flash chip and the 2nd
or 3rd are unknown - but I think that case is uncommon enough to warrant the
improvement in the common case. Use flashrom -frc forced read if you have the
uncommon case, and/or please add the flash chip to the flashchips array.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-03 23:10:05 +00:00
Peter Stuge 093f6d5379 flashrom: SST49LF016C TEST_OK_ PROBE READ ERASE WRITE
Per test report from Bari Ari. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-02 00:26:11 +00:00
Peter Stuge 98829def77 flashrom: SST25VF016B TEST_OK_ PROBE READ ERASE WRITE
Per test report from Ward.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-27 21:28:41 +00:00
Ed Swierk 4b461b6b78 flashrom: Recognize the Intel EP80579 LPC flash interface.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 20:31:41 +00:00
Stefan Reinauer 2319027d7e split the one file, as the several printing functions will continue to grow
immensly when they know more systems / cpus / chipsets

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 13:41:24 +00:00
Stefan Reinauer eb02f45e6f use seperate array for core 2 cpus (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-20 12:42:39 +00:00
Sean Nelson f83325ddf9 Add support for MSI KT4V to flashrom. The KT4V is autodetected and supports
the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet).

Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-19 21:51:39 +00:00
Stefan Reinauer 26ba091d51 inteltool: match cpuid before attempting to print MSRs (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-18 10:58:09 +00:00
Stefan Reinauer 67b35cb163 fix typo in superiotool (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-15 09:46:55 +00:00
Segher Boessenkool 716c720468 flashrom: Fix error -EINVAL on mmap()
Don't calculate "flash_baseaddr" until the final value of "size"
is known, otherwise we end up trying to map a page right after
the end of memory.

Fixes #112.

Signed-off-by: Segher Boessenkool <segher@kernel.crashing.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-12 11:58:00 +00:00
Peter Stuge 5e6e98a518 flashrom: ST M50FW040 TEST_OK PROBE READ ERASE WRITE
Per test report from Marcel Konrad. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-08 10:55:57 +00:00
Ward Vandewege ebc92186cc Add the contents of buildrom's
packages/mkelfimage/mkelfimage-autoconf.patch
  packages/mkelfimage/mkelfImage-2.7-x86_64.patch

to our svn copy of mkelfimage.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

These are the original commit messages from the buildrom svn tree:

-----------------------------------------------------------------------
r61 | jcrouse | 2007-11-28 13:06:23 -0500 (Wed, 28 Nov 2007) | 9 lines

[BUILDROM]  Fixup mkelfimage

My patch makes it so all targets use vmlinux and 2.7.  Including
the mkelfimage patch from Yhinghai Lu.

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>

------------------------------------------------------------------------
r80 | jcrouse | 2007-12-10 13:56:40 -0500 (Mon, 10 Dec 2007) | 8 lines

[BUILDROM] Fix breakage in the new mkelfimage autoconf scripts

Whack the autoconf scripts in mkelfimage to allow us to pass our
stack protection flags in.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>

------------------------------------------------------------------------



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-06 20:37:38 +00:00
Stefan Reinauer ab8bb8b061 update copyright year (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 15:13:58 +00:00
Stefan Reinauer 42fb71f626 tested another intel chip (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02 14:58:49 +00:00
Stefan Reinauer 62ab563ae1 fix build warnings for buildrom (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:20:33 +00:00
Stefan Reinauer 7e4954cd3f fix typos in config.g, and don't arbitrarily hide some build information
(doesn't make sense in v2). For silent build, use make -s
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:20:09 +00:00
Peter Stuge ec9e6e33a4 flashrom: Winbond W39V040C and MSI K8T Neo2-F
W39V040C does standard JEDEC commands except chip erase so add a small driver.
probe_w39v040c() prints the block lock pin status when a chip is found.

The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs.

Many thanks to Daniel McLellan for testing all of this on hardware!
Build tested by Uwe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21 17:48:40 +00:00
Stefan Reinauer a3f057935c superiotool: add support for SMSC SIO10N268 (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19 14:42:21 +00:00
Stefan Reinauer a12eb6a7e5 add support for 2 new SMSC superio chips. Information is a bit ambiguous
and scattered within the datasheets. (trivial patch)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19 14:07:35 +00:00
Carl-Daniel Hailfinger 2f45e770d7 Fix and clean up coreboot image detection heuristic.
Additional compile fix for NetBSD.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-11 00:06:38 +00:00
Peter Stuge a4793182e8 flashrom: Trivial SPI cleanups
While writing a new SPI driver I fixed some things in the SPI code:
All calls to spi_command() had unneccessary #define duplications, and in some
cases the read count define could theoretically become harmful because NULL was
passed for the read buffer. Avoid a crash, should someone change the #defines.

I also noticed that the only caller of spi_page_program() was the it87 driver,
and spi_page_program() could only call back into the it87 driver. Removed the
function for easier-to-follow code and made it8716f_spi_page_program() static.
The ichspi driver's static page functions are already static.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07 06:38:51 +00:00
Peter Stuge 5dc95de5e6 flashrom: Trivial indent fix in ichspi.c
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07 05:14:06 +00:00
Carl-Daniel Hailfinger 5bc95858d5 r3415 removed symbolic constants for device IDs by accident.
flash.h is a database of known IDs, whereas flashchips.c is a database
of chips for which support has been implemented. Keep it that way.

Trivial.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06 23:04:01 +00:00
Andreas Thienemann ce17f6bdb0 flashrom: Add AMIC A29002
This patch adds support to the AMIC A29002 chip in its top and bottom
configuration to flashrom. Additionally, the alphabetic order of the
AMIC chips was fixed.

The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>.

A29002T PREW functionality was tested and works.

This flash chip has asymmetric sector layout so it is important to use the
mx29f002 driver, which does chip erase before writing, rather than am29f040b,
which uses sector erase.

Signed-off-by: Andreas Thienemann <andreas@bawue.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06 17:35:30 +00:00
Stefan Reinauer 3c75baea46 Adding support for flashing system with Nvidia MCP67
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05 09:48:30 +00:00
Peter Stuge e9dcb8931e flashrom: Add PCI IDs for EPIA-CN
Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices
with their 1106:aa08 subsystem id:s for autodetection.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05 04:12:37 +00:00
Uwe Hermann 1a20cdec2c Minor cosmetics, e.g. make stuff fit in 80 chars/line etc. (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 19:26:44 +00:00
Carl-Daniel Hailfinger 3244b984e2 Mark SST49LF040B as tested.
Thanks to Paul Seidler and Ward Vandewege for testing.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 19:08:52 +00:00
Uwe Hermann 4321f8be6e Mark the SST SST49LF040 as OK (tested by me), all operations (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 18:58:58 +00:00
Peter Stuge 8fe1a42e7d flashrom: Winbond W25x80 TEST_OK PROBE READ ERASE WRITE
Per test report from Björn Gerhart. Thanks!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 16:54:05 +00:00
Carl-Daniel Hailfinger 039b848066 Improve coreboot image detection heuristic in flashrom. It's not
absolutely perfect, but the likelihood of this check to fail is
0.000000000000000000000000013 (1.3*10^-26) which is good enough for me.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de> 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03 14:40:06 +00:00
Peter Stuge f74c208256 flashrom: probe_flash() cleanup for better code readability
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 17:15:47 +00:00
Stefan Reinauer cac7286c0b set w39v080fa to fully supported. I'm am flashing this chip several times a
day.
Also enable unlocking which is only needed when running coreboot, that slipped
in the original commit and through the original review ;-) So it must be
trivial enough.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 13:33:09 +00:00
Peter Stuge c3c4472bd1 flashrom: Update to TEST_OK for Winbond W39V040FA PROBE READ
Thanks to Jake for the test report!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 03:07:46 +00:00
Peter Stuge 1ae669771c flashrom: Don't rm *~ in make clean, who knows what files that could be
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 03:03:58 +00:00
Peter Stuge 39a582569a flashrom: Unknown vendor:board message can be triggered by -m too
Thanks to Stefan for pointing this one out.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 00:59:29 +00:00
Peter Stuge 12224acb6f flashrom: Case insensitive matching of vendor:board strings in coreboot table
Needed at least for GIGABYTE:m57sli in coreboot to match gigabyte:m57sli in
flashrom.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02 00:47:30 +00:00
Stefan Reinauer d9b7ae8bec First attempt to clean up SPI probing and create a common
construct: the flash bus.

At some point the flash bus will be part of struct flashchip.

Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.

Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 23:45:22 +00:00
Rudolf Marek e16d43c041 Mine AMIC flash chip needs 4 bytes RDID. This enables to use the new probing code.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:48:54 +00:00
Rudolf Marek d8a7e7d043 Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:45:17 +00:00
Rudolf Marek 4a17e02003 This patch adds support for VIA SPI controller on VT8237S. It is similar with
few documented exceptions to ICH7 SPI controller.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30 21:38:30 +00:00
Carl-Daniel Hailfinger 7b425c1c11 Add a debug marker after ICH SPI opcode programming.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 10:57:13 +00:00
Peter Stuge 891f1a2650 flashrom: Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.

Also fixes a build error in ichspi.c with gcc 4.2.2.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29 01:30:41 +00:00
Carl-Daniel Hailfinger 50e4a095dd Use symbolic constants for PCI subsystem probing in flashrom.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-28 23:02:22 +00:00
Stefan Reinauer a1dd9142c6 * ICH7 SPI support
* fix some variable names in ichspi.c (Offset -> offset)
* Dump ICH7 SPI bar with -V
* Improve error message in case IOPL goes wrong. (It might not even be an IOPL)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27 16:28:34 +00:00
Stefan Reinauer 20e0599e69 indent according to development guidelines (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27 15:18:20 +00:00
Jens Kühnel 8613d628d5 Winbond W39V080FA: Probe and Read are OK.
Signed-off-by: Jens Kühnel <coreboot@jens.kuehnel.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26 11:57:27 +00:00
Peter Stuge d1cd7bc054 flashrom: Test status OK for ST M50FW040 PROBE READ
Per test report from Alex Perez. Thanks Alex!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 08:18:13 +00:00
Peter Stuge dc64a270be flashrom: Test status OK for Macronix MX25L8005 PROBE READ ERASE WRITE
Per test report from Andrew Paprocki. Thanks Andrew!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 04:17:14 +00:00
Peter Stuge 0667afd294 flashrom: Increase delay in probe_jedec() after Product ID Entry to 10ms
We should follow data sheet timing, even if chips have been tested to answer
faster in the field.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 02:09:09 +00:00
Peter Stuge 606a207d9b flashrom: Slight restructure of SPI probe_ functions
Preparation for a probe optimization patch. This patch does not change any
functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2.

The idea is to have error checks return error immediately when something
fails, rather than having code inside an if block where the condition
tests for success.

This means: Less indentation, more clear what the code is checking.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24 01:22:03 +00:00
Uwe Hermann 12afdd82ac Some flashrom documentation fixes, and removal of duplicated info (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 18:50:25 +00:00
Peter Stuge 6f78cd6eba flashrom: A few changes were committed before the DoC remove, update README.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:54:03 +00:00
Stefan Reinauer 8b835974cd as per Peter's suggestion. clean binary in make clean
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:15:03 +00:00
Peter Stuge b05b6a2555 flashrom: Remove dead M-Systems Disk on Chip code
DOC support has been disabled by default for many years. The write function
does nothing but print text. It has a call to write_page_md2802() commented
out, but that function does not exist. This is dead code with ugly #ifdefs.

Updates README to reflect that there was a time when there was code, but it
didn't work. Removes M-Systems #defines and also includes svn rm msys_doc.*

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 17:06:41 +00:00
Peter Stuge 67939dc75f flashrom: Update test status to TEST_OK_PREW for ST M50FLW080A and SST49LF008A
Many thanks to Julio Cesar Costa for the test report!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 02:04:49 +00:00
Peter Stuge a6b6711cf7 flashrom: Some Makefile cleaning
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22 02:00:39 +00:00
Peter Stuge 8239a1b2fd flashrom: Fix OBJS in Makefile to compile stm50flw0x0x.c like the others
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 04:39:17 +00:00
Peter Stuge 5f10902f39 flashrom: Uppercase AMIC since that's what they write in datasheets.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 04:23:10 +00:00
Peter Stuge 0e7d54a5b7 flashrom: Update comment to match delay change in probe_jedec() r3373
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3375 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 01:02:20 +00:00
Peter Stuge ad2ef07ff7 flashrom: Update test status for Atmel AT29C020 and SST29EE010
Thanks to Urja Rannikko for reporting test results with these flash chips.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 00:21:22 +00:00
Peter Stuge 4ff88b4d49 flashrom: Increase delay in probe_jedec() to 2ms to reliably detect AT29C020
Run time is increased a few 100ms but this is needed for reliability.
I consider this trivial.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-21 00:19:52 +00:00
Peter Stuge 5f2e30c9ed flashrom: Show expected and read byte on verify failure. Trivial.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3372 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-20 02:58:42 +00:00
Jens Kuehnel 42b127fe22 flashrom: Add support for AMIC Technology A49LF040A and do not probe W29EE011 anymore
Jens sent the first patch that added A49LF040A to flash.h and flashchips.c
using _jedec and _49lf040 functions.

An issue was found with probe_w29ee011() for the Winbond W29EE011, which
caused the A49LF040A to no longer respond to any commands.

Ward made a patch to disable probing by default for the W29EE011 following
some discussion. Using -c W29EE011 will make flashrom probe for the chip.

Peter did some more datasheet diving and found that the Pm49FL00x functions
suited this chip quite well because of the block locking registers in
A49LF040A, and finally tested PROBE READ ERASE WRITE to work on ALIX.3c3.

Ward confirmed that this works on alix.2c3 too.

Signed-off-by: Jens Kuehnel <coreboot@jens.kuehnel.org>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18 13:36:34 +00:00
Peter Stuge 646eb245e6 flashrom: Force read unknown flash chips
When flash chip detection fails, it is still useful and possible to read the
flash chip contents. If no flash chip is found in normal probes and the
-f -r -c CHIPNAME options are given, a successful probe for the specified
chip is forced, and then flashrom reads the flash chip using either the read
function for the specified chip, or if there is none, a simple memcpy().

The patch also moves the global variable int force in flashrom.c into main()
and passes it as a parameter to layout.c:show_id(), which was the only other
function that used the variable. This is needed to avoid confusion with the
new parameter int force which is added to flashrom.c:probe_flash() and used
to force probe success for the chip named in char *chip_to_probe.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3367 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-18 02:08:40 +00:00
Peter Stuge 01441bd5cf flashrom: Board enable and autodetection for GIGABYTE GA-7VT600
Uses the VT8237 ISA bridge with mainboard subsystem ID and Realtek 8139 with
mainboard subsystem ID for board detection.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-13 01:39:45 +00:00
Peter Stuge bc18fbbc60 flashrom: Add support for Amic Technology A29040B flash chip.
PROBE READ tested by Lyos Gemini Norezel on BioStar P4M80-M4.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11 02:24:15 +00:00
Peter Stuge d1f698ac27 flashrom: Board enable and autodetection for BioStar P4M80-M4.
Thanks to Reinder for clean room reverse engineering and data sheet diving!

This board is autodetected because there are some good BioStar subsystem IDs.
Matching uses onboard VT6420 SATA RAID with subsystem BioStar 3206 and
onboard UniChrome Pro IGP graphics with subsystem BioStar 1202.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-11 02:22:42 +00:00
Pierre Pronchery d63e0d041e Changes Makefile generation so that recursive "make" calls read
"$(MAKE)" instead, as GNU make (or "gmake") is currently necessary to build.

Signed-off-by: Pierre Pronchery <khorben@defora.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-08 23:05:24 +00:00
Tom Sylla 92af509faa Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware.
Signed-off-by: Tom Sylla <tsylla@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-07 11:36:30 +00:00
Peter Stuge 6196416c27 Ward writes:
SST SST49LF160C is confirmed to work for PROBE READ ERASE WRITE, at least on
2 MCP55-based boards (gigabyte m57sli v1 and supermicro h8dmr).

On the m57sli board, it only works > 512K when booted into coreboot; the
proprietary bios seems to do something weird where it locks rom access down
to the first 512K of the chip.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-03 00:22:00 +00:00
Stefan Reinauer 39d4e5f790 abuild: fix gnu getopt detection (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-28 08:40:23 +00:00
Mart Raudsepp 41b35b52d8 Revert r3357 and fix it as intended to (forgotten header commit instead of typo)
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 23:51:55 +00:00
Mart Raudsepp 012fbc796d Fix typo introduced in r3356 that breaks build (trivial).
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 22:20:30 +00:00
Peter Stuge 68229f35d1 flashrom: MX25L4005, S25FL016A, W39V040B, W39V080A, SST49LF008A tests.
I have tested MX25L4005, S25FL016A and W39V080A myself.

Thanks also to the following testers:
SST49LF008A Bernhard M. Wiedemann
W39V040B Dan Lenski

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 20:54:09 +00:00
Stefan Reinauer d9ce08dc8c not sure why this ever worked. Add --xml / -x to the supported options (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 20:06:30 +00:00
Stefan Reinauer 02a4e7f6f8 sync latest version of abuild (0.6) (trivial patch)
- parallel building
- fix non-gnu-getopt systems
- silent mode

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 18:29:26 +00:00
Mart Raudsepp ee9e1a3911 Mark SST49LF004A/B as tested (trivial).
Tested by me on actual hardware (all operations) - Artec Group DBE62 with SST 49LF004B

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-27 09:10:52 +00:00
Uwe Hermann 5dfee60cac Mark the following chips as tested (trivial).
- AMD Am29F040B
  - SST SST39SF020A
  - Winbond W29C020C
  - Winbond W29EE011
  - Winbond W49F002U

All of them tested by me on actual hardware (all operations).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-26 23:12:25 +00:00
Uwe Hermann 6eb5012a8c A bunch of cosmetic improvements (trivial).
- Fix typos and inconsistencies.
 - Drop duplicate line which tells us the chip name twice.
 - Also print the chip vendor, not only the name.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 22:47:04 +00:00
Uwe Hermann 1a02c8eeed Mark more chips as tested (all operations), tested on ASUS P4B266 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 21:26:42 +00:00
Uwe Hermann dccaf5fd00 Add support for the ASUS P4B266 board.
Tested on actual hardware.

This patch add an ich_gpio_raise() function which can be re-used by other
board-specific funtions which need to raise GPIOs on ICHx southbridges.

This also fixes bug #7, see http://tracker.coreboot.org/trac/coreboot/ticket/7,
as it turned out the ICH2 (and other ICHx) code works fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 21:19:38 +00:00
Rudolf Marek f40532c2b3 Add support for Amic A25L40P SPI flash.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 13:42:23 +00:00
Andriy Gapon 4b1cde877c Changes to make flashrom compile (and work) on FreeBSD.
This patch addresses different argument order of outX() calls,
FreeBSD-specific headers, difference in certain type names and system
interface names, and also FreeBSD-specific way of gaining IO port
access.

Signed-off-by: Andriy Gapon <avg@icyb.net.ua>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-22 13:22:45 +00:00
Peter Stuge 4cc35fdfa9 Myles reported SST49LF080A status -> TESTED_PREW
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-21 07:10:15 +00:00
Uwe Hermann 710e8b1ad0 Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).
Tested on hardware:
Intel Northbridge: 8086:1a30 (i845)
Intel Southbridge: 8086:2440 (ICH2)

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17 21:33:35 +00:00
Nikolay Petukhov ce1fb9d4e9 flashrom: Support Pm49FL004/2 Block Locking Registers
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.

This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c

Thanks go to Nikolay for this patch.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-17 01:08:58 +00:00
Carl-Daniel Hailfinger fb047a6a54 I looked at the datasheet and erase_sector_39sf020() is totally and
completely wrong. It was a straight cut'n'paste from SST 28SF040 code
and the person doing the cut'n'paste didn't even bother to check the
data sheet. The SST 39SF020 is completely incompatible with the 28SF040.

No need for replacement. According to the data sheet, standard JEDEC
commands will work and we have those commands in the tree already.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 21:11:53 +00:00
Carl-Daniel Hailfinger d9fa5d2aba ICH8 and ICH9 have an almost identical SPI interface, only the location
of the SPIBAR differs. Add ICH8 support to the ICH9 code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 14:39:39 +00:00
Dominik Geyer ed24da499d Add support for the Atmel AT25DF321 SPI flash (tested).
Change ST M25P32 status to tested.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 13:00:28 +00:00
Dominik Geyer fac0afb87d Add support for SPI chips on ICH9. This is done by using the generic SPI
interface.

Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 12:55:55 +00:00
Carl-Daniel Hailfinger e7b1157764 Enable IT8716F LPC-to-SPI write cycle translation in flashrom if the
IT8716F decodes any address to the attached SPI ROM.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-16 00:19:52 +00:00
Carl-Daniel Hailfinger 8e8eb7d261 Print detailed status register information for SST25VF series flash.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 22:32:08 +00:00
Carl-Daniel Hailfinger e3da00de8d Lots of new SST flash chip IDs. Only a subset has been added to
flashchips.c, but the IDs in flash.h will make lookups easier if anybody
wants to add support for them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 03:24:43 +00:00
Carl-Daniel Hailfinger a4868c44b5 Add support for the JEDEC RES (Read Electronic Signature and Resume from
Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>

This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15 03:19:49 +00:00
Uwe Hermann c7d29013db Some NSC Super I/Os can have their config port at 0x15c (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 22:56:47 +00:00
Uwe Hermann 9a6b6b51df Cosmetics, whitespace, coding style, partially ident-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 21:20:55 +00:00
Stefan Reinauer f9b99450ce add ICH7-M and ICH7 DH to inteltool (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 20:05:00 +00:00
Carl-Daniel Hailfinger 3f09561ec4 Add more infrastructure for flashrom ICH9 support.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:51:22 +00:00
Stefan Reinauer 58a1cc1d34 fix license mentioning in manpage (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:47:32 +00:00
Stefan Reinauer 9f7af6ef40 trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 14:22:59 +00:00
Stefan Reinauer d466e6a874 trivial patch to fix options. Thanks to Uwe Hermann for the hint!
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 13:52:50 +00:00
Claus Gindhart e173f9904c Add the Intel 6300ESB as known chipset to the chipset struct enables.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:22:38 +00:00
Carl-Daniel Hailfinger 42aab08d84 Fix crash caused by division by zero for unknown flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:09:31 +00:00
Carl-Daniel Hailfinger 68db3a2bdc Check the JEDEC vendor ID for correct parity. Flash chips which can be
detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 12:03:06 +00:00
Stefan Reinauer b69e46bca3 Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
have different register meanings, so they get their own lookup tables.

This is a trivial patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 11:38:22 +00:00
Carl-Daniel Hailfinger 1984067a86 Add lots of ATMEL SPI flash chips to flash.h.
Add a few flashchips already mentioned in flash.h to flashchips.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14 04:27:02 +00:00
Carl-Daniel Hailfinger b77fb6bd52 flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 23:03:12 +00:00
Stefan Reinauer 03646bebbe Add new revised inteltool that dumps all kinds of chipset information and drop old
gpio_dump utility.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 22:14:21 +00:00
Carl-Daniel Hailfinger 967214d559 flashrom: Move the SPI #defines from spi.c to spi.h
This patch has no code changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 14:58:23 +00:00
Carl-Daniel Hailfinger a2e7c48d38 Change the SPI parts of flashrom to prepare for a merge of
ICH9 SPI support. In theory, this patch has no behaviour changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13 14:01:22 +00:00
Carl-Daniel Hailfinger 6d3fdf9b62 MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OK
by Harald Gutmann.
SST39VF040 has been confirmed to probe OK by misi e.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12 21:19:53 +00:00
Carl-Daniel Hailfinger c95f2a737a Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF
series has the same IDs.
Add short AMIC vendor ID to flashrom.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12 14:25:31 +00:00
Carl-Daniel Hailfinger cd0b5631de Improve flashrom SPI abstraction, second step.
This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.

The third step would be calling SPI controller functions via a function
pointer.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10 23:40:51 +00:00
Peter Stuge 31ab0314d1 flashrom: Rename generic_spi_*() functions to spi_*()
This is a very early step toward cleaning up SPI code in flashrom.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10 23:07:52 +00:00
Uwe Hermann bbd337e364 Add support for dumping ITE IT8718F EC registers (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 14:37:12 +00:00
Uwe Hermann 8cb2458005 Don't split up register list in two blocks, otherwise "Register dump:"
will be printed twice in the output (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 13:50:23 +00:00
Claus Gindhart 15da8ed98b flashrom: Probe for up to 3 flash chips.
Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
For this reason some boards have multiple chips of different technologies
onboard. This patch makes flashrom probe for up to 3 chips and if more than
one chip is found flashrom exits, asking the user to specify -c.

[root@localhost src]# ./flashrom
...
Multiple flash chips were detected: SST49LF008A M25P16@ICH9
Please specify which chip to use with the -c <chipname> option.
[root@localhost src]# 

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Claus Gindhart <claus.gindhart@kontron.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08 00:31:44 +00:00
Ed Swierk 35993a231e Fix a typo in lbtdump output (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07 19:21:18 +00:00
Peter Stuge 4934fc03cb flashrom: Add a tested bitmap field to the flash chip table.
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.

All chips are TEST_UNTESTED for now.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-03 04:34:37 +00:00
Bari Ari e21f836e4e flashrom: Enable ROM decode range to 1MB for vt8237r
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-29 13:46:38 +00:00
Claus Gindhart b19973eb8b The generic jedec.c does not work for the ST M50FLW flash
devices, because they need an unlock command first.
For this reason, ST M50FLW support is moved to a
new HW support module, because any change in jedec.c
would bear the risk to cause problems with the already
supported devices.

It's already tested with ST M50FLW080A; the other
chips of this family i dont have available, so i couldnt
test it.

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 17:51:09 +00:00
Peter Stuge 26e08b5abe flashrom: Handle NULL probe, erase and write function pointers in the
flashchips table. The read pointer was already checked properly.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28 14:47:30 +00:00
Claus Gindhart 20ba8eb7ab Flash pages, which where excluded from updating using the exclude or the
layout option, as well as areas, whose flash contents already contain the
desired data, will be skipped.
These ensures absolute data security of critical areas (BIOS boot block), 
e.g. against a sudden power off or a CPU hangup during flashing. As a
nice side effect, it speeds up the flash process, if the BIOS to be flashed
is very similar to the version in flash. 

Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24 09:07:57 +00:00
Uwe Hermann bb33e4a2fe Detect SMSC SCH5027 (trivial).
This chip seems to be very similar to the SMSC DME1737, for coreboot
purposes it might even work without any code changes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23 09:27:18 +00:00
Ed Swierk c6092c0f34 ST M50FW016 and ST M50FW040 support the 82802ab command set, not jedec.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-07 22:33:33 +00:00
Uwe Hermann 42cccdf03b Make a few array entries only as big as they absolutely need to be (trivial).
This decreases the size of the superiotool binary from ca. 1.1 MB to 600 KB.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29 01:35:21 +00:00
Jon Dufresne c88b537461 Make the getpir output compile (Closes #70).
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3189 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-25 19:43:01 +00:00
Carl-Daniel Hailfinger e98edfa386 Add ICH9 detection to flashrom. Straight from the datasheet, untested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-18 00:54:10 +00:00
Stefan Reinauer 470d3650ad oops. forgot to add the file.
Support for the Winbond W39V080FA series of chips.
Support for flashing on the Kontron 986LCD-M board.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-18 00:36:18 +00:00
Stefan Reinauer 012ed48bf2 Support for the Winbond W39V080FA series of chips.
Support for flashing on the Kontron 986LCD-M board.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 22:59:40 +00:00
Uwe Hermann 969a9f69e8 Various smaller fixes in superiotool:
- Also dump the extra registers (e.g. EC regs) in --list-supported.

 - Small fix in the code to allow for building with -pedantic (yes,
   the fix is a bit silly, but it's simple and allows us to use the
   -pedantic flag to keep the code even cleaner and nicer).

 - Install the binary in /usr/sbin, as it's meant to be run as root.

 - Small typo in README.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-17 13:43:48 +00:00
Stefan Reinauer dd6877a46d check whether SST FWH chip was successfully erased on flashchip -E, too
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 19:44:13 +00:00
Uwe Hermann 568667da20 Sort list of flash chips alphabetically, add comment (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16 02:06:25 +00:00
Stefan Reinauer 582ce71cc5 remove nasty warning that happened due to our vendor detection
mechanism.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 23:41:19 +00:00
Stefan Reinauer 9dcfc00dc6 fix typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-15 16:30:39 +00:00
Uwe Hermann 1ce63770a1 Re-add code erroneously removed in r3140.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 23:55:58 +00:00
Joseph Smith 937ae9d9fe Changes M50FW080 to use 82802ab.c instead of jedec.c. This fixes the problem of not being able to erase the chip.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 23:32:03 +00:00
Carl-Daniel Hailfinger ae8a08df3b Prepare for ICH7/ICH8 SPI support by adding some debugging for all
ICH* chipsets. Functionality (except printing) should be unchanged.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.

Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 17:20:59 +00:00
Uwe Hermann c843636c88 Fix broken flashrom build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 01:24:39 +00:00
Carl-Daniel Hailfinger 4b0a41b5ca Fix up one forgotten revert in r3140.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 00:33:42 +00:00
Carl-Daniel Hailfinger 8729de48fa Revert the delete of 82802ab.c in r3137.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-14 00:02:25 +00:00
Uwe Hermann 912ee57a59 Also print the chip vendor name in --list-supported output (trivial).
Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 18:52:51 +00:00
Uwe Hermann ee2bb3a21e Also print the required -m option in --list-supported output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 18:41:07 +00:00
Carl-Daniel Hailfinger b7b22e3c57 Drop 82802ab.c as it is identical to sharplhf00l04.c.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-13 12:43:31 +00:00
Uwe Hermann 2ad17532a4 Drop the useless rom.layout file. It's just an example, likely never
been used in the last few years, and the contents are available in
the README already anyway.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 12:28:40 +00:00
Uwe Hermann 098913dadf Add --list-supported option to flashrom which lists the supported
ROM chips, chipsets, and mainboards (Closes #90).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-12 11:54:51 +00:00
Stefan Reinauer 2aa1436777 Add GPIO dumping utility for Intel ICH series southbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-10 22:26:18 +00:00
Uwe Hermann 917158f803 Drop some duplicate documentation from the README. The manpage and
'superiotool --help' already provide the same information (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04 17:21:04 +00:00
Uwe Hermann 9ae23628fb Add missing license header to layout.c. The file was written by
Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-04 16:29:54 +00:00
Uwe Hermann cbb5ba8633 Rename lxbios to nvramtool, step 3 (rename directory).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:09:01 +00:00
Uwe Hermann 66d83cfa84 Rename lxbios to nvramtool, step 2 (rename files).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3123 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:07:46 +00:00
Uwe Hermann 6e565947a5 Rename lxbios to nvramtool.
This is step 1 in a three-step commit:

 1. Apply patch, commit.

 2. Rename some files:
    $ svn mv lxbios.c nvramtool.c
    $ svn mv lxbios.1 nvramtool.c
    $ svn mv lxbios.spec nvramtool.spec
    $ svn ci

 3. Rename lxbios directory:
    $ svn mv lxbios/ nvramtool/
    $ svn ci

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 19:06:32 +00:00
Uwe Hermann eec5ff4ccb Small coding style fixes and documentation updates (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3121 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-01 18:49:39 +00:00
Ronald Hoogenboom 0be73bbf30 This patch adds support to dump other registers than the primary
pnp-style configuration registers, using the new option -e/--extra-dump.
This patch only adds dumping of the Environmental Controller
configuration registers for the IT8716f chip.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>

I (Carl-Daniel) checked the data sheets of the whole IT87[012] series 
and although the environment controller is sometimes called fan 
controller, the location of the register is the same for all models.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25 22:32:41 +00:00
Mart Raudsepp 787e4c9fd5 flashrom: Add board_enable for Artec Group DBE61 and DBE62
Also add a comment about NULL subsystem IDs leaving the board entry out
of auto-detection logic.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-20 11:11:18 +00:00
Rudolf Marek bb6f88d1d4 Should be part of changeset 3106.
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are
changed, but also a SPI flash interface which has enable on bit1 and not bit0.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-18 20:43:09 +00:00
Stefan Reinauer b34eea348c Importing mkelfimage from
ftp://ftp.lnxi.com/pub/mkelfImage/mkelfImage-2.7.tar.gz

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-15 18:16:06 +00:00
Clark Rawlins 46fc14dcc8 With this small change it is possible to build flashrom again when
specifying custom CFLAGS/LDFLAGS from the make command line like:

  make CFLAGS="..." LDFLAGS="..."

I need to do this when building flashrom in a cross compiler environment
like buildroot for a foreign target.

Signed-off-by: Clark Rawlins <clark@bit63.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-14 23:22:20 +00:00
Mart Raudsepp 9792a034e4 flashrom: further cleanups to enable_flash_cs5536
- Remove the "enable write to flash" message, as the caller appears to
   already report that.

 - Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
   we get an error there already.

 - Rename a perror string from "read" to "read msr", as we use the latter
   already in this function for another read.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-11 14:32:45 +00:00
Luc Verhaegen 2f7b7fb82a Flashrom: Add board enable for VIA EPIA SP.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-09 02:03:06 +00:00
Mart Raudsepp 2995cc69f7 Improve error handling and make RCONF_DEFAULT_MSR address be a constant.
Also, move a big code comment to the top of enable_flash_cs5536().

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-08 10:10:57 +00:00
Mart Raudsepp 99062ae5ad This implements support for devices using AMD Geode companion chip
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot Flash Chip Select).
We need to write enable it in the NORF_CTL MSR register for flashrom to
be able to write to it, including JEDEC probe commands.

This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
the DBE61.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-08 09:59:58 +00:00
Carl-Daniel Hailfinger c23b3a5732 Handle JEDEC JEP106W continuation codes in SPI RDID. Some vendors like
Programmable Micro Corp (PMC) need this.
Both the serial and parallel flash JEDEC detection routines would
benefit from a parity/sanity check of the vendor ID. Will do this later.

Add support for the PMC Pm25LV family of SPI flash chips.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard  <chris@stockwith.co.uk>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-06 22:07:58 +00:00
Jon Dufresne ca31bc3cd5 Fix mptable util so the output will compile
Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3084 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-28 00:04:23 +00:00
Peter Stuge e2bbcb10d1 Make the vendor name optional in the -m flashrom parameter when there's only
one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 16:21:21 +00:00
Peter Stuge 2d94dead69 Forgot to add Spansion S25FL016A to README, trivial.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-27 07:17:14 +00:00
Marc Jones 2db9464299 Correctly disable the ROM area Write Protect bit in the Geode LX.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-26 07:35:47 +00:00
Uwe Hermann 1a6177b720 Various small fixes and updates for lxbios (trivial).
- Update website URL to http://coreboot.org/Lxbios.

 - Use svn:keywords property to actually expand the $Id$ entries.

 - Update COPYING to the latest version from
   http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 15:08:37 +00:00
Peter Stuge f2a2a5ee2e Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
working.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-25 01:52:45 +00:00
Harald Gutmann bb9c1aa54e Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 16:03:19 +00:00
Carl-Daniel Hailfinger a6941beb43 Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.

This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.

"MX25L8005 found at physical address 0xfff00000.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 15:19:01 +00:00
Carl-Daniel Hailfinger 468413a337 Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-22 14:37:31 +00:00
Ronald Hoogenboom 21efd9ffe2 Omitting the wait for SPI ready when there is no data to be read, e.g.
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21 23:55:08 +00:00
Bernhard Walle 679c62c083 This patch adds version information to flashrom. Because 'v' and 'V'
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.

Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-21 15:24:22 +00:00
Uwe Hermann 593f5aab03 Add Bingxun Shi <bingxunshi@gmail.com> to the list of contributors (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 09:43:48 +00:00
Uwe Hermann fb348035a3 Small superiotool fix to detect more Winbond W83627EHF chips. The
patch is tested on actual hardware.

As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).

So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 09:40:17 +00:00
Bingxun Shi 34a576fb98 This patch is for winbond w83627DHG superio support in superiotool.
I have test that on my board, it works ;)

Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 00:32:07 +00:00
Ronald Hoogenboom 2f0f561f89 Support SPI flash chips bigger than 512 kByte sitting behind IT8716F
Super I/O performing LPC-to-SPI flash translation.

Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-19 00:04:46 +00:00
Uwe Hermann cd474afd08 Document the --list-supported option. Various small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 18:04:28 +00:00
Uwe Hermann d84d9ba445 Minor documentation improvements/fixes in the README and manpage (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 17:48:51 +00:00
Stefan Reinauer 7223ab7c4a rename linuxbios_* files in utils repository.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:17:44 +00:00
Stefan Reinauer ca374d455c rename linuxbios_* files, too.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 16:16:45 +00:00
Stefan Reinauer 997afe6ca5 util/ renames
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:34:24 +00:00
Stefan Reinauer f527e70333 rename linuxbios -> coreboot
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:33:49 +00:00
Stefan Reinauer 8df401db3b for some reasons the externals did not get committed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:33:10 +00:00
Stefan Reinauer f8ee1806ac Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18 15:08:58 +00:00
Robinson P. Tryon 552cfb7b74 Add new --list-supported switch for printing the list of Super I/Os
supported by superiotool (closes #91).

Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-15 22:30:55 +00:00
Bernhard Walle 6322baa50c This patch removes '\n' from the help output since this looks a bit strange.
After the patch [...] The line length is still below 80 characters.

Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Torsten Duwe <duwe@lst.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-11 00:32:07 +00:00
Harald Gutmann 2e152be16e Enable MX25L8005 support in flashrom. The #defines were already there.
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-10 13:27:22 +00:00
Carl-Daniel Hailfinger c7323f1b0c Add support for the SST25VF040B 4 Mbit SPI flash chip.
Straight from the data sheet, not tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-07 13:48:51 +00:00
Ronald G. Minnich 11e90e06d3 Add board enable for the gigabyte ga_2761gxdk board
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3033 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-04 17:22:44 +00:00
Carl-Daniel Hailfinger b5f9bd6ac9 Print at least the vendor for SPI flash chips if the exact chip ID is
unknown.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-04 16:22:09 +00:00
Carl-Daniel Hailfinger 717f66d1eb Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have
exactly the same ID. Improve model number printing.

Add EN29F002(A)(N)B support while I'm at it.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Markus Boas <bios@ryven.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31 14:05:08 +00:00
Carl-Daniel Hailfinger 85acc09786 Add continuation ID support to jedec.c
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.

(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)

Add support for EON EN29F002AT.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31 01:49:00 +00:00
Carl-Daniel Hailfinger 1704179acd This fixes a few vendor IDs to conform with JEDEC publication 106W
(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.

This patch should have no effect on code generation.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-31 01:18:26 +00:00
Carl-Daniel Hailfinger 19cf6a3890 All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.

A sector/block size field in struct flashchip would be nice, though.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-29 11:05:59 +00:00
Carl-Daniel Hailfinger 29df7a9662 Print the chip status register for all SPI chips on probe if verbose
output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-29 10:15:58 +00:00
Carl-Daniel Hailfinger d0ad60a795 Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-29 10:14:38 +00:00
Carl-Daniel Hailfinger 244dd82fd6 Add support for ST M25P05-A, M25P10-A, M25P20, M25P40, M25P16, M25P32,
M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets and double checked.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 22:22:40 +00:00
Ulf Jordan e9690bddd5 Add dump support for NSC PC87317.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 22:10:00 +00:00
Carl-Daniel Hailfinger 12a3f1edec To make it easier to add new SPI chips to flashchips.c, rename functions
with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-17 14:33:32 +00:00
Carl-Daniel Hailfinger 3b408fd237 Add support for ST M25P80 chips to flashrom. Detection was tested.
Print status register before erase to help debugging block locks.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-16 21:15:27 +00:00
Ulf Jordan c9a677b4b3 Add dump support for SMSC LPC47M192.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-14 20:00:58 +00:00
Ulf Jordan c7e12e2a9d Add dump support for NSC PC97317.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-14 00:04:16 +00:00
Ulf Jordan aa6dd7407d Add detection and dump support for NSC PC97307.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-13 23:56:16 +00:00
Ulf Jordan 48c7032c28 Add dump support for NSC PC8741x.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-13 23:41:45 +00:00
Frederico Silva 850c01cacf Add support for more atmel chips:
AT49F002
AT49F002N
AT49F002T
AT49F002NT

Only tested the read function on AT49F002T.
datasheet @ http://www.atmel.com/atmel/acrobat/doc1017.pdf

Signed-off-by: Frederico Silva <frederico.silva@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-10 16:57:59 +00:00
Ulf Jordan 94a84dee9e Add detection and dump support for NSC PC87309.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-08 00:17:19 +00:00
Uwe Hermann 11887f258d Add/fix some LDN descriptions (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-07 23:55:20 +00:00
Ulf Jordan 25df0c586a Fix typo. According to National's datasheet PC87317 has SID = 0xd0 and
PC97317 has SID = 0xdf. PC87371/PC97371 do not seem to exist.

Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-07 21:55:12 +00:00
Uwe Hermann 186a3875dc Various coding style fixes, constification, fixed typos (trivial).
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-04 21:49:06 +00:00
Jonathan A. Kollasch d795b9a9ec Add board-enable for Acorp 6A815EPD.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-02 19:03:23 +00:00
Uwe Hermann 59b99d9071 Various small fixes (trivial).
- Add missing contributors to the README.

 - Drop obsolete -D option from manpage.

 - Only list contributors who added non-trivial amounts of code as copyright
   holders (and do not list those who merely provided register dump support
   for Super I/Os). Those contributors are still listed in the README,
   of course. See discussion in the thread starting at
   http://www.linuxbios.org/pipermail/linuxbios/2007-October/025516.html

 - Make a function static.

 - Fix incorrect URL in code comment. Drop obsolete comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-29 02:43:50 +00:00
Robinson P. Tryon 29cbb367b0 Dump support for SMSC FDC37C67x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-25 21:43:29 +00:00
Ulf Jordan 4dea67193e Add dump support for the PC87366.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-24 21:49:39 +00:00
Uwe Hermann f811edefd9 Dump support for the SMSC LPC47B27x (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2977 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-22 03:36:18 +00:00
Uwe Hermann 74b29b9e33 Detection support for more Super I/Os. Small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2975 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-17 17:13:52 +00:00
Uwe Hermann 4c28034e58 Add detection and dump support for the SMSC FDC37N958FR (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-14 00:30:36 +00:00
Lane Brooks 9fe02e8c65 [LinuxBIOS] flashrom support for AMD Geode CS5536
Attached is a patch that enables AMD Geode CS5536 chipset support.  I
have tested it successfully on a MSM800 board from digital logic.

Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 16:45:22 +00:00
Ulf Jordan 3c225a7cb4 Add dump support for NSC PC87360.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 15:16:06 +00:00
Carl-Daniel Hailfinger 6d6146c377 Fix ATMEL 29C020 detection with flashrom. The JEDEC probe routine had
a delay of 10 us after entering ID mode and this was insufficient for
the 29C020. The data sheet claims we have to wait 10 ms, but tests have
shown that 20 us suffice. Allow for variations in chip delays with a
factor of 2 safety margin.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 14:56:54 +00:00
Frieder Ferlemann a422c2d3c6 Grouping register dumps by 8 register values per group for better readability.
Remove trailing spaces within the register dumps.

Signed-off-by: Frieder Ferlemann <Frieder.Ferlemann@web.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2957 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-13 09:09:33 +00:00
Uwe Hermann 9c22e8625f Drop superfluous exit_conf_mode*() calls, we don't want to call them twice.
Small cosmetic fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-11-12 21:02:44 +00:00
Uwe Hermann 246be7dd6d Use the preferred order of 'static const' instead of 'const static'.
This is the common style in both Linux as well as in LinuxBIOS.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-31 22:22:11 +00:00
Rudolf Marek f32325ed8a K8 resource dump utility from Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 01:12:20 +00:00
Uwe Hermann 825c809efe Add support for Intel 440MX systems.
Add support for the Fujitsu MBM29F400TC flash part.

Detection and reading works, writing is not tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-30 00:56:50 +00:00
Peter Lemenkov 5384dac57e Added Am29LV040B
Looking through the sources of Uniflash utility I found that this chip
is no more no less than low-voltage variant of Am29F040B but with
different ID.

So I created a very quick patch (attached).

Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-25 04:11:11 +00:00
Stefan Reinauer 50542a884b This change removes all warnings from romcc in my build environment,
making the output of "make -s" finally usable.. (still trivial, doesn't
change any logic or remove any code)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 11:14:14 +00:00
Stefan Reinauer a9e5821fdd smaller changes to silence build warnings. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 11:12:15 +00:00
Peter Lemenkov 2ef39274a3 Flashrom: Add more Vendor IDs and ensure correct sorting in flash.h.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 20:36:16 +00:00
Carl-Daniel Hailfinger c4a0b911d1 Introduce block and sector erase routines to flashrom, but do not use
them yet.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-22 16:15:28 +00:00
Carl-Daniel Hailfinger bd7602314b Remove hardcoded wait from SPI write/erase routines and check the chip
status register instead.
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18 17:56:42 +00:00
Uwe Hermann 69a392b5c6 Documentation fixes and updates (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18 00:29:05 +00:00
Carl-Daniel Hailfinger 79aa01a6c3 Add generic SPI flash erase and write support to flashrom. The first
chip the code was tested and verified with is the Macronix MX25L4005,
but other chips should work as well.
Timeouts are still hardcoded to data sheet maxima, but the status
register checking code is already there.
Thanks to Harald Gutmann for the initial code on which this is loosely
based.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-18 00:24:07 +00:00
Uwe Hermann dcb9abdf4c Some cosmetic cleanups in the flashrom code and output.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:55:15 +00:00
Uwe Hermann 7dabe5ea0d Drop support for the --human-readable option. It's not any more useful than
the --dump option, it just means lots of additional work for no gain, IMO.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:43:59 +00:00
Uwe Hermann d937b5243c Print the version number always, not only in verbose mode.
We often want to know the exact version number of superiotool which
was used to gather a certain output/dump.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:42:02 +00:00
Idwer Vollering 7a90c14e9c Add dump support for the Winbond W83697SF.
Signed-off-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 23:37:36 +00:00
Carl-Daniel Hailfinger 84453c02f7 Fix wrong values/typos in chipset_enable.c. This has been confirmed by
Ed Swierk in
http://www.mail-archive.com/linuxbios@linuxbios.org/msg09788.html .

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-17 22:30:07 +00:00
Uwe Hermann f8dabccdbf Multiple flashrom fixes:
- Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool.

 - Rename manpage from flashrom.1 to flashrom.8, as section 8 contains
   "System administration commands (usually only for root)".

 - Actually install the manpage upon 'make install'.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 23:36:34 +00:00
Uwe Hermann 398b605ddb Add detection support for the Winbond W83977AF as found in the
Advantech PCM-5820 board (confirmed by Erwan Velu <erwan@seanodes.com>
on IRC). Trivial (and tested) patch.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 21:56:32 +00:00
Michael van der Kolff e62537a948 Add Gigabyte M61P-S3 SPI flash support to board_enable.c
Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 21:18:43 +00:00
Carl-Daniel Hailfinger 259aaf00f5 Convert the existing it8716f_* functions to generic_spi_* functions by
applying abstraction and wrapping.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 21:09:06 +00:00
Uwe Hermann dc34cab5cb Fix the detection for the Winbond W83697SF. Unfortunately the revision
has a slightly different format than that of the W83697UF/UG so we have
to hack around it a bit.

This patch has been verified to work on real hardware by
Idwer Vollering <idwer_v@hotmail.com> on IRC (thanks!).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 18:15:25 +00:00
Idwer Vollering 92d3434f87 Dump support for the Winbond W83977TF.
Signed-off-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-16 00:34:03 +00:00
Carl-Daniel Hailfinger 16f6171eda (forgot to add spi.c)
Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.

The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 21:45:29 +00:00
Carl-Daniel Hailfinger a28edc524b Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.

The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 21:44:47 +00:00
Uwe Hermann 72c0584d37 Fix stupid thinko in the Winbond detection code which prevented some
of the Winbond chips from being detected (trivial fix).

This is verified on real hardware and works fine now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 15:46:59 +00:00
Uwe Hermann 4910809cad Add dump support for the NSC PC8374L (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-14 17:02:15 +00:00
Ulf Jordan 39a5bf74ef Set the superiotool version number from svn at build time.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-13 18:06:12 +00:00
Stefan Reinauer 45c1556df9 Dump support for the SMSC LPC47N227.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-13 17:06:21 +00:00
Ronald G. Minnich c63643dc90 Changes to flashrom to support the K8N-NEO3, first tested at Google on GSOC day :-)
Also minor changes to remove tab-space combinations where possible. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Index: jedec.c
===================================================================
--- jedec.c	(revision 2847)
+++ jedec.c	(working copy)
@@ -281,7 +281,7 @@
 	// dumb check if erase was successful.
 	for (i = 0; i < total_size; i++) {
 		if (bios[i] != (uint8_t) 0xff) {
-			printf("ERASE FAILED\n");
+			printf("ERASE FAILED @%d, val %02x\n", i, bios[i]);
 			return -1;
 		}
 	}
Index: board_enable.c
===================================================================
--- board_enable.c	(revision 2847)
+++ board_enable.c	(working copy)
@@ -153,7 +153,8 @@
 		return 1;
 	}
 	/* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note:
-	   We can't use writecnt directly, but have to use a strange encoding */
+	 * We can't use writecnt directly, but have to use a strange encoding 
+	 */ 
 	outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port);
 	do {
 		busy = inb(port) & 0x80;
@@ -202,43 +203,39 @@
 /*
  * Helper functions for many Winbond Super I/Os of the W836xx range.
  */
-#define W836_INDEX 0x2E
-#define W836_DATA  0x2F
-
 /* Enter extended functions */
-static void w836xx_ext_enter(void)
+static void w836xx_ext_enter(uint16_t port)
 {
-	outb(0x87, W836_INDEX);
-	outb(0x87, W836_INDEX);
+	outb(0x87, port);
+	outb(0x87, port);
 }
 
 /* Leave extended functions */
-static void w836xx_ext_leave(void)
+static void w836xx_ext_leave(uint16_t port)
 {
-	outb(0xAA, W836_INDEX);
+	outb(0xAA, port);
 }
 
 /* General functions for reading/writing Winbond Super I/Os. */
-static unsigned char wbsio_read(unsigned char index)
+static unsigned char wbsio_read(uint16_t index, uint8_t reg)
 {
-	outb(index, W836_INDEX);
-	return inb(W836_DATA);
+	outb(reg, index);
+	return inb(index+1);
 }
 
-static void wbsio_write(unsigned char index, unsigned char data)
+static void wbsio_write(uint16_t index, uint8_t reg, uint8_t data)
 {
-	outb(index, W836_INDEX);
-	outb(data, W836_DATA);
+	outb(reg, index);
+	outb(data, index+1);
 }
 
-static void wbsio_mask(unsigned char index, unsigned char data,
-		       unsigned char mask)
+static void wbsio_mask(uint16_t index, uint8_t reg, uint8_t data, uint8_t mask)
 {
-	unsigned char tmp;
+	uint8_t tmp;
 
-	outb(index, W836_INDEX);
-	tmp = inb(W836_DATA) & ~mask;
-	outb(tmp | (data & mask), W836_DATA);
+	outb(reg, index);
+	tmp = inb(index+1) & ~mask;
+	outb(tmp | (data & mask), index+1);
 }
 
 /**
@@ -248,37 +245,80 @@
  *  - Agami Aruma
  *  - IWILL DK8-HTX
  */
-static int w83627hf_gpio24_raise(const char *name)
+static int w83627hf_gpio24_raise(uint16_t index, const char *name)
 {
-	w836xx_ext_enter();
+	w836xx_ext_enter(index);
 
 	/* Is this the w83627hf? */
-	if (wbsio_read(0x20) != 0x52) {	/* SIO device ID register */
+	if (wbsio_read(index, 0x20) != 0x52) {	/* Super I/O device ID register */
 		fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
-			name, wbsio_read(0x20));
-		w836xx_ext_leave();
+			name, wbsio_read(index, 0x20));
+		w836xx_ext_leave(index);
 		return -1;
 	}
 
 	/* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
-	wbsio_mask(0x2B, 0x10, 0x10);
+	wbsio_mask(index, 0x2B, 0x10, 0x10);
 
-	wbsio_write(0x07, 0x08);	/* Select logical device 8: GPIO port 2 */
+	wbsio_write(index, 0x07, 0x08);	/* Select logical device 8: GPIO port 2 */
 
-	wbsio_mask(0x30, 0x01, 0x01);	/* Activate logical device. */
+	wbsio_mask(index, 0x30, 0x01, 0x01);	/* Activate logical device. */
 
-	wbsio_mask(0xF0, 0x00, 0x10);	/* GPIO24 -> output */
+	wbsio_mask(index, 0xF0, 0x00, 0x10);	/* GPIO24 -> output */
 
-	wbsio_mask(0xF2, 0x00, 0x10);	/* Clear GPIO24 inversion */
+	wbsio_mask(index, 0xF2, 0x00, 0x10);	/* Clear GPIO24 inversion */
 
-	wbsio_mask(0xF1, 0x10, 0x10);	/* Raise GPIO24 */
+	wbsio_mask(index, 0xF1, 0x10, 0x10);	/* Raise GPIO24 */
 
-	w836xx_ext_leave();
+	w836xx_ext_leave(index);
 
 	return 0;
 }
 
+static int w83627hf_gpio24_raise_2e(const char *name)
+{
+	return w83627hf_gpio24_raise(0x2d, name);
+}
+
 /**
+ * Winbond W83627THF: GPIO 4, bit 4
+ *
+ * Suited for:
+ *  - MSI K8N-NEO3
+ */
+static int w83627thf_gpio4_4_raise(uint16_t index, const char *name)
+{
+	w836xx_ext_enter(index);
+	/* Is this the w83627thf? */
+	if (wbsio_read(index, 0x20) != 0x82) {	/* Super I/O device ID register */
+		fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
+			name, wbsio_read(index, 0x20));
+		w836xx_ext_leave(index);
+		return -1;
+	}
+
+	/* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
+
+	wbsio_write(index, 0x07, 0x09);	/* Select logical device 9: GPIO port 4 */
+
+	wbsio_mask(index, 0x30, 0x02, 0x02);	/* Activate logical device. */
+
+	wbsio_mask(index, 0xF4, 0x00, 0x10);	/* GPIO4 bit 4 -> output */
+
+	wbsio_mask(index, 0xF6, 0x00, 0x10);	/* Clear GPIO4 bit 4 inversion */
+
+	wbsio_mask(index, 0xF5, 0x10, 0x10);	/* Raise GPIO4 bit 4 */
+
+	w836xx_ext_leave(index);
+
+	return 0;
+}
+
+static int w83627thf_gpio4_4_raise_4e(const char *name)
+{
+	return w83627thf_gpio4_4_raise(0x4E, name);
+}
+/**
  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
  *
  * We don't need to do this when using LinuxBIOS, GPIO15 is never lowered there.
@@ -335,12 +375,12 @@
 	pci_write_byte(dev, 0x59, val);
 
 	/* Raise ROM MEMW# line on Winbond w83697 SuperIO */
-	w836xx_ext_enter();
+	w836xx_ext_enter(0x2E);
 
-	if (!(wbsio_read(0x24) & 0x02))	/* flash rom enabled? */
-		wbsio_mask(0x24, 0x08, 0x08);	/* enable MEMW# */
+	if (!(wbsio_read(0x2E, 0x24) & 0x02))	/* flash rom enabled? */
+		wbsio_mask(0x2E, 0x24, 0x08, 0x08);	/* enable MEMW# */
 
-	w836xx_ext_leave();
+	w836xx_ext_leave(0x2E);
 
 	return 0;
 }
@@ -487,9 +527,11 @@
 	{0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
 	 "gigabyte", "m57sli", "GIGABYTE GA-M57SLI", it87xx_probe_serial_flash},
 	{0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
-	 "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise},
+	 "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
+	{0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+	 "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e},
 	{0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
-	 "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise},
+	 "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e},
 	{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
 	 NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
 	{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
@@ -509,8 +551,8 @@
  * Match boards on LinuxBIOS table gathered vendor and part name.
  * Require main PCI IDs to match too as extra safety.
  */
-static struct board_pciid_enable *board_match_linuxbios_name(char *vendor,
-							     char *part)
+static struct board_pciid_enable *board_match_linuxbios_name(char *vendor, 
+								char *part)
 {
 	struct board_pciid_enable *board = board_pciid_enables;
 
@@ -525,10 +567,11 @@
 			continue;
 
 		if (board->second_vendor &&
-		    !pci_dev_find(board->second_vendor, board->second_device))
+			!pci_dev_find(board->second_vendor, board->second_device))
 			continue;
 		return board;
 	}
+	printf("NOT FOUND %s:%s\n", vendor, part);
 	return NULL;
 }
 
@@ -545,20 +588,20 @@
 			continue;
 
 		if (!pci_card_find(board->first_vendor, board->first_device,
-				   board->first_card_vendor,
-				   board->first_card_device))
+					board->first_card_vendor,
+					board->first_card_device))
 			continue;
 
 		if (board->second_vendor) {
 			if (board->second_card_vendor) {
 				if (!pci_card_find(board->second_vendor,
-						   board->second_device,
-						   board->second_card_vendor,
-						   board->second_card_device))
+						board->second_device,
+						board->second_card_vendor,
+						board->second_card_device))
 					continue;
 			} else {
 				if (!pci_dev_find(board->second_vendor,
-						  board->second_device))
+							board->second_device))
 					continue;
 			}
 		}
@@ -582,7 +625,7 @@
 
 	if (board) {
 		printf("Found board \"%s\": Enabling flash write... ",
-		       board->name);
+			board->name);
 
 		ret = board->enable(board->name);
 		if (ret)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-12 21:22:40 +00:00
Uwe Hermann 6dbc0e12da Superiotool manpage/documentation improvements (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-11 18:30:05 +00:00
Uwe Hermann f904a596d0 Revert my last cleanup patch.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10 17:42:20 +00:00
Uwe Hermann 5982a0641b Cosmetic changes to make the flashrom output more consistent (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-10 16:31:30 +00:00
Uwe Hermann 0446dbbd60 Fixup a register dump attached to the wrong Super I/O. Seems something
went wrong in one of the recent commits.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-08 01:59:46 +00:00
Uwe Hermann 14f304ace1 Add detection support for lots more SMSC Super I/Os (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-08 01:11:11 +00:00
Uwe Hermann 44bb777062 Some more ITE chips and small fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 21:50:29 +00:00
Uwe Hermann abeb63df5f Detection support for a bunch of NSC Super I/Os (trivial).
Also, dump support for the NSC PC87351.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 21:48:26 +00:00
Uwe Hermann e9d4616a95 Print a short message if no Super I/O chip could be detected (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 20:01:23 +00:00
Uwe Hermann 84bf1e2506 Add a list of contributors to the README (trivial). Also, a small hint
about where to send additional register dumps.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 19:10:24 +00:00
David Hendricks c387b0b89e Add dump support for the Winbond W83627THF/THG.
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 19:04:26 +00:00
Uwe Hermann 09203573c1 Add a manpage for superiotool (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 15:26:40 +00:00
Robinson P. Tryon 8a9c03f0de Dump support for the SMSC FDC37B72x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 15:12:12 +00:00
Robinson P. Tryon e1073f1a54 Dump support for the SMSC FDC37B78x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 15:04:17 +00:00
Robinson P. Tryon 87c4999672 Dump support for the SMSC FDC37M81x.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07 14:33:13 +00:00
Rasmus Wiman 409b4f2273 Add dump support for the Winbond W83627HF/F/HG/G.
Signed-off-by: Rasmus Wiman <rasmus@wiman.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 21:58:03 +00:00
Uwe Hermann 23740c82e2 Add dump support for the SMSC LPC47M10x (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 15:11:38 +00:00
Robinson P. Tryon dc81769c9c Add dump support for the ITE IT8661F. Note that this chip will not yet
be detected, as it needs a non-standard init sequence.

Minor other fix: Drop incorrect 0x2b from LDN 5 of the ITE IT8705F.

Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05 13:47:04 +00:00
Uwe Hermann 5debf36d9d Add some more Winbond chips (trivial).
Add notes which IDs were taken from sensors-detect (as where we lack
datasheets, thus cannot verify them) and which we support but sensors-detect
does not (yet). I'll post patches on the lm-sensors list to sync up
the detected chips between superiotool and sensors-detect.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 18:34:36 +00:00
Uwe Hermann db5f953754 Add detection support for the LPC47B387 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 16:28:56 +00:00
Robinson P. Tryon 4354103078 Add dump support for the ITE IT8705F/AF.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 15:44:19 +00:00
Uwe Hermann 8b8d03974e * Convert the NSC code to the common code structure all other Super I/Os use.
* Improve the --verbose output a bit more. Print the "Probing..." text for
   all Super I/Os and if a Super I/O is not known, show the data we were
   able to read from the chip (what data this is is very vendor/chip specific).

 * Thus the common no_superio_found() is dropped, it's not useful.
   The "read from 0x20" part was wrong for all Super I/Os other than the
   NSC ones anyway.

 * Winbond: For the 'olddevid' only use bits 3..0, mask away the others.

 * SMSC: Print which ID registers we try to read (in --verbose mode).

 * Minor cosmetic fixes.
   * Rename PC8374 to PC8374L (as per datasheet).
   * Rename probe_idregs_simple() to probe_idregs_nsc().
   * Rename dump_readable_ns8374() to dump_readable_pc8374l().

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 15:23:38 +00:00
Jordan Crouse 573ff508ab [FLASHROM] Fix the help, and print a message when nothing happens
The help implied that writes happen by default, which they don't.  Fix
the text, and say something when we dont specify any commands.

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>    
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-04 06:26:41 +00:00
Uwe Hermann 209148c535 Add a copy of the GPL (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-03 18:56:51 +00:00
Robinson P. Tryon ec1edd1cd9 Print superiotool version when run with --verbose.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-02 23:32:21 +00:00
Carl-Daniel Hailfinger 0de6f0a36f This patch aims to restructure SPI flash support in a more reasonable
way. It introduces a generic SPI host driver for the IT8716F Super I/O
which will enable easy SPI programming without having to care for the
peculiarities of the SPI host.

To activate probing for the IT8716F, you have to use the gigabyte:m57sli
mainboard override. SPI support will then use the gathered SPI host data
to access the SPI flash.

This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the
GA-M57SLI v2.0, which has a MX25L4005 SPI flash part.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-02 15:49:25 +00:00
Uwe Hermann e4d4ebabbd De-uglify the --version output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-01 13:39:02 +00:00
Uwe Hermann afe8309202 Random minor fixes. Use svn revision as superiotool version number.
Make the -V output more informative.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-28 15:45:43 +00:00
Uwe Hermann 945045b1ea Add support for some more Fintek chips and an ALi chip.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-28 15:39:10 +00:00
Uwe Hermann 5f45fc234f Fix up the SMSC detection code to probe _both_ old- and new-style
Super I/Os from SMSC. Otherwise not all of them are detected (and there
could theoretically be _two_ of them in a system, so we should probe
for both types anyway).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-28 15:02:17 +00:00
Carl-Daniel Hailfinger 7fe8f5da4d Add preliminary SPI flash identification support for SPI chips attached
to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte
M57SLI board. It works only with rev 2.0 of the board, but it will bail
out on earlier versions, so no damage can occur.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-27 14:29:57 +00:00
Uwe Hermann c3da36681d Add detection support for lots more Winbond Super I/Os (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26 16:14:16 +00:00
Uwe Hermann e0ffaa164d Dump support for the Fintek F71805 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-26 15:48:09 +00:00
Uwe Hermann 48cac24742 Detection support for the Winbond W83627HF (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 23:24:46 +00:00
Ward Vandewege 2ee78d8b06 Fix compilation warning.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 22:02:31 +00:00
Uwe Hermann 0f86732a5e Add detection support for quite a number of SMSC Super I/Os. Also, add
dump support for the SMSC DME1737 and the ASUS A8000. Random minor fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-24 01:40:09 +00:00
Uwe Hermann 6b4ad4304a Minor fixes/improvements in the Fintek code (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-23 13:17:29 +00:00
Uwe Hermann 420f6abc11 Add register dump capability for ITE IT8718F (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-21 14:48:04 +00:00
Uwe Hermann eddc473ce0 Add -D / --dump-readable option which prints the Super I/O register
contents in human-readable form (e.g. "COM1 enabled" etc.) instead
of the hex-table format from -d / --dump.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 23:57:44 +00:00
Uwe Hermann b4db2209f9 Decouple the ITE code from fintek.c, it doesn't belong there.
Add common 'enter configuration mode' function for most Winbond/Fintek/ITE
chips which use the 0x87 0x87 sequence for that reason.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 23:37:56 +00:00
Uwe Hermann 0702469f16 Fix up and generalize the ITE IT8708F code. It was only working out of
pure luck (and broken code elsewhere). Needs some more fixing.

Add more LDN descriptions to various Super I/Os.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 22:13:48 +00:00
Uwe Hermann 2c290e3362 Superiotool: Add dump support to the Winbond W83697HF/F.
Minor coding style changes and code simplifications.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-20 00:00:49 +00:00
Uwe Hermann e474956590 Implement usage for --help and put the same information into the README, too.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 16:26:18 +00:00
Uwe Hermann 7e7e9ac607 Add support for the Winbond W83697HF/F and W83627EHF/EF/EHG/EG.
Various minor fixes and improvements (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 15:52:23 +00:00
Uwe Hermann 3acf31e4ea Further code simplifications and improvements.
Add command line option handling code. The following options
are defined at the moment:

-d|--dump      Dump Super I/O registers.
-V|--verbose   Verbose mode.
-v|--version   Show the superiotool version.
-h|--help      Show a short help text.

Per default (no options) we just probe for a Super I/O
and print its vendor, name, ID, version, and config port.

Example:

$ ./superiotool
Found SMSC FDC37N769 Super I/O (id=0x28, rev=0x01) at port=0x03f0

$ ./superiotool -d
Found SMSC FDC37N769 Super I/O (id=0x28, rev=0x01) at port=0x03f0
idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00
def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00

$ ./superiotool -s
./superiotool: invalid option -- s

$ ./superiotool -h
Usage: superiotool [-d] [-V] [-v] [-h]

$ ./superiotool -v
superiotool 0.1


Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 01:55:35 +00:00
Uwe Hermann 25a6c0f18c Split out enter_conf_mode_*()/exit_conf_mode_() functions, we'll soon need
them. Reduce code duplication a bit by improved 'no dump available' handling.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:48:42 +00:00
Uwe Hermann de24a0e585 Use uint16_t and friends where appropriate (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-19 00:03:14 +00:00
Uwe Hermann d754d2c6c4 Make the code a bit more generic (trivial). Different Super I/Os
use different config ports.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-18 23:30:24 +00:00
Uwe Hermann 6ff6af7621 Superiotool: Add support for the SMSC FDC37N769.
Here's what a register dump looks like on my test system:

No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
Super I/O found at 0x03f0: id=0x28, rev=0x01
SMSC FDC37N769
idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 
val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00 
def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00 
Probing 0x0370, failed (0xff), data returns 0xff

I'm self-acking this as it's pretty simple stuff, but please let me
know if anything could be improved here, or if you think this
is not trivial enough to warrant self-acking.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-18 22:24:34 +00:00
Uwe Hermann d8a18a2adb Add a README for superiotool (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-18 00:01:27 +00:00
Uwe Hermann 519419b476 Split out a dump_superio() function from ite.c, and make it slightly more
generic, so that we can use it for other Super I/Os, too.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-16 20:59:01 +00:00
Uwe Hermann 4cb7e71732 Make 'struct superio_registers' globally available, pretty much
all Super I/Os can (and should!) use this (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-16 18:17:44 +00:00
Uwe Hermann 0120e1a3d8 Split up superiotool.c into multiple source files, one per vendor.
As there will be lots more supported Super I/Os soon, the file is
really getting way too big...

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-16 18:11:03 +00:00
Alex Beregszaszi 7798c888e8 Change out/in combinations to pci_read/write_byte in
sis630 chipset enable.

Signed-off-by: Alex Beregszaszi <alex@rtfs.hu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-11 15:58:18 +00:00
Uwe Hermann f9b0f7fd91 Remove useless 'extern' keywords (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2769 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 20:24:29 +00:00
Uwe Hermann 863c1bf525 Add '(C)' where it's missing (for consistency reasons).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 20:21:05 +00:00
Uwe Hermann 09735cb517 Add missing license header to udelay.c.
I'm self-ack'ing this, as the origin of the code in udelay.c (and thus
the license and copyright owner) is pretty clear.

The code which is now in udelay.c was split out from flash_rom.c in r1428,
and flash_rom.c, in turn, has been around since the beginning and had a
'Copyright 2000 Silicon Integrated System Corporation' line as well as the
usual GPLv2-or-later license header.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-09 20:02:45 +00:00
Uwe Hermann 9398958cfa Add a copy of the GPL in the flashrom repository as it's an independent
project (being packaged by distros, among other things).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-08 14:36:01 +00:00
Uwe Hermann 98ef9cefc8 Small consistency fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 21:20:29 +00:00
Uwe Hermann 2046ff92f0 Various coding style and whitespace fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 21:02:44 +00:00
Carl-Daniel Hailfinger c4c54a5df3 Add ITE IT8716F support to probe_superio. This helps especially
GA-M57SLI board owners who wish to debug remaining problems or handle
SPI flash of newer board versions.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 20:24:30 +00:00
Uwe Hermann 1ae8e83baa Rename probe_superio.c to superiotool.c.
Flesh out Makefile with all the usual stuff, e.g. install targets etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 20:20:41 +00:00
Uwe Hermann 8c14e45bfd Move probe_superio into the global util/ directory.
Rename it to superiotool while we're at it.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 19:44:36 +00:00
Uwe Hermann bd26392f42 Add support for the ITE IT8708F.
Here's a dump from my test system which has an IT8708F:

No SuperI/O chip found at 0x002e
probing 0x002e, failed (0x87), data returns 0x87
SuperI/O found at 0x2e: id=0x8708, chipver=0x0
ITE IT8708
idx 07 20 21 22 23 24 25 26 27 28 29 2a 2e 2f 
val 02 87 08 00 00 00 00 00 03 01 01 00 00 00 
def NA 87 08 00 00 NA 3f 00 ff ff ff ff 00 00 
switching to LDN 0x0
idx 30 60 61 70 74 f0 f1 
val 01 03 f0 06 02 00 80 
def 00 03 f0 06 02 00 00 
switching to LDN 0x1
idx 30 60 61 70 f0 
val 01 03 f8 04 00 
def 00 03 f8 04 00 
switching to LDN 0x2
idx 30 60 61 70 f0 f1 f2 f3 
val 01 02 f8 03 00 50 01 7f 
def 00 02 f8 03 00 50 00 7f 
switching to LDN 0x3
idx 30 60 61 62 63 64 65 70 74 f0 
val 01 03 78 07 78 00 80 07 03 0b 
def 00 03 78 07 78 00 80 07 03 03 
switching to LDN 0x4
idx e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 
val 80 61 00 00 00 00 00 00 80 00 30 00 80 00 de 
def NA NA 00 00 00 00 00 00 00 00 00 00 00 NA NA 
switching to LDN 0x5
idx 30 60 61 62 63 70 71 f0 
val 01 00 60 00 64 01 02 0c 
def 01 00 60 00 64 01 02 00 
switching to LDN 0x6
idx 30 70 71 f0 
val 01 0c 02 00 
def 00 0c 02 00 
switching to LDN 0x7
idx 70 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c5 c8 c9 ca cb cc cd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc 
val 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03 01 01 00 00 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 7f 20 51 00 0e 00 00 00 00 00 00 00 
def 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA NA NA NA NA NA 00 00 00 00 00 00 00 00 00 00 00 NA 00 
switching to LDN 0x8
idx 30 60 61 
val 00 02 01 
def 00 02 01 
switching to LDN 0x9
idx 30 60 61 70 f0 
val 00 03 10 0b 06 
def 00 03 10 0b 00 
switching to LDN 0xa
idx 30 60 61 70 f0 
val 00 03 00 0a 40 
def 00 03 00 0a 00 
No SuperI/O chip found at 0x004e
No SuperIO chip found at 0x004e
No SuperIO chip found at 0x004e

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-09-01 19:42:42 +00:00
Uwe Hermann 8a5a264748 Fix typo for the ITE IT8712F (trivial).
The default for LDN 5 (keyboard), index 0xF0 is not 0x00
but rather 0x08 as per datasheet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-31 20:51:00 +00:00
Markus Boas 736c1d8618 Add support for the Winbond W29EE011.
Signed-off-by: Markus Boas <ryven@ryven.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30 10:17:50 +00:00
Markus Boas 3b78de6887 Add support for the Winbond W29C040P.
Signed-off-by: Markus Boas <ryven@ryven.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-30 10:11:08 +00:00
Uwe Hermann 6c71f73786 Change all flashrom license headers to use our standard format.
No changes in content of the files.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-29 17:52:32 +00:00
Carl-Daniel Hailfinger b1786c2bce This patch makes ITE Super I/O probing/dumping a little bit more generic,
fixes minor coding style issues and prepares the table for supporting
more chips of the ITE IT87xx Super I/O family.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-28 10:43:57 +00:00
Carl-Daniel Hailfinger 7a7890aced This patch rewrites probe_superio almost completely.
Common code sequences have been factored out, the code has been made
more generic, has better handling of corner cases and is actually much
shorter.

It also adds probing for almost all recent (since 1999) ITE Super I/O
chips to probe_superio. I did verify against all ITE datasheets
(including those not available any more) that the probing was
non-destructive.

For the ITE IT8712F, the complete configuration is dumped and as
comparison the default value from the data sheet is printed.
More information can be extracted easily, however this needs loads of
datasheet surfing.

This code has been tested extensively, dumping for other ITE chips will
follow as a separate patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-27 07:28:28 +00:00
Uwe Hermann ba9ce9f7f9 Cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 16:08:21 +00:00
Uwe Hermann 0a6bb91062 Drop duplicated code (copies of plain JEDEC functions).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 15:20:38 +00:00
Uwe Hermann 2fe239134c Drop a bunch of useless header files, merge them into flash.h.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 13:34:59 +00:00
Uwe Hermann 3a9bbc2cc8 Move code into *.c files, there's no reason to have it in header files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-23 10:20:40 +00:00
Ed Swierk 3436698b6a Fix bug in probe_28sf040() causing flash corruption on SST49LF160C verify.
The first byte of the flash chip was read at the start of the function
and later written back to address 0 if the flash chip was not identified
as SST28SF040, which means most of the time. This write caused corruption
of flash contents when verifying a SST49LF160C part.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-13 04:10:32 +00:00
Luc Verhaegen 4d43255bef flashrom: Add board enable for the EPoX EP-BX3.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-08-11 16:59:11 +00:00