Since there is only one device ID used for UART,
an array is not needed. Therefore, just save the
device ID to the device variable.
Change-Id: Icd325e1102a85cc175f6025519a47a1b64ee5b46
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch moves the PCI ID definitions to pci_ids.h file
and replaces every occurrence with the new names.
The resulting binary doesn't differ from the one
without this patch.
Used documents:
- Intel 337018
Change-Id: Ib7d2aae78c8877f3c9287d03b20a5620db293445
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This time, it failed to build if measured boot was not enabled. Fix this
problem, and make sure flashconsole will not break like that again.
Change-Id: I5f5ffd14a3225804524cb0c1518e3d99737e0a93
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move print_me_fw_version(), remove print_me_version/dump_me_version from
cnl/skl/apl and make changes to call print_me_version() which is defined
in the CSE lib.
TEST=Verified on hatch, soraka and bobba.
Change-Id: I7567fac100b14dc207b7fc6060e7a064fb05caf6
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch includes the change required to display Apollo Lake platform
information which reports CPU, MCH, PCH and IGD information in romstage.
BUG=None
TEST=
1. Boot to OS on Bobba board.
2. Verified below info from CPU Console log in romstage
CPU: Intel(R) Celeron(R) N4000 CPU @ 1.10GHz
CPU: ID 706a1, Geminilake B0, ucode: 00000031
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 31f0 (rev 03) is Geminilake
PCH: device id 3197 (rev 03) is Geminilake
IGD: device id 3185 (rev 03) is Geminilake EU12
Change-Id: Id4edfeae7faee9f5f80698cf34b31fdcb066a813
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38824
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.
TEST=Able to connect ITP/DCI with target system.
Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
The following plumbs through the enabling of Intel's TetonGlacierMode
allows for reconfiguring the PCIe lanes at runtime for hybrid drives
to be accessable via devicetree.
BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.
Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch overrides required FSP-S UPDs to enable 8254 timer
support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected.
TEST=Required to boot TianoCore payload.
Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This patch makes all legacy 8254 FSP UPDs (Enable8254ClockGating and
Enable8254ClockGatingOnS3) depend on CONFIG_USE_LEGACY_8254_TIMER to
avoid discrepancy between S0 and S3 resume flow.
TEST=Able to boot to TianoCore without any hangs and errors, also
verified S3 resume path doesn't clock gate 8254 timer using FSP-S UPD.
Change-Id: Id6fe74a51537abbb9ff48db925e37a64e5b21f78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39110
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch cleans soc/intel/{cnl, icl, tgl} by moving common
soc code into common/block/cse.
Supported SoC can select existing HECI_DISABLE_USING_SMM option to
select common cse code block to make heci function disable using
sideband interface during SMM mode at preboot envionment.
BUG=b:78109109
TEST=Able to make HECI disable in SMM mode successfully without any hang
or errors in CNL, ICL and TGL platform.
Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Thermal Design Current (TDC) defaults for CML:
1. TdcEnable
2. TdcPowerLimit
BUG=b:148912093
BRANCH=None
TEST=build coreboot and Intel FSP with fw_debug enabled, flash image to
the device, capture the log from the serial port during boot-up and
check TdcEnable and TdcPowerLimit for each domain in captured log
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ie4b17e5b4ce41c1adb436ae5646f0d8578a440e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Default FSP values for "GtFreqMax" and "CdClock" UPDs are "Auto", hence
related FSP-S UPD override can be avoided from coreboot.
As per FSP-S UPD Header (FspsUpd.h)
/** Offset 0x020E - GT Frequency Limit
0xFF: Auto(Default)
**/
UINT8 GtFreqMax;
/** Offset 0x0209 - CdClock Frequency selection
0: (Default) Auto
**/
UINT8 CdClock;
TEST=Able to get Pre-OS display on ICLRVP and Dragonegg platform.
Change-Id: Ie500dd5fad5cd358ea3fad4d5c0be1b0c148584b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This patch makes all bit field macro definition for SMI_STS register
(offset 0x44) be consistent i.e. ending with "_STS_BIT".
Also modified relevant files where those macros are getting used.
Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The STM is a part of the core VTx and using ENABLE_VMX will make the
STM option available for any configuration that has an Intel
processor that supports VTx.
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: I57ff82754e6c692c8722d41f812e35940346888a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38852
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tigerlake irq.h and pci_irqs.asl have differences compared to
Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as
pci_irqs_tgl.asl
Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake
SoC and allowing irq.h and pci_irqs.asl to choose the correct file based
on SoC selected.
BUG=None
BRANCH=None
TEST=Compilation for Jasperlake board is working
Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
PCH_DEV_P2SB already covers both __SIMPLE_DEVICE__ cases. The values are
only used for PCI-config access functions, which also check for NULL
when necessary.
The PCI_DEV_INVALID case can't occur by definition, and if we wanted to
check, we could do so at compile time using _Static_assert().
Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Below helper function is added:
cse_wait_com_soft_temp_disable() - It polls for CSE's operation mode
'Soft Temporary Disable'. CSE enters this mode when it boots from
RO(BP1) partition. The function must be called after resetting CSE to
wait for CSE to enter 'Soft Temporary Disable' Mode.
BUG=b:145809764
Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Send HMRFPO_GET_STATUS command when CSE's current working state is Normal.
TEST=Verified on hatch.
Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Configure UPDs to support Audio enablement.
Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Make sure the Skylake comment refers to the correct BWG paragraph and
update the text for all.
BUG=N/A
TEST=build
Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI
offset 0x80. This is specified in PCH BWG par 2.5.1.5.
Add the support to make sure this PCR is always set correctly.
BUG=N/A
TEST=tested on facebook monolith.
Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With CL:1940398, this option is no longer needed. Recovery
requests are not cleared until kernel verification stage is
reached. If the FSP triggers any reboots, recovery requests
will be preserved. In particular:
- Manual requests will be preserved via recovery switch state,
whose behaviour is modified in CB:38779.
- Other recovery requests will remain in nvdata across reboot.
These functions now only work after verstage has run:
int vboot_check_recovery_request(void)
int vboot_recovery_mode_enabled(void)
int vboot_developer_mode_enabled(void)
BUG=b:124141368, b:35576380
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI files for xhci in JSL is different from TGL. Hence, renaming
xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL.
Also, allowing xhci.asl to choose the correct file based on the SoC
selected.
BUG=None
BRANCH=None
TEST=Compilation for JasperLake board is working
Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
By updating the FSP submodule we now got all FSP headers from within
that repo. This commit changes the default paths to use these and
fixes some include paths to allow the usage of
vendorcode/intel/edk2/UDK2017 together with the official Intel
distribution.
We are also adding back the CHANNEL_PRESENT enum, that is
missing in the official headers.
This was tested on the Razer Blade Stealth (late 2019).
Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add function to return the fixed io decode ranges contained in register
0x80 of the LPC interface.
BUG=N/A
TEST=build
Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Selecting STM on an arbitrary platform would likely result in a brick,
so let's hide the prompt by default.
Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <cedarhouse1@comcast.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move some of the common memory code that was being performed in
mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Below changes have been implemented in send_heci_reset_req_message():
1. Modify return values to align with other functions in the same file.
2. Add additional logging.
3. Replace macro definitions of reset types with ENUM.
4. Make changes to caller functions to sync with new return values.
5. Rename send_heci_reset_req_message() to cse_request_global_reset().
Test=Verified on hatch board.
Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Below changes are implemented:
1. Fix typos.
2. Rename 'padding' field of hmrfpo_get_status_resp struct to
'reserved' to match with ME BWG Guide.
3. Add documentation for HMRFPO Status.
TEST=Build and boot hatch
Change-Id: I4db9bdf7386c48e17ed0373cf334ccff358d1951
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Below changes are implemented:
1. Move HFSTS1 register definition to SoC since HFSTS1 register definition
is specific to a SoC. Moving structure back to SoC specific to avoid
unnecessay SoC specific macros in the common code.
2. Define a set of APIs in common code since CSE operation modes and
working states are same across SoCs.
cse_is_hfs1_com_normal(void)
cse_is_hfs1_com_secover_mei_msg(void)
cse_is_hfs1_com_soft_temp_disable(void)
cse_is_hfs1_cws_normal(void)
3. Modify existing code to use callbacks to get data of me_hfs1 structure.
TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards.
Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Originally a part of security/intel/stm.
Add get_pmbase to the intel platform setup code.
get_pmbase is used by the coreboot STM setup functions to ensure
that the pmbase is accessable by the SMI handler during runtime.
The pmbase has to be accounted for in the BIOS resource list so
that the SMI handler is allowed this access.
Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2
Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With Audio DSP OSC qualification disabled from S0ix criteria.
S0ix is achieved before the DSP is suspended. When driver tries
to suspend DSP its already turned off.
BUG=b:139481313
Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes duplicate CPUID entry between KBL and CFL.
CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL
CPUID (0x806EA) for CFL-D0.
TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with
CPUID 0x806EA.
Change-Id: I078dd7860891896b512967dc8dec5dd94d069193
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to
some value which can't be overriden outside of soc/intel/common. So
adding a non-SoC platform thats uses code from soc/intel/common is not
possible.
TEST=build test on wip platform
Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
This patch adds CMP-H LPC IDs.
TEST=Build an image and boot with discrete TPM chip.
Enable measured boot and kernel could get the measured
data from TPM chip.
Change-Id: I7eac8b0514f79b47a05973210e2472dd1dc3d0ed
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38251
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fwts method test reports errors on the methods implementing
processor throttling control. The T states are not supported in coreboot
at this moment.
Remove the methods required by processor throttling control. They can be
restored when the required support has been added to the SoC
implementation.
BUG=https://ticket.coreboot.org/issues/252
TEST=tested using fwts on facebook monolith.
Found-by: fwts 19.12.00
Change-Id: Ib50607f60cdb2ad03e613d18b40f56a4c4a4c714
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
TGL FSP does just pin mux for image clock pins by UPD and image clocks
are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder.
Disable image clocks by UPD for bypassing FSP pin mux and do pin mux
in gpio.c according to board design.
BUG=none
BRANCH=none
TEST=Build and boot to OS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The names of each spi flash cause quite a bit of bloat in the text
size of each stage/program. Remove the name entirely from spi flash
in order to reduce overhead. In order to pack space as closely as
possible the previous 32-bit id and mask were split into 2 16-bit
ids and masks.
On Chrome OS build of Aleena there's a savings of >2.21KiB in each
of verstage, romstage, and ramstage.
Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch updates SA DRAM registers bit definitions as per
SKL datasheet vol 2, doc 332688.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As per PC client TPM specification, the TPM description contains the
base address of the TIS interface 0xfed40000 and the size of
the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed
system memory from getting used by OS.
Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence
additional reservation might not required.
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds ASL methods like GRXS, GTXS, STXS and CTXS
which are used to get, set and clear gpio values. We use
ASL 2.0 syntax here for gpio.asl.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board
Change-Id: I17e75ff2a7cb67e94669059a1ed9d73a720ebcb1
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38442
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups in coreboot so that they are mapped properly.
GPIO comuinities in coreboot should match with the kernel gpio
communities also. Kernel reads the ASL file from coreboot. This
patch adds the proper community mapping in ASL code to match with
kernel code. In gpio_soc_defs.c file we are indexing the groups
correctly. In gpio.h file we define all the gpio devices as kernel
populates sysfs with separate gpio device for each community. This
patch is created based on Intel Tiger Lake Processor PCH Datasheet
with Document number:575857 and Chapter number:27.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. In /sys/kernel/debug/pinctrl
verify INTC34C5:0<1-3> listing all the pins for each community.
e.g., #cat /sys/kernel/debug/pinctrl/INT34C5:00/pins should list
all the community 0 pins.
Change-Id: I40c386db060d84c1b7fba9c587f960d6a92f84ba
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Configure SATA FSP UPD according to mainboard design.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates system agent related registers bit definitions
as per EDS.
For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.
CNL EDS doc number: 566216
Also provide provision to program 64bit values as per SA EDS definitions
TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.
Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups from coreboot so that they are mapped properly.
GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h are used to
configure the MISCCFG registers.
BUG=b:144680462
BRANCH=none
TEST=Build and boot tigerlake rvp board. Verified that after
setting the gpe from devicetree the GPP_EN register for
that community gets updated setting that specific bit.
From the iotools i checked that GPE_EN register for that
community is updated with that specific bit set to 1.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I585100375feee39b5a9105bdf6d9f5ca3a5bb2fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Add Elkhartlake CPU, SA and PCH IDs.
EHL PCH is code named as MCC.
Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update interrupt header and interrupt mapping per Intel Silcon reference code.
Need to match pci_irqs.asl with FSP setting which followed by PCH BIOS spec.
Reference
PCH BIOS spec#613495
https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSiliconPkg
/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/PeiItssPolicyLibVer2.c
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iffc4efad4d0aa55fc0de88d7fe32c0356dbc3c60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38258
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates pci dev definition according to TGL EDS.
Add GSPI3 case in chip.c according to updated pci dev definitions.
Reference
TGL Process EDS#575681 rev1.0
TGL PCH EDS#576591 rev1.2
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4717ac3cc877b13978b18ada504740512f10c709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38341
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the CBFS locator override for the Apollolake SoC and
instead integrates the extra sanity check it was used for straight in
the boot device initializer.
Change-Id: Iccdb885be233bb027a6a1f2cc79054582cbdf3fc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch moves common pch code SOC_INTEL_COMMON_BLOCK_THERMAL Kconfig selection
into SoC specific Kconfig selection as PCH thermal device is not available
with latest PCH (i.e. TGP and JSP).
Also added TODO for TGL thermal configuration as applicable.
TEST=Able to build and boot TGL RVP with this CL
Change-Id: Ibce17cc9f38fb666011ccd8f97bee63033ff5302
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38444
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fast spi driver implements hardware sequencing which abstracts away
the underlying spi flash commands in the hardware block. It also has its
own spi flash probe function to intercept the spi flash ops. As such it's
not necessary to include all spi flash drivers.
On a hatch Chrome OS build this saves 9.5KiB of text in each of verstage,
romstage, and ramstage.
Change-Id: Ifb1b962cde3a6a02353ddf83279234057a9ec2fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a new Kconfig option, SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS,
to make it easier for other parts of the code base to indicate that
all spi flash drivers should not be included.
Change-Id: Ibf2c4f1d2b8a73cff14bb627ddf759d7970920ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This avoids including platform-specific headers with different
filenames from common code.
Change-Id: Idf9893e55949d63f3ceca2249e618d0f81320321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
New Kconfig for Jasperlake soc was created and fsp_param for Jasperlake
has differences compared to Tigerlake. Thus renaming fsp_params.c to
fsp_params_tgl.c to point out correct file as per soc selected.
Also adding new file for fsp_param_jsl for Jasperlake SoC and currently
its the copy of fsp_param_tgl.
TODO: update files with correct fsp_params
Change-Id: I12815ae28a1eb4c64afda0a85b5c14fc0da3e4b1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37267
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also change some of the types to match the register widths
of the controller. It is expected that these prototypes
will be used with SMBus host controllers inside AMD chipsets
as well, thus the change of location.
Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to use the more recent version in sb/intel/common.
Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
