Commit Graph

753 Commits

Author SHA1 Message Date
Eric Biederman 709850a21b - Ensure every copy of Options.lb uses:
CROSS_COMPILE
  CC
  HOSTCC
  OBJCOPY


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 10:48:04 +00:00
Eric Biederman 41d0fa38af - Modify all of the Opteron motherboards to have a separate logical
chip for the amdk8/root_complex


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 07:26:56 +00:00
Eric Biederman 8bd555297e - Add a new chip northbridge/amd/amdk8/root_complex
- Moving the functionality around in northbridge/amd/amdk8/northbridge.c
  to put the pci_domain and the apic bus on the root_complex.
  Everything else remains with the individual northbridges.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 07:04:54 +00:00
Yinghai Lu 7bf1b48bd4 *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 03:44:01 +00:00
Li-Ta Lo 9562049df5 reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 23:42:54 +00:00
Yinghai Lu b2d77282e0 debug device added
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 22:36:18 +00:00
Li-Ta Lo 652ae6f533 we decide not to enable BM DAM form them
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 21:48:39 +00:00
Yinghai Lu 8085f032f8 SI Class code check
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 21:00:13 +00:00
Li-Ta Lo 2d2bdd3846 removed #if 0 #endif code
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 20:31:04 +00:00
Li-Ta Lo f84926efca tell people that the segment descriptors are different for ROMCC and
GCC code.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 18:36:06 +00:00
Li-Ta Lo 1995f1af35 removed the comment in the very beginning of hardwaremain(). I don't
think it is relevant now.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 18:33:33 +00:00
Eric Biederman 23bc47db17 Add Options.lb to various motherboard ports
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 11:09:12 +00:00
Eric Biederman 018d8dd60f - Update abuild.sh so it will rebuild successfull builds
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 11:04:33 +00:00
Yinghai Lu 4403f60823 *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-03 00:47:40 +00:00
Stefan Reinauer e507c85fe3 This hurts more than it helps. byebye
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-03 00:10:15 +00:00
Stefan Reinauer e4932dc760 get qemu-i386 target building again
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 20:33:12 +00:00
Yinghai Lu bf8bb42d6a *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 18:05:22 +00:00
Yinghai Lu 3974363f09 *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 17:46:43 +00:00
Yinghai Lu 9434c1b661 Tyan update for ROM_IMAGE_SIZE > 64K
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 02:34:28 +00:00
Stefan Reinauer 0979969732 fix solo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-31 23:03:10 +00:00
Eric Biederman 432aa6a255 - Update console.c to have non-inline versions of functions
- Add exception.c
  Sorry for not including these ealier.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30 22:59:35 +00:00
Eric Biederman f8a2dddb57 - To reduce confuse rename the parts of linuxbios bios that run from
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30 08:05:41 +00:00
Mark Wilkinson 0afcba7a3d Changes to allow Via/Epia code to be compiled after recent code changes.
New Files :-
	src/cpu/via/model_centaur/Config.lb
	src/cpu/via/model_centaur/model_centaur_init.c

Updated Files :-
	src/arch/i386/include/arch/smp/mpspec.h
		- make write_smp_table a define for non smp systems
	src/cpu/x86/lapic/lapic_cpu_init.c
		- change possible typo
	src/mainboard/via/epia/Config.lb
	src/mainboard/via/epia/Options.lb

	src/mainboard/via/epia/auto.c
	src/mainboard/via/epia/chip.h
	src/mainboard/via/epia/failover.c
		- updated after recent code changes
	src/northbridge/via/vt8601/chip.h
	src/northbridge/via/vt8601/northbridge.c
	src/northbridge/via/vt8601/raminit.c
		- corrections after recent code changes to allow compiling
	src/southbridge/via/vt8231/chip.h
	src/southbridge/via/vt8231/vt8231.c
		- initial pass to allow compiling after recent code changes.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-29 16:16:43 +00:00
Yinghai Lu 97035448f3 *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-28 18:44:38 +00:00
Eric Biederman 79186eaecd - Look for all 8 possible cpus
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 18:54:13 +00:00
Stefan Reinauer a58cd524fb some more porting to the merge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 17:27:10 +00:00
Eric Biederman 6e53f50082 sizeram removal/conversion.
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 08:53:57 +00:00
Yinghai Lu 20fc678d65 spare 4s for restart
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 02:12:22 +00:00
Eric Biederman 63f2f721b4 - kill the broken and duplicate 855pm directory. Hopefully I have kept
the least broken one.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:58:26 +00:00
Eric Biederman dfde9bb649 - Actually enable the Pentium-M cpus
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:18:47 +00:00
Eric Biederman 3566b3d545 - Bug fixes to the P-III support
- Initial Pentium-M support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:18:16 +00:00
Yinghai Lu eefdb03898 S2885 winbond Superio all resource set
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 00:37:30 +00:00
Yinghai Lu fb198640d8 ops and tsc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 19:55:30 +00:00
Yinghai Lu 9cf950ca5a s2735 minor changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 19:49:50 +00:00
Ronald G. Minnich 3f637906c4 added file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 16:01:30 +00:00
Ronald G. Minnich 7ae74b40bf from Mark Wilkinson, some fixes.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 14:57:24 +00:00
Eric Biederman 8e2847c28e - For now use port 0x80 based delays in for the e7501 memory initialization.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 03:00:02 +00:00
Eric Biederman 60216355d2 - With Xeon cpus it seems best to use the tsc calibrated with timer2 as
the time source.  The apic timer also has a variable time base.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 02:47:13 +00:00
Eric Biederman 720a8f57ef - Update e7501 northbridge.c to work in the new structure.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 02:32:23 +00:00
Yinghai Lu 8abb054c0e *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 00:05:22 +00:00
Yinghai Lu 2560dbdd50 for S2735 support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 21:33:08 +00:00
Yinghai Lu e99433157b *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 21:03:26 +00:00
Yinghai Lu 79cf1be9e4 *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 18:49:09 +00:00
Yinghai Lu ccf0bc01aa s2735 half update
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 18:45:36 +00:00
Eric Biederman a1653cfea5 - Better memory I/O space distinguishing in amd_mtrr.c
This is way to much code duplication but for now things work.
- Fix the typo in amd8111_lpc.c
- Remove an unused macro, use continue instead of break in mtrr.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 04:41:53 +00:00
Eric Biederman 4f9265fdc6 - kill typo so resources are not mixed up in amdk8/northbridge.c
- Enable resources on the lpc bus.  PCI now longer do this by
  default for their children unless they are bridges.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 02:33:51 +00:00
Stefan Reinauer 584e078231 adapt config files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 20:52:53 +00:00
Stefan Reinauer 800a55bb5c get solo building after last infrastructure changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 18:51:13 +00:00
Stefan Reinauer a49f4161f5 update failover handling of some amd64 boards
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 17:06:49 +00:00
Eric Biederman dbec2d4090 - Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 10:44:08 +00:00
Eric Biederman f3aa4707d3 - Explicitly disable the fixed dram extensions bits.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 02:53:25 +00:00
Eric Biederman 29490a17ce - We already know the cache is disabled so don't bother disabling it.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 02:43:15 +00:00
Yinghai Lu f19e2c766a better support enable_dev for amd8111
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 01:52:21 +00:00
Yinghai Lu 6014983bab add Option.lb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20 17:54:01 +00:00
Yinghai Lu 6a61d6a4ae Tyan update to work with new CPU Config
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20 05:07:16 +00:00
Eric Biederman abed01d81d - Fix typo with reversing memory resources.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 23:35:53 +00:00
Li-Ta Lo 812688bf3c change struct chip* to struct device*
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 17:49:32 +00:00
Stefan Reinauer de24e61df7 - add support for socket 754
- fix configuration creation for amd solo (doesn't compile yet)


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 10:30:32 +00:00
Eric Biederman a172d98233 - Fix bug with > 4GB of memory where PAE was left enabled.
Why didn't this show up until I had > 4GB on one cpu?


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 05:07:18 +00:00
Eric Biederman 04da1d35d1 - Bump MAX_LINKS to 4 I have actually found an i2c bridge that needs this
- Fix the hdama Config.lb to not longer use the link keywords oops,
  and instead to have it nest everything properly.
- Update config.g to not support the link keyword
- update config.g to not support northbridge/southbridge/cpu/pmc noise words
  we can just use chip now.
- Remove old link handling from the code
- Detect and handle duplicate paths so we generate one device with multiple links


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 19:58:35 +00:00
Eric Biederman 858ac5c5cd - Make all ports use config.h for if they have chip_config or chip_info structures.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 09:13:23 +00:00
Eric Biederman 92986807bb - Cleanup the bugfix in elfboot.c
- Add forgotten amd8111 chip.h


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 08:45:29 +00:00
Eric Biederman f3ed1cfad7 - HDAMA boots!
- Set the bootstrap processor flag in the mptable.
- Implement 64bit support in our print statements
- Fix the reporting of how many cpus we are waiting to stop.
  It is the 1 less than the actual number of cpus running.
- Actually enable cpu_initialization.
- Fix firstsiblingdevice in config.g
- Add IORESOURCE_FIXED to all of the resources set by config.g
- Fix the apic_cluster rule to add an apic_cluster path not an apic path.
- Add a div64.h to assist in the 64bit printf.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 08:38:58 +00:00
Eric Biederman 7003ba4a88 - First stab at running linuxbios without the old static device tree.
Things are close but not quite there yet.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 06:20:29 +00:00
Eric Biederman 216525d1fd - Fix config.g and the hdama config so everthing builds again.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 02:48:37 +00:00
Li-Ta Lo e2ad5ce697 fixed function prototype for die()
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 23:05:08 +00:00
Eric Biederman 3287f0b9a1 - Change broken usage of get_resource to find_resource.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 23:02:00 +00:00
Eric Biederman 448bd635c0 - Finish interrupted merge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:52:15 +00:00
Ronald G. Minnich e5ac2959bb oops.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:44:26 +00:00
Eric Biederman 119e00e2e1 - Fix fat fingered merge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:35:23 +00:00
Eric Biederman 3614eebc13 - Update so we no longer require console.inc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:29:26 +00:00
Eric Biederman 1944680bfd - Sync up northbridge/amd/amdk8
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:06:29 +00:00
Eric Biederman 297b06e6f9 - Update the header files in reset_test.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:55:53 +00:00
Eric Biederman 73f2282ea1 - Add a generic device that does nothing
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:43:24 +00:00
Ronald G. Minnich 4b93394872 more breakage, thanks to Ron
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:40:58 +00:00
Eric Biederman 03acab694b - Updates for 64bit resource support, handling missing devices and cpus in the config file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:25:53 +00:00
Eric Biederman 992cd008f1 - Update the device header files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:10:23 +00:00
Eric Biederman b78c1972fe - First pass through with with device tree enhancement merge. Most of the mechanisms should
be in place but don't expect anything to quite work yet.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:54:17 +00:00
Eric Biederman cadfd4c462 - Add arch/cpu.h
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:52:22 +00:00
Eric Biederman 65186ce66c - remove old cpu header files
- Update cpu.h for the new cpu initialization scheme


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:15:40 +00:00
Eric Biederman c84c1906b7 - Renamed cpu header files
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:13:01 +00:00
Eric Biederman b84166e8e5 - remove deprecated directories
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 19:39:27 +00:00
Eric Biederman fcd5ace00b - Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 19:29:29 +00:00
Ronald G. Minnich 02fa3b2743 epia-m support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06 17:33:54 +00:00
Ronald G. Minnich 4fa89208a1 f'ing thing still won't work.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06 17:19:49 +00:00
Ronald G. Minnich ed9f18d545 mods for i855pm that don't seem too wrong. ha!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30 22:50:13 +00:00
Ronald G. Minnich a4779e80c3 digital logic stuff, fixes for the smbus code in 82801dbm
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30 16:37:22 +00:00
Ronald G. Minnich a26c8ef2a0 add support for ICH4. more i955pm stuff.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-28 20:09:06 +00:00
Stefan Reinauer c3c27a50d9 add include to fix build
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-09 07:19:40 +00:00
Li-Ta Lo 7b08c116b9 removed unused code, code reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-07 21:20:53 +00:00
Li-Ta Lo 981faa09e4 rename variable from addr to dev
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-07 19:24:40 +00:00
Ronald G. Minnich 43dd85e7ec more fixes.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-30 16:08:30 +00:00
Stefan Reinauer 009f87a30b build fix for epia-m so that nobody beats ron to it ;)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-27 21:39:59 +00:00
Ronald G. Minnich 6707a45eb1 just a few changes before we hit the big fun.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-26 16:13:40 +00:00
Ronald G. Minnich 1ddc8eaddb more updates for 855
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-25 18:19:08 +00:00
Ronald G. Minnich e6552bcf39 changes for the dbm part. Still need to remove the sata file ...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-25 15:40:47 +00:00
Ronald G. Minnich 3b0096313a compiles.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 22:27:55 +00:00
Ronald G. Minnich 74bfa2c8b2 stupid ron! need to start names with a letter.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 22:17:33 +00:00
Ronald G. Minnich 7da4d6a089 start of port of adl855pc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 17:29:29 +00:00
Ronald G. Minnich 0fb38825cb fixed up tables.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 17:23:37 +00:00
Ronald G. Minnich 182615d635 new intel io hub.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 16:20:46 +00:00
Ronald G. Minnich c66444c175 new mainboard
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24 16:11:50 +00:00
Ronald G. Minnich 300e1b569a random fixes.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23 21:04:36 +00:00
Ronald G. Minnich 92d159f27d dpx114
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23 20:41:25 +00:00
Ronald G. Minnich 55a6d461a6 new mobo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23 20:25:17 +00:00
Ronald G. Minnich 03935036ab adding 855pm
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23 16:43:25 +00:00
Stefan Reinauer 198409afe0 create some technologic systems ts530 infrastructure
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-07 19:58:46 +00:00
Stefan Reinauer 40ab2d1213 add Config file for ts5300
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-07 19:34:46 +00:00
Li-Ta Lo 4c5060dc2b move default_resource_map to its own file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08 16:59:06 +00:00
Li-Ta Lo f76a613a9a code reformat, removed unused code
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08 16:57:43 +00:00
Li-Ta Lo 9ab91f5acb code reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-08 16:54:20 +00:00
Ronald G. Minnich badf114438 fixed again.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-06 16:57:44 +00:00
Ronald G. Minnich 737de849d5 fix for simple error
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-06 16:35:50 +00:00
Yinghai Lu e89137b2ad remove_logical_cpus need call get_option
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01 04:21:49 +00:00
Yinghai Lu 70093f7875 Intel E7501 P64H2 ICH5R support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01 03:55:03 +00:00
Eric Biederman 7dea9552d5 - Small bug fixes to romcc. The deep problems with not inlining functions remain
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-29 05:38:37 +00:00
Stefan Reinauer 7fb8916011 make cpuid and mtrr check conditional. They are not there on cpus older than
i586/i686.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-28 12:06:20 +00:00
Stefan Reinauer f2065a4cf9 add qemu graphics card initialization driver
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-28 12:04:06 +00:00
Stefan Reinauer e2b53e1432 add northbridge code for qemu-i386
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-28 11:59:45 +00:00
Stefan Reinauer 4a3bb76aa8 commit initial qemu support (see http://fabrice.bellard.free.fr/qemu/)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-28 11:57:31 +00:00
David W. Hendricks c7d4db7ff1 Now it should build on the first try :)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-16 15:32:43 +00:00
Li-Ta Lo 99efe80122 add support for AMD Serenade mainboard, why we have phantom devices here?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-15 23:55:55 +00:00
Li-Ta Lo 6ae2ac3739 add support for AMD Serenade mainboard, why we have phantom devices here?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1606 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-15 23:37:34 +00:00
Li-Ta Lo 9b1a2ff96f code reformat, is the pirq table correct?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-15 03:00:35 +00:00
Stefan Reinauer 0b607b39ba simplify pirq handling. Only apply consistency fixes on the copied version
of the pirq table.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1604 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-07 10:25:42 +00:00
Greg Watson ab8ff84402 Add extra phase before memory init.
Rename sdram_init to memory_init
NOTE: need to test sandpoint and ep boards!


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-05 14:54:46 +00:00
Greg Watson 8ce104f487 memory and pci up!
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-05 14:36:23 +00:00
Greg Watson 2f2e63bc7d BDI2000 config file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-04 22:46:30 +00:00
Greg Watson c72e27616d enable early uart
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-04 22:28:23 +00:00
Greg Watson cb5f0ce6a7 fix addressing
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-04 22:27:33 +00:00
Greg Watson 91d60a8fca first cut
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 16:57:09 +00:00
Greg Watson 2906362ea7 nothing yet
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 16:56:01 +00:00
Greg Watson 5b2565a6df fixup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 16:55:24 +00:00
Greg Watson f78ba9dfa6 prelim sdram
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 16:53:41 +00:00
Greg Watson 0ba0ce6b79 briQ timer support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 16:51:18 +00:00
Greg Watson 66c07cdc94 Make names more sensible.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 16:30:02 +00:00
Greg Watson ca68a91eff Clock (not timer) routines are board specific. Moved to appropriate
mainboard dir.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 14:39:16 +00:00
Greg Watson 0dcb172904 Clock (not timer) routines are board specific. Moved from mpc74xx dir.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 14:38:12 +00:00
Stefan Reinauer 515f6b68a0 disable noop usb drivers. remove warnings
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03 07:57:12 +00:00
Stefan Reinauer bb20a72163 This will never happen unless the code is buggy (in which case it's easy to
reenable debugging output).


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-28 15:10:04 +00:00
Stefan Reinauer 34e3a146a9 console code cleanup.
- drop srm console code (not supported anyways)
 - make internal uart8250 console functions static
 - split vsprintf.c into vsprintf.c and vtxprintf.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-28 15:07:03 +00:00
Stefan Reinauer 319d6730e9 add some debugging
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-28 14:55:28 +00:00
Eric Biederman d67e76568a - Added volatile to asm statements in auto.c and failover.c
- Updated the romcc version in Config.lb
- Fixed type sizes in romcc_io.h and io.h inl() returning a byte was nasty


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-28 14:18:45 +00:00
David W. Hendricks 6f52a90ad3 Fixed a silly typo :)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-27 21:10:47 +00:00
Stefan Reinauer d5994ce9c1 fix build. :( sorry, forgot to commit this one.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-27 13:54:38 +00:00
Stefan Reinauer 76712933a0 gcc uses slightly different syntax
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-27 11:13:24 +00:00
Stefan Reinauer 4bfb1f6ce0 cosmetics
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-27 11:09:14 +00:00
David W. Hendricks bb8602b6ea GPIO2 and GPIO3 support for HF part.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-26 19:18:21 +00:00
David W. Hendricks 58133c29fe Early work on IWill DK8S2 motherboard.
Tweaking in progress.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-26 17:21:02 +00:00
Stefan Reinauer 36a74b0c18 cleanup
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-26 15:54:41 +00:00