Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the
changes from kernel driver. IMX319 has two PLLs and it can be configured
either single or dual. Previous driver implemente dual PLL mode, however
image sensor vendor prefer single PLL mode and calculate the pixel rate
became easier. So the kernel driver changed to use single pll, coreboot
change will match that.
Bug=b:116082248
Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28736
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While these pins were set to a pull-down 20KOhm, NPCX EC consumes
~2.1mW higher power. Becasue there was leakage current on both GPIO67
and GPIO70 from NPCX EC. With the external pull-up 10KOhm for
USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current.
BUG=b:117139495
TEST=Check nxpc EC power to see power improvement
Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/29007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update CPU passive temperature threshold value from 70C to 80C,
to avoid early throttling for spiky workloads. Also, change CPU
throttling interval from 1 sec to 5 sec for CPU temperature.
BUG=b:116400298
BRANCH=None
TEST=Manual performance testing on nocturne.
Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29044
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Syndra.
We need to disable rear camera/DMIC on all Syndra sku.
BUG=b:112876867
Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
More platforms are not able to hibernate under certain circumstances,
such as when AC is plugged. This original path was conservatively put in
to prevent potential damage when cr50-update-caused asynchronous resets
occur. Julius' compelling argument that async resets from recovery mode
requests should have enough coverage of the design over the course of
project development. Remove the hibernate path and assume all is well
going forward.
Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29076
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a variant callback to read google_chromeec_event_info
from variant at runtime to allow override of any events based on
factors like board id.
This callback is used in ramstage and smm to get
google_chromeec_event_info structure for performing various actions
like setting masks and logging wake events from EC.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.
BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.
Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled. This change disables WAKE#.
BUG=b:117284700
TEST=none
Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses the generic device driver to provide DMIC properties
in ACPI table to the OS driver.
BUG=b:112888584
Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber
test, but the root cause is unclear.
Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal
reset issue, so we would apply it until find root cause of this issue.
BUG=b:117130599
BRANCH=poppy
TEST=Built and passed on reliability test with modified coreboot
Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds the ACPI controls for power sequencing the touchscreen.
The initial setting is to keep the touchscreen powered off and in
reset. When linux is ready to talk to the touchscreen, it powers it
on and releases reset via ACPI.
BUG=b:110286344
TEST=verified touchscreen is functional in chromeos
Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_C19 is not being set as the code is incorrectly setting
GPP_C16 instead, causing SAR sensor not to work, so this change
sets GPP_C19 to NF1.
GPP_E3 is not being initialized in the code. Initialize GPP_E3
to a no connect as documented in the board schematic.
BUG=b:117124878
TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and
verify that i2c transactions work for the left SAR sensor.
Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28867
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the reset delay for the touchscreen to 10 ms.
BUG=b:116857433
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, log in and execute the following two commands:
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind
and verify the bind command does not echo back a
"-bash: echo: write error: No such device" error.
Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28803
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS"
so that the audio topology file can be loaded properly by the
operating system.
BUG=b:112945714
BRANCH=master
TEST=There is no error message like "failed to load topology firmware" in
kernel v4.4 log.
Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase power limit1 maximum value from 5W to 7W. This value as per
recent measurement on closed system which shows better performance
results.
BUG=None
TEST=Build and tested on Nocturne system. Performance tests
show better results.
Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The previous does not work well enough when testing with
high ambient temperature. Update DPTF settings to make
it work better.
List of tweaks:
1. Raise DRAM Critical temperature from 48C to 55C
Note that there are mechanisms in EC that complement
this because of DPTF limitation that we can't have
multiple passive temperatures.
2. Lower response time for DRAM temp sensor from 60s to 5s.
3. Increase throttle priority to the charger when DRAM hit
passive temperature from 100 to 200.
BUG=b:112550414
BRANCH=None
TEST=Manually tested by thermal team.
Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/28738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for
the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL.
BUG=none
TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake
boards and also check the margin data is proper in FSP.
Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28568
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved
to DMIC0.
BUG=b:113744731,b:111106010
TEST=none
Change-Id: I8ef42627e542182707c81389af9da33a114bc184
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28689
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets the MRC UPD CmdTriStateDis for the atlas boards.
Atlas is a LPDDR3 design without RTT for CMD/CTRL.
The original change for
nocturne is I0f593761dcbd121e7e758421af178931b9d78295
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
BUG=b:111812662
Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On rammus, headset uses DA7219 so that we need to enable it.
BUG=b:112945714
BRANCH=master
TEST=emerge-rammus coreboot chromeos-bootimage
Flash FW and check in kernel to see if DA7219 is up.
Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28537
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the MRC UPD CmdTriStateDis for the
nocturne boards.Nocturne is LPDDR3 design without RTT
for CMD/CTRL.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: I0f593761dcbd121e7e758421af178931b9d78295
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and
clock#4.
BUG=b:113369699
TEST=booted on atlas
Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On rammus, system halt was observed because of gspi clk value being set to 0.
Log info from serial coreboot:
FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes)
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
VBNV: Restore from flash failed
ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443
gspi.c
442
443 assert(gspi_clk_mhz != 0);
444 assert(ref_clk_mhz != 0);
445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK;
BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28405
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus-Wifi with m3 AP got a halt issue during CTS test.
Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was
validated only with Celeron. Since Celeron deos not support turbo
boost mode, its steady power demend and lower CPU frequency may not
reflect the potential noise hidden inside the board.
Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the
potential noise coupling to VCC_GT/SA, and we verified this change
makes this issue go away on Nautilus-Wifi board.
Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have
better grounding and less noise/ripple than 8L PCB.
BUG=b:111417632
BRANCH=poppy
TEST=Verified CTS test pass without an issue.
Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the mainboard.c in order to support the sku id in smbios
table where the sku id is queried from the eeprom via EC.
BUG=b:113714761
BRANCH=master
TEST=check the result of 'dmidecode'
Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node.
Without DRIVERS_SPI_ACPI, the kernel will popped out the below error:
cr50-update[592]: Starting cr50 update
cr50_get_name[595]: updater is /usr/sbin/gsctool -s
cr50-update[609]: exit status: 3
cr50-update[613]: output: Could not open TPM: No such file or directory
cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod'
cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod
cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state
cr50-update[682]: not running
cr50-result[782]: Not running normal image. Skip setting Board ID
trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory
BUG=none
BRANCH=master
TEST=/dev/tpm0 is created
Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:113101335
BRANCH=atlas
TEST=manual performance/power testing on nocturne.
No longer see messages like below in syslog,
'CPU0: Package temperature above threshold'
Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619
Reviewed-on: https://review.coreboot.org/28325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:67459049
BRANCH=nocturne
TEST=manual performance/power testing on nocturne.
No longer see messages like below in syslog,
'CPU3: Package temperature above threshold'
Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458
Reviewed-on: https://review.coreboot.org/28324
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is meant to solve an issue where the proximity sensor may fluctuate
between CLOSE / FAR in rapid succession upon the user removing their hand
from the unit, before settling on the correct output.
Using the hardware debouncing filter solves this issue and removes the
spurious fluctuations.
BRANCH=None
BUG=None
TEST=manual on Nocturne, observing events come in
Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/28112
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nami doesn't support wakeup from hibernation by CR50. This causes the
device to remain turned off after CR50 update.
This patch disables turning off EC on cr50 update. CR50 resets the
whole system. So, EC reset is not required.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.
Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709
Reviewed-on: https://review.coreboot.org/28113
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file contains two instances of "dptf_enable" = "1". This change
removes the 2nd instance (it doesn't have an explicit comment like the
1st instance).
The dptf devices still seem to be present even with this change, as
expected.
Change-Id: I890006644be9176ebaf555cc121c816e12f2b596
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The spec of the sx9310 says the I2C interface can handle standard
(100kb/s) and fast mode (400kb/s). The current setting is using fast
plus (1000kb/s) so this change is reducing the speed to fast mode.
I've been using the sensors with this change for a few weeks now, though
I also don't recall seeing an issue prior to this change.
Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 1fdb76945a.
Camera power is now handled by ACPI rules - no need to force the GPIOs
on by default.
BUG=b:80106316,b:111141128
Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28072
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This defines new GPIO pin for controlling the display panel CABC
function. The default value is high (enabled).
BUG=b:112154569
Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the DPTF sensor names to reflect the sensor locations on
the board.
BUG=b:75454415
TEST=verified new strings show up in
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description
Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28069
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates Power Limit (PL) for AML.
- PL1 as 5W TDP as POR
- PL2 as 18W TDP as POR
BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP.
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power
5000000 (5W TDP)
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power
18000000 (18W TDP)
Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/27427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove icc_max overrides to allow SoC code to set proper
icc_max based on CPU SKU.
BUG=b:78122599
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash to
nocturne, boot to kernel and verify device doesn't hang after
a few minutes.
Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27996
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27997
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skylake SoC code now sets the icc_max based on the CPU SKU, so we
should not hard-code it in the device tree.
BUG=b:110890675
BRANCH=None
TEST=boots on atlas
Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on,
it may cause damage on the GPIO pad.
To prevent, we would set this pad to GPO on romstage before EDP power on.
Since we need to cover all systems in market, I put it into romstage
instead of early_gpio_table.
BUG=b:111860510
BRANCH=poppy
TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on
Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds variant callback to get GPIO configuration table in
romstage and configures these GPIOs before memory training is
performed.
BUG=b:111860510
BRANCH=poppy
Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the default value for Iccmax which is specified in vr_config.c.
The AcLoadline and DcLoadline keep the poppy value. Besides, the
USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT
and the others on the daughterboard are set to USB2_PORT_LONG.
Those setting need to be fine tuned later.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: Icabfac04c94b3d480872c243d811509e274ef122
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The gpio setting is based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tuning of fan speed for different temperature values. Earlier while
running few benchmarks, fan was always getting on and starting at
higher speed. With this change fan will start with lower speed and
slowly speed gets increased if temperature continue going high.
Thermal team provided these data after fine tuning of fan speed.
BUG=None.
TEST=Verified on Nami running with different benchmarks and observed
fan speed.
Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Nami is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:112081534
BRANCH=None
TEST=Build and boot Nami
Verify that suspend/resume and consecutive reboots are working
Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds a function to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings. Tested on Vayne and Akali.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change primarily moves the PowerResource up to a more common scope so
that the _PRx references are simpler. The ^ scope modifier isn't well
supported everywhere amongst OSes and drivers. Windows 10 will BSOD
early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could
not find the object referenced by a _PRx) with the way things are currently
laid out).
I've also not seen a firmware outside of coreboot that tries to reference
count _ON and _OFF. Isn't it up to the OS to deference count, and whatever
it tells ACPI is what should happen (i.e., on means on and off means off)?
Some of the _UIDs are also duplicated. This change makes them unique.
A few cosmetic changes are made so that diffing cam0.asl against
cam1.asl has fewer extraneous differences.
Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.
BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.
Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable nocturne to wake from lid attach/detach events.
BUG=b:111803637
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has
commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne
wakes from suspend on a lid attach/detach event.
Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27649
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some fields were only required during early stages of IPU3.
Remove some fields that aren't used for the current version of IPU3.
BUG:None
TEST=Launch camera app and check if it works properly.
Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.
We would set GPP_D21 to high to change LTE tx power to normal mode as
default.
BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default
Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the new setting for fan performance state.
BUG=b:111860513, b:11865138
TEST=Fan do not run below trip point
Change-Id: I894460b8b418217e2477608094c37018437cbb78
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
These values are Intel recommended.
IccMax = 28A
DC and AC LL = 4mOhms
Pl2 = 18w
BUG=b:79666828
BRANCH=none
TEST=Enabled p-states with patch
Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then
"emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi
image onto nocturne, boot to kernel and verify device stays alive and
responsive for several minutes without locking up.
Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27175
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables p-states for nocturne which was disabled by commit
de31587a (mb/google/poppy/variants/nocturne: disable p-states). p-states
feature was disabled as a temporary work-around as system was getting
hung while booting up. Now with IMVP7 firmwware turning and hardware
rework the issue is not seen, so its safe to enable p-states.
BUG=b:79666828
BRANCH=none
TEST=cherry picked Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
patch and then "emerge-nocturne depthcharge coreboot chromeos-bootimage"
, flash spi image onto nocturne, boot to kernel and verify device stays
alive and responsive for several minutes without locking up.
Change-Id: I82d1516998cc26b789faa5d4e897feb06dc06020
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27257
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.
Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds variant rammus derived from baseboard poppy.
The setting is copied from the poppy and will be modified later
BUG=b:111579386
BRANCH=master
TEST=emerge-rammus coreboot
Change-Id: I169c225e28183a7a93f1142a3bf87a60b26ce9ca
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable DW9807 NVM support by adding required ACPI code
BUG🅱️110815821
TEST=On Nautilus board, execute "cat /sys/bus/i2c/devices/i2c-INT3499:00/eeprom"
in the terminal and see if there is any data to be dumped.
Change-Id: Ib83fa1a522402a59566e3f55fa5c1af4490266e4
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Nautilus-WiFi board doesn't have external pull-up on USB2_OC2# route,then
abnormal over-current is asserted on USB type-A port.
It causes USB type-A port to be blocked, so we need this internal pull-up.
BUG=b:111578984
BRANCH=poppy
TEST=Verified over-current not triggered abnormally on basic sku board
Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable the GEO SAR feature for nocturne. OxM programs wifi_sar VPD key in factory.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:65155728
BRANCH=none
TEST= Set the wifi_sar VPD with below command (values are junk for test purpose only,
actual values would be set be OxM)
sudo vpd -f <coreboot.rom> -s wifi_sar=30313233343536373839303132333435363738393030313
24142433435364445463031324142433400364445463031323343444546303132333435
Flash the <coreboot.rom> and boot to kernel. Get ACPI table and WGDS would get created
with VPD values passed in.
Change-Id: I32ad591f15fdb34704c8d98d98646dfa2d8882ff
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add new Pantheon sku-id for loading vbt-pantheon.bin
BUG=b:78663963
BRANCH=firmware-nami-10775.B
TEST=Boots to OS and display comes up.
Check the board specific vbt binary loaded.
Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27432
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board
schematics.
Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://review.coreboot.org/27433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Remove "IshEnable" from soc_intel_skylake_config since it's not
used anymore.
Enable/disable ISH by checking if ISH device is turned on or not.
Refer to https://review.coreboot.org/#/c/coreboot/+/26485/.
BUG=b:79244403
BRANCH=none
TEST=Built.
Change-Id: I4d2889af118659852431c87cb516fd19b577efc5
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To enable ISH device on atlas board, change "device pci 13.0 off end" to
"device pci 13.0 on end" in file
mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is
not needed.
Config atlas board specific ISH setting in devicetree.cb.
Dynamically load gpio setting for ISH enabled/disabled cases.
BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.
Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is
defined as IRQF_TRIGGER_LOW, so do not invert it twice.
BRANCH=poppy
BUG=b:78613978
TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not
increment wildly.
Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/27221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the keyboard
in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
TEST=Keyboard works fine after booting to OS even if user hits keys
during BIOS to OS handoff.
Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Image Processing Unit and CIO2 device that constitute IPU3.
BUG=None
TEST=Build and boot up into Nocturne platform and check with lspci.
Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/27124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sensors and CSI2 receiver configuration for Nocturne platform.
IMX355 module has VCM, NVM and is on the second port of receiver.
IMX319 module has NVM and is on the first port of receiver.
Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/26283
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These bits start the acquisition process. They should only be set by the
driver.
BUG=b:74363445
TEST=compile
Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/27265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to sona thermal table, PL2 need to check cpu id.
And then set PL2 value.
BUG=b:110867809
TEST=The thermal team verify OK
Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit changes the uid and desc fields for the sx9310 entries
in the devicetree to be unique, and correctly identify the position
of the respective sensors.
Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
We would use GPP_B20 instead of board id to determine nautilus SKU.
BUG=b:80052672
BRANCH=poppy
TEST=Verified the new coreboot could determine SKU correctly
Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27220
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V
leakage. To fix this problem, add GPP_C3 into config for Pantheon
Synaptics touchscreen.
BUG=b:78436458
BRANCH=None
TEST=Let DUT in S0ix mode and check GPP_C3 is normal.
Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures a GPIO pin for enabling/disabling bluetooth on the
next version of the atlas board. The default is for bluetooth to be
enabled at this point.
BUG=b:110614620,b:110613353
BRANCH=none
TEST=none
Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.
This patch fixes the above issue.
BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.
Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a temporary hack to test camera presence before we have full
camera support implemented. Basically, we can now probe the camera
over i2c to verify that it's connected and the camera LED turns on.
BUG=b:80106316
BRANCH=none
TEST=camera LED comes on and camera can be probed over i2c.
Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27128
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We plan to use i2c-hid compatible trackpads on atlas, so this switches
the trackpad config to i2c-hid.
BUG=b:80662079
BRANCH=none
TEST=used trackpad to verify motion tracking
Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27126
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change defines SAR sensor device into devicetree.cb.
Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio.
BUG=None
BRANCH=poppy
TEST=Verified SAR sensor device is loaded by driver in Chrome OS
Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27149
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.
BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot
Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.
BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update dptf.asl and TCC parameters from tuning of the thermal team.
BUG=b:72974136
TEST=Match the result from DPTF UI
Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an
output and initialize it high (high = out of reset).
BUG=b:80089559
BRANCH=none
TEST=none
Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of
GPP_D8 as it needs a 3.3v gpio to provide enough power to also
directly power the camera LED.
BUG=b:79667559,b:78122599
BRANCH=none
TEST=none
Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Add tablet motion control config to nami devices.
BUG=None
BRANCH=None
TEST=run evtest
make sure tablet switch value is 1 in tablet mode and 0
when not in tablet mode
Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26970
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TPM over SPI/I2C config selection got changed in
https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the
same.
BUG=None
BRANCH=None
TEST=Build for Soraka & make sure that TPM is probed over I2C interface
rather than SPI.
Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26890
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since there are two cameras on Nami and only one camera on Pantheon.
We need to disable rear camera/DMIC on all Pantheon sku.
BUG=b:109720689
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Pantheon
Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Issue observed on the board is: too many jack interrupts.
cat /proc/interrupts | grep da7219
58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad
Updated pad configuration for Jack IRQ pin to fix the issue.
BUG=b:109655907
TEST=Jack insertion & removal detection is working.
Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
During measurement of signals during Elan touchscreen power on, saw
that the enable_gpio delay was not sufficient as there is a +1.5 ms
delay during power on. Adding more delay to take this into account.
BUG=b:78311818
BRANCH=None
TEST=probe power on signals to ensure meet timing requirements
Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Power off does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/power off.
BUG=b:78311818
BRANCH=None
TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled
Make sure delays are consistent with spec
Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Vayne added one more skuid 3A67, we need to disable rear
camera/DMIC for vayne skuid 3A67.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Vayne
Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26855
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The driver only supports streaming images flipped horizontally
and vertically. In order to ensure that all current users will
be fine if or when support for upright streaming is added,
require the presence of the "rotation" control now.
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: I7e3abdea9071da1a089c7165f6bb609428090792
Signed-off-by: Lai, Jim <jim.lai@intel.com>
Reviewed-on: https://review.coreboot.org/26727
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FPMCU is using the standard cros-ec-spi interface on GSPI1.
Configure the GPIOs controlling the MCU too.
We need to be able to wake from S3 on the MCU interrupt, re-configure
GPE0 DW0 to point to GPP_C bank.
BRANCH=poppy
BUG=b:79666174
TEST=exercise the cros_ec interface, e.g. 'ectool --name=cros_fp version',
verify the MKBP events by doing 'ectool --name=cros_fp fpmode fingerup'
then 'ectool --name=cros_fp waitevent 5 10000', toggle the other GPIOs
with the flash_fp_mcu script.
Change-Id: Ib417dcf84cda8e354060785cd16a7b6b812148d5
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/26684
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves PL2 override to variant_devtree_update for two reasons:
1. This function was added to basically override devtree settings in
variant specific code. So, it would be a good idea to perform all the
overrides in a single place.
2. Adding a device for performing nami_enable would require changes to
devicetree and special handling for calling this device enable. Thus,
nami_enable was never getting called.
BUG=b:80148703
Change-Id: Ifa24a7b6e99cad2368b3d656a757f26297373121
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Drive SPKR_RST_L (GPP_A19) high at boot to take audio amps out of
reset.
BUG=b:78122599
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", boot to kernel,
and verify sound works via "aplay /dev/random"
Change-Id: Ia49931f2dc7802edc8a46114b081e4a96eeee604
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/26317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The I2C CLKs of SoC should be 400kHz, but waveform show 460kHz to
470kHz. Add I2C parameters to adjust I2C CLKs which 5% lower than
400kHz.
BUG=b:78819970
TEST=The I2C CLKs are 5% lower than 400kHz.
Change-Id: I2c3012b5b59c089801cda8fd7b0c433aad9df36d
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update dptf.asl from tuning of the thermal team.
BUG=b:72974136
TEST=Match the result from DPTF UI.
Change-Id: I21ddc337359c3e11ad9756e61ba174b33dfc3c75
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Since there are two ALS device nodes on Nami, need to remove one.
BUG=b:79227879
BRANCH=master
TEST=Verify if only one ALS node is found in /sys/bus/iio/devices
Change-Id: I850af06bec833739afa0c8c516d351d81952ce2c
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26271
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.
BUG=b:79396300
Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a new SPD entry for samsung's new 4GB memory and updates
atlas to use it instead of the previous gen memory.
BUG=b:79444337
TEST=booted on atlas
Change-Id: I19567736c45a1321586378c3d964c2cbebe24755
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/26185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.
2) I2S2 is used for Boot Beep.
So, update GPP_F0 ~ F2 pins accordingly.
3) Include DMIC-4ch configuration.
BUG=b:79362472
TEST=None [Waiting for HW to verify]
Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change:
1. Allows mainboard to add OEM table to CBFS
2. Provides mainboard specific smbios_mainboard_manufacturer that reads
OEM ID from EC using CBI and compares it against the OEM ID in CBFS
table to identify the right OEM string.
BUG=b:74617340
Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
From coreboot side, include DMIC 4ch NHLT configuration and its
DMIC blob. In OS side, cras picks the needed channels using UCM's
channel map configuration.
So, this patch updates to include DMIC 4ch config.
BUG=b:79158926
TEST=Verified 4-ch record with arecord
TEST=Also verified internal mic record with cras using
'cras_test_client --capture_file dmic.raw --rate 48000
--num_channels 2 --duration 10'
Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This gpio should be active low, but is not currently configured that way.
Changing gpio configuration to reflect that.
BUG=b:73121017, b:77941823
BRANCH=None
TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen
is ejected, gpio is low and when pen is inserted, gpio is high.
Also tested that wake upon pen eject is working.
Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig. They're actually sorted according
to the variant name, but previously, that was impossible to tell.
- Add a comment to the top of variants in Kconfig.name
- Inset each variant name. If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.
It now looks like this:
*** Beltino ***
-> Mccloud (Acer Chromebox CXI)
-> Monroe (LG Chromebase 22CV241 & 22CB25S)
-> Panther (ASUS Chromebox CN60)
-> Tricky (Dell Chromebox 3010)
-> Zako (HP Chromebox G1)
Butterfly (HP Pavilion Chromebook 14)
Chell (HP Chromebook 13 G1)
Cheza
*** Cyan ***
Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This configures GPP_A23 as a wake source for the trackpad. We also
need to set up GPP_A GPE0_DW0, thus evicting GPP_B. We don't have any
interesting signals in GPP_B, so we won't be missing it.
I don't have hardware with A23 wired up, so i just tested the wake
source using A19 which is essentially identical to A23.
BUG=b:78541883
TEST=verified we can trackpad can wake system from suspend
Change-Id: If800464c8b2319d758b1823850571919f85bdc6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds keyboard backlight feature for Nami platform
BUG=b:78360907
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.
Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change sets VmxEnable to 1 to match the kernel setting.
If this feature is enabled at the kernel level and not in FSP,
then there is an issue where FSP expects it to be disabled so
it forces a cold reboot on every warm reboot.
BUG=b:78129261
BRANCH=poppy
Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25698
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating some GPIOs based on changes in the latest schematics. Also
renaming signals to match that of latest schematics.
BUG=b:73749640
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Make sure different SKUs still boot.
Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The commit enables DPTF function. The DPTF parameters are provided by
thermal team.
BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot then check the parameters in DPTF ui tool
Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15).
BUG=b:77893710
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14).
BUG=b:77930401
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since there are two cameras on Nami and only one camera on Vayne.
We need to disable rear camera on all Vayne sku.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera shown on Vayne
Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6).
BUG=b:77290144
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace
Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
Add a new variant of Poppy for the Atlas board.
BUG=b:75454415
TEST=tested on a P0 board. System boots and is mostly
functional, though some peripherals are not ready so there
are no touchpad/touchscreen devices configured yet.
Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8).
BUG=b:76086834
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25379
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an SPD for this particular Hynix memory type to the poppy board
so it can be used by poppy variants.
BUG=b:75454415
Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change remove work-around code for the power issue of MIPI and
USB cameras on previous board revision. With the work-around code,
PMOF ACPI method cannot turn off MIPI camera. So we need to remove
it.
BUG=b:74214248
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7becaf61de364f82976ec0be7f8c9e4ef1a7aedd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/25337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to
read the sku id. In order to support "-1", we need to use
uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type.
Otherwise, tools/scripts will read 65535 instead of -1.
Another reason to change this is that sku_id can be
supported by ec up to 4 bytes.
BUG=b:73792190
TEST=mosys output "Platform not supported" for -1 sku id
arc-setup read -1 sku id
Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in
the latest schematics.
BUG=b:74347464
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25154
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since nami proto did not have any external pull on MEM_CONFIG_4, use a
weak internal pull down before reading it.
BUG=b:74420123
TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami.
Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make sure that fields that are not updated in
variant_memory_params keep a default value of 0.
In particular, use_sec_spd is intended to have a default value of
0 on all platforms. Without this patch, a random value is used
and all boards (except nami) get stuck on boot.
BRANCH=poppy
BUG=b:74439917
TEST=Nautilus and poppy can boot, and do not get stuck at
"CBFS: 'sec-spd.bin' not found."
Change-Id: I06c6511625de930903ae13788bdcd27667a17886
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/25101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change SECONDARY_SPD_SOURCES to SEC_SPD_SOURCES as that is what the
spd target expects.
TEST=Verified that sec-spd.bin is present in coreboot.rom
Change-Id: I4299df1eb9009095ef899c5b83823750dfc715d8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Per vendor datasheet, corrected linkfreq of imx258 as
{633600000, 320000000}
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/24990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO.
BUG=b:73514687
BRANCH=None
TEST=None
Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add spd files for LPDDR3 based on info received from factory team.
BUG=b:73287172
BRANCH=None
TEST=None
Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds support for variants to use secondary SPD if
required. This enables a variant to have different types of memory
supported using the same image.
BUG=b:73514687
Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
