Commit Graph

12201 Commits

Author SHA1 Message Date
Aaron Durbin c41c6a4412 elog: fix improper assumption for year values
The elog format stores the year of the event in bcd format.
Semi-recently rtc_get() started returning the full year,
e.g. 2015. However, bin2bcd takes a uint8_t as a parameter.
Converting a full year (2015 or 0x7df) to a uint8_t results
in passing bad values (223 or 0xdf) to bin2bcd. In other words
the input value of bin2bcd needs to be a number between 0 and 99.
Therefore fix that mistake.

BUG=chrome-os-partner:47388
BRANCH=None
TEST=Events show up with correct year in eventlog now.

Change-Id: I9209cb9175c0b4925337e2e5d4fea8316b30022a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95a86013234dc999c988291f636e2db3803cc24a
Original-Change-Id: I12734bc3a423ba9d739658b8edc402b8d445f22e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311263
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12410
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13 00:52:48 +01:00
zbao 2603812c87 AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1
1. This is required the BLOB change Ie86bb0cf
AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)

2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the
boards can boot to Windows 10. PCIe slots, USB and NIC work.

Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 22:42:04 +01:00
Timothy Pearson 0111459119 southbridge/amd/sb700: Fix SATA port 4/5 drive detection
Change-Id: I01481f25189d01b6f4ed778902b2ecc4d39c7912
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 22:16:54 +01:00
Timothy Pearson 5260a44a96 southbridge/amd/sb700: Recover if AHCI disk detection fails
The SB700 silicon is somewhat buggy; if the links come up in an
incorrect state after POR the silicon cannot automatically recover.

If a disk fails to come online, reset the associated link and try
disk detection again.

Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 22:16:27 +01:00
Timothy Pearson 31ec0f3257 northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
The existing prefetcher configuration was incorrect; use the correct
values from the AMD Family 10h and Family 15h BKDGs as appropriate.

Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12417
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 22:16:16 +01:00
Timothy Pearson 7fd3ef57cb northbridge/amd/amdmct: Clear memory before enabling ECC
The existing code enabled ECC before clearing memory.  As the
AMD CPUs will generate MCEs on any invalid check bits, this
resulted in random lockups during memory training due to the
uniniailized check bits.

Initialize ECC check bits before enabling ECC hardware.

Change-Id: I992e7040520570893ba6a213138dd57bfa14733b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11996
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12 22:16:09 +01:00
Timothy Pearson 14ebf951e4 src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startup
In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts),
with the probability of a failure increasing with the number of disks
connected to the controller.  Resetting the SATA controller appears to
show the true state of the underlying hardware, allowing the drive
detection code to attempt link renegotiation as needed.

Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11998
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-12 21:24:49 +01:00
Timothy Pearson 398540f568 southbridge/amd/sb700: Do drive detection even in AHCI mode
SeaBIOS AHCI drive detection randomly fails for drives present
on the secondary channel of each AHCI SATA BAR.  Forcing native
drive detection in AHCI mode resolves this issue.

Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11997
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 21:23:03 +01:00
Timothy Pearson 795ee1a6cd mainboard/asus/kgpe-d16: Add sata_alpm CMOS option
Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12409
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 21:22:11 +01:00
Timothy Pearson ef62eacb3b mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS option
Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12 21:21:15 +01:00
Timothy Pearson f3b9fd3265 src/northbridge/amd/amdmct: Add option to override bad SPD checksum
Certain DIMMs, for example DIMMs on which the EEPROM has been modified
by the end user, may not contain a valid SPD checksum.  While this is
not a normal condition, it may be useful to allow a checksum override
while memory timing parameters are being altered, e.g. in the course
of overclocking or underclocking, or when recovering from a bad SPD
write.

This is an advanced level feature primarily useful for debugging
and development.

Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-12 21:11:47 +01:00
Zheng Bao 861f920cdf AMD/Mullins: Fix the interrupt routing
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if devices actually use
no-msi.

Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12363
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12 09:26:08 +01:00
Zheng Bao 266609968b AMD/Kabini: Fix the interrupt routing
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if the devices actually use
no-msi.

Change-Id: Id6d35224312aeb6e3a175ec9990e0bb34bad67e7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12362
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12 09:25:45 +01:00
Timothy Pearson 83b7761373 southbridge/amd/sb700: Add option to disable SATA ALPM
The AMD Register Programming Reference states that the user should
have the option to disable Active Link Power Management for two
reasons.  First, some drives may not function correctly with the
ALPM implementation of the SP5100, and second there are some
situations where low latency access is more important than the
power savings created by using ALPM.

Allow the user to disable ALPM if desired.

Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11993
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 00:56:26 +01:00
Timothy Pearson f902722357 mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card
Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11988
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 00:55:47 +01:00
Timothy Pearson f70946ff4d northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11986
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 00:51:23 +01:00
Timothy Pearson ab87c4db30 mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS option
Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12407
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-11 22:01:32 +01:00
Timothy Pearson 9b5480dd5e northbridge/amd/amdmct: Fix crash on startup due to NULL pointer access
Change-Id: I47089f2ad886a6fda4e0cd4472efd975bb8e06c5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11995
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-11-11 20:53:33 +01:00
Timothy Pearson fe2ae61906 mainboard/asus/kgpe-d16: Set SP5100 subtype
Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11994
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 20:50:54 +01:00
Timothy Pearson e36fb7434c northbridge/amd/amdmct: Fix hang on boot due to invalid array access
Change-Id: I47755caf7d2ff59463c817e739f9cb2ddd367c18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11989
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 20:50:23 +01:00
Timothy Pearson 010d62311e northbridge/amd/amdfam10: Add ability to set maximum P-state limit
Under specific circumstances, for instance in low power or fanless
machines, it may be useful to cap the maximum P-state of the CPU.

Allow the maximum CPU P-state to be set via an NVRAM option.

Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11985
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-11 20:49:56 +01:00
ZhengShunQian 0dc117aa5d google/veyron_emile: adjust to the spec of emile
o. Make some gpio changes base on Emile spec.
o. Init sdmmc function.
o. Revert cpu freq reducing in recovery mode since Emile
   have more effective thermal than Mickey.
o. Revert the changes of lpddr3-samsung-2GB config.

BUG=chrome-os-partner:46658
TEST=build and boot on Emile
BRANCH=veyron

Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999
Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307651
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:43 +01:00
Archana Patni 278f20e88d intel/kunimitsu: Enable wake from touch pad.
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.

BUG=chrome-os-partner:43491
BRANCH=none
TEST=Build for kunimitsu. Tested wake from touchpad on a reworked kunimitsu board.

Change-Id: I4347be8f7a4552c6b583f0797fab64045aa9792e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c21f3b5df21d96937975dc20ee5e2f83fb3d75e
Original-Change-Id: I76e69bdba81ec22ae67c7cff3a807cea8c54a5b3
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311007
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:41 +01:00
ZhengShunQian e4d438e8dc google/veyron_emile: Add new board of veyron
This is a copy of mickey and renamed.

CQ-DEPEND=CL:306967
BUG=chrome-os-partner:46658
TEST=build coreboot
BRANCH=veyron

Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde
Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307620
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:36 +01:00
Duncan Laurie b87f2a55a2 google/chell: Add chromeos.c to verstage
When enabling CONFIG_SEPARATE_VERSTAGE the functions in chromeos.c need
to be put into verstage.

BUG=chrome-os-partner:46289
BRANCH=none
TEST=enable SEPARATE_VERSTAGE and build for chell

Change-Id: Ic58a6e383806a7a64b9af760e194fddf15c645f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 403f0707074802371237beecf1941034c1612f10
Original-Change-Id: Ib1154869974337b53a64efa5892a83ecd81973b8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/310928
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:31 +01:00
Duncan Laurie c1f864e257 google/chell: Disable Deep S3
In order to wake from trackpad and wifi we cannot enable Deep S3.

BUG=chrome-os-partner:46289
BRANCH=none
TEST=wake from trackpad on chell

Change-Id: Ieb2210d5d15b5f5d744a686c743df11e5d72558f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbc74e13b754249869144df84ab2bb9b7e77119a
Original-Change-Id: I84265197fb964e0594a4672a40fd3e2362e29ae1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311306
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12392
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:23 +01:00
Duncan Laurie a85f3ae852 google/chell: Add SPD for new memory type
This adds the SPD for SK-Hynix H9CCNNNCLTMLAR memory to be
used in the EVT build.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: I45d0840e43ed81d8286b005f0a99b014b7f0cf28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1e917440141c586cb370147f9c5b782d6e77ea10
Original-Change-Id: I02f1349f38d83f4a09887adf81384b5a8f475dd0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311214
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12391
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:10 +01:00
Duncan Laurie 0ca1b2f547 intel/skylake: mainboards: Add MAINBOARD_FAMILY kconfig entry
The family variable was not being set yet for skylake, add this
to the current boards.

BUG=chromium:551715
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec
Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311213
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:00 +01:00
Duncan Laurie b13845191f google/chell: Fix USB port assignment again
The net names are offset by 1.  My board is not stable enough
to really test all of these yet...

BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b
Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:43:52 +01:00
Timothy Pearson c7e4c27c3b mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12400
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-11 20:33:13 +01:00
Timothy Pearson 45de61de8b northbridge/amd/amdmct: Skip DCT config write to Flash if unchanged
Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11980
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-11 20:30:45 +01:00
Timothy Pearson 83abd81c8a cpu/amd: Add CC6 support
This patch adds CC6 power save support to the AMD Family 15h
support code.  As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.

Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.

Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11 18:45:14 +01:00
Patrick Georgi dd4390b6e0 via/cx700: Fix hidden compile error and make sure it won't hide again
A wrong function name made an #ifdef'd code path not compile. Fix that,
and also use IS_ENABLED() to make sure that such issues won't come up
again there.

Change-Id: Iccb98842dde498cce32cd86a770e22a506ad4cc2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12296
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 09:13:27 +01:00
Urja Rannikko b31017b3ac asus/k8v-x: Add more subsystem IDs to device tree
This is an attempt at better compatibility with driver matching etc.

Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 09:12:25 +01:00
Urja Rannikko 406834717a asus/k8v-x: Add PIRQ tables to init PCI IRQ config
Pulled getpir from the attic and used data provided by it
to create the table a bit more programmatically and
added the AGP slot so the video card is given an IRQ

Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12350
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 09:12:19 +01:00
Werner Zeh 737c54d4d3 fsp_baytrail: Add macros for legacy GPIO output set up
Up to now the GPIO set up macros for input sets up GPIOs to be
mapped to memory space while macros for outputs sets up GPIOs
to be mapped to legacy io space. This patch adds two additional
macros for legacy output definition and changes the old macros
to memory space mapping.

In addition, the intel/minnowmax mainboard is modified to use
the legacy macros for outputs to ensure this mainboard stays
unchanged in terms of functionality.

TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux.

Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12340
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11 06:42:01 +01:00
Timothy Pearson 74e03a4fdd mainboard/asus/kgpe-d16: Enable CC6
Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-11 06:39:13 +01:00
Timothy Pearson cfb93e70bf northbridge/amd/amdfam10: Enable CC6 DRAM save area setup
Change-Id: Ibeb35da3395dc77a21a2f92f0e1d0845be53d175
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11977
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11 06:31:28 +01:00
Timothy Pearson df1fb9c05f amd/amdmct/mct_ddr3: Use training values from previous boot if possible
DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid.  Use them
if the DIMM configuration has not changed since the last boot.

The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device.  If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.

Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11 06:14:20 +01:00
Timothy Pearson 1b708656b2 southbridge/amd/sb700: Fix build failure from merging patches out of order
Change-Id: Ib6d1be64691cf5a1c0b7464284fbae4e583f383e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12402
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11 06:05:58 +01:00
Julius Werner 86fc11d0c9 arm/arm64: Generalize bootblock C entry point
When we first added ARM support to coreboot, it was clear that the
bootblock would need to do vastly different tasks than on x86, so we
moved its main logic under arch/. Now that we have several more
architectures, it turns out (as with so many things lately) that x86 is
really the odd one out, and all the others are trying to do pretty much
the same thing. This has already caused maintenance issues as the ARM32
bootblock developed and less-mature architectures were left behind with
old cruft.

This patch tries to address that problem by centralizing that logic
under lib/ for use by all architectures/SoCs that don't explicitly
opt-out (with the slightly adapted existing BOOTBLOCK_CUSTOM option).
This works great out of the box for ARM32 and ARM64. It could probably
be easily applied to MIPS and RISCV as well, but I don't have any of
those boards to test so I'll mark them as BOOTBLOCK_CUSTOM for now and
leave that for later cleanup.

BRANCH=None
BUG=None
TEST=Built Jerry and Falco, booted Oak.

Change-Id: Ibbf727ad93651e388aef20e76f03f5567f9860cb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-11-11 05:08:07 +01:00
Julius Werner fe4cbf1167 arm64: mmu: Make page table manipulation work across stages
In order to have a proper runtime-modifyable page table API (e.g. to
remap DRAM after it was intialized), we need to remove any external
bookkeeping kept in global variables (which do not persist across
stages) from the MMU code. This patch implements this in a similar way
as it has recently been done for ARM32 (marking free table slots with a
special sentinel value in the first PTE that cannot occur as part of a
normal page table).

Since this requires the page table buffer to be known at compile-time,
we have to remove the option of passing it to mmu_init() at runtime
(which I already kinda deprecated before). The existing Tegra chipsets
that still used it are switched to instead define it in memlayout in a
minimally invasive change. This might not be the best way to design this
overall (I think we should probably just throw the tables into SRAM like
on all other platforms), but I don't have a Tegra system to test so I'd
rather keep this change low impact and leave the major redesign for
later.

Also inlined some single-use one-liner functions in mmu.c that I felt
confused things more than they cleared up, and fixed an (apparently
harmless?) issue with forgetting to mask out the XN page attribute bit
when casting a table descriptor to a pointer.

BRANCH=None
BUG=None
TEST=Compiled Ryu and Smaug. Booted Oak.

Change-Id: Iad71f97f5ec4b1fc981dbc8ff1dc88d96c8ee55a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12075
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11 05:07:58 +01:00
Julius Werner 03a0a65172 armv7: mmu: Make fine grained page tables work across stages
Among its other restrictions (which are noted in a comment above the
function prototype and stay in place), our makeshift fine-grained page
table support for ARM32 has the undocumented feature that it relies on
a global bookkeeping variable, causing all sorts of fun surprises when
you try to use it from multiple stages during the same boot. This patch
redesigns the bookkeeping to stay completely inline in the (persistent)
TTB which should resolve the issue. (This had not been a problem on any
of our platforms for now... I just noticed this because I was trying to
solve the same issue on ARM64.)

BRANCH=None
BUG=None
TEST=Booted veyron_jerry. Mapped a second fine-grained memory range
from romstage, confirmed that it finds the next free spot and leaves the
bootblock table in place.

Change-Id: I325866828b4ff251142e1131ce78b571edcc9cf9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12074
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-11 05:07:48 +01:00
Timothy Pearson 95b97848cc mainboard/asus/kgpe-d16: Set correct supported SATA port count
Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12401
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-11 02:47:43 +01:00
Timothy Pearson 22dfccf5b7 southbridge/amd/sb700: Disable broken SATA MSI functionality
Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11983
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 02:47:23 +01:00
Timothy Pearson f89a05ed9f southbridge/amd/sb700: Indicate iSATA/eSATA port type
Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11984
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 02:07:42 +01:00
Timothy Pearson 2b206775fa mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs
Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11982
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 02:01:47 +01:00
Timothy Pearson 5d7dc5545d southbridge/amd/sb700: Add AHCI support
Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11981
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 01:56:35 +01:00
Timothy Pearson 45ded7df03 amd/amdmct/mct_ddr3: Improve SPD DIMM detect reliability
Upon bootup the hardware reads at minimum 256 * 16 bytes (4Kb, or 32KB) over
I2C on a system with all DIMM slots populated.  If even one of those reads
has a single flipped bit in it (due to EMI, cross coupling with another trace,
 or just poor margins on some cheap DIMM) the system will hang and require a
hard reset.  In practice I've seen failure rates as high as 1 failed boot in
50 due to this issue, granted with cheap DIMMs, but even so retrying the read
resolves the corruption issue.

I2C is not designed for continuous data transmission with high reliability, and
there is no hardware error checking, therefore a single retry when transferring
this amount of data makes sense.

Change-Id: Ifab63eca2233c63a6a42ab8b7e742f8e47fb2a09
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 01:20:03 +01:00
Stefan Reinauer 7593bda5a8 [REMOVAL] tyan/s2875
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I36c2b0290f95f4c0f6bed6a7427fb3aab968d4da
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12376
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 23:04:13 +01:00
Timothy Pearson 69ded8f79f northbridge/amd/amdmct/mct_ddr3: Clean up curly brace style violations
Change-Id: I1ad581454e08f7a24395f50623f29ec14e07f5fb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12360
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-10 22:30:03 +01:00
Stefan Reinauer 39456c2cca [REMOVAL] tyan/s4882
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I866440595a0a38b65ce037dc9a1f7e4c02c6beb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12385
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:50 +01:00
Stefan Reinauer 1115625595 [REMOVAL] tyan/s4880
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I41d1f9eac2f4c37bec4d046a68f3f1cf95b51703
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12384
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:39 +01:00
Stefan Reinauer 9fc5e0bc89 [REMOVAL] tyan/s2892
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Idd6011302d2164275fe01954ad3e4e13474ec7a9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12382
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:10 +01:00
Stefan Reinauer 7c29040442 [REMOVAL] tyan/s2891
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I915d5dd4a095b84023a19c9a0474634320207a08
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12381
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:00 +01:00
Stefan Reinauer 52c0180dcc [REMOVAL] tyan/s2885
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Icfdcc5d6043987e22ef9b4db84847d62c91bd305
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:34:51 +01:00
Stefan Reinauer c5ab0979f6 [REMOVAL] tyan/s2882
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ie44a3c46b82e77028921339c50ae4c176e38055c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12379
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:34:22 +01:00
Zheng Bao 3844d9a30c AMD Bettong: Add a special case for SPD address of rev F
Rev F's SPD address is different from other revision.

            0   1
Channel A  A0  A2
Channel B  A4  AC

Change-Id: I620d1f9c295f9a0e30e3821ea36a05dd9f7d3495
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12342
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-10 21:24:46 +01:00
Stefan Reinauer 8993df1d16 [REMOVAL] tyan/s2895
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I9099f90c073197cc95bb9630788016b7b8221922
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12383
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:21:19 +01:00
Stefan Reinauer f3601c406f [REMOVAL] tyan/s2880
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ifd1dfa35ae13ec01d932250994086edebece924d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12377
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 21:20:56 +01:00
Stefan Reinauer 502a7e41df [REMOVAL] tyan/s2881
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Idfec80ce79c906717e679d6576dc94e71da994c9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12378
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 21:16:42 +01:00
Stefan Reinauer 9f21230e36 [REMOVAL] tyan/s2850
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ibf3849dcd7a1ef1d8bc5dfc864172a8254a64b6f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12375
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:15:12 +01:00
Stefan Reinauer f76de841f1 [REMOVAL] tyan/s2735
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I460208c18964857be73d9a4449ecfd872ccad98a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12374
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:15:04 +01:00
Stefan Reinauer 63d5088bb6 [REMOVAL] iwill/dk8s2
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I4a942150590fb69ff97279ff2b48b3be83abafa4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12372
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:14:53 +01:00
Stefan Reinauer 029f3550ef [REMOVAL] digitallogic/adl855pc
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I5b0fb633b7611e2a69aeb33cd31ca8fd4a83592c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12369
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:14:31 +01:00
Stefan Reinauer a2d131511f [REMOVAL] drivers/trident/blade3d
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I180fd548e8f45fc94e5086159c0e3e9465c74598
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12386
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-10 20:23:36 +01:00
Stefan Reinauer bb3934c3c2 [REMOVAL] iwill/dk8x
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I1913ca75aa6f2a2c6b97d49faaabc16afd2799f5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 20:23:07 +01:00
Stefan Reinauer b38e9a962e [REMOVAL] newisys/khepri
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: If0e0a7f69b77cf4bcab4c0dcb58a153485380069
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12373
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 20:22:45 +01:00
Stefan Reinauer 43f6fd3827 [REMOVAL] ibm/e325 + ibm/e326
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I8854c31f242c13b6f91901452f7eb7ce0ef0b255
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 20:21:16 +01:00
Stefan Reinauer 7804bb002f [REMOVAL] arima/hdama
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ic71d8a9137f0bd2a0cc7571a43f9dddb50168d8d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12368
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 20:17:17 +01:00
Stefan Reinauer 158abf9737 Drop SuperIO fintek/f71889
All boards using this SuperIO have been removed from the tree already.

Change-Id: I3c43a431d92d76b6ed3ec72b203d3e80925cadea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12247
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 20:16:49 +01:00
Timothy Pearson 1f780994eb cpu/amd/car: Add romstage BSP stack overrun detection
NOTE: This commit switches CacheBase in CAR to use the DCACHE_RAM_BASE
Kconfig variable.  There should be no functional difference between
the existing code and the new code, however hardware verfication is
encouraged on lesser used architectures such as AMD Geode.

Change-Id: Ia2e8f99be9df388e492a633c49df21ca1c57ba13
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 20:00:56 +01:00
Timothy Pearson 453b543716 northbridge/amd/amdmct: Read SPD data into cache to decrease bootup time
Change-Id: Ic16a927a3f1fc6f7cb1aea36a8abe8cc1999cb52
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11973
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 19:31:46 +01:00
Martin Roth 4c502697ee cpu: Add a way to use microcode .h files back to the build
The build was changed to remove usage of microcode .h files when
all of the .h files were converted to binary.  This is still
needed for some builds when microcode binaries aren't in the
blobs tree.

Change-Id: Ia323c90efe8aa0b8799fc5cce6197509e466a105
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12333
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-11-10 19:22:40 +01:00
Patrick Georgi 47b6a825a7 mainboard/**/irq_tables.c: Remove reference to getpir
The obsolete and removed getpir utility remarked in its output that the
data is autogenerated. The tool was removed because it wasn't very
reliable, so there's no need to point that anymore.

Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12354
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-10 14:11:06 +01:00
Yakir Yang e78a1bedc5 rockchip/rk3288: hdmi: configure display output mode with EDID information
'edid->hdmi_monitor_detected' would indicate whether the monitor
interface is HDMI or DVI.

BRANCH=none
BUG=chrome-os-partner:43789
TEST=Previously, my LG monitor couldn't show dev screen. But now I can see
     dev screen have been posted normally.

Change-Id: Id71f051b2cd792712e52bee7a763db383c1962a8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88101589a22d06f0bc25e0750b2862cf66b55391
Original-Change-Id: I157861d327926b834e1e8606b0b676f413491c70
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309056
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 14:09:57 +01:00
Yakir Yang 85810cce50 edid: add hdmi_monitor_detected in data struct edid
HDMI driver need to know whether the monitor is DVI
or HDMI interface, so this commit just introduce a
new number 'hdmi_monitor_detected' to struct edid.

There were four bits to indicate the monitor interfaces,
it's better to take use of that. But those bits only
existed in EDID 1.4 version, but didn't persented in
the previous EDID version, so I decided to detect the
hdmi cea block.

BRANCH=none
BUG=chrome-os-partner:43789
TEST=When mickey connect with HDMI monitor, see 'hdmi_monitor_detected' is 'true'.
     When mickey connect with DVI monitor, see 'hdmi_monitor_detected' is 'false'.

Change-Id: I1a4f1410e1cce1474ffae858db161a18578cac3a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 409f041805d9fdff2d49faa1a3a262cf4dc609c2
Original-Change-Id: Ife770898b0f2b4f58b8259711101a0cab4a5e4ac
Original-Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309055
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 14:09:51 +01:00
david dc5b10bd92 google/{chell,lars}: Enable Fan control support
Copy from the CL https://chromium-review.googlesource.com/#/c/307028/
(I40c540dad32beefe249f025b570c347d3ad08c36)

BRANCH=None
BUG=None
TEST=emerge-lars coreboot

Change-Id: I131fb729661f0f3bfd198cdf238c627bf38a46a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70d471c507d12924466979c93742944975a03f27
Original-Change-Id: I0128dc65110ba363185db9c2aca5cdb140c344c2
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310394
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12344
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-10 14:09:43 +01:00
zbao dcbb1287a7 AMD/Bettong: Set on-board eMMC as SD 2.0
The on-board eMMC is designed as 2.0. If it is set as 3.0,
it can not be detected.

Change-Id: I9fd913f76535e65c1672924ebdeba3d35dea59cc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11748
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 10:37:51 +01:00
Zheng Bao fbdfed01eb AMD/Bettong: Memory configuration for DDR3 and DDR4
1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.

2. DDR4 uses different memory configuration in AGESA.
Pass memory configuration parameters in agesawrapper_amdinitpost.

3. Tested on Rev C and Rev F.
Both of them can boot to Windows 8 and have the correct memory size.

Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11733
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-10 10:34:51 +01:00
Zheng Bao f3aea52a70 AMD/Bettong: add function to read board version
Bettong uses 3 GPIO(5-7) pins to identify board.
The GPIO ports are mapped to MMIO space.
The GPIO value and board version are mapped as follow:
GPIO5 GPIO6 GPIO7 Version
  0     0     0      A
  0     0     1      B
  ......
  1     1     1      H

Change-Id: I72df28043057d8c4ccc4a2e645011ca5379e9928
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11732
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-10 10:34:32 +01:00
Felix Held 69e89f249f asus/kgpe-d16: fix DIMMSetVoltages
The RAM voltages can be set per socket, which contains two nodes.

Only reset the allowed voltages per socket before processing a new socket and
not after every node.

Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12297
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-10 01:45:09 +01:00
Jonathan A. Kollasch b65fd3e305 sunw/ultra40m2: initialize hardware monitor and fan control
Change-Id: I3fbb897feb68d899e5dec075a09d0dd605eca5ce
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12309
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-10 00:58:19 +01:00
Jonathan A. Kollasch 7c62e17f2e mainboard: Add Sun Ultra 40 M2 port
The Ultra 40 M2 is a dual Socket F workstation with MCP55/IO55 chipset,
DME1737 superio and onboard Firewire.  This board port is for family
0Fh (K8) processors.

Due to existing bugs, having memory on the second node will cause
raminit to fail.

Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12304
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-10 00:57:55 +01:00
Jonathan A. Kollasch d9247828fd mainboard: copy nvidia/l1_2pvv to sunw/ultra40m2 and rename
Change-Id: Ia275a697caa73168553b5d588d54df651e0539d7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 00:57:45 +01:00
Timothy Pearson 59597ead1f mainboard/lenovo/t400: Add initial hybrid graphics support
TEST: Booted T400 with Intel/ATI hybrid graphics in integrated
mode with native Intel graphics init and verified integrated
panel framebuffer functionality in SeaBIOS and Linux.

Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9319
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-10 00:45:40 +01:00
Urja Rannikko 9849f35459 asus/k8v-x: set superio ROM ctrl reg to enable writes
This is required for flashrom to work...

Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12349
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 00:42:21 +01:00
Urja Rannikko 00018c8270 amd/model_fxx: fix code style in FID&VID support check
This is in AP code, fixed in preparation for copying
the same check to BSP.

Change-Id: I0750919d9fdb3d4e6666221ad82097e0c479cf14
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12359
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-10 00:41:09 +01:00
Paul Menzel 8a3ff6aa34 mainboard: Remove empty mainboard.c files
All the deleted mainboard files contain no code besides some print
statements denoting, that the init is executed.

If such statements are desired, this should be done in common code so it
does not have to be added to each mainboard.

Therefore, also delete files with just print statements.

Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12355
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 00:40:10 +01:00
Marc Jones 3b0a626edc mainboard/intel: Add Stargo2
The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.

Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 00:25:14 +01:00
Marc Jones 2d72345f80 cpu/intel: Add socket BGA1284
Add an additional Sandy(Ivy)bridge processor socket.

Change-Id: I7eff7183d0c003e61fdda5350579f4d3dec7504d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12168
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
2015-11-10 00:19:01 +01:00
Marc Jones cb492da913 superio/intel: Add i8900 device
The Intel i8900 Super I/O is similar to the previously
supported i3100.

Change-Id: I9a5b651cab35991c3c3e09fc4668d35ca2d221ba
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12169
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
2015-11-10 00:15:22 +01:00
Marc Jones 31f4d00c95 northbridge/intel: Add i89xx header file
The Intel northbridge must be paired with a southbridge. Add
the ii89xx southbridge header based on the config setting.

Change-Id: Ied708006310efaba31afe6977ab7e57fe4e5ceec
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12167
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-10 00:12:28 +01:00
Marc Jones 5a4554a73f southbridge/intel: Add FSP based i89xx southbridge support
The Intel i89xx is a communications chipset that pairs with
Sandy(Ivy)bridge processors. It has a lot in common with
the bd82x6x chipset, but fewer devices and options.

Change-Id: I11bcd1edc80f72a1b2521def9be0d1bde5789a79
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12166
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 00:00:46 +01:00
Marc Jones 721c407caa superio/windbond: Add WPCD376I device
The Winbond WPCD376I is a desktop Super I/O often selected on
Intel mainboards. The support is similar to other Winbond and NSC SIOs.
Based on output from superiotool -d.

Change-Id: Ib4786b410b1d83606e8d79a9f686c14a5d25cadf
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12165
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-09 23:54:22 +01:00
Werner Zeh 1e8a3015e9 fsp_baytrail: Add functions to set a GPIO
Add two functions to set a memory mapped GPIO to a given value.

TEST=Booted siemens/mc_tcu3 board and confirmed GPIO-value after
     using this functions.

Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-09 22:25:43 +01:00
Timothy Pearson e619a9ac9b mainboard/asus/kgpe-d16: Add initial Family 15h CPU support
Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11967
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-09 20:24:42 +01:00
Kyösti Mälkki 3ff36b05cd AMD binaryPI: Allow fine-tuning platform memory configuration
The RDK amd/db-ft3b-lc board will use this for on-board DDR3.

Change-Id: I2ffd38e7e949d3a60487e91188ddaab04b03d4b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12358
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
2015-11-09 14:00:38 +01:00
zbao f8537c1cd1 commonlib: Remove unused static function.
Building with Clang without option -Wno-unused-function causes building
error. I don't know why GCC doesn't have that issue.

------------
coreboot/src/commonlib/fsp1_1_relocate.c:47:23: error:
 unused function 'le8toh' [-Werror,-Wunused-function]
static inline uint8_t le8toh(uint8_t byte)
                      ^
1 error generated.
------------

Change-Id: Iecd1e84e4321446412ef68d65dc918baf1ab45ce
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>
2015-11-09 12:26:31 +01:00
Timothy Pearson 8bd1c36abb cpu/amd/family_10h-family_15h: Increase BSP stack size
The additional local data storage requirements of the full DDR3
DRAM training algorithm make a BSP stack overrun a distint
possibility.  Increase the BSP stack size to compensate.

Change-Id: I51af31442f2b77cb64a4b788751ccc7186acb283
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11972
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-08 01:18:19 +01:00
Timothy Pearson 6ee6bdec25 amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h
Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11969
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-08 01:11:27 +01:00
Timothy Pearson 4e0d794039 cpu/amd/family_10h-family_15h: Add Family 15h microcode file
Change-Id: I019f94b99d2fc33e19567acecaaad93813ab6b04
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11968
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-11-08 01:10:28 +01:00
Furquan Shaikh fdb3a8d07d arm64: Remove cpu intialization through device-tree
Since, SMP support is removed for ARM64, there is no need for CPU
initialization to be performed via device-tree.

Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11913
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:29:35 +01:00
Furquan Shaikh b3f6ad3522 arm64: Remove SMP support
As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove SMP
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.

Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11909
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:29:14 +01:00
Aaron Durbin 1148786c05 arm64: remove spin table support
As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove spintable
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.

Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11908
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:28:50 +01:00
Aaron Durbin 0325a45fd0 arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
With the removal of secmon from coreboot there are no
power down operations required. As such remove the
A57 power down support.

Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11898
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-07 03:28:29 +01:00
Aaron Durbin 8c8e2b7e4c arm64: remove secmon
It's been decided to only support ARM Trusted Firmware for
any EL3 monitor. That means any SoC that requires PSCI
needs to add its support for ATF otherwise multi-processor
bring up won't work.

Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11897
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:28:06 +01:00
Kyösti Mälkki a62191b827 amd/00730F01: Add missing headerfile
Change-Id: Id69b339bbed03d7a1f64aa5935721e7e8aab62fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12265
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-06 21:12:22 +01:00
Kyösti Mälkki 55ed6728b1 amd binaryPI: Fix usbdebug
EHCI functions have moved.

Change-Id: I47e79d3790b272b0fc322d534de733889679622b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12264
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-06 21:09:21 +01:00
Kyösti Mälkki ed98e945c0 amd/00730F01: Add correct CPU model
Change-Id: I887f9eb890f1f1c6f88b7984f0520bd17be8b88b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12284
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06 21:07:03 +01:00
Kyösti Mälkki 740edf4f95 AMD binaryPI: Fix include paths
Do not mix open-source AGESA and binaryPI includes.

Change-Id: I1e43334ba8d5a17d3580f81e023ca2c8caf86f7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12283
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-06 21:04:12 +01:00
Kyösti Mälkki a58c0b02ba AMD binaryPI BiosCallouts: Remove cast
This cast only hides errors in matching the API properly.

Change-Id: I9b878ab997b8ff087a7209f94522646b10b94bf6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12271
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06 21:01:19 +01:00
Kyösti Mälkki 82860f8549 AGESA BiosCallouts: Remove cast
This cast only hides errors in matching the API properly.

Change-Id: Ic396dfb572a50ac5ce5c1c83424e1f17f15bad1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12270
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06 20:59:52 +01:00
Kyösti Mälkki 625b944e75 amd/00660F01: Fix MMCONF resource
Fixed resources have to be declared early.

Change-Id: I03bb846e0685d47e0befc20bf7bc14c06694cb66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12262
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-06 16:56:11 +01:00
Kyösti Mälkki 5d49038704 amd/00730F01: Fix MMCONF resource
Fixed resources have to be declared early.

Change-Id: Iedd92e5e7ee43a833bda48e6377da1b78fa4bd81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12261
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-11-06 16:25:35 +01:00
zbao 1897c2c350 AMD Bettong: Enable S4 feature for Windows 7
PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise
going into hibernation can not be wake up.

Change-Id: I692497bad24d745738d670897e725a568c1db114
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11373
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-06 07:53:00 +01:00
zbao aeb2103ab5 amd/pi/Makefile: Remove cp option '-u'
"-u" is only for GNU cp. Cp of BSD and Solaris don't
take this option.

It is not necessary to compare the files before copying.

Change-Id: I60cf57991275db0e075278f77a95ca5b8b941c7f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11601
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-06 07:52:28 +01:00
zbao eb90aaf29e AMD bettong: Fix the interrupt routing.
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.

Change-Id: I893e73f2aab3227381e44406fa285613e4ba2904
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11374
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-06 07:51:46 +01:00
Vladimir Serbinenko d5d94ea90a intel/i945: Consolidate MADT handling
Change-Id: Ic3cdfa6086a45aa231aa817d5ef6998823589818
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7108
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 23:31:49 +01:00
Martin Roth 8346aca83a Kconfig: Remove obsolete Kconfig symbols from google/intel boards
- CACHE_ROM is no longer used in the coreboot code.  It was removed in
commit 4337020b (Remove CACHE_ROM.)
- CAR_MIGRATION is also no longer used in coreboot code - it was removed
in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION)
-  MARK_GRAPHICS_MEM_WRCOMB was removed in
commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB)

Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12327
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05 21:49:34 +01:00
Duncan Laurie 77d37d21db google/chell: Fix USB port assignment
The PCH pin names in the schematic were incorrectly labeled.

BUG=chrome-os-partner:46289
BRANCH=none
TEST=build and boot on chell

Change-Id: I6153137b7c04d22db5b3f00f5eaf3f400f4c344c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f362900b0635dc392c63b25a88a7723f22b467a
Original-Change-Id: If6f8744f020a35a76647366b247723b03c02991a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/310061
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12324
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:40:26 +01:00
Sumeet Pawnikar 47657ea1e1 intel/kunimitsu, google/glados: Enable Fan control support
This patch enables the Fan thermal participant device
in the device tree for thermal active cooling action
for DPTF on SKL-U fan based kunimitsu board.
This patch defines the _ART table in dptf ASL file.
With active cooling policy (_ART), we can control the
fan on/off and speed.

BRANCH=None
BUG=chrome-os-partner:46493
TEST=Built for kunimitsu board. Tested to see that the
thermal devices and the participants are enumerated and
can be seen in the /sys/bus/platform/devices. Also,
checked the FAN type the cooling devices enumerated
in the /sys/class/thermal with sysfs interface.

Change-Id: I40c540dad32beefe249f025b570c347d3ad08c36
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82ae11643ca23e65780006f3890f1d173363b8af
Original-Change-Id: If44b358052a677d13c74919f09a3eb89611fccad
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307028
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12323
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:40:23 +01:00
Sumeet Pawnikar 2ca76e688c intel/skylake: Add Fan control support
This patch adds the ASL file for Fan as cooling device
/participant for thermal active cooling action for DPTF
on SKL-U fan based kunimitsu board.
With active cooling policy (_ART), we can control the fan
on/off and speed.

BRANCH=None
BUG=chrome-os-partner:46493
TEST=Built for kunimitsu board. Tested to see that the
thermal devices and the participants are enumerated and
can be seen in the /sys/bus/platform/devices. Also,
checked the FAN type the cooling devices enumerated
in the /sys/class/thermal with sysfs interface.

Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4
Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307027
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12322
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:40:17 +01:00
Joseph Lo a28e9084bf nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0
The MC/SMMU should be resumed by the kernel. And the unexpected value
in the MC_INTSTATUS should be cleared before that. Or it will cause
some noisy MC interrupt once we enable the IRQ in the kernel.

BUG=chrome-os-partner:46796
BRANCH=none
TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors
     should not be observed on resume.

Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e
Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309248
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Joseph Lo <yushun.lo@gmail.com>
Original-Tested-by: Joseph Lo <yushun.lo@gmail.com>
Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95)
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309497
Original-Commit-Ready: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/12321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:40:11 +01:00
Aaron Durbin 2524be4aff fsp1_1: pass ROM_SIZE to FSP for cacheable RO region
As vboot verification works on regions outside of CBFS
pass the entire ROM_SIZE to FSP for creating a cacheable
RO region.

Additionally remove the CACHE_ROM_SIZE_OVERRIDE as it doesn't
work with non-power of 2 CBFS_SIZE. In practice the entire
ROM should be attempted to be cached.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados w/ a 3MiB CBFS_SIZE.

Change-Id: I61404c626ab2bcfd039d6eb3c01d9c13a0928446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 92568c630c48446b1ad9d4f22056f22e0679970c
Original-Change-Id: I032e4d615d2b68d3a2e597555eb1b5034a74bf0a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309770
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12260
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:40:05 +01:00
Rizwan Qureshi 0dd72e8b1d skylake: Set Pkg Power clamping bit in Power Limit MSR
Setting the Package Power clamping bits in Power Limit MSR
(MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested
P or T state for the time window specified for PL1 or PL2.

BRANCH=none
BUG=chrome-os-partner:47041
TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL,
	change the power limit value from default (TDP or 15W) to any lower value
	note that the Pkg power comes down and also the CPU frequency is lowered.

Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef
Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309556
Original-Tested-by: Charulatha Varadarajan <charuprasanna@gmail.com>
Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:39:46 +01:00
Nico Huber 593e7de5a7 nb/intel/sandybridge: Limit GFX workaround to Sandy Bridge
The touched workaround for Sandy Bridge reserves two memory regions that
could cause graphics corruption if mapped by the integrated graphics
device. To the best of our knowledge, the workaround is not needed for
Ivy Bridge revisions.

Tested on kontron/ktqm77 (Ivy Bridge): Booted Linux and checked the
memory regions are not reserved. Couldn't test on Sandy Bridge, due to
lack of hardware.

Change-Id: I4273d1d804b490cf93c23426782eb1ffaf29f7d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12326
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Tested-by: build bot (Jenkins)
2015-11-05 16:09:42 +01:00
Timothy Pearson 855fc1fcdb cpu/microcode: Remove EXTERNAL / ADDED_DURING_BUILD variables
There has been a concerted effort to clean up coreboot's microcode
handling that has included a move away from coreboot-specific
microcode file collections.  As a result, the ability to specify
a single microcode file to be added to the image is of less utility
than before.

NOTE: This patch remove the built-in external microcode feature,
however the user can still specify no microcode during build and
manually add the correct microcode file(s) to the CBFS image after
the build is complete.

Change-Id: Ifea94c21e531a74953f5a0e2f489378c20ef3b5c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11903
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-05 02:24:45 +01:00
Timothy Pearson 24391321e8 mainboard: Remove last_boot NVRAM option
The last_boot NVRAM option was deprecated and removed in
commit 3bfd7cc6.  Remove the last_boot option from all
affected mainboards to eliminate user confusion.

Change-Id: I7e201b9cf21dfe5dda156785bad078524098626d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12316
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2015-11-05 02:21:52 +01:00
Timothy Pearson 5a1f3370ea src/amd: Increase maximum blootblock execution count
Most AMD hardware requires at minimum two warm resets
when booting from S5 (power off).  This is uncomfortably
close to the maximum bootblock execution count, and has resulted
in unstable normal/fallback operation on some machines.

Increase the default max bootblock execution count before fallback
to 6.  This translates to roughly 2 - 3 failed boots before fallback
mode will engage, with an absolute worst case of pushing the reset
button 5 times to engage fallback mode in the absence of a dedicated
recovery jumper.

Change-Id: I1911f1b77f168835b516e6a915d5b6949f47219a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12317
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 02:17:51 +01:00
Nico Huber 9d9ce0d6d2 nb/intel/sandybridge: Add ACPI DMAR table
Add a DMAR table to advertise IOMMU and IRQ remapping capabilities to
the OS.

Tested with kontron/ktqm77. Under Linux, the table is detected and
interrupt remapping is enabled automatically.

Change-Id: Id6ee601a0a8543ed09c6bb8d308a3a3549fc34e5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12195
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04 18:17:25 +01:00
Nico Huber bb9469c450 nb/intel/sandybridge: Enable basic IOMMU support
Sandy Bridge and Ivy Bridge processors have two IOMMU units. One for the
integrated graphics controller and one for all other PCI devices. Assign
resources for both IOMMUs and apply some quirks.

Tested with kontron/ktqm77 and a Muen based system that makes use of the
IOMMUs. Not tested on Sandy Bridge, but register dumps show the same
settings that are applied here.

Change-Id: I43b5e20b750e7529f448acac35de173185678fd9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12194
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04 18:17:19 +01:00
Nico Huber b2dae79301 sb/intel/bd82x6x: Assign unique bus/dev/fn for I/O APIC + HPETs
Assign unique bus/dev/fn values for the I/O APIC and each HPET. The
values are taken from an example DMAR table. They are used as source-id
for MSI requests and as completer-id for reads from the device' MMIO
space [1, 2]. The former is usefull for source-id verfication during
interrupt remapping.

[1] Intel 6 Series Chipset and Intel C200 Series Chipset
    Datasheet
    Document-Number: 324645

[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
    Datasheet
    Document-Number: 326776

Change-Id: Ib46f8cfb7d966dd1cf2b026f671bc45ffcc43d25
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12193
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04 18:17:11 +01:00
Timothy Pearson bc39b488a5 mainboard/asus: Increase reboot count on boards with recovery jumper
On server boards with a recovery jumper, having the fallback path
less sensitive to power fluctuations or BMC issues makes sense.

Increase the maximum number of boot attempts before automatic
fallback to 10 on these boards.

Change-Id: Iabe0b0cbf332686db8e9380a8b65a1477173599c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12320
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-04 18:15:55 +01:00
Nico Huber 6c4751d596 ACPI: Add functions for DMAR I/O-APIC and HPET entries
Refactor acpi_create_dmar_drhd_ds_pci() and add similar functions for
I/O-APICs and MSI capable HPETs. We violate the spec [1] here, which
talks about 16-bit source-ids spread over start_bus and path entries.
Intel actually uses bus/dev/fn identification for those devices too,
and so do we.

[1] Intel Virtualization Technology for Directed I/O
    Architecture Specification
    Document-Number: D51397

Change-Id: I0fce075961762610d44b5552b71e010511871fc2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12192
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04 16:17:12 +01:00
Nico Huber e561f35fa5 ACPI: Make DMAR flags settable
Add a parameter to acpi_create_dmar() for the flags field and define
flags given by the spec [1].

[1] Intel Virtualization Technology for Directed I/O
    Architecture Specification
    Document-Number: D51397

Change-Id: I03ae32f13bb0061bd3b9bef607db175d9b0bc5e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12191
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04 16:14:06 +01:00
Stefan Reinauer 50a29f8170 Drop SuperIO smsc/fdc37m60x
All boards using this SuperIO have been removed from the tree already.

Change-Id: I52847bc2fc16b27ac0de0bc7c847221b1e5cb744
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12245
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-04 01:00:19 +01:00
Timothy Pearson 82cb7875ff arch/x86/bootblock_normal: Fix failure to build
Fix a function call in the normal path using the original function
name and arguments in code that was changed in commit 3bfd7cc6
(drivers/pc80: Rework normal / fallback selector code)

This commit reworked most of the fallback / normal code,
however the normal code paths were not fully tested by Jenkins,
so this was missed.

Change-Id: Ied66334977272a13b7a7307ff4d9f34eb22040aa
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12315
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
2015-11-03 23:39:26 +01:00
Timothy Pearson 3bfd7cc61e drivers/pc80: Rework normal / fallback selector code
Per IRC and Gerrit discussion, the normal / fallback
selector code is a rather weak spot in coreboot, and
did not function correctly for certain use cases.

Rework the selector to more clearly indicate proper
operation, and also remove dead code.  Also tentatively
abandon use of RTC bit 385; a follow-up patch will
remove said bit from all affected mainboards.

The correct operation of the fallback code selector
approximates that of a power line recloser, with
a user option to attempt normal boot that can be
cleared by firmware, but never set by firmware.
Additionally, if cleared by user, the fallback
path should always be used on the next reboot.

Change-Id: I753ae9f0710c524875a85354ac2547df0c305569
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12289
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-03 21:55:20 +01:00
Timothy Pearson c1daad2e6f cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10h
The K8 PowerNow! state generator does not generate _PSS objects
for nodes other than the first CPU package.  This patch backports
the PowerNow! core count fixes for Family 10h to the K8 CPUs.

Change-Id: I7b411ab75155dfb4bf51ae04301aa16fb2ae89f3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12286
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-03 16:42:45 +01:00
Patrick Georgi 6e99c59223 via/cx700: remove unused #define
Change-Id: I0180e0ae2aeeffcef46a97892356f1955f581efd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12295
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-03 09:09:08 +01:00
Aaron Durbin 1ca2d864dd cbmem: add coreboot table records for each cbmem entry
In order to not expose the cbmem data structures to userland
that are used by coreboot internally add each of the cbmem
entries to a coreboot table record. The payload ABI uses
coreboot tables so this just provides a shortcut for cbmem
entries which were manually added previously by doing the
work on behalf of all entries.

A cursor structure and associated functions are added to
the imd code for walking the entries in order to be placed
in the coreboot tables.  Additionally a struct lb_cbmem_entry
is added that lists the base address, size, and id of the
cbmem entry.

BUG=chrome-os-partner:43731
BRANCH=None
TEST=Booted glados. View coreboot table entries with cbmem.

Change-Id: I125940aa1898c3e99077ead0660eff8aa905b13b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11757
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-03 00:19:46 +01:00
Timothy Pearson 730a043fb6 cpu/amd: Add initial AMD Family 15h support
TEST: Booted ASUS KGPE-D16 with single Opteron 6380
 * Unbuffered DDR3 DIMMs tested and working
 * Suspend to RAM (S3) tested and working

Change-Id: Idffd2ce36ce183fbfa087e5ba69a9148f084b45e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02 23:45:19 +01:00
Timothy Pearson d150006c4a cpu/amd/family_10h-family_15h: Use correct label for break state
Change-Id: I07e517f239807cbe76037308f0beff80c9a6f2ba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12101
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2015-11-02 23:37:54 +01:00
Timothy Pearson b30d7ed8f0 cpu/amd: Move model_10xxx to family_10h-family_15h
Change-Id: I34501d3fc68b71db7781dad11d5b883868932a60
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02 23:37:24 +01:00
Timothy Pearson 69b11f9d40 northbridge/amd/amdmct/mct_ddr3: Fix S3 suspend overrunning the stack size limit
Change-Id: Id7441dacef2e46e283d1fc99d5e5fa3f20e0d097
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02 23:36:37 +01:00
Timothy Pearson 502d457bf9 mainboard/asus/kgpe-d16: Set DDR3 memory voltage based on SPD data
Change-Id: I21777283ce0fd3c607951204a63ff67dc656c8cc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11956
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02 23:36:08 +01:00
Timothy Pearson 2a83935d9f northbridge/amd/amdfam10: Set DIMM voltage based on SPD data
Change-Id: I67a76cf0e4ebc33fbd7dd151bb68dce1fc6ba680
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11957
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-02 23:26:41 +01:00
Kyösti Mälkki 65eec4d959 amd/olivehillplus: Tidy up devicetree
Some comments and leftover static USB devices whose function
numbers changed.

Change-Id: I4d7c7499fe436588ef7e5ae030212c2638a4505f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12263
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-02 16:41:33 +01:00
Kyösti Mälkki 6882574093 asrock/e350m1: Add ACPI S3 support
To store memory configuration in SPI flash currently adds
some 150 ms delay in ramstage, visible in timestamps listing
at 75:cbmem post.

Change-Id: I1160259054b58e9a8df2a105c730e0f4140be1f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02 03:26:09 +01:00
Kyösti Mälkki d28474b46d asrock/e350m1: Match super-io GPIO configuration with vendor
Disables mouse ps2 data/clock signals, not connected in hardware.
Purpose of other GPIOs is not really known, but match them
with superiotool dump taken from vendor bios.

Change-Id: I7b549fbd7dd3fa4cbd507d76882b60bc324a4bd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12214
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-02 03:25:39 +01:00
Kyösti Mälkki 3b01cf17d2 superio/nuvoton/nct5572d: Add missing logical devices
While the actual pins behind these devices are not exposed on the chip,
the enable registers are implemented in hardware. Allow to turn these LDNs
off, like the vendor bios for asrock/e350m1 does.

Change-Id: I4d6d5a8de12b09095138cacbad62b2dfbbe54028
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12213
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-02 03:25:23 +01:00
Timothy Pearson 70460249fd mainboard/asus/kfsn4-dre_k8: Fix ramstage using Family 10h structs
Several ramstage files were inadvertently using Family 10h-specfic
structures, causing unstable operation.  Use the K8-specific
structures instead.

Change-Id: I64066dfdca83557393499b77726051e25b814381
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-02 03:23:47 +01:00
Timothy Pearson b2a1a59ab5 northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hex
This resolves a Kconfig warning.

Change-Id: Ic77c8bf89613c116dfdc73572709aeb354e33b2a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12287
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-10-31 23:47:50 +01:00
Timothy Pearson babb2e67bc mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) support
Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11954
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-10-31 22:14:48 +01:00
Timothy Pearson 160ad6aa75 northbridge/amd/amdfam10: Update RAM speed table with DDR3 values
Change-Id: I8ab7b2cd9bf36d53b744a11d32dd40c750149567
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12272
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31 22:12:09 +01:00
Timothy Pearson 0746452a26 southbridge/amd/sb700: Remove acpi_get_sleep_type for early CBMEM
The acpi_get_sleep_type function in SB700 ramstage is only needed
for boards / CPUs that require late CBMEM initialization.

Providing this function in early CBMEM-compatible boards breaks
building of the ACPI S3 code due to multiple definitions of
acpi_get_sleep_type.

Change-Id: Ieebc2640a586812e3e2bfd410987205d64147314
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12267
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31 22:11:04 +01:00
Konstantin Aladyshev 3c47e8a782 intel/gma: Return success for Intel int15 VGA set panel type hook
One of the interrupts in intel_vga_int15_handler lacks
positive return status. Write correct status to avoid
error messages in log.

TEST=With this change `int15 call returned error` is not shown anymore
     on a custom board with Intel Atom CPU, i945GME northbridge and
     i82801gx southbridge.

Change-Id: I740b2df9bd6a7d261d89bef74b924edbb64354aa
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/12255
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-31 21:39:02 +01:00
Patrick Georgi a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Timothy Pearson 74b13a5616 mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
The existing KFSN4-DRE support hung during ramstage while initializing
AP #3 if a second CPU package was installed.  After analyzing the
Sun Ultra 40 M2 support code it became apparent that the K8 code
cannot function correctly if sequential RAM training is disabled,
and that there were a few other missing calls.  This patch adds
the missing calls, adjust the CAR space to an appropriate level, and
explicitly defines the link numbers and connections in devicetree.cb

TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed.

Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12285
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-31 21:29:40 +01:00
Patrick Georgi ab355750fc arch/x86: avoid race condition on build.h
Change-Id: I15375ac1247b7cc8d80d910a767c7f3e67eb8739
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11904
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-31 19:23:47 +01:00
Nico Huber 0ace013523 sandybridge: Disable parallel CPU initialization
Disable the parallel CPU initialization for model_206ax, that is Sandy
Bridge and Ivy Bridge processors. We never did it the way that Intel
recommends and it became unreliable with the introduction of SMM_MODULES
in commit a3e41c0 Migrate 206ax to SMM_MODULES.

Tested by booting kontron/ktqm77 2.6k times into Linux user space. No
issues so far.

Change-Id: Idffc352341419f22a36bf772534a5e11e711edf1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12266
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-31 14:22:12 +01:00
Stefan Reinauer f7613ecacc cpu: port amd/pi to 64bit
Change-Id: I66ef081fa1a520f0199366587800783ea1ef8719
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11023
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-30 23:08:05 +01:00
Stefan Reinauer 42444f6f53 Drop SuperIO nuvoton/nct6779d
All boards using this SuperIO have been removed from the tree already.

Change-Id: I57eacf2a88077d0d0bffdcf44b3c2ecbd301e625
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12242
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:54:28 +01:00
Stefan Reinauer a57ad8f2ab Drop SuperIO ite/it8661f
All boards using this SuperIO have been removed from the tree already.

Change-Id: Ifca91ae44ab222371808ff1e0027a7cbd4646b0a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12243
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:49 +01:00
Stefan Reinauer 53552cc08c Drop SuperIO nuvoton/nct6776
All boards using this SuperIO have been removed from the tree already.

Change-Id: Ic5604c75de249b945dca58aa904edec86558d3ec
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12241
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:37 +01:00
Stefan Reinauer 6c4ea738ff Drop SuperIO nsc/pc97307
All boards using this SuperIO have been removed already.

Change-Id: I667a8d15a2d16671115f62de656b1c5c6a8259b9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12240
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:29 +01:00
Stefan Reinauer 0cca93162f Drop SuperIO nsc/pc8374
All boards using this SuperIO have been removed from the tree.

Change-Id: I1d13ec7c5f27e82523612af7f07fca3176953600
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12239
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:24 +01:00
Stefan Reinauer 3e6ba4dacc Drop southbridge intel/esb6300
All mainboards using this southbridge have been removed from
the tree already.

Change-Id: I4398ef1e270bd0f36c5dd1c6ec3bfec6c2c091e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12238
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:19 +01:00
Stefan Reinauer 3efcd2eeee Drop southbridge intel/i82801cx
All boards using this southbridge have been removed from
the tree already.

Change-Id: I08269931d845d1f57b34174238bcce245ad77894
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12237
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:13 +01:00
Stefan Reinauer 31ff120a2c Drop northbridge/i440lx
All boards using it have been deleted a long time ago.

Change-Id: Ib1c4018ab6ec27868c0e2fdbf9c91323ead076fb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12236
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:53:08 +01:00
Stefan Reinauer ac901e6bed wakeup: Switch back to 32bit mode first
On x86_64 we need to leave long mode before we can switch to 16bit
mode. Oh joy! When's my 64bit resume pointer coming?

Why didn't this get caught earlier? Seems the Asrock E350M2 didn't
do Suspend/Resume?

Yes, I know it's Intel syntax. Will be converted to AT&T syntax
as soon as the whole thing actually works.. 8)

Change-Id: Ic51869cf67d842041f8842cd9964d72a024c335f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11106
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:52:45 +01:00
Stefan Reinauer f79d05b778 Drop geode_post_code.h
It's unused and empty.

Change-Id: Ieb9225083cb779b7b94ca47488dad4d7beb30a94
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12235
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:52:13 +01:00
Stefan Reinauer 01327d185b smm: 64bit fixes
Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11089
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:39:37 +01:00
Stefan Reinauer 16643aa686 Drop unused code from gcc-intrin.h
Change-Id: I3df66320d0bc18221f947b47e7f09533daafabad
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11108
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:39:03 +01:00
Stefan Reinauer dd132a5d2d AMD mainboards: Fix 64bit BiosCallOuts.c
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11080
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:31:35 +01:00
Stefan Reinauer 5fa4cb6d32 cpu/amd: Fix cbtypes.h to match UINTN convention
There are some inconsistencies in AMDs APIs between the coreboot
code and the vendorcode code. Unify the API.

UINTN maps to uintptr_t in UEFI land. Do the same
here. Also switch the other UEFI types to map to
fixed size types.

Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:24:39 +01:00
Stefan Reinauer d91ddc8d31 vendorcode/amd: 64bit fixes
Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11081
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:24:07 +01:00
Stefan Reinauer 772029fe73 More Hudson 64bit fixes
Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11083
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:23:52 +01:00
Stefan Reinauer 0390cc6b3a SB900 64bit fixes
Change-Id: I5ea0f9338ccdd658b5fbec72aa35b4f80d63d4f9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11084
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:20:43 +01:00
Stefan Reinauer a843211481 SB700: 64bit fixes
Change-Id: Ib4b643441a5b887abf73cc55930ea9b01037f6ea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11085
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:20:26 +01:00
Stefan Reinauer 6a2df9a5e8 RD890: 64bit fixes
Change-Id: I326c070398c72a877054969d3a03e6e427edc304
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11086
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:20:11 +01:00
Timothy Pearson 59d0e040c8 northbridge/amd/amdmct/mct_ddr3: Add initial Suspend to RAM (S3) support
Change-Id: Ic97567851fa40295bc21cefd7537407b99d71709
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:19:37 +01:00
Timothy Pearson 4ea0cc087e northbridge/amd/amdfam10: Add Suspend to RAM (S3) Flash data storage area
Change-Id: I169fafc3a61e11c3e4781190053e57bf34502d7b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-30 18:19:11 +01:00
Stefan Reinauer fce128cdfb Hudson: Port to 64bit
Bring http://review.coreboot.org/#/c/10582/ to Hudson

Change-Id: I1ba3047699c304a769215fe901dc3511bf23199d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11022
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:16:28 +01:00
Stefan Reinauer 77a1d1adae Port AGESA based northbridge code to 64bit
This is extending http://review.coreboot.org/#/c/10583/
(29e6548) to the remaining AGESA northbridge drivers.

Change-Id: I6fa53b36a1420e92cb4aecb0f7b4c71541a94c71
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11021
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:15:15 +01:00
Stefan Reinauer 273911cfd6 mainboard 64bit fixes
Change-Id: I2b4338927d56a2075c0a95f2ab981f1beaf69cc7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11082
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 18:13:53 +01:00
Timothy Pearson 5c5c4a6943 cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage
This mirrors a similar commit made to Family 10h support
in changeset 11966 file model_10xxx_init.c

TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222

Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12250
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30 17:44:10 +01:00
Timothy Pearson e3b5d36321 cpu/amd/model_fxx: Enable FIDVID code on Socket F K8
The existing Kconfig option for FIDVID was permanently
set to "no" due to Kconfig stopping at the first matching
value set when parsing the file.  This patch moves the
conditional set above the unconditional set, resolving
the issue.

Change-Id: Ic19f68f6b17943f9133ff32a9b6538f0bf942eca
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12224
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30 17:44:02 +01:00
Timothy Pearson 6b171b3163 cpu/amd/model_fxx: Backport APIC code and debug aids from Family 10h
Backport a handful of debugging routines and the extended APIC
initialization code from Family 10h support to K8 support.

Change-Id: I08cc5c8bc65635ce09a69e32940dd7edd8d3be87
TEST: Booted ASUS KFSN4-DRE with 1x Opteron 8222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12251
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:33:46 +01:00
Timothy Pearson e67d240444 cpu/amd/car: Honor BKDG recommendations for DisFillP in CAR
The recommendation to set DisFillP during CAR initialization
on K8 NPT CPUs was ignored.  The consequences of this are
largely unknown; fix up coreboot to follow the recommendations.

Change-Id: Ide512bbc1d9aa284179628e2aa598ef5475e8eeb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12249
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:32:51 +01:00
Timothy Pearson 2caf3cbac0 mainboard/asus/m2n-e|msi/ms9282: Clean up FIDVID mistakes
These two mainboards contained trivial mistakes related
to FIDVID that broke build when FIDVID was enabled.

Change-Id: Ie7bec77f26ec37eada21308984db4a9fd7a1866f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12226
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:08:05 +01:00
Timothy Pearson 56699948b7 southbridge/nvidia/ck804: Fix FIDVID build failure on CK804
Change-Id: I74c285ff86993898e0120170cf07f48ef4dc9612
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12225
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:07:04 +01:00
Timothy Pearson c6cd5d4ed5 cpu/amd/model_fxx: Fix invalid P-state power values
Change-Id: Ifdb1d1f267af289d962effe1150c7bc0a39cb5d2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12233
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-30 16:01:45 +01:00
Timothy Pearson ab95702f1e mainboard: Add initial K8-compatible version of the KFSN4-DRE
This is a clone of the original Family 10h-compatible ASUS
KFSN4-DRE board, modified for basic K8 support to allow for
future K8 Socket F Opteron testing.

TEST: Booted KFSN4-DRE with 1 Opteron 8222 processor

KNOWN ISSUES:
 * Second CPU package fails to initialize AP
   This prevents use of a secondary CPU package
 * Second memory channel of at least CPU package #0
   does not function (crash at CAR handoff)

Change-Id: I591725babe685fa50a0d7473b17005fbd258056e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12212
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:01:13 +01:00
Timothy Pearson 529fd81f64 cpu/amd/model_fxx: Add Socket F CPU ID mappings
Change-Id: If1df7f3ae9661fae49557c07def397b36b1d38f0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12210
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-30 16:00:57 +01:00
Kyösti Mälkki 439a527014 Revert "device/pciexp_device: Tune PCIe bridges before scanning children"
This reverts commit 785b3eb6e8.

The commit re-tuned the upstream link again, it does not tune secondary side.

Change-Id: I9be70e95b06ceff99beba8a7c7eb6402b32fcca1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12253
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-30 00:36:07 +01:00
Douglas Anderson 6db10452b4 rockchip/rk3288: If we fail to read the EDID 5 times in a row, it's an error
Previously if we tried to read the HDMI EDID several times and failed
each time then we're return from hdmi_read_edid() with no error.  Then
we'd interpret whatever happened to be in memory at the time as an
EDID--not so great.

Let's actually look at the error.

BRANCH=none
BUG=chrome-os-partner:46256
TEST=Monitor that can't read EDID not shows that in the log

Change-Id: I6e64b13ae3f8c61bf1baaa1cfc8b24987bd75cf3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44bda7311f9ee677235e4dc8db669226518b3895
Original-Change-Id: I9089755b75118499bec37bdb96d1635f66252e65
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309298
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12231
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 21:07:19 +01:00
Timothy Pearson 919d9ba633 mainboard/asus/kgpe-d16: Add nvram option to enable/disable IEEE 1394
Change-Id: I4f0f6c1cb1fad5b65f196dc6b443252a0ecc70a1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11947
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-10-29 20:21:57 +01:00
Aaron Durbin 5907eb8f5a commonlib/region: add xlate_region_device
There are cases where one region_device needs to be
accessed using offset/sizes from one address space
that need the offset translated into a different
address space for operations to take place. The
xlate_region_device provides an offset that is
subtracted from the incoming transaction before
deferring to the backing access region.

Change-Id: I41d43924bb6fbc7b4d3681877543209e1085e15c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12227
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-29 18:58:07 +01:00