Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables.
Use Kconfig for reversable configuration if using old OS.
BUG=b:62241143
Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Use GENERIC_SPD_BIN method of adding the SPD bins to final rom.
Change-Id: I242e393bafac41aa7743f83b52cadf027019ee6e
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.
BUG=b:65484600
TEST=Build & boot
Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new ultima variant
Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""
Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This updates board info of PC Engines platforms, changes board names
to official manufacturer's names and adds info about ROM. Removing
"Clone of" option for ALIX platforms makes them independent.
Change-Id: Ie76d65ea84f14b9043a8e5b86678a9da4c187cc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Martin Roth <martinroth@google.com>
SPI mode needs to be set early to normal and Quad I/O disabled
on this board for some reason
Change-Id: I4dbc52010eebf492087d0b1c155a24a307bcc8b0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
TESTED on Biostar A68N-5200: boots to GNU/Linux
With proprietary VBIOS, even the gfx works in SeaBIOS.
Change-Id: Id44b81345ba189f82413042760d570a746294a1e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Support the required AGESA_DO_RESET in bootblock.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50. SPI is more reliable
than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI.
BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
run cold_reset and warm_reset and make sure both
boot successfully.
CQ-DEPEND=CL:714237
Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram
Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix typos in determining single/dual channel in cyan variants
which resulted in all boards being reported as 4GB/dual channel
in the cbmem console log.
These typos were found and fixed in yet-to-be-merged variants;
this patch applies the same fixes to already-merged boards.
Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Like happend in commit efd0eb35af
(siemens/mc_apl1: Add delay to wait for legacy devices) add the
feature to mc_bdx1 as it uses the same legacy devices.
Change-Id: I355a53ce7aea70098d7bc08f24dc6a4e43d1d618
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Depthcharge was complaining that the GPIO for this flag wasn't set.
The GPIO also needs to be an input, not an output.
BUG=b:67614692
TEST=Depthcharge no longer complains that there is no GPIO set for flag5.
The system boots again.
Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This patch is to enable the support of device sleep
for SATA port 1 and disable unused SATA port 0.
BUG=b:65808359
BRANCH=None
TEST=Ran "suspend_stress_test -c 2500" and passed the test.
Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")
This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.
BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.
Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on PCIe express port 9 of PCIe controller 3,
to enable NVMe SSD via M.2 socket 3 on RVP board.
TEST=Boot to OS using Intel NVMe SSD Pro 6
Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard_memory_init_params() and mainboard_silicon_init_params()
methods already have weak definitions in drivers/intel/fsp1_1,
so having them declared as weak in the cyan baseboard has the effect
of them not being called at all unless overridden at the variant level.
Therefore, remove the weak declarations in the baseboard and ensure
that each variant has its own init functions if needed.
TEST: build/boot google/cyan
Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time)
removed the delay after taking device out of reset since it seemed
unnecessary in system resume case (because there is enough time after
taking device out of reset and before communication with device
starts).
However, without the delay, kernel driver runs into issue while
talking to the device during boot-up and runtime
suspend/resume. (Observed this error in dmesg: "i2c_hid
i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms
delay after taking device out of reset. Verified on multiple Soraka
system that with 10ms delay, kernel driver does not run into any issue
talking to the WCOM device during boot-up, runtime suspend/resume and
system suspend/resume.
BUG=b:65358919
TEST=No more errors talking to WCOM device in kernel dmesg.
Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Adapt code to latest schematic changes, revision 1.1.
Configure GPD2 for EC_PCH_WAKE_ODL,
GPP_D5 for EC_I2C_SENSOR_SDA,
GPP_D6 for EC_I2C_SENSOR_SCL,
GPP_D7 for WWAN_SAR_INT_ODL,
GPP_D9 for touchscreen power enable,
GPP_D10 for wifi power enable,
GPP_D11 for wwan power enable,
GPP_D13 change to "No Connect" (was VOL_UP_ODL),
GPP_D14 change to "No Connect" (was VOL_DOWN_ODL).
BUG=b:66265441
BRANCH=None
TEST=None
Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Dell Optiplex 790 desktop board has a logical 10MiB flash, so it
needs to select BOARD_ROMSIZE_KB_10240. Provide it, so it can be used.
Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Note: For some of the boards affected ACPI S3 support
was never tested but feature was just copy-paste from
reference design.
Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.
BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.
Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already
includes this.
Change-Id: Ib2de0f384a547240528b18f07327566354164699
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.
BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.
Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Other than switch to use common gpio implementation for skylake based
platform, also apply the needed changes for purism board.
Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V
or 3.0V. We thought this mechanism was disabled by default, but it turns
out it wasn't. We want to use that pin as an output GPIO on Scarlet so
we need to reconfigure the respective SoC controls before we do that. It
seems that we also need to explicitly pinmux the pin away from that
special function (to normal GPIO) or weird things happen on some boards.
BUG=b:66534913
TEST=Sprinkled several long udelays, poked test points with a
multi-meter on Scarlet.
Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook the new required AGESA callout functions into the callouts tables.
BUG=b:66690176
TEST=Build and boot Kahlee - see the functions get called.
Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some fam14 boards will need more work on this area,
those are to be addressed with followup patches.
Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.
BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.
Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We need support two touchpad for Robo project,
so adding Synaptices touchpad to coral.
BUG=b:63134907
TEST=Compiled, verified by ODM
Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50
Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.
BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.
Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It shares the same northbridge, cpu, romstage with asus/p2b-ls, which is
already on EARLY_CBMEM_INIT as of commit e14d7de.
Change-Id: I8e7c468f0363a5cb9885020bc116e5ae3480ec17
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Boot tested on p2b-ds. Migrate p2b-d as well because they share
the same mainboard romstage.
Change-Id: I3e4b98cc6191d557325fc5da97744902996673af
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is required to transmit button information from EC to kernel.
BUG=b:65980005
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I3cd524aec47ca988d6044cb089e7aa7636e64ab2
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Reviewed-on: https://review.coreboot.org/21633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
It makes no sense for Das U-Boot which uses the same setting.
Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/21611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
This file mostly mimics Porting.h and should be removed.
For now, move it and use it consistently with incorrect form
as #include "cbtypes.h".
Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy-paste, was not really used at all.
Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17
is insufficient to use.
Using VPD to control could prevent H/W change.
BUG=b:65339688
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I55ab741354797e022dd945da9c8499ee5e041316
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
variant_board_sku() callback exists to allow some of the variants to
report the sku id differently based on board implementation. However,
there are cases where there are multiple ways to encode the sku id, but
the original way should be used as a fallback. As such expose a helper
function, sku_strapping_value(), such that there isn't code duplication
for the common fallback case.
BUG=b:65339688
Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update I2C5 bus parameters to obtain clock frequency <400kHz.
BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.
Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The x220 and x230 do have BDC detection, but it's broken.
Disable BDC detection on those two boards, and add a comment
why it doesn't work.
The issue has been reported and tested on Lenovo X220.
Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With reset default of the clockgen on this board the SATA clock which
needs to be 100MHz depends on FSB BSEL straps.
This explains why SATA was originally tested to be working but fails
with CPUs operating at different FSB.
This change sets a bit in the clockgen configuration which fixes the
SATA clock.
TESTED on with a 1333MHz FSB CPU.
Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Unlike Chromebooks, Purism laptops are only sold under one vendor name,
so MAINBOARD_VENDOR only needs to be set in src/mainboard/purism/Kconfig.
Change-Id: If0b33df01ff3327272d089b7efb8e64fa1233fdf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21591
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants
Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/banon (Acer Chromebook 15 CB3-531) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new banon variant
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Gardenia (with Stoney Processor) has a single memory channel, not two.
This corrects DMI type 17 reporting and the memory clear functions.
Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21602
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
IRQ 9 is used for different purpose on this mainboard so move SCI away
to IRQ 10.
Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable LTR for Root port 0, where wifi card is connected.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Linux Pstore area must not be cleared on a reboot. Set the option
to not clear the memory in AGESA.
BUG=b:64193190
BRANCH=none
TEST=Memory clear isn't called in AGESA.
Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21596
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee has a single memory channel, not two. This corrects DMI type 17
reporting and the memory clear functions.
BUG=b:65403853, b:64193190
BRANCH=none
TEST=AGESA DMI reports the correct number of DIMMs.
Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add lens_focus property with reference to VCM device for OV13858
camera module to register the corresponding v4l2 sub-device
asynchronously.
BUG=b:64133998
BRANCH=none
TEST=Build and boot soraka. Dump DSDT and verified that it has the
required entries and verified the camera functionality.
Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set keyboard backlight to 75% on boot, except when resuming
from S3. This enables the backlight at a reasonable level
prior to the OS driver taking over, providing early proof-of-life
and enhanced usability in grub etc.
Uses same method as other google boards with a keyboard backlight
(chell, link, samus). 75% value determined based on user feedback.
TEST: boot google/lulu,gandof boards, observe keyboard backlight
enabled in pre-OS environment.
Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/reks (Lenovo Chromebook N22/N42) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new reks variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-reks-7287.133.B,
commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
variants other than cyan
Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data
Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add EC entries into chromeos.fmd file.
BRANCH=None
BUG=None
TEST=Flash image and confirm system can get out of reset successfully.
System will not be able to reach reset vector if flash map described in
coreboot does not match intel flash map generated from fit.
Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are old legacy onboard devices which are too slow for a coreboot
boot with log level BIOS_ERR. In this case coreboot is so fast that these
devices do not have enough time to become visible on the PCI bus and
this in turn leads to missing resource allocation for this devices. The
most generic way to work around this problem on existing hardware is to
introduce a delay right before the PCI enumeration starts. The needed
delay time depends on the hardware and will therefore be get from
hwinfo.
Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fine tune usb 2.0 strength for port 4 to pass eye diagram.
BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.
Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These two boards have been boot tested with EARLY_CBMEM_INIT
and is good to go.
Change-Id: I2e69901ed83502894f6794b3c1d7bab9aab95e51
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21351
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This board uses the reset defaults for DxxIP and DxxIR.
The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family"
mistakenly says in the D31IP register that all function have INTB as
default. This is however not true as documented in the reset default
value.
This fixes the DSDT such that the SMBus device gets a route for the
INT C interrupt it uses.
Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21442
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TESTED: NGI works on VGA with adapter on DVI-I port
Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This makes the VGA output on the DVI-I connector usable.
This reuses vendor settings.
Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For boards with cimx/sb800, mainboards defined only empty
stubs. Reset functionality is handled as BiosCallout.
For amd/inagua, the defined function was actually initial
GPIO programming.
For cimx/sb700, function had prototypes but no callers.
For cimx/sb900, everything was commented out already.
Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for BDC detection, based on the schematics for each board.
Support for boards without schematics needs further testing.
Needs test on all boards.
Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The RO_VPD region is required for ChromeOS.
BUG=b:65408869
TEST=Build and check coreboot.rom with fmap_decode.
Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
APL internal UARTs are not used on this mainboard.
Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.
Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Vendorcode expects some DRAM controller registers to
be writable, but they are actually locked after soft
resets if C6 states are enabled.
Without the workaround, raminit fails on soft resets.
Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's too critical to ignore when sending the message on
SMBus fails, so allow for a fair amount of retries.
Failure here causes watchdog to do hard reset later.
Move it out of mainboard.c as we need to call this
early in romstage while we are debugging.
Change-Id: I1006b079269d6dd44de630db7a5694124af2f974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Fix regression caused by commit:
714709f AMD fam10 ACPI: Use common fixed sleepstates.asl
Adding common sleepstates.asl got lost in rebase process.
Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 6c0f3c7ee1.
Reason for revert:
Broke master builds, this was submitted out-of-order, some
of the dependencies have not passed review with +2 yet.
Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
There is no serial port on this platform.
In addition, put the LPC serial IRQ into quiet mode.
Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The deprecation of late (post-romstage) CBMEM initialization was
announced in this blog post:
https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/
There are two warnings:
* In LATE_CBMEM_INIT's help text, I've added a multi-line warning, that
aims to explain the problem.
* In src/mainboard/Kconfig (just below the mainboard selection), there's
a warning which points the user at LATE_CBMEM_INIT, if such a board is
selected.
Also update the function that needs to be implemented, as pointed out by
Keith Hui and Kyösti Mälkki.
Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
08f7d1ae0d ("mainboard/via*: Drop AMD car.h file") did the same for all
Via mainboards that were in tree at that time, but the winnet/g170 was
merged a bit later.
Change-Id: Iedb33f4c2fce6fc2cf2669fee4ffb25bf793c92b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently PMIC (tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.
With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow run time power
saving when camera is not in use.
PMIC will be reset in first boot & across S3 & S0ix cycles.
Also, remove the smi handler for PMIC power management & handle it as
part of sensor and VCM ACPI PowerResource.
BUG=b:63903239
TEST= Build for Soraka. Check Camera probe, Capture image across
S3 & S0ix cycles.
Also checked the following & found no regression:
1. Typical camera use cases
2. Stability tests related to camera
3. Reliability tests related to camera
4. PnP tests related to camera
5. Latency related tests with camera
Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.
Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
DPTF is up and running.
Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
We have no wacom digitizer on I2C#3, so remove it.
TEST=build and boot on soraka.
Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21309
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MPC.HPCE bit of the ExpressCard root port is not set in vendor
firmware, so autoport didn't generate the right pcie_hotplug_map to
support ExpressCard hotplug.
Also add comments for each PCIe root port.
Change-Id: Ic53e36a7192b9bfa8ff9fca57f4556e972e2611b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/21310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some of these will move to EARLY_CBMEM_INIT.
Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario.
Also, remove DVS support for CENTERLOGIC.
BUG=b:64702054, b:63537905
TEST=build coreboot
Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/21176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enabling XHCI is additionally controlled with Kconfig
option HUDSON_XHCI_ENABLE. Even when it is enabled,
it EHCI debug works on the USB port next to the
DVD drive door.
Change-Id: I83738da6015f58ecd0819c553d333a176365dc78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Support code for Trinity and Richland is identical now.
I have also come across a unit with Trinity model CPU,
whose CPUID was not listed in f15rl while f15tn already
had support for f15rl.
Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=b:64987428
TEST=Verified that touchscreen works on boot-up and after
suspend/resume. No power leakage via stop gpio in suspended state.
Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We no longer use this touchscreen device, so get rid of it.
BUG=b:64987428
Change-Id: I67af787d231317a80998fb483eed5674de19aeb4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update cyan's SPD-related functions to more closely mirror
those of other Braswell boards, in order to simplify the upcoming
baseboard/variant setup for Braswell ChromeOS boards.
TEST: boot google/cyan, observe SPD correctly identified in
cbmem log, RAM-related data correct in SMBIOS tables.
Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Replaces the ics/954309 driver with a more generic version to
accommodate clockgens with a different amount of registers.
It also features a mask to only touch certain bits of the clockgen.
TODO: set appropriate mask for X60/T60 since the datasheets for their
clockgens can be found.
Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add a 16ms delay to DMIC init by the kernel driver in order to
prevent an audible 'pop' noise when starting to record.
BUG=b:63413023
TEST=manual testing to ensure this device property is present in SSDT:
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package () {
Package () {
"realtek,dmic-init-delay",
0x10
}
}
})
Change-Id: If9160ce6992153ba49719029de336595bbf4ae72
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot
Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
What is present is APIC and legacy interrupt routing and the soft-off sleep
state. Other sleep states are missing, so are the SuperIO devices.
Boots Linux with and without "noapic" and a Windows XP (installed with
factory BIOS, the installer reportedly requires legacy keyboard).
Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Initialize IRQ routing for legacy non-PNP OSes the same as the factory
firmware would do.
Change-Id: I0c7a7d584a2c47471456ab54ef6da815a2dc4e7c
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.
Copied from mainboard/bcom/winnetp680 which seems to be a similar
board with an extra PCI slot.
The p680 should probably be moved to winnet/ too, since the board is an
OEM WinNET board, with BCom being just a machine that happens to it.
Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Remove obsolete code. The same settings are always done in southbridge.
Change-Id: Ic893ddbace73ae8b122c4fb675febc7d1e0b5da9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.
Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.
BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.
I2C0: 375 - 400
I2C1: 377 - 400
I2C2: 377 - 400
I2C4: 375 - 397
I2C5: 375 - 397
Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add critical and passive threshold to be advertised in thermal zone 0.
Change-Id: Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The LED polarity was set incorrectly, fix using values derived
from original Chromium sources:
branch firmware-mccloud-5827.B, ToT
src/mainboard/google/mccloud/smihandler.c
src/mainboard/google/mccloud/romstage.c
TEST: boot google/mccloud, observe power LED on normally,
blinking in S3/S4, and off in S5.
Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Commit 0562783182 applied
this change to other Google boards, but cyan was left out.
Bring cyan in line with other Google boards.
Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Cleaning up code to remove support for pre-EVT rev of cyan board.
Analogous to what was done for intel/strago in commit 103f00d.
Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit a162348.
Remove the hard coded IRQ number for the keyboard interrupt.
IRQ number can change based upon the gpio bank index ordering.
Hence pass the gpio bank and index number so that kernel calculates
the IRQ number.
Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit dc59188.
Disable L1 sub state to prevent WiFi randomly disappear condition.
Original-Change-Id: I8975bb4bbbc2fc89b91b06ae02716367890c672d
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Oriignal-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Change-Id: I51a1bcca6431e6bc28baf9b09433cec13db925c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit 1138727.
Elan touchscreen driver expects the first gpio resource in asl
to be the reset line.
The driver considers the gpio based irq line as reset gpio resource
and changes the direction to output.
This will cause irq registration to fail.
Solution is to pass Interrupt resource for touchscreen irq
instead of GpioInt.
Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit e49deb1.
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is board
specific.
Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to pass type C USB2 eye diagram for sku Santa,
USB2 port#1 PHY register needs to be overridden.
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the fchec.h files, which do not seem mainboard specific, out of
the mainboard directories into the southbridge/soc directories.
Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is not specific to a board but the binary IMC firmware
used on the platform. Also remove unused IMSP and IMWK methods.
Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It was not intentional to change oem_fan_control() to non-static
with commit
23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control
Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.
Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert from #if to if() for all fan control
setup code. Where necessary, make functions non-static to match the
prototypes in imc.h.
Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert all #if to if() for fan control setup.
Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Don't include src/include/cpu/amd/car.h in Via motherboards.
Change-Id: I9d2b3cfb619cf831c7a677992ca03d5f42e5ffd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
