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1212 commits

Author SHA1 Message Date
Stefan Reinauer
a14b46895c final rename orgy. sorry for the inconvenience. This should fix it again 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-04 07:50:59 +00:00
Stefan Reinauer
c76b85d6a7 ouch. it's 8_2_371. I'll fix it. This commit breaks compilation 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2362 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-04 07:47:28 +00:00
Stefan Reinauer
d34758f05a rename southbridge i440bx to its actual name i8371eb 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-04 07:45:45 +00:00
Indrek Kruusa
8e3464109e Changelog: 
* src/cpu/amd/model_lx/model_lx_init.c
  L2 cache initialization removed (moved to northbridge.c)
* src/include/cpu/amd/lxdef.h 
  more checked values
* src/northbridge/amd/lx/northbridge.c
  L2 cache initialization added
  cpubug() commented out
* src/northbridge/amd/lx/raminit.c
  empty function sdram_set_registers() is in use, don't remove
* src/mainboard/artecgroup/dbe61/Config.lb
  irqmap changes
* src/mainboard/artecgroup/dbe61/irq_tables.c
  tentative changes to irq table (currently not in use)
* src/mainboard/artecgroup/dbe61/mainboard.c
  irq assigned manually to NIC
* src/mainboard/artecgroup/dbe61/Options.lb
  gcc 4.0 is OK
* targets/artecgroup/dbe61/Config.lb
  64K for VSA is OK at moment
 
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-03 16:48:18 +00:00
Stefan Reinauer
8ad7c06535 slightly changed C.D. Hailfinger's precompressed rom stream patch 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-03 16:19:27 +00:00
Jonathan McDowell
085cb4b4ca Allow setting of serial port speed in EPIA-M config file. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-02 12:46:13 +00:00
Jonathan McDowell
5eca3489b7 Add newer Via Nehemiah stepping levels. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-02 12:26:47 +00:00
Indrek Kruusa
f4c0b596a2 Geode LX: this patch adds configuration/status/self-test MSR definitions 
for L2 cache and fixes wrong  P2D defines.
This also patch adds L2 cache initialization for Geode LX CPU.

Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-08-02 11:30:32 +00:00
Richard Smith
d7088c459c - Fix some copy bugs and thinkos in the i440bx SMbus 
read code.  SBbus reads to RAM now work. Yah!  
- Rename the register constants to something I can look at 
more easily.
- Make the logic flow match the flow from V1 assembly 
- #if 0 out other SMbus functions that are still broken.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-30 00:23:20 +00:00
Richard Smith
01789b630f - fixup Bitworks/IMS to use private copy of SMbus debug routines 
Re-enable the SPD dump routine in this Bitworks/IMS code and make
it work like the Asus/p2b.  This avoids having to hack the
sdram/generic_dump_spd.c for a single mem controller.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-29 18:01:43 +00:00
Richard Smith
924f92faa2 - Add support _framework_ for the Asus p2b. 
- New superIO winbond/w83977tf
- Add single memory controller SBbus debug routine
into a file private to the i440bx

This adds support the start of support for an Asus p2b
mainboard.  Current limitations are the same as for the 
Bitworks IMS board.  Reads from the SMbus don't work.

Moving dump_spd_registers() into its own private copy
solves the problem of having to go hack on the version that
included in src/sdram to only do one memory controller.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-29 17:40:36 +00:00
Ron Minnich
5e9dc23120 This patch adds support for the AMD LX cpu. 
There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok.  Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.


Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-28 16:06:16 +00:00
Ronald G. Minnich
59fc4db642 "Hey Ron - Attached is a simple patch that enables the upper banks on the 
UART.  If the upper banks are enabled, then the Linux 8250 driver knows
how to set baud speeds greater then 115200.  This was prompted by David
Woodhouse.

Jordan"




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-27 04:05:43 +00:00
Richard Smith
cb8eab482f add framework for i440bx chipset 
add support for NSC pc87351 SuperIO
add Bitworks/IMS manboard config

This is a very basic framework for the i440bx chipset and the 
Bitworks IMS board that uses it.  Most things are 
structure only.

Known issues:
- SMbus reads to the RAM SPD come back
all zero.
- dump_spd_registers() is commented out since it breaks with
the default setting of generic_dump_spd.c where it wants
2 memory controllers.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-24 04:25:47 +00:00
Ronald G. Minnich
4788effb04 restore the old code for enabling flash. The new amd code did not work. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-21 23:21:01 +00:00
Ronald G. Minnich
da7ee9fa07 These changes incorporate steve goodrich'es fixes, and one bug that is 
disabled. 

cs5536: add new entires for SB  control etc. 
cs5536.c: chip_enabled function moved to chip_init, so it only gets run
once.
IRQ setup improved
gx2def.h: new defines added
vr.h: new file, with new def's for virtual register control. 
mainboard config.lb: new entries added for nb and sb control.
chipsetinit.c: new controls added -- I forget all the details :-)
grphinit.c: new function added
northbridge.c: new IRQ control added. FlashChipSetup added, controlled
by chip info setupflash struct member. Currently, if enabled, this hangs
OLPC in linux PCI scan.
chip.h: new struct members added for unwanted device enable, flash setup 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-21 19:21:38 +00:00
Stefan Reinauer
87f194dd9e this code is for writing the mp table, so only execute it when 
we actually have one. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-19 16:58:43 +00:00
Stefan Reinauer
4f1cb23426 move mptable to 960k to 1M 
https://openbios.org/roundup/linuxbios/issue55

This patch is a little bit enhanced, it keeps the ppc table consistent,
which Yinghai's original patch did not.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-19 15:32:49 +00:00
Stefan Reinauer
792ebfecd3 closing issue 44: rename ram clocks in cmos.layout 
https://openbios.org/roundup/linuxbios/issue44



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-19 14:26:41 +00:00
Stefan Reinauer
ef0a24381b fixing aruma build as suggested by mail ;-) 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-18 18:09:36 +00:00
Stefan Reinauer
f780d02295 sorry for the inconvenience. this is a test commit. 
breaking a build is intentional. It will be fixed in a bit.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-18 16:53:19 +00:00
Stefan Reinauer
e26d66e9dd fix handling of mkelfImage'd binaries 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-07-11 09:04:52 +00:00
Ronald G. Minnich
707097fc1c fix interrupt for f5 (ehci) 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-27 02:26:06 +00:00
Ronald G. Minnich
aad235e906 changes per steve goodrich. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-27 01:38:17 +00:00
Ronald G. Minnich
92e8b809b4 fix typo on duplicate line. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-24 14:46:26 +00:00
Stefan Reinauer
5560a34c88 fix compilation of s2892. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-23 20:10:21 +00:00
Ronald G. Minnich
53a00b7138 match settings per steve goodrich. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-23 03:39:10 +00:00
Ronald G. Minnich
88fb1a6c37 set up interrupt values for the southbridge, and add a function to 
manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c 
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-22 04:37:27 +00:00
Ronald G. Minnich
9d0b30dd2b Fixes from AMD. Tested to build on rumba and olpc, and builds. 
Tested to booting linux on olpc, and boots. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-20 03:53:54 +00:00
Stefan Reinauer
1f96360315 delete two empty files 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-18 07:44:45 +00:00
Stefan Reinauer
3951027f57 * delete two empty files 
* commit SMM lock code.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-18 07:41:48 +00:00
Ronald G. Minnich
2d7bb59018 fix idiiot typo I did not catch. 
add support for conditional enable of uarta interrupt.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-18 02:28:07 +00:00
Ronald G. Minnich
48415d5cf6 add irq mapper support for OLPC and other boards that need this mapping 
done for the gx2 north. tested on OLPC. 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-18 01:29:42 +00:00
Stefan Reinauer
6ab0fa9fed add k8 processor name handling as required by the k8 revision guide. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-14 23:22:04 +00:00
Ronald G. Minnich
fd14d4414a remove erroneous cache disable. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-14 13:56:28 +00:00
Ronald G. Minnich
73c92a4a7c ron forget an svn add. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2319 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-12 20:37:33 +00:00
Ronald G. Minnich
90dc0db6de Get rid of #if 01 and debug prints that are compiled out. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-12 20:36:51 +00:00
Ronald G. Minnich
fb93749642 changes from AMD for making OLPC video work. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-10 22:57:15 +00:00
Ronald G. Minnich
890ee09a32 further development of OLPC. Set vsm size to 35k. add PCI IRQ for USB. 
Set linuxbios size to 28k. Drop debug level to 8.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-06-08 14:19:49 +00:00
Stefan Reinauer
2d1fe3700e fix two mainboards that have been broken by someone who does not use abuild.sh 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-26 16:23:00 +00:00
Ronald G. Minnich
b5fcfdbf89 add DK8HTX support. 
VSAs now required to be nrv2 compressed


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2312 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-25 22:08:23 +00:00
Stefan Reinauer
d0cffada3c fix broadcom/blast, tyan/s2735, tyan/s2891, tyan/s2895 broken by r2307 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-25 12:40:03 +00:00
Yinghai Lu
9dd8d56192 co processor support with s2891 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2310 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-18 17:09:14 +00:00
Yinghai Lu
9a8e36da2d init the ECC for BSP and AP at the same time. So reduce init cpus time 
from 2.1x to 1.1x or from 4x(SERIAL_CPU_INIT) to 1.1x  


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-18 17:02:17 +00:00
Yinghai Lu
2b396cdcf2 add option to decide to use onboard vga or addon card. 
CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-18 16:54:30 +00:00
Ronald G. Minnich
bad9d105cf cleanup some of the compressed rom stream ugliness -- more to do! 
olpc and rumba can now boot linux out of flash. vsa was resized to 64K. 
olpc and rumba now used compressed payload -- thanks stefan!


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-18 03:07:16 +00:00
Ronald G. Minnich
5d573c28e7 Commit for IDE NAND FLASH 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-16 02:51:16 +00:00
Ronald G. Minnich
98e904ea7c OLPC now builds and works just fine. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-15 04:44:15 +00:00
Ronald G. Minnich
b9a335cb9b correct it, finally. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-12 20:05:08 +00:00
Ronald G. Minnich
6084160f2d memory size in cf07 
goodrich pll code
disable havedmi


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-12 18:42:34 +00:00
Ronald G. Minnich
49a89f19f2 Use a real variable to configure rom base for vsa ... 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-06 02:54:45 +00:00
Ronald G. Minnich
694d20e2d6 This is to enable COM1 early. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-05 18:18:33 +00:00
Ronald G. Minnich
1656c18d76 reorder early startup so that it might work. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-05 03:54:31 +00:00
Ronald G. Minnich
070a10f759 mods for early printing on OLPC 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-04 23:05:49 +00:00
Stefan Reinauer
ab4f5d0c10 fix the tree 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-04 10:08:04 +00:00
Yinghai Lu
7ac38a33f6 don't wait core0 started twice 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-04 01:05:22 +00:00
Yinghai Lu
52377deec0 core range and set_init_ram_access 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-04 00:58:14 +00:00
Yinghai Lu
b73fd56488 rm unused file 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-04 00:48:49 +00:00
Yinghai Lu
608d4b2c44 merge zrom to rom_stream and print olen ilen 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-04 00:47:15 +00:00
Stefan Reinauer
4c47532134 oops! Slap me on the head for this one. Quick fix for ward until 
YhLu's suggestions are all there..


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-03 23:10:00 +00:00
Ronald G. Minnich
c01fe5d1b6 more changes; rumba enet works fine now. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-03 03:30:23 +00:00
Stefan Reinauer
dc7b71cffa enable compressed payload per default 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-02 12:07:36 +00:00
Stefan Reinauer
ead73689db add automatic payload compression method to LinuxBIOS 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-02 12:05:13 +00:00
Ronald G. Minnich
d3ba4aaa24 Fall back to pre-broken settings and setup for GX2. 
We lost a few things, but this is still worth it.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-05-02 03:07:11 +00:00
Stefan Reinauer
ae3cbe951b typo 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-29 00:12:30 +00:00
Li-Ta Lo
64f07fb21c remove more code 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-27 20:44:53 +00:00
Li-Ta Lo
c1a4b2b0e5 code cleanup, comments added 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-27 18:40:15 +00:00
Ronald G. Minnich
b947b14734 more code removal and removal of incorrect register settings. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-27 17:46:27 +00:00
Ronald G. Minnich
94571a4767 removing redundant and unneeded calls to functions. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-27 17:37:23 +00:00
Ronald G. Minnich
3716427e7f we don't need msr_init 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-27 15:10:55 +00:00
Li-Ta Lo
b7a09b4f19 some todo and comment for ron. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-26 22:07:16 +00:00
Ronald G. Minnich
417d8c44f9 set irq options. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-25 20:05:38 +00:00
Ronald G. Minnich
cf120d1a89 builds and should do the right things for sb for interrupt routing. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-25 19:57:39 +00:00
Ronald G. Minnich
1c2f49e74a to give ollie a look. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-25 19:40:20 +00:00
Ronald G. Minnich
5ee2bbb90c fix the msr.lo for olpc 0x20000019 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-25 04:07:44 +00:00
Stefan Reinauer
6c20eb4400 hex values with 0x prefix 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-24 16:56:05 +00:00
Richard Smith
2a7352cb9d Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device() 
Default is 255.

This allows mainboard configs for working across various groups
of boards that differ a device that may not loaded.

If you search for a device that is not loaded and max buses is 255
then there can be up to a 8 second delay to search the entire PCI space.
Board configs that know thier max bus can limit this search space.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-23 23:12:21 +00:00
Ronald G. Minnich
2f19800268 fix so that olpc uarts come up enabled. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-23 19:21:12 +00:00
Jonathan McDowell
496450c4eb Lower debug progress messages in vt8623 init to debug level rather than error. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-21 16:43:06 +00:00
Li-Ta Lo
a910a3a022 more 5536 -> 5536 conversion 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 22:54:32 +00:00
Li-Ta Lo
bbdaeaf55c change to 5536 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:40:20 +00:00
Li-Ta Lo
32c315b1ef change to 5536 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:38:14 +00:00
Li-Ta Lo
b8f4f8891d remove dup files 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:32:43 +00:00
Li-Ta Lo
5d69896c87 add cs5536 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:31:47 +00:00
Li-Ta Lo
05c0869fac boot to kernel 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:26:01 +00:00
Li-Ta Lo
37784b429d added cs5536 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:22:40 +00:00
Li-Ta Lo
bc5a821f1e add cs5536 directory 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:21:25 +00:00
Li-Ta Lo
5c97d78b1a add cs5536 directory 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-20 21:21:13 +00:00
Li-Ta Lo
965b5ad85b resolve conflict 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-19 15:11:01 +00:00
Ronald G. Minnich
36c00aa39b fix adjustment for sizeram 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 22:40:53 +00:00
Ronald G. Minnich
61083dad0f add back in missing line 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 21:34:32 +00:00
Ronald G. Minnich
55e10fe3a4 set up timing 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 21:21:10 +00:00
Ronald G. Minnich
170ce333ca add ram resources 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 20:42:58 +00:00
Ronald G. Minnich
df46cb205d added the olpc target and support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-18 16:36:58 +00:00
Ronald G. Minnich
ea9db56d0e add SystemPreInit() and support 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-13 19:44:50 +00:00
Li-Ta Lo
d8d8fffa0e minor modification 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-13 17:00:38 +00:00
Stefan Reinauer
cf648c9a99 this was in my queue since 2005/10/26 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-11 19:23:57 +00:00
Stefan Reinauer
fbce0ffb92 small fixes to get Ward Vandewege's Tyan board booting. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-11 18:36:42 +00:00
Ronald G. Minnich
4b8cf1d30a added chipsetinit function, many defines. addec call to chipsetinit to 
northbridge.c
builds fine on lippert


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-10 23:32:23 +00:00
Ronald G. Minnich
45f6c5e3d4 add cpureginit to romcc code. 
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
 2006-04-10 16:40:19 +00:00