Also show hart id in trap information for easier debugging.
Change-Id: I20acf86e1af111600c158295ae03b2167838d127
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
1. Simplify payload code and convert it to C
2. Save the FDT pointer to HLS (hart-local storage).
3. Don't use mscratch to pass FDT pointer as it is used for exception handling.
Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8
Signed-off-by: Xiang Wang <wxjstz@126.com>
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31179
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE.
Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch ensures to enable IFD GBE region only for required
CFL RVP8 and 11 supported by Intel IOTG team.
TEST=Ensure CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not selected
for CFL-U and WHL-U boards
Change-Id: If3fcd23c32f9afd2004fb176c0324f089f2ee412
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Have the generated Chrome OS ACPI GPIO table provide the ACPI GPIO
pin number instead of the raw GPIO number when possible.
This is necessary if the OS uses a different numbering for GPIOs
that are reported in ACPI than the actual underlying GPIO number.
For example, if the SOC OS driver declares more pins in an ACPI GPIO
bank than there are actual pins in the hardware it will have gaps in
the number space.
This is a reworked version of 6217e9beff
which does not try to convert CROS_GPIO_VIRTUAL.
BUG=b:120686247
TEST=pass firmware_WriteProtect test on Sarien
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7
Reviewed-on: https://review.coreboot.org/c/31080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Datasheets describe the used command as 'I2C Read' but adding the
word 'eeprom' in between should avoid further confusion with other
block commands.
Followups will add a symmetrical pair of commands i2c_block_read()
and i2c_block_write() that operate via I2C_EN bit and have a 32
byte size restriction on block transfers. For some hardware revision
these block commands are available, while 'I2C Read' was not.
Change-Id: I4494ab2985afc7f737ddacc8d706a5d5395e35cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Convert vboot_platform_prepare_reboot() to call a function in
soc//stoneyridge. A subsequent patch will add another call to
the new function, and this change removes any inference of a
dependency on vboot.
BUG=b:122725586
Change-Id: I634fcd030e206c790bda697a3dbef4e8cc21b3a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable ASPM L1.2 support for embedded realtek card reader, after change
the power consumption for SD controller from 5mW to less than 2mW.
BUG=N/A
TEST=Build and boot up on Arcada platform, check the PCI configuration
on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader
is also 0x0f.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0
Reviewed-on: https://review.coreboot.org/c/31145
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI
configuration in devicetree. This change enables exporting the bluetooth
reset GPIO to the kernel for use in an rf-kill operation.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS
Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
XHCI is currently named as XHC1. This leads to namespace lookup error in
the kernel when children USB ACPI devices are added under the scope of
XHCI device.
BUG=b:123296264
BRANCH=octopus
TEST=Boot to ChromeOS; Ensure that the below error is resolved in the
kernel dmesg
[ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup
failure, AE_NOT_FOUND (20170728/dswload-210)
Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add separate functions for selecting the port and reading the port.
Romstage can now read incremental from the data port.
Change-Id: I0ffde3bc2a4415a8af99af2275d16f6609099e37
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reduce the number of fw_find_file calls by returning the file structure
at fw_cfg_check_file. The file structure can then be used to allocate memory
and access the file content directly without recurrence searching.
Remove now unnecessary function fw_cfg_load_file.
Fixed breaking function calls and add include guard at fw_cfg_if.h.
Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
In payloads, we didn't set GPIO modes. We have to set up GPIO mode in
coreboot for payloads.
BUG=b:80501386
BRANCH=none
TEST=HW reboot works in depthcharge
Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31148
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:31139 fixs few ACPI type error. Here is few more typo mistake.
Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31152
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move functions not available in PRE_RAM into seperate file.
Makes it easier to share code between rom and ramstage.
Change-Id: I0b9833fbf6742d110ee4bfc00cd650f219aebb2c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently, selflock_check() verifies that the binary is loaded in an
usable RAM area.
Extend its functionality so we can also check that BL31 is loaded in
a manually reserved area, and fail early if the range is not protected.
Change-Id: Iecdeedd9e8da67f73ac47d2a82e85b306469a626
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Modifiy Makefile so that we can get board ID in verstage.
BRANCH=none
BUG=b:117916698
TEST=manually
Change-Id: Idcdb6e07f565c937185cab811abac0ce47e5e3a7
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Currently SMBUS registers are accessed through IO, but with stoneyridge
they can be accessed through MMIO. This reduces the time of execution by
a tiny amount (MMIO write is faster than IO write, though MMIO read is about
as fast as IO read) as most of the time consumed is actually transaction
time. Convert code to MMIO access.
BUG=b:117754784
TEST=Used IO to write and MMIO to read, to confirm a one to one relationship
between IO and MMIO. Then build and boot grunt.
Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.
Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.
TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad.
This patch corrects the configuration.
BUG=NONE
BRANCH=octopus
TEST=emerge-octopus coreboot
Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake
the AP from suspend. Also create a task to initialize the hostevent
wake mask properly.
BUG=b:123325238,b:123325720
BRANCH=None
TEST=from AP console: powerd_dbus_suspend
from EC console: hostevent (make sure wake mask set)
from EC console: gpioset PCH_WAKE_L 0
Make sure device wakes up
Also, checked to make sure keyboard press wakes up
device from S3.
Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Unless things changed considerably, this file doesn't contain any
firmware. It is merely replacing a configuration EEPROM for the MAC
address etc. So don't call it firmware.
Change-Id: Ife6190639e7f05da2cb6eddeb1b0db0e8ffc8e6e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
List Raydium touchscreen in the devicetree so that the correct ACPI device
are created.
BUG=b:121105424
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
reflash the coreboot to DUT, make sure the Raydium touchscreen can work.
Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf
Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31116
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL moves some initialization steps from bootblock to verstage. This
will save us about 2700 bytes (before compression) / 1024 bytes (after
LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled,
these initialization steps will be done in romstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/30331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now we have usb2eye configuration register in FSPUPD, so we need
to add an interface to override usb2eye setting.
BRANCH=octopus
BUG=NONE
TEST=Verified usb2eye custom setting works
Change-Id: I5c500964658072eaaf59364242aa928df25d99d1
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW
reset for SoC and H1.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; manually verified the do_board_reset() on
Kukui P1
Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Separate WDT reset function from WDT driver, then we can use the common
WDT driver and have a board-specific reset function on different boards.
In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config
"MISSING_BOARD_RESET" in Kukui to pass the build for now.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot; emerge-kukui coreboot;
Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31121
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board has almost the same schematics as [xt]60 so this should work.
See also commit 7971582e with Change-Id
Iff6dac5a5f61af49456bc6312e7a376def02ab00.
Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch removes stale ASL entries added in past due to chromeos
requirement.
BUG=115755982
TEST=Build and boot ICL platform without any problem.
Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31117
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If the VTd feature is enabled, there will be up to two fixed resources
which are set up by the FSP. Add these resources to the list of system
resources so that the PCI enumerator will know them.
Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents.
In addition turned off Vtd and verified that no DMAR table is generated
at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In preparation of generating DMAR tables, provide the hook in SoC scope
for the systemagent to write ACPI tables. The complete functionality is
SoC-specific. Therefore the entry hook is defined as a weak function which
can be overridden by SoC code. If the SoC does not have support for
generating DMAR tables this hook will do no harm.
Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Select FSP_M_XIP if MAINBOARD_USES_FSP2_0, since all SkyKabylake
boards require FSP-M XIP when FSP 2.0 is used, and since not
having it selected results in a non-booting image.
Also, put select FSP_T_XIP if FSP_CAR in proper alphabetical order.
Change-Id: I6d3986eda18297b12490cefb236f5de5faca6550
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In some cases (e.g. Arm architecture variants), include paths are stuck
into <stage>-generic-ccopts rather than CPPFLAGS_<stage> (in fact, the
whole redundancy between these two is kinda stupid and we should
probably eliminate the latter, but I don't want to get into that right
now). This patch makes sure those paths are also correctly translated
when invoking $(MAKE) for vboot.
Change-Id: I37f09b88e555567590664e0e6fac23c34fd887df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Working:
- USB (Partially. Check "Not working")
- PCIe
- PCIe graphics
- All SATA ports
- Native memory init
- On-board audio (back and front)
- S3 (Sleep and wake)
Not working:
- Fan control
- USB (If the keyboard has a USB Hub or if the keyboard
is connected through 2 or more hubs then it doesn't
initialize in time. A simple reboot allows the
keyboard to be used in SeaBIOS and the bootloader)
Untested:
- PS/2
- On board graphics
Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2
Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30767
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.
BUG=b:79982669
TEST=Checked that code compiles with changes.
Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ELAN touchpad supports up to 400KHz, so we need to limit its CLK
frequency to 400HKz.
BUG=b:123376618
BRANCH=octopus
TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz
Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
While branded as thinkcentre a58 this board can also be found as
"L-IG41M".
Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Current Melfas touchscreen driver cannot unregister ifself when
connecting without Melfas touchscreen or connecting with other devices.
And Melfas touchscreen FW can use I2C and HID over I2C driver, so
switch to using HID over I2C driver.
BUG=b:122710830
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186
Reviewed-on: https://review.coreboot.org/c/31062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
MASK_STATUS disables interrupt status generation for the entire GPIO
controller when any debounce register is configured. This causes
problems when the kernel is loading drivers because we could lose
interrupts for previously loaded devices.
sb_program_gpios is also not setup to wait when configuring
PAD_DEBOUNCE, so there is a potential that we could lose the interrupt
status enable bit for other registers. By disabling MASK_STATUS we avoid
that problem.
BUG=b:113880780
BRANCH=none
TEST=Ran a reboot stress test that concluded that we are no longer
losing TPM interrupts while booting.
Change-Id: Ife1db3b1449f205092509595cbc3eca511bff57a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Also make soc_get_tss_table public and weak instead of static
in intelblock so it can be overridden in denverton.
Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Intel RTC common code driver need to turn on RTC itself.After the
change, cannonlake and icelake platform will have RTC enabled.
BUG=b:123372643
TEST=build and boot up on sarien platform, check .config to see
CONFIG_RTC is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536
Reviewed-on: https://review.coreboot.org/c/31112
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit dc666f5 (soc/intel/cannonlake: Change in SaGv options) added a
conditional preprocessor directive, but its condition was incorrect
because SOC_INTEL_CANNONLAKE is selected for CNL, CFL and WHL. Thus, an
explicit check for !SOC_INTEL_COFFEELAKE is required.
While we are at it, clean up the comment above a bit.
BUG=b:123184474
Change-Id: I8a6959bb615fb5668cbfe54339747d135bd5a005
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31095
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Upper 128bytes of CMOS and RCBA are already enabled at bootblock.
Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boots again to payload not found on qemu.
Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/30554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This board does not have PMH7.
Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31065
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Port the existing denverton tables to intelblock
- Add C-States table for denverton
Note: Removed code is functionally identical to corresponding
common code.
Tested-on: scaleway/tagada
Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
New emmc DLL values for Ampton
BUG=b:122307153
TEST=Boot to OS on 5 systems
Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
By default this board is configured to not power up after an
EC reset. However in the case of a cr50 firmware update that
will reset the EC it will end up powered off. In order to have
it stay powered up configure the board to power up. This will
get reset to the configured default when it boots again.
BUG=b:121380403
TEST=update cr50 firmware and reboot to ensure system boots and
does not end up powered off.
Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to allow the mainboard to configure the system before a
cr50 initiated update reset add a weak function that the mainboard
can override if necessary.
This will allow a board that would otherwise be configured to
stay off after an EC reset to instead power up after the reset and
not end up in a shut down state after a cr50 update.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot
Change-Id: I11f9e8c9bfe810f69b4eaa2c633252c25004cbd0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Export the SOC level function to set the After G3 state so it
can be changed by the mainboard. The setting will be restored
by a normal boot but in some circumstances coreboot wants to
ensure that it will be powered up again after a reset.
BUG=b:121380403
TEST=update cr50 firmware on sarien and reboot and ensure the
host does not power off after the cr50 initiated reset.
Change-Id: I6cd572ac91229584b9907f87bb4b340963203c32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling CpuRatio UPD for FSP will ensure it does not force a
hard reset to set the CPU Flex Ratio at boot. This is important
in a recovery mode boot where the SOC will lose power and need
to set the flex ratio again.
Disabling SaGv makes recovery mode training faster and mirrors
the setting that was done on Skylake.
BUG=b:123305400
TEST=reliably enter recovery mode on sarien
Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for
upcoming payloads.
BUG=b:121169122
TEST=Build and boot up fine into OS on sarien and arcada platform.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237
Reviewed-on: https://review.coreboot.org/c/31054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It was observed system suspend/resume failure while running
RunInDozingStress. Apply correct GLK usb clock gating register
value to mitigate the failure.
BRANCH=octopus
BUG=b:120526309
TEST=Verified GLK clock gating register value after booting
to kernel.
Change-Id: I50fb16f5ab0e28e79f71c7f0f8e75ac8791c0747
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support Synaptics touch pad for Aleena/Kasumi.
BUG=b:122549449
BRANCH=master
TEST= Check if synaptics touch pad working in ChromeOS.
Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31064
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.
The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.
The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z
The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.
Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The iGPU always needs access to its stolen memory. For proper IOMMU
support, we have to make the OS aware of that.
Directly below TOLUD lies the data stolen memory (BDSM) followed by
the GTT stolen memory (BGSM), the iGPU needs access to both.
Change-Id: I391d0a5f1ea14bc90fbacabce41dddfa12b5bb0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Send required EC command to enable ACPI S3 wake up from lid switch.
BUG=b:120748824
TEST=Put Sarien system into S3 and then wake up from lid switch
successful.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I13f3469847b0886147b8b624311a1ece796f847b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This reverts commit ab1227226e.
There were significant changes around soc_reset_tco_status() that this
code needs to be adapted to.
Change-Id: I563c9ddb3c7931c2b02f5c97a3be5e44fa873889
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
ARCH_RISCV_RV{32,64} will now select ARCH_RISCV.
Change-Id: Ia7a1a8f0bfab20e91b8429dd6dd3e9a4180a0a5b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25427
Reviewed-by: David Guckian
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ratio_max step is appearing twice when (ratio_max - ratio_min)
is evenly divisible by the ratio step.
This is because in this case there are no rounding down of ratio_max in
the for loop.
Thanks Jay Talbott for the step calculation algorithm.
Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A programmable logic device used by Kontron as EC on their COM express
modules. The name `kempld` is taken from Linux kernel sources, as is the
I2C driver. The meaning of the acronym is unclear, probably: Kontron
Embedded Module PLD.
Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to support the physical recovery GPIO on sarien it needs
to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO
number in the coreboot table appropriately so that depthcharge can
correctly determine the GPIO number. The same is done for the
write protect GPIO in this table.
Additionally since we are reading a recovery request from H1 it
needs to cache the result since H1 will only return true on the
first request. All subsequent queries to H1 will not indicate
recovery. Add a CAR global here to keep track of the state and
only read it from H1 the first time.
BUG=b:121380403
TEST=test_that DUT firmware_DevMode
Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31043
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable gpio_keys driver for bobba and add required configuration in the
device tree to handle the pen eject event.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder.
Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently without any trigger the wakeup event is generated on both the
rising and falling edges of the GPIO input. Add support to specify the
trigger explicitly so that the configuration can be passed to the
kernel.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder and ejected from its holder.
Change-Id: Ifb08ba01106031aa2655c1ae2faab284926f1ceb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add new helper macros to enable configuring debounce duration for a
GPIO input. Also ensure that the debounce configuration is not masked
out.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce
duration is configured as expected.
Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently all the helpers support configuring GPIO_DW0/1 registers. In
some architectures there is an additional configuration GPIO_DW2 register
that can be used to configure debounce duration etc. Add a helper macro
to enable configuring GPIO_DW2 pad register.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the current
configuration is not disturbed by turning on the GPIO_DEBUG option and
verifying the debug output before and after the change.
Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There's no such limit on 64 Bit coreboot builds.
* Fix comment in cbmem.h
* Remove 4 GiB limit on Cavium SoCs
Tested on opencellular/elgon.
Still boots Linux as payload.
Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
This CL adds a new function mt8183_early_init, which includes all
initializations that should be done in early stages. All mainboards
using MT8183 should manually call it in either bootblock or verstage.
BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel
Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Added new routine cr50_i2c_probe() which ensures that communication
with the Cr50 over I2C is good prior to attempting other initialization
of the Cr50 and TPM state. This avoids a race condition when the Cr50
is first booting that it may reset it's I2C slave interface during the
first few I2C transactions initiated from coreboot.
BUG=b:120009037
BRANCH=none
TEST=Run the Cr50 factory update against Careena board. Confirm that
I2C reads are retried until the DID VID is valid. Tested against debug
Cr50 firmware that forced failure of cr50_i2c_probe() and verfied that
coreboot shows recovery screen.
Change-Id: I47c59a32378ad00336277e111e81ba8d2d63e69a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to
enable USB 2 port 6 and USB3 port 5 which is already enabled in device
tree related changes.
BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.
Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable PCIe WLAN for hatch
1. Enable PCI port 14 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 3 for PCI port 14
3. GPIO pad config for WLAN and BT
USB port for BT has already been enabled so not included in this patch
BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics
Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Intel DG41WV, the stage cache gets properly created and used
on S3 resume.
Change-Id: Ie46c1416f8042d5571339b36e1253c0cae0684b8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Foxconn D41S.
Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25605
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Lenovo thinkpad X200: on cold boot the external stage cache
gets created and the cached ramstage gets successfully used on the S3
resume path.
Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25604
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Tested on Intel D945GCLF and Lenovo Thinkpad X60, on cold boot the
external stage cache gets created and the stage cache gets properly
used on S3 resume.
Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25603
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some CPUs, (Intel core2 and pineview) have slightly different SMRR
MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different
location, have slightly different semantics and need SMRR enable in a
locked down IA32_FEATURE_CONTROL MSR.
This change takes away the possibility to (not) lock
IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to
work. Since sockets cover multiple CPUs of which only some support
SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place,
even though it gets meaningless on those CPUs. Locking that bit was
the default anyway.
With this patch Intel Netburst CPUs also configure
IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures
Software Developer's Manual those CPUs support that MSR so issues are
not to be expected.
Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27586
Tested-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup to different block transactions are similar
enough to have common place to call execute_command()
in.
Change-Id: I671fed280f47e6bc673eb7506f09ed6ed36d2804
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26763
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds helper to test for SMBHSTSTAT flags for
hardware having finished or failed a transaction.
Change-Id: Idea15e03edde7aeedf198c1529f09c24a5bc0b06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implement the common start of transaction.
Fixes a problem where smbus_wait_until_active()
can miss SMBHSTSTS_HOST_BUSY being set, if
transaction completes very fast. Or if we are
single-stepping or executing under SerialIce
emulation.
Change-Id: Icb27d7d6a1c54968950ca292dbae05415f97e461
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implements the common parts of any SMBus transaction
with a stub to log and recover (TBD) from timeout
errors.
Bits in SMBHSTCTL register are no longer preserved
between transactions.
Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Enable COM1, COM2, PMC1 and PMC2
TODO: Look at additional configuration and EC space.
Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.
Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Add support for the SuperIO part of IT8528E
* Based on the IT8528E datasheet and tests on vendor firmware
TODO: Add support for accessing EC space, which should be
implemented in src/ec/ instead, as it's a separate logical unit.
No datasheet is publicy available.
Tested on wedge100s.
The serial works under the OS without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Quick and ugly approach, just paste the file in place,
dropping any __PRE_RAM__ parts. That's the way it was
previously done for fam15tn already, refactoring common
parts will happen on a later date.
Change-Id: I29fd421fb4aef984d117912ac836dee71d3d73ea
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The two IO regions of the keyboard controller are 1 byte long, not 8.
Change-Id: I7319ce9f84181759f4dc7b59c0020f3a5dd5dc03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/30958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Replace device name from B0D4 with TCPU for DPTF sensor. This
helps to maintain consistency between coreboot and UEFI BIOS.
Change-Id: I962d74fc1baa07581d065734aaabb4dcd5e3d247
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
RPFN is a R/WO register we write on it in i945/early_init.c and i82801gx/pcie.c
Drop the romstage write.
Change-Id: If9a131ad12530876a650b7a38daa9c9fc52aefb7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is possible to configure debounce, but leave it disabled by specifying
a 0 value for the timeout. Add a define for allowing to do so via the
PAD_DEBOUNCE() macro.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=compile
Change-Id: I9de61297b0677cc904535a51c16970eecb52021d
Reviewed-on: https://review.coreboot.org/c/30998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable dptf functionality for IceLake based U and Y systems.
Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination
Configuration.
BUG=b:79982669
TEST=Checked that code compiles with changes.
Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kukui with vboot enabled will build with `detachable_ui`, which needs
larger space in CBFS for more complicated assets. So we need to revise
FMAP sections:
- BOOTBLOCK (not really used) only needs <= 32K.
- GBB can be much smaller since assets moved from GBB to CBFS.
- FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can
get larger continuous space.
- COREBOOT(CBFS) should take all space left.
Since FMAP and COREBOOT have changed location, the system will need to
reflash EC (which contains the new bootblock) as well.
BUG=b:123202015
TEST=Builds and boots on Kukui P1
Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
disable unused usb2 ports of bard and ekko skus
BUG=120874946
TEST=build a test firmware and run lsusb to check usb ports
Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30986
Reviewed-by: Vincent Wang <vwang@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove guards around CPU code on which all platforms use parallel MP
init code.
This removes the option to disable HT siblings.
Tested on Foxconn D41S.
Change-Id: I89f7d514d75fe933c3a8858da37004419189674b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use parallel MP init code to initialize all AP's.
Also remove guards around CPU code where all platforms now use
parallel MP init.
This also removes the code required on lapic init path for
model_6fx, model_1017x and model_f4x as all platforms now use the
parallel MP code.
Tested on Intel DG41WV, shaves off about 90ms on a quad core.
Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.
Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.
This removes the option to disable HT siblings.
Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This places the parallel mp ops up in the model_1067x dir and is
included from other Intel core2 CPU dirs that can use the same code.
Tested on Thinkpad X200 on which boot time is reduced by ~35ms.
Change-Id: Iac416f671407246ee223075eee1aff511e612889
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/23434
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 13v3 is just a 13v2 with TPM added, so duplicate 13v2 config
and change strings where needed. Leave MAINBOARD_PART_NUMBER unchanged
since boards were initially shipped with 13v2 firmware, and changing
it now would cause flashrom to throw a board mismatch error.
Change-Id: I1a5e4c84cc9444bb9731b6dcc4de2ce7427dbbb1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/31010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Adjust default CBFS_SIZE to match that used in configs for building
Change-Id: Ibe1312560a923dcdefb8af52a721ab76c0b08a2e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/31008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
close the FP module power in power off (s5)
BUG=122887366
BRANCH=Nami
TEST= build test firmware and measure the fp power enable pin
Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30910
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Vincent Wang <vwang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Followup removes SIPI_VECTOR_IN_ROM and it seems reasonable
enough to force the alignment unconditionally to page size.
Reason for the conditionals is the alignment is not possible
with romcc bootblocks having total size less than 4 kiB.
Change-Id: I0ff2786f80a319ebb3215d4fd696cda3e15c3012
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30855
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New emmc DLL values for Meep.
BUG=b:122308271
TEST=Boot to OS on 13 Meep system
Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31021
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BMC KCS interface must be advertised to the host OS in order
for automatic load of the ipmi module to work. Expose the KCS
interface via ACPI.
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/c/19822
Reviewed-by: Piotr Kubaj <pkubaj@anongoth.pl>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b.
Reason for revert:
It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config,
not its SCI configuration.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:113880780
BRANCH=none
TEST=Boot grunt, does not go to recovery screen
Change-Id: I500934f3e03e66c97873accd4a979a23d4509675
Reviewed-on: https://review.coreboot.org/c/30997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Fix regression after commits
4ad7f5b AGESA: Use pcidev_on_root()
33ff44c binaryPI: Use pcidev_on_root()
Previously used call dev_find_slot() returned
pointers to PCI device nodes that were actually
not present in the hardware at all. Register
reads would come back with invalid (0xff) values
and writes would be ignored.
After change to pcidev_on_root(), attempting to
do register operations with non-present PCI
hardware immediately halts with error
get_pbus: dev is NULL!
Change-Id: I785350c171a642207c5fab884a953d45a3bfe592
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds a few southbridge calls needed for parallel MP init.
Moves the smm_relocate() function to smm/gen1/smi.h, since that is
where this function is defined now.
Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU.
Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25618
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Philipp Hug