Commit graph

1305 commits

Author SHA1 Message Date
Aaron Durbin
79587ed894 soc/intel/apollolake: enable postcar console
Unconditionally turn on postcar console for apollolake.

BUG=chrome-os-partner:57513

Change-Id: I3d956be4a5834a4721767d34216eebeabef3e315
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16620
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19 17:02:32 +02:00
Aaron Durbin
dfe614ff9f soc/intel/apollolake: cache boot media post romstage
When the boot media is memory mapped mark it as cacheable
after romstage. Otherwise the boot media is uncacheable and
all loads from it take longer. Loading FSP-S alone in ramstage
went down to 17.5ms from 54ms.

BUG=chrome-os-partner:56656

Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16613
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19 17:01:23 +02:00
Shaunak Saha
c8ae5995bb soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.

BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16564
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15 03:16:46 +02:00
Naresh G Solanki
16e9d459a0 driver/intel/fsp20: move lb_framebuffer function
move lb_framebuffer function in soc/intel/apollolake
to driver/intel/fsp20 so that fsp 2.0 bases soc's can
use common lb_framebuffer function.

Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-09-15 01:16:41 +02:00
Barnali Sarkar
5bf42c6c23 soc/intel/skylake: Add FSP 2.0 support in romstage
Populate SoC related Memory initialization params.

Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.

TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.

Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 00:46:11 +02:00
Duncan Laurie
f8a7b2c008 lpss_i2c: Add Kconfig option to enable debug
It is very useful to have the ability to see I2C transactions
performed by the host firmware.  This patch adds a simple
Kconfig option that will enable debug output.

Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16590
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-14 22:24:06 +02:00
Duncan Laurie
772555a214 lpss_i2c: Change handling of controller enable/disable
This change modifies the lpss_i2c driver to behave more like
the Linux kernel driver.  In particular the controller is only
enabled when processing a transaction, and is disabled after.
This means that errors in one transaction will not affect later
transactions.

Also when disabling the controller the code is supposed to wait
on the enable bit in the "enable status" register and not in
the enable control register.  In order to get access to this
register the reg map was expanded to include all registers.

This was tested with the cr50 TPM driver to ensure that if a
transaction does fail that it can be successfully retried instead
of the bus being unusable.

Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-14 22:23:52 +02:00
Sumeet Pawnikar
35240ebe3c soc/intel/apollolake: Update PL1 value in RAPL MMIO register
Due to an incorrect value set for the power limit PL1, the
system is not able to leverage full TDP capacity. FSP code
sets the PL1 value as 6W in RAPL MMIO register based on
fused soc tdp value. This RAPL MMIO register is a physically
separate instance from RAPL MSR register. This patch sets
PL1 value to 15W in RAPL MMIO register.

BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package power
with heavy workload.

Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 22:18:42 +02:00
Vaibhav Shankar
ef8deaffcb soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0,
_ON/_OFF methods to power gate PCIe during S0ix entry, and
PERST_0 assertion/de-assertion methods.

BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14 22:17:47 +02:00
Aaron Durbin
9e81540b85 soc/intel/apollolake: initialize GNVS structure to 0
The code was not previously initializing the GNVS structure
to all 0's in the ACPI write tables path. Fix this and also
rearrange the ordering of updating the fields to only handle
the chip_info specific bits till last such that most of the
structure is filled in prior to bailing out in the case of a
bad devicetree.

Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16597
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14 15:40:16 +02:00
Werner Zeh
4f2754c720 fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode
The serial IRQ (SERIRQ) used by the LPC interface can operate either in
continuous or in quiet mode. Add a Kconfig switch to select the desired
mode. This switch can now be used on mainboard level to enable the
needed mode per mainboard.

Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:52:53 +02:00
Werner Zeh
9d18e330fd siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC
Since this mainboard provides 4 COM ports on LPC, enable decoding of
the corresponding addresses using the generic LPC decode registers.

Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 22:41:45 +02:00
Werner Zeh
91aea428b5 fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.

Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 06:33:53 +02:00
Vaibhav Shankar
e6a5f608e1 soc/intel/apollolake: Add functions to calculate GPIO address
Provide iosf and GPIO functions for GPIO address
calculation.

BUG=chrome-os-partner:55877

Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16349
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-09 23:51:01 +02:00
Werner Zeh
b5026bf9e0 fsp_broadwell_de: Adjust printed address in SPI debug messages
For an unknown reason the printed address in the SPI debug messages is
modified before it is printed by subtracting the constant 0xf020 from
the passed in address.
What I suppose this debug code should do is to print the used register
address within the SPI controller while any parts of this address that
belongs to the SPI base address should be omitted. To fix that remove
the subtraction of 0xf020 and adjust the address mask to 0x3ff so that
only the offset to the registers inside the SPI controller will be
visible in the debug messages.
In addition switch to uint8_t and friends over u8 to sync up with used
types in this file.

Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16500
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-08 06:12:13 +02:00
Venkateswarlu Vinjamuri
88df48c555 soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cb
BUG=chrome-os-partner:56034

Change-Id: Id88d262b32dea468536575117fc34d52076a3096
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07 18:54:14 +02:00
Werner Zeh
bd366ab485 fsp_baytrail: Refactor code for SPI debug messages
Use the config switch CONFIG_DEBUG_SPI_FLASH on compiler level rather
then on preprocessor level to ensure that the code is compiled even if
the switch is not selected. In addition the following two changes are
introduced:

1. Prepend the debug messages with 'SPI:' to make the output more
   meaningful.
2. Change the address mask from 0xffff to 0x3ff and remove the subtraction
   of the constant value 0xf020 in order to print only the register
   offset within the SPI controller and avoid the visibility of any
   fragments from SPI base address.
3. Switch to uint8_t and friends instead of u8 to sync up with other
   code in the same file.

Change-Id: Iaf46f29a775039007a402fe862839df06a4cbfaa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06 21:17:59 +02:00
Shamile Khan
93c5470434 google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 lines
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.

BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
     on the screen. Also the interrupt count for i8042 increments
     immediately in /proc/interrupts.

Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-09-06 20:22:27 +02:00
Iru Cai
2128d625ca Makefile.inc: Use $(MAINBOARDDIR)
Commit 93ef3ff makes the following only print the part number when
the ROM is built. In Makefile.inc, $(MAINBOARDDIR) is the variable
that has the quotes stripped off from $(CONFIG_MAINBOARD_DIR), so
use it instead of $(MAINBOARD_DIR).

build_complete:: coreboot
        printf "\nBuilt %s (%s)\n" $(MAINBOARD_DIR) \
                $(CONFIG_MAINBOARD_PART_NUMBER)

Change-Id: I729a583182937db7a926eb75aa28dfb53360046c
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/16410
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04 05:33:25 +02:00
Duncan Laurie
d1cab66502 lpss_i2c: Increase default timeout to 4ms
Increase the default timeout in the LPSS I2C driver to 4ms
from 2ms.  During testing with some slower devices I found
that the existing timeout could be too short leading to
transaction failures.

Change-Id: Ied86c7a0aa26d55b31f447c5938803c194d0045e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16392
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-04 05:31:37 +02:00
Brandon Breitenstein
eb2e688a8e apollolake: relocate fsp header files to vendorcode
FSP header files should be located in vendorcode, not soc directory.
This patch includes changes any references to the old location to
the new location.

Change-Id: I44270392617418ec1b9dec15ee187863f2503341
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02 18:12:57 +02:00
Brandon Breitenstein
c31ba0ef52 drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.

BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully

Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02 18:12:24 +02:00
Martin Roth
26d484a237 Fix newlines at the end of files
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.

Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-02 18:04:48 +02:00
Furquan Shaikh
477bc97ba0 soc/intel/apollolake: Use consistent convention for community names
Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO
community names, follow one single convention. This allows for re-using
macros easily.

Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16353
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-01 07:30:56 +02:00
Elyes HAOUAS
4a83f1cf24 src/soc: Add required space before opening parenthesis '('
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31 20:09:42 +02:00
Rizwan Qureshi
1222a73205 skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.

The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.

Add the below files,
car_stage.S:
	Add romstage entry point (car_stage_entry).
	This calls into romstage_fsp20.c and aslo handles
	the car teardown.
romstage_fsp20.c:
	Call fsp_memory_init() and also has the callback
	for filling memory init parameters.

Also add monotonic_timer.c to verstage.

With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.

TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0

Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-31 20:02:07 +02:00
Andrey Petrov
c42a9ac4ab soc/intel/apollolake: Disable Periodic Retraining per-SKU
Certain LPDDR4 models have some HW issues that can be worked around
by turning off Periodic Retraining feature in the memory controller.
Add option to disable PR per SKU.

BUG=chrome-os-partner:55466
TEST=run RMT test, pass

Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-31 19:23:50 +02:00
Brandon Breitenstein
07215aaf71 soc/intel/apollolake: Update FSP UPD header files for SIC 1.1.3
Update FSP Header files to provide UPD for periodic training
disable. This is for the SIC 1.1.3/150_11 FSP release.

BUG=chrome-os-partner:54100
BRANCH=none
TEST=built coreboot image with new headers for reef

Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16352
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-31 19:23:15 +02:00
John Zhao
3156934bf8 soc/intel/apollolake: Gather microcode revision
Expose get_microcode_info in cpu initialization. Microcode
revision is retrieved and stored into log file at verstage.

BUG=chrome-os-partner:56544
BRANCH=None
TEST=Built coreboot image and validate log file

Change-Id: I1e792e70f1318df64b4b85a319700013f3757952
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16311
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31 17:02:51 +02:00
Werner Zeh
62d1313925 fsp_broadwell_de: Refactor code for SPI debug messages
Currently boards based on fsp_broadwell_de fail to compile if the config
switch CONFIG_DEBUG_SPI_FLASH is selected. The error is caused by the
usage of const for the address pointer in the functions writeb_, writew_
and writel_. The reason why it stayed hidden for so long is the fact that
the switch is used with the preprocessor and nobody really selects it
until there is a bug one want to find in this area.

This patch fixes the parameter type definition which solves the error.
In addition the config switch is not used on preprocessor level anymore
but instead on compiler level. This ensures that at least the code
syntax is checked on build time even if the config option is not
selected. Also prefix the messages with "SPI:" to make them more
meaningful in a full log.

Change-Id: I3514b0d4c08bf5a4740f2632641e09af1b3aaf3a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16347
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-30 17:55:42 +02:00
Barnali Sarkar
9912310181 soc/intel/skylake: Include Kabylake specific IGD Device IDs
Add Kabylake specific Graphics IDs in report_platform.c and igd.c.

BUG=none
BRANCH=none
TEST=Built and boot kunimitsu

Change-Id: I3b810d0ff51eb51d396b783e282779aefb2dcb8c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-30 16:55:04 +02:00
Aaron Durbin
41a3fa66a0 soc/intel/apollolake: add option for SLP_S3_L assertion width
In order to provide time for the S0 rails to discharge one needs
to be able to set the SLP_S3_L assertion width. The hardware default
is 60 microcseconds which is not slow enough on most boards. Therefore
provide a devicetree option for the mainboard to set accordingly
for its needs. An unset value in devicetree results in a conservative
2 second SLP_S3_L duration.

BUG=chrome-os-partner:56581

Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16326
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-30 03:15:32 +02:00
Andrey Petrov
3f4aece4e0 soc/intel/apollolake: Add CQOS CAR implementation
Add new option to set up Cache-As-RAM by using CQOS, Cache Quality of
Service. CQOS allows setting ways of cache in no-fill mode, while keeping
other ways in regular evicting mode. This effectively allows using CAR
and cache simultaneously.

BUG=chrome-os-partner:51959
TEST=switch from NEM to CQOS and back, boot

Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28 18:38:48 +02:00
Andrey Petrov
7f72c9b30e soc/intel/apollolake: Update stage link addresses for 768 KiB cache
Update link addresses for romstage and verstage. Also update FSP-M relocation
address.

BUG=chrome-os-partner:51959

Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15454
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28 18:35:03 +02:00
Andrey Petrov
0dde2917a5 soc/intel/apollolake: Handle CAR sizes other than 1 MiB
Since whole L2 (1MiB) is not used, it is possible to shrink CAR size
to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to
set it up. This is a part of CQOS enabling.

BUG=chrome-os-partner:51959

Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15453
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-28 18:33:11 +02:00
Elyes HAOUAS
03b040b95f src/soc: Remove unnecessary whitespace before "\n" and "\t"
Change-Id: I89bc8b26f2dba4770aea14b8bbc7e657355e8c59
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16325
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28 18:25:14 +02:00
Brandon Breitenstein
3b0e761dd5 soc/intel/apollolake: Enable ELOG
Add in the base for ELOG for APL. Some PM events still need to be
added but the basic events are logged here. This enables the
basic functionality of ELOG for Apollolake.

BUG=chrome-os-partner:55473
BRANCH=none
TEST=Verified image boots on Amenia

Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15937
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-25 23:51:27 +02:00
Shaunak Saha
de9fed4c2a intel/common: Clear wake status bits before sleep
Call power management utility function clear_wake_sts
from southbridge_smi_sleep before going to sleep.
This is needed to clear the wake status bits in ACPI
registers GPE0.

BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
     powerd_dbus_suspend command issued from built-in
     keyboard.

Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-25 23:43:58 +02:00
Shaunak Saha
d6bb5495f9 intel/apollolake: Add power management utility function
This patch adds a power management utility function to
clear wake status bits in ACPI GPE0 registers. We need
to call this function before going to sleep from
common smi handler function.

BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
     powerd_dbus_suspend command issued from built-in
     keyboard.

Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16298
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-25 23:43:50 +02:00
Furquan Shaikh
70385968ce soc/intel/skylake: Bump up bootblock size to 48K
When UART_DEBUG is enabled bootblock size grows more than the current
32K. Bump this up to 48K.

Change-Id: I580137dfdc9b4ad226c866f2b23b159bd820c62c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16317
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-24 20:02:14 +02:00
Aaron Durbin
a6914d2343 soc/intel/skylake: align chromium Chrome OS config
The chromium tree is currently using a different config for
Chrome OS than what is being built in coreboot.org. Align those
settings to reflect how skylake Chrome OS boards are actually
shipped to provide proper parity between coreboot.org and chromium.

Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16313
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-24 20:02:04 +02:00
Vaibhav Shankar
93f34e1a74 soc/intel/apollolake: Add ASL methods for eMMC
Implement PS0 and PS3 methods to support eMMC power gate
in S0ix suspend and resume.

BUG=chrome-os-partner:53876
TEST=Suspend and Resume using 'echo freeze > /sys/power/state'.
System should resume from S0ix.

Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16233
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-24 06:44:48 +02:00
Saurabh Satija
6f23374590 soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmic
Update the config variable that gets set to use DMIC 2 channel blob for
intel/apollolake platforms. This flag is set in mainboard.

Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/16251
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-23 15:42:36 +02:00
Furquan Shaikh
97e0a65081 intel/skylake: Do not halt in poweroff if in SMM
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered
preventing the system from entering sleep state. Fix this by calling
halt only if ENV_SMM is not true.

BUG=chrome-os-partner:56395

Change-Id: I3addc1ea065346fbc5dbec9d1ad49bbd0ae05696
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16259
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20 10:48:47 +02:00
Furquan Shaikh
3828e55a8c intel/apollolake: Do not halt in poweroff if in SMM
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered
preventing the system from entering sleep state. Fix this by calling
halt only if ENV_SMM is not true.

BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified lidclose behavior on reef.

Change-Id: If116c8f4e867543abdc2ff235457c167b5073767
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20 10:48:27 +02:00
Furquan Shaikh
200f11eb87 intel/apollolake: Fix typo in gpi_status_get
sts_index is calculated incorrectly because of wrong use of
parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef
and lidclose event was missed.

BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified that lidclose event is seen and handled by SMM in
coreboot on reef.

Change-Id: I56be4aaf30e2d6712fc597b941206ca59ffaa915
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16256
Tested-by: build bot (Jenkins)
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20 10:48:19 +02:00
Ravi Sarawadi
15f6f3aa58 soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
Read FSP produced memory HOB and use it to populate DIMM info.
DIMM 'part_num' info is stored statically based on memory/SKU id.

BUG=chrome-os-partner:55505
TEST='dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-20 08:56:32 +02:00
Aaron Durbin
e4cc8cd00b soc/intel/skylake: use SPI flash boot_device_rw() for ealy stages
If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.

BUG=chrome-os-partner:56151

Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16202
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19 18:15:50 +02:00
Aaron Durbin
7b2c781dbd soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stages
If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.

BUG=chrome-os-partner:56151

Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16201
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19 18:15:24 +02:00
Aaron Durbin
67d487e687 soc/intel/skylake: make SPI support early stages
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable. Additionally,
include the SPI support code as well as its dependencies in
all the stages.

BUG=chrome-os-partner:56151

Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16196
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-08-19 03:09:49 +02:00
Aaron Durbin
1ad9f946b6 soc/intel/apollolake: make SPI support early stages
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable.

BUG=chrome-os-partner:56151

Change-Id: If4f5484e27d68b2dd1b17a281cf0b760086850a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16195
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19 03:09:01 +02:00
Aaron Durbin
e8e118dd32 Kconfig: introduce writable boot device notion
Indicate to the build system that a platform provides support
for a writable boot device. The following will provide the
necessary support:

COMMON_CBFS_SPI_WRAPPER users
soc/intel/apollolake
soc/intel/baytrail
soc/intel/braswell
soc/intel/broadwell
soc/intel/skylake

The SPI_FLASH option is auto-selected if the platform provides
write supoprt for the boot device and SPI flash is the boot
device.

Other platforms may provide similar support, but they do that
in a device specific manner such as selecting SPI_FLASH
explicitly. This provides clearance against build failures
where chipsets don't provide SPI API implementations even
though the platform may use a SPI flash to boot.

BUG=chrome-os-partner:56151

Change-Id: If78160f231c8312a313f9b9753607d044345d274
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16211
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19 03:05:18 +02:00
Aaron Durbin
16c173fdf5 Kconfig: separate memory mapped boot device from SPI
Make the indication of the boot device being memory mapped
separate from SPI. However, retain the same defaults that
previously existed.

BUG=chrome-os-partner:56151

Change-Id: I06f138078c47a1e4b4b3edbdbf662f171e11c9d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16228
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19 03:04:54 +02:00
Furquan Shaikh
cb6096d71d intel/apollolake: Skip ITSS configuration in SMM
In SMM, gpio configuration could be done to avoid leakage. ITSS
configuration is not required when entering sleep. Thus, bail out early
from itss configuration if in SMM.

BUG=chrome-os-partner:56281

Change-Id: I4d8be0513aa202f001f980bb91986b50b8ed2a5b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16242
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-19 03:03:54 +02:00
Rizwan Qureshi
3ad63565a5 soc/intel/skylake: Correct Cache as ram size
DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to
set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000
is used to calculate the _car_region_end in car.ld. If the FSP CAR
requirement is greater than or even close to DCACHE_RAM_SIZE then,
the CAR region for FSP will be determined to be below the overall
CAR region boundary i.e, out of CAR memory range.

This is working with FSP 1.1 because we provide the FspCarSize
and FspCarBase explicitly in a UPD. Hence, FSP is still able to
use the upper region of CAR memory for its purpose.
However, it will be a problem in case of FSP2.0 where FSP usable CAR
is calculated using _car_region_end.

So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set
DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB)

Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16236
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-08-18 18:13:55 +02:00
Naresh G Solanki
ecd9a94213 soc/intel/skylake: Move bootblock specific code from skylake/romstage
There is a lot of code that is being referred to in bootblock but
resides under skylake/romstage folder. Hence move this code
into skylake/bootblock, and update the relevant header files
and Makefiles.

TEST=Build and Boot kunimitsu.

Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-18 18:13:42 +02:00
Rizwan Qureshi
cf73c1317d skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
Prepare Skylake for FSP2.0 support.

We do not use FSP-T in FSP2.0 driver, hence guard the
FspTempRamInit call under a switch.

In addition to the current early PCH configuration
program few more register, so all in all we do the following,
* Program and enable ACPI Base.
* Program and enable PWRM Base.
* Program TCO Base.
* Program Interrupt configuration registers.
* Program LPC IO decode range.
* Program SMBUS Base address and enable it.
* Enable upper 128 bytes of CMOS.
And split the above programming into into smaller functions.

Also, as part of bootblock_pch_early_init we enable decoding
for HPET range. This is needed for FspMemoryInit to store and
retrieve a global data pointer.

And also move P2SB related definitions to a new header file.

TEST=Build and boot Kunimitsu

Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-18 06:26:40 +02:00
Furquan Shaikh
e7de6fb162 intel/apollolake: Fix check for return value of pmc_gpe_route_to_gpio
pmc_gpe_route_to_gpio returns -1 on error. However, the value was being
stored in unsigned int and compared against -1. Fix this by using local
variable ret.

Change-Id: I5ec824949d4ee0fbdbb2ffdc9fc9d4762455b27b
Reported-by: Coverity ID 1357443, 1357442, 1357441
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16218
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-18 01:07:36 +02:00
Rizwan Qureshi
0bb62294ac soc/intel/skylake: restore MCHBAR and DMIBAR programming
Program MCHBAR, DMIBAR, EPBAR, EDRAMBAR and GDXCBAR.
Also program the PAM registers. The system agent was being
programmed in romstage during pre-console initialization, after
moving to C_ENVIRONMENT bootblock this was missing, restoring
the same.

TEST=Build and Boot Kunimitsu

Change-Id: Iaf310cfb83e58eb8d5affb481dfc343f5d45961b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16224
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-17 22:42:46 +02:00
Aaron Durbin
c3b024e99b Revert "Kconfig: separate memory mapped boot device from SPI"
This reverts commit a83bbf5854.
This was submitted out of order.

Change-Id: Ic5a28faf94c1f1901a72e46343722eb4224c5086
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16226
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-15 21:24:02 +02:00
Aaron Durbin
e56191e8ec soc/intel/skylake: don't include all SPI flash drivers
The SPI host controller for the SPI boot device doesn't allow
normal probing because it uses the hardware sequencer all
the time. Therefore, it's pointless to include unnecessary
SPI flash drivers.

BUG=chrome-os-partner:56151

Change-Id: Ifcc6492b4bccf7d01b121d908976c9087d12deb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16189
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-15 21:02:33 +02:00
Aaron Durbin
bdb6cc97eb soc/intel/apollolake: don't include all SPI flash drivers
The SPI host controller for the SPI boot device doesn't allow
normal probing because it uses the hardware sequencer all
the time. Therefore, it's pointless to include unnecessary
SPI flash drivers.

BUG=chrome-os-partner:56151

Change-Id: I04551fdb0b207c7ec2f1f171cff62ed7334a5ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16188
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-15 21:02:18 +02:00
Aaron Durbin
a83bbf5854 Kconfig: separate memory mapped boot device from SPI
Make the indication of the boot device being memory mapped
separate from SPI. However, retain the same defaults that
previously existed.

BUG=chrome-os-partner:56151

Change-Id: Ibdd7c8754f9bf560a878136b1f55238e2c2549d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16193
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-15 21:00:25 +02:00
Furquan Shaikh
5ff952259a intel/quark: Fix assert check
Having an assignment in assert does not make sense. This seems like it
was intended to check if chip is always same as segments->chip.

Change-Id: I297d9e76a0404a1f510d43f8b9c39e96b557689f
Reported-by: Coverity ID 1357439
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-08-15 19:49:43 +02:00
Barnali Sarkar
49eca13353 soc/intel/skylake: Change name pmc_tco_regs to smbus_tco_regs
The function name "pmc_tco_regs" is changed to "smbus_tco_regs"
since TCO offsets belongs to SMBUS PCI device.

BUG=none
BRANCH=none
TEST=Built and booted kunimitsu

Change-Id: I4ac26df81a8221329f2b45053dd5243cd02f8ad7
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16155
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-14 19:20:55 +02:00
Ravi Sarawadi
3a21d0f341 soc/apollolake: enable access to RTC NVRAM
FSP unconditionally locks parts of the NVRAM in the RTC.
This change will enable coreboot to update the locking policy
and be able to unlock the region

BUG=chrome-os-partner:55944
TEST=Check 'crossystem dev_boot_usb=1'

Change-Id: I70fd2bafa6ff9eb9cdf284b9780e4b90dee0f4ce
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16144
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-11 22:43:53 +02:00
Subrata Banik
c1645faeff soc/intel/common: Add support for serial console based ACPI debug
This patch enables serial debug functionality for ASL code based on
UART type(legacy/LPSS).

From Skylake onwards all Intel platform uses LPSS based UART for serial
console hence provide option to redirect ASL log over LPSS UART.

Example:
Name (OBJ, 0x12)
APRT (OBJ)
APRT ("CORE BOOT")

Output:
0x12
CORE BOOT

BUG=none
BRANCH=none
TEST=Built and boot kunimitsu to ensure to be able to get ASL console log.

Change-Id: I18c65654b8eb1ac27af1f283d413376fd79d47db
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/16070
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-11 16:03:29 +02:00
Kevin Paul Herbert
d7127b09ae fsp_Broadwell_DE: Do not set IRQ3 and IRQ4 to level
When booting Linux as a coreboot payload, serial access does not work
properly. This is because the setup code erroneously sets IRQ3 and
IRQ4 to level. The UART on Broadwell is 8250/16550 compatible, thus
ISA and edge-triggered.

This change is not necessary on the non-FSP version of Broadwell support.
The non-FSP version does not set these IRQ overrides.

Fix verified booting Linux 4.6.0-rc2 on Intel Camelback Mountain CRB,
using Intel FSP 1.0.

Change-Id: I17b466676e7f4891c3e75ce6208e1580c9eaf742
Signed-off-by: Kevin Paul Herbert <kevin@trippers.org>
Reviewed-on: https://review.coreboot.org/16065
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-11 15:16:40 +02:00
Lee Leahy
5e07a7e474 soc/intel/quark: Switch to using serial routines for FSP
Switch from passing FSP the serial port address to passing FSP the
serial port output routine.  This enables coreboot to use any UART in
the system and also log the FSP output.

TEST=Build and run on Galileo Gen2

Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16105
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10 22:31:52 +02:00
Martin Roth
93ef3ffdf0 Makefiles: Use $(MAINBOARD_DIR) instead of $(CONFIG_MAINBOARD_DIR)
The variable MAINBOARD_DIR already has the quotes stripped off.

Change-Id: Ib434ce92bdbc49180fb3f713b26d65ba4cf8c441
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/16117
Tested-by: build bot (Jenkins)
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-10 21:12:03 +02:00
Shaunak Saha
09115a92f6 soc/apollolake: add GPIO SMI support
GPIOs which trigger SMIs set the GPIO_SMI_STS status bits in SMI_STS
register. This patch also sets the SMI_EN bit in enable register for
each community based on GPIOROUTSMI bit in gpio pad. When SMI on a
gpio happens status needs to be gathered on gpio number which is done
by reading the GPI_SMI_STS and GPI_SMI_EN registers.

BUG=chrome-os-partner:54977
TEST=When system is in firmware mode executing the command
     lidclose from ec console shuts down the system.

Change-Id: Id89a526106d1989c2bd3416ab81913e6cf743d17
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15833
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-10 21:10:59 +02:00
Aaron Durbin
2d45c28675 soc/intel/common: fix gsmi handler
The gsmi_exec() expects the parameter to be a pointer
to the 32-bit register storage of the SMI save state.
The previous code was passing a pointer with the value
obtained from the saved-state -- not a pointer to the
storage of the register value. This bug causes gsmi
to not log events because it's interrogating the
parameter buffer itself as if it were a pointer.

BUG=chrome-os-partner:55932

Change-Id: I37981424f1414edad1456b31cad1b99020d57db6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16087
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08 18:38:57 +02:00
Aaron Durbin
16246ea9ce chromeos chipsets: select RTC usage
Since RTC is now a Kconfig ensure RTC is selected on the
x86 chipsets which are in Chrome OS devices. This allows
the eventlog to have proper timestamps instead of all
zeros.

BUG=chrome-os-partner:55993

Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08 18:37:37 +02:00
Barnali Sarkar
a7b97510ae soc/intel/skylake: Clean up SoC ASL code.
List of changes done here in this patch

1. Remove CARD definition from EMMC and SD Card Controller in scs.asl
since _RMV method does not get evaluated while setting up removable
attribute in sysfs in kernel.
"cat /sys/block/mmcblk1/removable" this command always returns 0.

This CARD Device includes _ADR which follows SDIO Bus format. But,
SD/EMMC sits on PCI Bus.
Hence this CARD Device specific _ADR code is also not needed.

2. Remove Base Address for ACPI debug output memory buffer in
systemagent.asl as it is not getting used throughout the code.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu

Change-Id: I29effaffdafcc21e26445ec3c54aedecdbc50274
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16068
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08 18:31:38 +02:00
Barnali Sarkar
8f2f22d258 skylake/devicetree: Add PIRQ Routing programming
Program PIRQ Routing with correct values, as done by FSP, and also in
'soc/intel/skylake/romstage/pch.c' file. If not done, these values get
overridden by "0" during PxRC -> PIRQ programming in ramstage, in
'soc/intel/skylake/lpc.c' file pch_pirq_init()function.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu

Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16044
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08 18:24:04 +02:00
Barnali Sarkar
0dddcd76d7 soc/intel/skylake: Cleanup patch for Skylake SoC
Here is the list of items of code cleanup
1. Define TCO registers in smbus.h and not in pmc.h (as per EDS).
2. Include smbus.h wherever these TCO register defines were used.
3. Remove duplication of define in gpio_defs.h.
4. Remove unnecessary console.h include from memmap.h as no prints done.
5. Remove unnecessary comment from pch.c.

BUG=none
BRANCH=none
TEST=Built and boot kunimitsu.

Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16027
Tested-by: build bot (Jenkins)
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08 18:18:57 +02:00
Rizwan Qureshi
5d41949782 soc/intel/skylake: Add Kabylake device Ids
Adding kabylake device ids for chip inits.
Skylake and Kabylak do not differ much, the intention
is to support both SoCs in the same code base.

Change-Id: I9ff4c6ca08fe681798001ce81cca2c085ce32325
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16049
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-06 04:36:46 +02:00
Lee Leahy
d924fac759 soc/intel/quark: Add missing breaks
Add missing breaks in reg_access.c.

TEST=Build and run on Galileo Gen2

Found-by: Converity Scan #1361261

Change-Id: I8be57f0758e5918a605e20ab9002747e0cc958e0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16069
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-08-05 15:36:18 +02:00
Lee Leahy
3de7d4a9b2 soc/intel/quark: Add bootblock_c_entry
Add the bootblock_c_entry routine to make it more explicit where the
code transitions from assembler to C.

TEST=Build and run on Galileo Gen2

Change-Id: Ib5f580c30b58d3c82fedddf63c368e617d401515
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 01:55:41 +02:00
Lee Leahy
f74ce24de1 soc/intel/quark: Clean up debug output levels
Change the debug output levels for quark:
*  Remove excess debug output
*  Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c

TEST=Build and run on Galileo Gen2

Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05 01:55:17 +02:00
Lee Leahy
d52636113a soc/intel/quark: Disable FSP serial output
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW).  Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.

TEST=Build and run on Galileo Gen2.

Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-05 01:54:55 +02:00
Lee Leahy
f26fc0f28b soc/intel/quark: Add FSP 2.0 romstage support
Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build.  Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.

TEST=Build and run on Galileo Gen2

Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 01:53:49 +02:00
Lee Leahy
102f625360 soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.

TEST=Build and run bootblock on Galileo Gen2

Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05 01:50:45 +02:00
Shaunak Saha
60b4618a84 soc/apollolake: Return correct wake status in _SWS
Wake status is calculated from the four pairs of gpe0 in
cbmem CBMEM_ID_POWER_STATE which is filled very early
in romstage and depends on the routing information in
PMC GPE_CFG register. Coreboot sets the proper value
of routing based on devicetree from pmc_init. But when
system goes to S3 on waking up PMC is writing default
values again in GPE_CFG which results in returning
wrong wake status in _SWS. This patch corrects that
behaviour by correcting the gpe0 pairs in cbmem after
PMC sets the routing table in resume path.

BUG=chrome-os-partner:54876
TEST=On resume through powerbtn, lidopen, keyboard press,  etc.
     we are getting proper wake status.

Change-Id: I5942d5c20d8c6aef73468dc611190bb7c49c7c7a
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16040
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
2016-08-04 16:14:14 +02:00
Jagadish Krishnamoorthy
b6739d1b56 soc/intel/apollolake: Configure gpio ownership
For the gpio based irq to work, the ownership of the pad
should be changed to GPIO_DRIVER.
Provide an option in the gpio defs to configure the PAD onwership.

BUG=chrome-os-partner:54371
TEST=none

Change-Id: I26d242d25d2034049340adf526045308fcdebbc0
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-04 16:13:34 +02:00
Barnali Sarkar
d03596f4ca soc/intel/skylake: Correct address of I2C5 Device
This corrects the address of the I2C5 Device. The I2C
Controller #5 is on PCI Bus 0: Device 25: Function 1. The ACPI
Address Encoding Logic is - High word = Device #.
                            Low word = Function #.
So, I2C5 (_ADR) = 0x0019 0001.

BUG=none
BRANCH=none
TEST=Build and boot kunimitsu

Change-Id: I4719a843260ef58cc2307e909e9ccbffea519177
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16048
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-04 16:12:13 +02:00
Lee Leahy
5fafc6ad54 soc/intel/quark: Support access to CPU CR registers
Add support to access CR0 and CR4.

TEST=Build and run on Galileo Gen2.

Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 18:03:46 +02:00
Lee Leahy
38e0cc0aa4 soc/intel/quark: Add header files for FSP 2.0
Add the FSP 2.0 header files for Quark.  These files were run through
the drivers/intel/fsp2_0/header_util to convert the data types so that
they are compatible with the coreboot build system.

TEST=Build and run on Galileo Gen2.

Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15863
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:48:53 +02:00
Lee Leahy
01728bb2ed soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.

TEST=Build and run on Galileo Gen2

Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 17:47:53 +02:00
Lee Leahy
3d0e3cf4b1 soc/intel/quark: Initialize MTRRs in bootblock
Initialize the MTRRs for use by bootblock and romstage.
Display the MTRRs.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib1d422c738820163f54771c65034ae77301237ec
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15861
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:46:36 +02:00
Lee Leahy
14d09264a2 soc/intel/quark: Remove use of EDK-II macros and data types
Include assert.h to use coreboot's ASSERT macro.
Replace the use of UINT32 data type with uint32_t.
Replace the use of UINT8 data type with uint8_t.

TEST=Build and run on Galileo Gen2

Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15858
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03 17:31:39 +02:00
Werner Zeh
1cfb555e71 fsp_broadwell_de: Add DMAR table to ACPI
Create DMAR table for Broadwell-DE SoC.

TEST=Booted MC BDX1 into lubuntu15, dumped ACPI tables with acpidump and
     disassembled DMAR table using iasl. The table contents are as
     expected and the kernel loads DMAR table without errors.

Change-Id: I7933ba4f5f0539a50f2ab9a5571e502c84873ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15913
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-03 12:44:25 +02:00
Lee Leahy
d87d8eaca1 soc/intel/quark: Make ramstage relocatable
Relocate ramstage into CBMEM.

TEST=Build and run on Galileo Gen2

Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15994
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-03 06:21:22 +02:00
Lee Leahy
806fa2463f drivers/intel/fsp2_0: Handle FspNotify calls
Other SOC platforms need to handle the FspNotify calls in the same way
as Apollo Lake.  Migrate the FspNotify calls into the FSP 2.0 driver.
Provide a platform callback to handle anything else that needs to be
done after the FspNotify call.

Display the MTRRs before the first call to fsp_notify.

TEST=Build and run on Galileo Gen2

Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:17:31 +02:00
Lee Leahy
9671faa497 drivers/intel/fsp2_0: FSP driver handles all FSP errors
Move all FSP error handling into the FSP 2.0 driver.  This removes the
need to implement error handling within the SOC code.

TEST=Build and run on Galileo Gen2

Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-03 06:17:02 +02:00
Kane Chen
5976143475 google/reef: Add pull up 20K for LPC SERIRQ
per hw team's check and info from EDS, this pin needs to be pu 20K.
Otherwise SoC may not notice interrupt request from
EC over LPC because SERIRQ line is floating.

BUG=chrome-os-partner:55586
BRANCH=none
TEST=boot ok and Quanta factory verified the keyboard issue is gone

Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a
Reviewed-on: https://review.coreboot.org/15951
Tested-by: build bot (Jenkins)
Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-02 18:41:08 +02:00
Shankar, Vaibhav
67d169721a soc/intel/apollolake: Add iosstate macros for GPIO
IO Standby State (IOSSTATE): The I/O Standby State defines
which state the pad should be parked in when the I/O is in a
standby state. Iosstate set to 15 means IO-Standby is ignored
for this pin (same as functional mode), So that pin keeps on
functioning in S3/S0iX.

Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/15776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-02 18:39:38 +02:00
Furquan Shaikh
8d66bee7be intel/apollolake: Enable upper CMOS bank in bootblock
Upper CMOS bank is used to store the boot count. It is important to
enable it as soon as possible in bootblock.

BUG=chrome-os-partner:55473

Change-Id: I7c4f49c337c2e24a93c1e71466e2f66db04be562
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15998
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-02 18:38:04 +02:00
Furquan Shaikh
b168db78d6 intel/skylake: Fix UART build options
1. skylake does not support UART over I/O. So, NO_UART_ON_SUPERIO needs
to be selected by default.
2. Move BOOTBLOCK_CONSOLE under UART_DEBUG.
3. Include bootblock/uart.c only if UART_DEBUG is selected.

Change-Id: I4e996bea2a25b3b1dfb9625d97985a9d3473561b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16025
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-08-02 05:58:49 +02:00
Prabal Saha
0f2025da0f intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano
Without this patch, eDP output is non-functional pre-graphics driver
regardless of payload (SeaBIOS, Tianocore) or video init method
(VBIOS, GOP driver) and once the standard Windows Intel HD graphics
driver is loaded.

Test: Boot Windows on peppy and auron_paine, install Intel HD
Graphics driver, observe functional eDP output with full video
acceleration.

Debugging method: adjust location of call to run VBIOS within
coreboot, observed that eDP output functional if the VBIOS is run
before the power optimizer lines, broken if run afterwards.

Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514
Signed-off-by: Prabal Saha <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/15261
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-02 00:47:26 +02:00
Lee Leahy
6e8233a60b soc/intel/quark: Enable use of hard reset
Select HAVE_HARD_RESET in the KCONFIG file to enable use of the
hard_reset routine.

TEST=Build and run on Galileo Gen2

Change-Id: Ib11a80b64cf1c55aec24f2576d197da9017b9751
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01 22:14:48 +02:00
Lee Leahy
aac31ca221 soc/intel/common: Fix build error in reset.c
Fix build error caused by macro substitution in the function definition
when the Kconfig value HAVE_HARD_RESET is not selected.

src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0
 void hard_reset(void)
                     ^
src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token
 {
 ^
make: *** [build/bootblock/soc/intel/common/reset.o] Error 1

TEST=Build and run on Galileo Gen2

Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15988
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01 22:14:08 +02:00
Martin Roth
0cd338e6e4 Remove non-ascii & unprintable characters
These non-ascii & unprintable characters aren't needed.

Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01 21:44:45 +02:00
Martin Roth
bb9722bd77 Add newlines at the end of all coreboot files
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01 21:43:56 +02:00
Lee Leahy
4c18de2de9 soc/intel/common: Enable MTRR display during bootblock & postcar
Update Makefile.inc to allow MTRR display during bootblock and postcar.

TEST=Build and run on Galileo Gen2

Change-Id: If12896df46b9edfc9fff3fab3a12d2dae23517a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15990
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01 06:16:05 +02:00
Lee Leahy
0c1843aeb9 soc/intel/quark: Fix car_stage_entry routine name.
Change routine name from car_state_entry to car_stage_entry.

TEST=Build and run on Galileo Gen2

Change-Id: Ifd11db3fa711f2fe52ade1c6cde94f9be1f3a652
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15857
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01 06:15:47 +02:00
Elyes HAOUAS
038e7247dc src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 19:27:53 +02:00
Patrick Georgi
e8f2ef51e1 intel/broadwell: fix typo
(pci_read_config32(...) > 14) & 0x3 looks rather unusual (and prevents
"case 3" below from ever happening)

Change-Id: Id90655c39ff53da9569441278bbf73497d643480
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1293139
Reviewed-on: https://review.coreboot.org/15965
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 19:01:56 +02:00
Patrick Georgi
90ed31beac intel/skylake: Enable signalling of error condition
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.

Change-Id: I7d1cdb6af4140f7dc322141c0c018d8418627434
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/15964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 19:00:00 +02:00
Martin Roth
4c72d3612b Remove extra newlines from the end of all coreboot files.
This removes the newlines from all files found by the new
int-015-final-newlines script.

Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:19:33 +02:00
Aaron Durbin
b0f81518b5 chromeos mainboards: remove chromeos.asl
Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30 01:36:32 +02:00
Furquan Shaikh
6e37e90193 soc/intel/apollolake: Include gpe.h in chip.h
This is required for using GPE_* macros in devicetree.cb.

BUG=chrome-os-partner:55670

Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15946
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30 00:53:27 +02:00
Zhuo-hao.Lee
ce37e47f46 skylake: fix VSDIO is at 0.8V when SDCard is not inserted
1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card
   is removed. When SD-card is disconnected, the pull-down is
   disabled.
2. Provide path for weak leakage from buffers of SD_CMD/D* signal
   to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V.

BUG=chrome-os-partner:54421
TEST=no power leakage when SDCard isn't inserted on skylake platform

Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8
Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://review.coreboot.org/15910
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-29 00:12:53 +02:00
Abhay Kumar
ec2947fb07 soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume
Do not pass VBT table to fsp in normal mode and S3 resume so that
PEIM GFX will not get initialized.

Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/14575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-29 00:09:05 +02:00
Brandon Breitenstein
df12d1923f soc/intel/apollolake: Update FSP Header files for version 146_30
Add new UPDs for Fspm and Fsps. Update headers to make new UPDs
available for use. New UPDs enable various memory and trace funtionality
options as well as support for zero sized IBB region.

BUG=chrome-os-partner:55513
BRANCH=none
TEST=built and tested with no regressions

Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15815
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28 21:21:06 +02:00
Shaunak Saha
cd9e1e423f intel/apollolake: Update gnvs for dptf
This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
       under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a
       thermal zone of type TCPU exists there.

Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 20:13:34 +02:00
Shaunak Saha
5dd2b18540 intel/apollolake: Add soc specific DPTF values
This patch adds apollolake soc specific change. DPTF
ASL files are now in src/soc/intel/common so that
they can be reused but different soc can have different values
e.g., for skylake cpu soc thermal reporting device is at
Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
Function 1. This patch adds a dptf asl file in soc directory where we
can define all values which can change across soc's and can be
included in mainboard dptf asl.

BUG=chrome-os-partner:53096
TEST=In Amenia and Reef board verify that the thermal zones are
       enumerated under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a thermal
       zone of type TCPU exists there.

Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15619
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 20:10:15 +02:00
Shaunak Saha
44887c3e36 intel/common: Add ASL code for DPTF
This patch adds the common ASL code for Intel
platforms. This is the basic ASL needed to add support
for DPTF controlled devices. We are moving
these commmon ASL files to src/soc/intel/common/acpi as
these are same codes used in all Intel platforms and
hence no need to duplicate.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
	under /sys/class/thermal. Navigate to
	/sys/class/thermal, and verify that a thermal
	zone of type TCPU exists there.

Change-Id: I01078382a9008263c6ad99f6bf07558885af6a63
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15093
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 20:09:58 +02:00
Martin Roth
2098778726 intel/common/opregion.c: only write 16 bytes to 16 byte field
Including the terminating null, 17 characters were being written to the
field, overwriting the a byte of the size field.

Fortunately, the size was updated soon after this.

Fixes coverity warning 1229570 - Destination buffer too small.

Change-Id: I39285a9283dd9a17d638afe5b2755c7e420d7698
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15889
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28 19:22:35 +02:00
Subrata Banik
a90f41bdd7 intel/fsp1_1: Add C entry support to locate FSP Temp RAM Init
FSP temp ram init was getting called earlier from ROMCC bootblock.
Now with C entry boot block, it is needed to locate FSP header and
call FspTempRamInit.

Hence add fsp 1_1 driver code to locate FSP Temp ram and execute.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built kunimitsu and ensure FSP Temp Ram Init return success

Change-Id: If40b267777a8dc5c473d1115b19b98609ff3fd74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15787
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:29:46 +02:00
Subrata Banik
e4a8537ce2 soc/intel/skylake: Add C entry bootblock support
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34

Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:15:58 +02:00
Subrata Banik
68d5d8b28a soc/intel/skylake: Do cache as ram and prepare for C entry
Enable cache-as-ram and prepare for c entry in bootblock.

BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A

Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>

Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 05:14:38 +02:00
Furquan Shaikh
3339861435 soc/intel/skylake: Use init_vbnv_cmos from vboot vbnv
BUG=chrome-os-partner:55639

Change-Id: I7a536bc1cab51e7c942b2e0e48dfe18d8de08a6e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15925
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:41:55 +02:00
Furquan Shaikh
0faf401823 soc/intel/broadwell: Use init_vbnv_cmos from vboot vbnv
BUG=chrome-os-partner:55639

Change-Id: Ie38cdbec513e2bb66e276399c8b4490cbe34a747
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15924
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-28 00:41:40 +02:00
Furquan Shaikh
0325dc6f7c bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.

BUG=chrome-os-partner:55639

Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28 00:36:22 +02:00
Furquan Shaikh
2a12e2e8da vboot: Separate vboot from chromeos
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.

BUG=chrome-os-partner:55639

Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 00:36:00 +02:00
Furquan Shaikh
c31973760f soc/intel/common: Store MRC data in next available slot in the cache
Currently, coreboot performs an erase of the entire MRC cache region on
flash if there is a version mismatch for the MRC data. Instead of doing
that, store the new MRC data in the next available slot, if there is
enough space available in the cache region.

BUG=chrome-os-partner:55699

Change-Id: Ib24a94f0a47c79941ed9f60095360ae3aad5540b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 23:53:03 +02:00
Bora Guvendik
60cc75df83 soc/intel/apollolake: Disable monitor mwait
The monitor/mwait is broken on Apollolake. So use ACPI legacy
mwait IO redirection as a work around

BUG=chrome-os-partner:55110

Change-Id: I2e1834130d9586b4310466d3549d19bf427ffe24
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/15890
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-27 19:36:01 +02:00
Lee Leahy
ae738acdc5 cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions.  In this case
use a SOC specific routine to support the setting of the MTRRs.  Migrate
the code from FSP 1.1 to be x86 CPU common.

Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c.  Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.

TEST=Build and run on Galileo Gen2

Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27 13:50:11 +02:00
Furquan Shaikh
b8257df83b intel/skylake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

With recovery module in vboot handling the saving of recovery reason
across reboots, there is no need to have special fsp reset handling
under soc.

BUG=chrome-os-partner:55431

Change-Id: I0b7ce14868a322072d3e60c1dae43f211b43fdbf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15804
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25 18:58:38 +02:00
Furquan Shaikh
7c7b291e55 intel/apollolake: Select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
This allows the board to save the recovery request in case of unexpected
reboots caused by FSP.

BUG=chrome-os-partner:55431

Change-Id: If71802d2cba52a426f4c2db90d6c5384ed03ce68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:58:03 +02:00
Furquan Shaikh
a6c5ddd595 vboot: Clean up vboot code
1. Remove unused functions/structures.
2. Add checks for NULL return values.
3. Change prefixes to vb2 instead of vboot for functions used internally
within vboot2/
4. Get rid of vboot_handoff.h file and move the structure definition to
vboot_common.h
5. Rename all functions using handoff structure to have prefix
vboot_handoff_*. All the handoff functions can be run _only_ after cbmem
is online.
6. Organize vboot_common.h content according to different
functionalities.

BUG=chrome-os-partner:55431

Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:35 +02:00
Furquan Shaikh
610a33a7f4 skylake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15822
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:21 +02:00
Furquan Shaikh
87b1bcc4af apollolake: Move CHROMEOS config to SoC
All the mainboards share the same config options for CHROMEOS. Instead
of duplicating those in every mainboard, move the CHROMEOS config to SoC
and make it dependent on MAINBOARD_HAS_CHROMEOS.

BUG=chrome-os-partner:55431

Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-25 18:55:01 +02:00
Aaron Durbin
2c29d34b37 soc/intel/apollolake: ensure usb port 0 is in host mode
The controller for device mode USB is not plan of record
on apollolake. However, one still needs to configure the
one port to be host mode by default such that the devices
work as expected when plugged into the board.

BUG=chrome-os-partner:54581,chrome-os-partner:54656
TEST=Enabled xdci controller. Used USB type C->A dongle to
     check that a mass storage device worked on port 0 on
     reef.

Change-Id: Ia9ec5076491f31bc5dc3d534e235fb49f7b2efac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15781
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-24 00:08:22 +02:00
Jagadish Krishnamoorthy
df7ad44853 soc/intel/apollolake: Correct the gpio bank irq
The gpio bank irq is not correct and hence gpio
bank handler is never called in case of gpio based irq.
Correct the gpio bank irq to enable gpio based irq.

BUG=chrome-os-partner:55433
TEST=cat /proc/interrupts | grep INT3452 should
output 14.

Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15756
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 18:57:48 +02:00
Aaron Durbin
48f662d941 soc/intel/apollolake: clarify meaning of LPDDR4 density meaning
The 'dram density' is a misnomer because the memory initialization
code treats that input parameter as a per rank density. Therefore,
update the variables to further clarify how it's actually being
used.

BUG=chrome-os-partner:55446

Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15773
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22 18:51:29 +02:00
Aaron Durbin
17dbec1593 soc/intel/apollolake: add dual rank option to meminit
Despite the UPD comments the Chx_RankEnable fields are a bit
mask which indicates which ranks are enabled for physical
channel. Add the ability to set the rank mask correctly for
dual rank LPDDR4 modules.

BUG=chrome-os-partner:55446

Change-Id: I9dbed7bb6a4b512e57f6b4481180932a7cce91ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15771
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22 18:50:49 +02:00
Aaron Durbin
aa00e0893e soc/intel/apollolake: die() when FSP silicon init fails
The reset requests are handled in the FSP 2.0 wrapper, but
the current code doesn't check any non-successful return
values. Provide parity with the memory init path which die()s
under those circumstances.

Change-Id: I9df61323f742b4e94294321e3ca3ab58a68ca4dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15766
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 18:50:40 +02:00
Abhay Kumar
67870f508f soc/intel/apollolake: Add new Intel HD Graphics Device ID's.
B stepping onwards we have to support two Graphics Device ID.

BUG=chrome-os-partner:55449

Change-Id: I520791ad8573dc5deb6ea1e33e1486f05050438c
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/15767
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-21 04:34:09 +02:00
Lee Leahy
b0672402ec soc/intel/quark: Fix legacy GPIO reads
Add missing break to LEG_GPIO_REGS case to return the correct value for
legacy GPIO reads.  Fixes coverity issue CID 1357460.

Found by Coverity, Fixes:
* CID 1357460 (#1 of 1): Unused value (UNUSED_VALUE)
  returned_value: Assigning value from reg_legacy_gpio_read(step->reg)
  to value here, but that stored value is overwritten before it can be
  used.

  value_overwrite: Overwriting previous write to value with value from
  reg_pcie_afe_read(step->reg).

TEST=Build and run on Galileo Gen2.

Change-Id: I6c52e8801a32f510ac94276fe0c097850cbfde57
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15732
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-20 17:08:02 +02:00
Andrey Petrov
3a94a3ba5b drivers/intel/fsp2_0: Split reset handling logic
FSP 2.0 spec only defines 2 reset request (COLD, WARM) exit codes. The
rest 6 codes are platform-specific and may vary. Modify helper function
so that only basic resets are handled and let SoC deal with the rest.

Change-Id: Ib2f446e0449301407b135933a2088bcffc3ac32a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-07-19 21:03:03 +02:00
Andrey Petrov
91ef21df62 soc/intel/apollolake: Implement reset_prepare()
At first boot CSE spends long time preparing media for use. As result
it may not be able to deal with a CPU reset. Add reset_prepare()
callback that polls CSE readiness.

BUG=chrome-os-partner:55055
TEST=build with release version of fsp, reboot, observe polling for
CSE, then proper reboot happening

Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19 20:20:39 +02:00
Andrey Petrov
6401188024 soc/intel/common: Add reset_prepare() for common reset
Some Intel SoC may need preparation before reset can be properly
handled. Add callback that chip/soc code can implement.

BUG=chrome-os-partner:55055

Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15720
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19 20:20:13 +02:00
Andrey Petrov
fcd51ffae8 soc/intel/apollolake: Add basic HECI support
Add functions to read Host Firmware Status register and a helper
function to determine if CSE is ready.

BUG=chrome-os-partner:55055
TEST=none

Change-Id: If511a51c04f7e59427d7952fa67b61060e2be404
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15713
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19 20:19:51 +02:00
Aaron Durbin
32ac01823b drivers/intel/fsp2_0: load and relocate FSPS in cbmem
The FSPS component loading was just loading to any memory address
listed in the header. That could be anywhere in the address space
including ramstage itself -- let alone corrupting the OS memory on
S3 resume. Remedy this by loading and relocating FSPS into cbmem.
The UEFI 2.4 header files include path are selected to provide the
types necessary for FSP relocation.

BUG=chrome-os-partner:52679

Change-Id: Iaba103190731fc229566a3b0231cf967522040db
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15742
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
2016-07-19 20:18:08 +02:00
Aaron Durbin
d04639b3d6 drivers/intel/fsp2_0: handle XIP and non-XIP for FSPM component
The previously implementation for loading the FSPM component didn't
handle platforms which expects FSPM to be XIP. For the non-XIP case,
romstage's address space wasn't fully being checked for overlaps.
Lastly, fixup the API as the range_entry isn't needed any longer.
This API change requires a apollolake to be updated as well.

BUG=chrome-os-partner:52679

Change-Id: I24d0c7d123d12f15a8477e1025bf0901e2d702e7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15741
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19 20:16:11 +02:00
Aaron Durbin
b4302504e3 drivers/intel/fsp2_0: implement common memory_init() tasks
Instead of performing the same tasks in the chipset code move
the common sequences into the FSP 2.0 driver. This handles the
S3 paths as well as saving and restoring the memory data. The
chipset code can always override the settings if needed.

BUG=chrome-os-partner:52679

Change-Id: I098bf95139a0360f028a50aa50d16d264bede386
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15739
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19 20:15:33 +02:00
Aaron Durbin
2792868519 drivers/intel/fsp2_0: set BootLoaderTolumSize generically
The amount of reserved memory just below the DRAM limit in
32-bit space is defined in the FSP 2.0 specification within
the FSPM_ARCH_UPD structure. There's no need to make the
chipset code set the same value as needed for coreboot.
The chipset code can always change the value if it needs
after the common setting being applied.

Remove the call in soc/intel/apollolake as it's no longer
needed.

BUG=chrome-os-partner:52679

Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15738
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19 20:15:15 +02:00
Aaron Durbin
ddbdcc3898 soc/intel/apollolake: remove unused FIT_POINTER define
Change-Id: I97be4f8cecbf9cf2adda2e0c1650e03acd7eb1cb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15736
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-07-19 20:13:55 +02:00