Similar to commit b45ed65, the HOB structure is actually a 8 byte
address pointing to the HOB data.
Tested=Verified the values of the hob fields are the same printed by
soc_display_memmap_hob().
Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable long mode in SMM handler.
x86_32 isn't affected by this change.
* Enter long mode
* Add 64bit entry to GDT
* Use x86_64 SysV ABI calling conventions for C code entry
* Change smm_module_params' cpu to size_t as 'push' is native integer
* Drop to protected mode after c handler
NOTE: This commit does NOT introduce a new security model. It uses the
same page tables as the remaining firmware does.
This can be a security risk if someone is able to manipulate the
page tables stored in ROM at runtime. USE FOR TESTING ONLY!
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Add new librem_whl baseboard and Librem Mini variant.
Tested with SeaBIOS, Tianocore, and Heads payloads.
All functions working normally except SATA, which is limited
via a FSP UPD to 3Gbps until the correct HSIO PHY settings
can be determined.
https://puri.sm/products/librem-mini/
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
FSP enables IPU (Imaging Processing Unit) by default even if its
disabled in devicetree. We need to fill FSP upd based on the device
enablement in devicetree.
BUG=None
BRANCH=None
TEST=IPU is disabled and doesn't show in lspci.
Change-Id: I0f9a40e85427fd88bb12a40770ecf7b939b1d8cd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable the introduced LPSS ACPI uart driver.
Tested on Hermes using Linux 5.6:
The UART2 appears as /dev/ttyS2.
Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the
device vendor ID reads as 0xffff, the PCI devices is still operate.
Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H.
The mainboard's devicetree needs to be adapted to include the chip
driver and the PCI ID when it wouldn't have been hidden.
Example:
chip soc/intel/common/block/uart
device pci 19.2 hidden
register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
end # UART #2
end
Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2.
Tested on Windows for all other UARTs.
Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPE events were not be recorded in the eventlog. Add those
to the eventlog when the status register indicates those events.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that no one is consuming this object, remove its definition.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that no one is consuming this object, remove its definition.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that all users of the functions manipulating global state
and using soc-specific objects are removed remove those functions.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status(). However,
in subsequent patches picasso will be snapshotting state way sooner than
ramstage.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status().
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to reduce code duplication provide an acpi_fill_gnvs()
helper function. Intent is to move stoneyridge and picasso over
to using this common implementation instead of duplicating it.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The existing code in common/block/acpi is mixing multiple operations:
saving things to cbmem in common code but then soc code uses that
information, reliant upon soc-specific struct soc_power_reg object,
and only saving/snapshotting ACPI registers very deep in ramstage.
To unwind the above provide some functions that are more targeted:
- Add struct acpi_pm_gpe_state object
- Add acpi_fill_pm_gpe_state()
- Add acpi_pm_gpe_add_events_print_events()
- Add acpi_clear_pm_gpe_status()
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This fix is required to avoid the division-by-zero error described at
https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html
while trying to run the DDR3 memory at 1866 MT/s (933 MHz).
With this fix in place, ASUS A88XM-E boots fine with RAM at 1866 MT/s.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Required for adding the XMP profiles support. SPD buffer is
already 256 bytes at AMD AGESA vendorcode, so this is fine.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Naming a device allows an ACPI _ROM method to be written for it. GPUs
may require this to make the configuration data contained within
available to an OS driver. This may be required for GPUs that do not
contain their vBIOS, or perhaps the drivers require it in this form/fashion.
Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully
obtains the vBIOS via ACPI (kernel 5.7.11).
Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With new board designs being introduced it does not make sense for the default
devicetree setting to be retimer disabled on port 0 for Aux Orientation.
Change the default to be Aux Orintation retimer controlled on all ports and
move the SOC controlled overrides to the corresponding overridetree files.
BUG=NONE
BRANCH=NONE
TEST=Built image for delbin and verified that port 0 flip is working.
Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This change sets the EFS config for SPI read mode to normal read mode
when using em100. With this, the boot is stable again without any
random hangs in PSP.
BUG=b:164429022
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
And also remove the deprecated by cl#43989
https://review.coreboot.org/c/coreboot/+/43989
BUG=None
TEST=Build the magolor board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board also supports Atom processors, which have four physical cores.
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Change-Id: I98a3da660052eb7ad2f18b0c7fc0e67a609eac54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
current setting got 0.278us which is less than the min 0.3us.
increase i2c2 data hold time for TP.
BUG=b:163613330
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. data hold time measured by scope: 0.3805us
Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This applies to the goodix touch screen on both the volteer and
volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen
"Report_Switch" signal. Goodix defines a 1ms (minimum) delay after
stop off. In addition, no longer drive this GPIO high by default as it
is now controlled by the kernel through ACPI.
BUG=b:153705232
TEST=touch screen still functional on volteer; confirmed timings with
scope (VDD, RESET, REPORT_SWITCH)
Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
More space is required in the COREBOOT CBFS to accommodate some features.
Currently no alternate firmware is stuffed into RW_LEGACY CBFS and has
~1 MB of unused space. Borrow some space from RW_LEGACY CBFS and extend
the RO_SECTION. Even within RO_SECTION, GBB requires only 12 KiB. So
adjust the GBB region accordingly and extend the COREBOOT CBFS.
BUG=b:162159386
TEST=Build the JSLRVP mainboard.
Change-Id: Ia8bb381c31ddf76f3211f9d4ac5c8c18c27834b7
Signed-off-by: Karthikeyan Ramasubramanain <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Value stored to 'size' is never read.
Also drop unused parameter.
Change-Id: If3e96ac90f06966ee408964e0748730bc237ec19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All the Sandy/Ivy Bridge EliteBook and ProBook laptops currently
supported by coreboot and on review all support TPM 1.2 according the
maintenance and service guide manuals of these laptops. So select the
Kconfig options of TPM and TPM 1.2 and add the entry of it to the
common device tree.
The device tree C source files of 8460p generated by sconfig before
and after this change are compared. All the device nodes still exist
with nodes under LPC having different device number.
Tested with 2560p, which still works without problems, and the TPM can
be detected and used in the system.
Change-Id: Ic6158d3346a55e3d09c0a4ced9fd141b9a6c4256
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Most of the code is generated by autoport. The laptop works well under
coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel
5.4.39 and 5.6.11.
Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Allwinner code has been removed from the master branch for quite
some time now.
Change-Id: I9e5fd267140c180ae145d12b325cc489725f9ad0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This can be used in romstage in particular to know if dram is ready.
Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
INVD is called below so if postcar is running in a cached environment
it needs to happen.
NOTE: postcar cannot execute in a cached environment if clflush is not
supported!
Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects that value assigned to variable "ret" is overwritten
before it is used. Fix the issue by returning right value.
Found-by: Coverity CID 1255942, 1241836
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I2e1fb5400ff64c6178bb30601896780f8d67b5c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CPU variant has a different CPUID signature.
Change-Id: Ice2c1b86382e5d91d9eda717e6522ed0a9c2229f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on JSLRVP.
Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on waddledoo.
Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Initialize watch dog so the system won't reboot on timeout.
In addition, print the reason of reboot triggered by watch dog.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I7e849659700218f1c50365c2d68a32be2f703d94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Initialize CPU mmu and config range.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I5ba405dab87d51d373704657ccb44c07c7249041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Those flags already get unconditionally set in soc/amd/picasso/acpi.c.
Change-Id: I978c7d67480499d92c193d5bb87bc876211187db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Two of the items in the FADT ACPI table frequently are partially board-
specific, so let's make it easy to update them via devicetree settings.
- fadt_boot_arch 0="legacy free" which while reasonable, probably isn't
what will be wanted by most mainboards, so this should generally get
updated in the specific devicetree.
- In fadt_flags all chipset-specific flags get set while the mainboard
has to set all other flags that it needs to have set.
This patch changes the default for fadt_boot_arch.
Change-Id: I6e8d0c60cadfdd24b6926703b252abbc56d436de
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The DISPLAY_3D class is for graphics devices that are not connected to
displays. This includes GPUs implementing muxless Nvidia Optimus.
According to CB:31502, some AMD GPUs are identified as DISPLAY_OTHER.
Therefore, consider the entire DISPLAY class as GPUs.
Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores).
Current coreboot SMM is unable to handle more than ~32 CPU threads.
This patch introduces a version 2 of the SMM module loader which
addresses this problem. Having two versions of the SMM module loader
prevents any issues to current projects. Future Xeon-SP products will
be using this version of the SMM loader. Subsequent patches will
enable board specific functionality for Xeon-SP.
The reason for moving to version 2 is the state save area begins to
encroach upon the SMI handling code when more than 32 CPU threads are
in the system. This can cause system hangs, reboots, etc. The second
change is related to staggered entry points with simple near jumps. In
the current loader, near jumps will not work because the CPU is jumping
within the same code segment. In version 2, "far" address jumps are
necessary therefore protected mode must be enabled first. The SMM
layout and how the CPUs are staggered are documented in the code.
By making the modifications above, this allows the smm module loader to
expand easily as more CPU threads are added.
TEST=build for Tiogapass platform under OCP mainboard. Enable the
following in Kconfig.
select CPU_INTEL_COMMON_SMM
select SOC_INTEL_COMMON_BLOCK_SMM
select SMM_TSEG
select HAVE_SMI_HANDLER
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Debug console will show all 36 cores relocated. Further tested by
generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all
cores entering and exiting SMM properly. In addition, booted to Linux
5.4 kernel and observed no issues during mp init.
Change-Id: I00a23a5f2a46110536c344254868390dbb71854c
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify some if-blocks which are used for the configuration, enablement
and disablement of the PEG devices.
This changes the logic of the code, since it configures PegxEnable
before the if-blocks, where x is the number of the PEG device, and the
further configuration of the PEG devices depends on the enablement of
PegxEnable.
Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Move InternalGfx config option out of the if-else-block and replace the
left over config option IgdDvmt50PreAlloc by a ternary expression. Also,
adjust related code comments to fit the new logic of this code.
This changes the logic of the code, since InternalGfx is configured
first and IgdDvmt50PreAlloc depends on its value. The negation in the
ternary expression is removed to improve the readability.
Change-Id: I89ff17f4574a7ade228c1791f17ea072fb731775
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.
Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if
the DB doesn't support USB4 the platform as a whole should only be USB3
capable and TBT functionality on both ports should not be enabled.
BUG=NONE
BRANCH=NONE
TEST=Built coreboot and verified that TBT was disabled on platform with
USB3 DB and enabled on platform with USB4/TBT DB
Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is
reset as part of global reset, TPM initialization fails. This is because
AP reset is not detected by TPM hosting an older firmware version. Request
Embedded Controller (EC) to perform AP reset so that TPM can detect that
event.
BUG=b:162290856, b:162386991
TEST=Ensure that the device boots to OS with the board-specific reset
sequence when CSE Lite jumps from RO to RW with an older and newer Cr50
firmware.
Cq-Depend: chromium:2337430
Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add a helper function to initiate AP reset through Embedded Controller
(EC).
BUG=b:162290856
TEST=Ensure that the EC resets AP on boards where the command is
supported.
Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is
reset as part of global reset, in some boards TPM initialization fails.
This is because AP reset is not detected by TPM hosting an older firmware
version. To signal TPMs running older firmware version about AP reset, a
modified reset sequence needs to be performed. Hence add support to
perform board-specific reset sequence.
BUG=b:162290856, b:162386991
TEST=Ensure that the device boots to OS with the board-specific reset
sequence when CSE Lite jumps from RO to RW with an older and newer Cr50
firmware.
Change-Id: I8663e7f25461e58e45766e2ac00d752bfa191d8b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44187
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested=On OCP Delta Lake, BMC SOL can see POST codes
Change-Id: I2c27055475e6dadcd4282cd1bf191a1b83150f02
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set default value of ModPhyIfValue parameter in FSPS_UPD.
Without this setting, it will be set to '0' and system may not detect
USB 3.0 device.
BUG=b:163382089
BRANCH=firmware-octopus-11297.B
TEST=Built
Change-Id: Ide3d1637f99dba28251102f771b6ce370cc5d8e4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Per the datasheet and the it87 kernel driver, the IT8728F supports
both 5 fans (vs 3) and use of a single 7-bit register for the
PWM slope (5 bits in closed-loop mode).
Change-Id: I3d1e6f5030f18d2c8ff533965ae4718be0f3c279
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for tachometer closed loop mode, and programming
of initial RPM vs initial PWM value.
Change-Id: Idff29331c979f8518021103b6f8d19e75e657e3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently sku_id is used to enable/disable eMMC as boot media on
Dalboz. This patch will check eMMC bit in firmware configuration
table to enable/disable eMMC.
On Dalboz Proto and EVT devices with eMMC, there was an issue found
after SMT. This patch checks for board_version instead of SKU_ID to
configure eMMC in HS200.
Configure HDMI based on daughterboard_id in FW_CONFIG.
BRANCH=none
BUG=b:152817444
TEST=Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: Ifa2a49a754d85fb6269f788c970bd9da58af1dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently SKU_ID is used to enable/disable eMMC as boot media on
Ezkinil. This patch will check eMMC bit in firmware configuration
table to enable/disable eMMC.
BRANCH=none
BUG=b:162344105
TEST=Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I62318cf71ec70790f2d9e787febd1e0b787741fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
After confirming that all zork variants and phases have valid
FW_CONFIG value in CBI, this patch is dropping FW_CONFIG validity checks
like VARIANT_HAS_FW_CONFIG and VARIANT_BOARD_VER_FW_CONFIG_VALID in Kconfig
and will also remove associated helper functions.
BRANCH=none
BUG=b:162344105,b:152817444
TEST=Check if FW_CONFIG bits can be read in coreboot and FW_CONIFG helper
function do not return 0 if board has a valid FW_CONFIG in CBI.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I633dc7c500ef8759f3fffb0db6b76d96257c3c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets the GPP_H1 to PAD_CFG_GPO which is general
purpose output with no pullup/down. We need this GPIO for
the detection of soundcard in TGL RVP's.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp successfully. From "aplay -l"
output check that soundcards are listed properly.
Change-Id: Ic0ef33079af7940360c986efacabd6d367aad516
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
To be consistent with the rest of the tree, replace all left ternary
expressions, which are used for device enablement / disablement,
with `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO
Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13
Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0
based, so it doesn't reuse coreboot's stack, but sets up its own stack.
In contrast to all other FSP 2.0 based platforms, this stack isn't in
the CAR region, since AMD Picasso doesn't support CAR and the DRAM is
already available when the x86 cores are released from reset. Selecting
FSP_USES_CB_STACK ended up doing the right thing, but is semantically
wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso
we take the corresponding code path if ENV_CACHE_AS_RAM is false which
is only the case for non-CAR platforms.
BUG=b:155501050
TEST=Timeless build results in an identical binary for amd/mandolin,
asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases
here.
Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This reduces the differences between both ME source code files.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I08e07ca2691bb854682692476153a98967bf05da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This patch updates regions-for-file function in the
security/vboot/Makefile.inc to support adding a CBFS file into
required FMAP REGIONs in a flexible manner. The file that needs to be
added to specific REGIONs, those regions list should be specified in the
regions-for-file-{CBFS_FILE_TO_BE_ADDED} variable.
For example, if a file foo.bin needs to be added in FW_MAIN_B and COREBOOT,
then below code needs to be added in a Makefile.inc.
regions-for-file-foo := FW_MAIN_B,COREBOOT
cbfs-file-y := foo
foo-file := foo.bin
foo-type := raw
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I1f5c22b3d9558ee3c5daa2781a115964f8d2d83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DRAM resource in ramstage to load payload.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The first Makefile to support building minimal stage files for MT8192 SOC.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO
to 8MiB") updated the flash layout which moved RW_SECTION_A and
RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION
and PICASSO_FW_B_POSITION configs need to be updated accordingly to
retain the same behavior as before i.e. amdfw_a/b are placed at the
start of FW_MAIN_A/B by placing them right after the CBFS header.
This change fixes the value of PICASSO_FW_A_POSITION and
PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS.
BUG=b:161949925
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Starting with v3.6 of reference schematics, headphone jack interrupt
is moved to a standard GPIO instead of using CODEC_GPI. Thus, we no
longer need I2S wake to be enabled in the ACP for boards using v3.6+
version of schematics.
This change sets `acp_i2s_wake_enable` and `acp_pme_enable` to default
0 in baseboard devicetrees and overrides to 1 in update_hp_int_odl()
if the board is still using older version of reference schematics.
BUG=b:159934887
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Latest EDK2 code inside
"UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c"
is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence
coreboot need to fill required information (package, core and thread
count).
TEST=Able to see package, core and thread information as part of FSP
debug log.
Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.
BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.
BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia
system. Add information on sensors, power limits and tcc_offset for DTT
based thermal control.
BRANCH=None
BUG=b:161993459
TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
espi_poll_status describes better what the function actually does, since
it polls the status register instead of just doing a single read to
check.
Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the ranges of bitfields as comments on the struct.
Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Also remove the meaningless `sata_traffic_monitor` devicetree option.
Function parameters will be removed in a reproducible follow-up.
Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There's no mobile ICH10 variant. This was copied from i82801ix.
Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Taken directly from i82801jx code.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These were probably copy-pasted from some ICHx southbridge, and then
some were corrected because native PCH init uses them. Delete the
definitions which are unused and are invalid for this southbridge.
Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These were probably copy-pasted from some ICHx southbridge. However,
datasheet shows that some of these are located elsewhere, and some
others have disappeared completely. As they aren't in use, drop them.
Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Create the lindar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.2).
BUG=b:161089195
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_LINDAR
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: I08923cde932b7304bcb01cd747530c87949e4692
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable PCI_COMMAND_MASTER for SATA controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.
BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.
Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On CNP-H, only four I2C controllers are available, so PCI devices 19.0
and 19.1 are missing. However, PCI device 19.2 still exists as UART 2.
That function 0 is missing means UART 2 can only be used in ACPI mode.
Both devices need to be marked as hidden on the devicetree so that the
allocator takes UART 2 into account.
Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Values are taken from pci_irqs.asl.
The common code will make use of those defines to generate ACPI
SSDT code for LPSS uarts operating in "ACPI mode".
Change-Id: I5ef93493965834cda30d70918e65de3129e547b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reorganizes flash map layout for zork to allow WP_RO to
grow to 8MiB. This is to allow more space for the firmware UI screens
in RO. Following changes are made in the layout:
1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for
MRC cache. Next section can start on 64K boundary immediately after
MRC cache.
2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB
each. Each region is currently at ~2MiB of usage.
3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size
supported by coreboot.
4. SMMSTORE is restricted to 4K.
5. RW_LEGACY region is dropped down to ~1.9MiB.
BUG=b:161949925
TEST=Verified that write-protection for RO still works fine, device
boots in recovery and non-recovery mode. Also, verified that the dump
of fmap looks correct:
dump_fmap -h firmware/image-trembyle.serial.bin
name start end size
WP_RO 00800000 01000000 00800000
RO_SECTION 00804000 01000000 007fc000
COREBOOT 00875000 01000000 0078b000
GBB 00805000 00875000 00070000
RO_FRID 00804800 00804840 00000040
FMAP 00804000 00804800 00000800
RO_VPD 00800000 00804000 00004000
RW_LEGACY 0061d000 00800000 001e3000
SMMSTORE 0061c000 0061d000 00001000
RW_NVRAM 00617000 0061c000 00005000
RW_VPD 00615000 00617000 00002000
RW_SHARED 00611000 00615000 00004000
VBLOCK_DEV 00613000 00615000 00002000
SHARED_DATA 00611000 00613000 00002000
RW_ELOG 00610000 00611000 00001000
RW_SECTION_B 00310000 00610000 00300000
RW_FWID_B 0060ff00 00610000 00000100
FW_MAIN_B 00312000 0060ff00 002fdf00
VBLOCK_B 00310000 00312000 00002000
RW_SECTION_A 00010000 00310000 00300000
RW_FWID_A 0030ff00 00310000 00000100
FW_MAIN_A 00012000 0030ff00 002fdf00
VBLOCK_A 00010000 00012000 00002000
RW_MRC_CACHE 00000000 00010000 00010000
SI_BIOS 00000000 01000000 01000000
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
In order to help identifying right DRAM info (especially in user space),
we want to unify the mapping table and do the device-specific mapping by
a virtual offset based on build config.
BUG=b:161768221,b:159301679
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
With a CPUID of 10676, it is clearly model_1067x... Wait, it's already
there, but the comment is wrong. This ID isn't for Core Duo CPUs.
Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The base address of the memory mapped I/O registers should not
be cached across resource allocation. This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.
Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change namespace from _PR to _SB.
Cq-Depend: chrome-internal:3208104
BUG=b:153242529
TEST=Boot a trembyle with change applied and dump SSDTs to ensure
processors are in _SB scope.
Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.
Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When address and data register for the SIO control register access is
passed as one I/O region with a size of 2, the corresponding special
decode enable register should be used instead of a generic one to save
the rather limited generic ones for other decode ranges.
Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We can just return at all places where the ret variable was written
before its value gets returned at the end of the function.
Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since this is a bit mask applied to the raw value of a 32 bit register,
this should be a 32 bit unsigned type.
Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Th register number passed to the low level read/write functions should
never be negative.
Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some fields in GNVS seem to be copied over from Apollolake to
Stoneyridge. This patch removes the unused fields.
Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The USB OC pin mapping is similar enough to move it to the base board
and just have two overrides for trembyle, which is based on an older
version of the schematics, and one override for woomax, which doesn't
use one USB port.
BUG=b:163081097
Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add comments found when testing ECC scrubbing code.
This is a cosmetic change.
Change-Id: I7975f6070c2002930eec407a6b101a1295495b25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The scrubbing method was never correct nor tested.
Fix that by observations made on mrc.bin.
Tested on HP Z220 with ECC memory and Xeon E3 CPU:
The whole memory is now scrubbed.
Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add ECC test code when DEBUG_RAM_SETUP is enabled
* Move ECC scrubbing after set_scrambling_seed() to be able to observe
what has been cleared in the test routine. If clearing happens
before set_scrambling_seed the data is XORed with a different PRN.
Data read from memory will look random instead of all zeros.
* ECC scrubbing must happen after dram_dimm_set_mapping()
The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In
normal mode the ECC bits are calculated and stored on write
transactions.
* Move method out of try_init_dram_ddr3().
This satisfies point 2 and point 3 of the list above.
Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to
GPP_D16 but there is a RTS5261 requirement to pull up this pin and not
drive it at power on. We can meet this requirement without breaking
other boards by changing GPP_D16 to be a no-connect with an internal
pull up. Other boards use this signal as an enable input, so changing
this to pull up is OK.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The interface selection register of the environment controller (EC)
gives the choice between "Internal generated 32 MHz" and "24 MHz" for
the "SST/PECI Host Controller Clock Selection".
Previously the chip was always configured for the 32 MHz clock. Add an
option that can be set from devicetree.cb to allow using the 24 MHz
clock.
Without this setting the automatic fan control on an Acer Aspire M3800
was slow to respond to temperature changes.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This applies to the automatic fan control mode of the environment
controller (EC). Previously the affected bit was always cleared while
the default value is 1 according to datasheets. Add a variable that can
be set per mainboard in devicetree.cb.
In the IT8783E datasheet that bit is marked as reserved.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This isn't reproducible for some reason, but it is relatively simple.
Change-Id: I507229be71ac2c589c7ecd81495d38ce363d26a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43275
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do it quick and dirty but in a reproducible manner. Variants will be set
up properly in subsequent commits.
Tested with BUILD_TIMELESS=1, both Lippert FrontRunner-AF and Toucan-AF
remain identical.
Change-Id: I71ff50099787e7806a9ab67429890a1c77061929
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43274
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the same names as on other intel socs.
Will be used in intel common uart driver.
Change-Id: Ia418fefb3f925fe4d000683b5028682cf0b68a9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and
0:19.2 can't be detected using standard PCI probing.
Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms
that advertise its PCI conformance by the _ADR attribute.
Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL.
Removing the register programming for these platforms. The write to
this register does not take effect and remains configured to 0, even
when programmed.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I3f581b90ea99012980f439a7914e8d901585b004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Intel CPX-SP ww32 release has a number of bug fixes:
a. It fixed the issue related to some PCIe ports being hidden. This
affected DeltaLake config A, made the onboard PCIe NIC device not
working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu.
b. It fixed the regression related to MRC cache.
c. It fixed the issue related to VT-d support, and added X2apic UPD
paramter. A separate PR will be submitted to enable VT-d in coreboot.
d. It fixed the issue related to enabling thermal device with PCI
or ACPI mode. [CB:44075] was submitted to enable it in coreboot.
e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel
not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS
remotely.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.
Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.
All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.
Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This option has been removed from the parameters structure for Intel
Skylake CPU (commit 9c1c009).
Change-Id: I9dc6649ad693d18fdc85046ebbcc730a17fed0bf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner
Add MT8192 address map, memlayout and first Kconfig. MT8192 is similar to
MT8183.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I4e34c03a11a77ed98674ffd8eeddb20ef5fea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43957
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts the code from commit 728c0787f2 that removes the reset
GPIO from the touchscreen ACPI interface.
That patch exposes a bug which leads to an invalid opcode trap in the
touchscreen code. Reverting this gets the system working again, but is
not a long-term solution.
BUG=b:162596241
TEST=System boots to login screen.
Change-Id: I57a070d94f961cec43834c8bedd5dafc8a54171a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43078
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.
Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.
All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.
Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
These values in GNVS are written, but never read/used. aoac.asl contains
proper ACPI power management functions for the AOAC devices that
directly access the state from the device's registers instead of relying
on cached values in GNVS, so the corresponding GNVS entries can be
dropped.
BUG=b:161165393
TEST=Mandolin still boots and dmesg shows no new ACPI errors.
Change-Id: Iee78df215308bd9b656228be787fac121d10ca99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Lynxpoint and Broadwell.
Change-Id: I759aa98b80c70c5024213bd8795375061bdbbf10
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42622
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MSR macros were treated as memory addresses and the loops had
off-by-one errors. This resulted in a CPU exception before GETSEC, and
another exception after GETSEC (once the first exception was fixed).
Tested on Asrock B85M Pro4, ACM complains about the missing TPM and
resets the platform. When the `getsec` instruction is commented-out, the
board is able to boot normally, without any exceptions nor corruption.
Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Meera Ravindranath