Somehow, enabling the notification to the OS driver breaks the
functionality it was meant to enable. Until this can be resolved,
disable the driver notification, so that the key functions as intended.
Test: build/boot librem_bdw and librem_skl boards, verify trackpad
enable toggle via Fn+F1 works properly.
Change-Id: Ic7bdb3154a87c4202b5ee1fd333281ef78db1104
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55657
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Decrease SA slew rate to match other domains and reduce
high-frequency noise slightly.
Change-Id: I02cd93481f6bfba6249cb338a0e2f47d471a438e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If the early crtm is not initialised there is nothing to write to PCR
in the early tpm init.
Change-Id: I9fa05f04588321163afc817de29c03bd426fc1f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
CSE error codes may be applicable to move than just CSE Lite SKU errors,
therefore move this enum to the intelblocks/cse.h file so that it can be
used in other CSE-related code. While copying, remove `LITE_SKU` from a few
of the enum values that are not necessarily CSE Lite SKU-specific.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0351587c67ce12f781c536998ca18a6a804d080a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55672
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write
protect signal is decoupled from the hardware write protect signal.
Instead, we'd like for it to mirror the software write protect status.
This commit simply checks the software write protect status of the SPI
flash and sets the CBI EEPROM write protect if it's enabled. To prevent
changing the WP signal at run-time, the GPIO configuration is also
locked down after the level has been set. If HW WP is deasserted, the
CBI EEPROM WP will be deasserted as well.
BUG=b:191189275,b:184592299
BRANCH=None
TEST=Build and flash lalala, disable SW WP by running `flashrom -p host
--wp-disable` from a root shell and verify that the GPIO is asserted
after a reboot. Export the gpio via sysfs and verify that attempting to
change the value of the GPIO is futile. Enable SW WP via `flashrom -p
host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs
and verify that attempts to change the GPIO value are futile.
localhost ~ # iotools mem_read32 0xfd6e08d0
0x44000200
localhost ~ # cd /sys/class/gpio/
localhost /sys/class/gpio # echo 217 > export
localhost /sys/class/gpio # cd gpio217/
localhost /sys/class/gpio/gpio217 # echo out > direction
localhost /sys/class/gpio/gpio217 # cat value
0
localhost /sys/class/gpio/gpio217 # echo 1 > value
localhost /sys/class/gpio/gpio217 # cat value
1
localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0
0x44000200
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit adds a method called `mainboard_smi_finalize` which provides
a mechanism for a mainboard to execute some code as part of the finalize
method in the SMM stage before SoC does its finalization.
BUG=b:191189275
BRANCH=None
TEST=Implement `mainboard_smi_finalize` on lalala and verify that the
code executes in SMM.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit simply adds the offset for the PADCFGLOCK register for the
Intel Jasper Lake platform. This enables pads to be locked.
BUG=b:191189275
BRANCH=None
TEST=Enable pad locking on lalala by calling `gpio_lock_pad` and verify
that the pad configuration is locked and cannot be manipulated from the
OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Iccfe536b4a881f081f22bcc258a375caad3ffcb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55648
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a method for locking a GPIO pad configuration and its
TX state. When the configuration is locked, the following registers
become Read-Only and software writes to these registers have no effect.
Pad Configuration registers
GPI_NMI_EN
GPI_SMI_EN
GPI_GPE_EN
Note that this is only effective if the pad is owned by the host (set in
the PAD_OWN register).
Intel platforms that wish to leverage this function need to define the
PADCFGLOCK offset for their platform.
BUG=b:191189275
BRANCH=None
TEST=With some other code, call gpio_lock_pad() against a pad and verify
that the pad configuration is locked and the state of the pad cannot be
changed from the OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Id3c0da2f6942099c0289ca1e33a33c176f49d380
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Per the Intel External Design Specification (doc #618876), the opcode
for GPIO_LOCK_UNLOCK is 0x13. This commit fixes a bug where the opcode
was defined as 13 decimal instead of hexadecimal. Additionally, it
fixes another issue where the `pcr_execute_sideband_msg()` function
doesn't actually write the data when this opcode is selected.
BUG=b:191189275
BRANCH=None
TEST=With additional code that uses this opcode, verify that the lock
functionality works by locking a pad in firmware and attempting to
modify the configuration of the pad from the OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.
This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).
Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.
BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the raw values of the enum elements are used, explicitly assign
the value 0 to the first element to make it clearer that the absolute
values matter here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69f58cca7130ce5f0ebe4743754e4e31f55db289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Using existing defines instead of magic values improves readability of
the code. Also add comments to the MADT IRQ overrides to make it clearer
what those actually do.
TEST=Timeless build results in identical binary for amd/gardenia
(Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add mt6691 buck control for DRAM to run fast calibration test.
It is needed to get and set voltage during testing.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Change-Id: I4fb9f7245d44383a6a3a0cf8d00f7f503cbdeb06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55575
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To enable display, we have to:
1. Configure panel power and backlight
2. Configure eDP driver
BUG=b:189985956
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: Ida6c157a6a3bd904d3fa3dd2001385ced34f7711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55574
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes the storage size to reflect the proper bits instead
of bytes. It was a bug in the initial HEST patch
(https://review.coreboot.org/c/coreboot/+/52090), and commit ID d4db36e672 . Also fixed the
comments to properly reflect the range being used.
Change-Id: I9e968bb09f1c9cd805ff1d0849551b9c2ce2e2b6
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55393
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the default rom size to 32MB and remove chromeos.fmd
because Chrome OS is not supported on EHL for now.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I49d9404eb901087037b5423a4a503c5271e14138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ia20cabcaf9724882c68633eb9b510230e993768c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add FSP_ARRAY_LOAD macro for checking and loading
array type configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes unnecessary __packed attribute from the structure
defined in chip.h
BUG=None
TEST=Tested WFC camera on Brya
Change-Id: I1174606cd22cd353f01d865d0c25bb6f8f8de055
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Turn on CBI and add helper functions for determining the board
configuration from the firmware config settings in CBI.
BUG=b:187316460
TEST=Built
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change also restores GPIOs to their proper settings for prior board
revs.
BUG=b:189362981
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Configure I2C high / low time in device tree to ensure I2C
CLK runs under I2C_SPEED_FAST (400 kHz).
Touchpad: 387.7kHz
Touchscreen: 389.4kHz
Audio: 387.6kHz
P-sensor: 372.5kHz
BaUG=b:178092096
BRANCH=dedede
TEST=Build and EE check after tuning I2C clock is under 400kHz
Change-Id: I4f6bdd3802cd94671325a89458cde981a2ffa929
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
google_chromeec_get_event returns an event number and 0 when there's no event.
This function is usually called in a loop until there are no more events, so
it makes sense to return 0 (i.e. no event) when there's an error.
BUG=b:184074997
TEST=Boot guybrush, no ec errors
Change-Id: I6c0186e4637af9ae24f45cce3638f0913227d6a7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The GPIO_GSC_AP_INT itself is active low, but the payloads will
create the IRQ using its eint driver, which is active high.
BUG=b:188392736
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie39f3b9a5dbe15057ef3e96f6c99211949692003
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Any chip entry without a device node below them are silently dropped by
sconfig. Copy the same device node from the devicetree to prevent this.
Change-Id: I778f6b2d980e78142ae12ef941e7d9bd1f753057
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55540
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the default state of the MMIO UART devices in the chipset
devicetree is off, the mainboard devicetree entries that disable MMIO
UART devices are removed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Defining the memory mapped base in fmap for example "FLASH@0xff800000
0x80000" for a 8M flash is optional in fmap files. This will also
reflect in the generated fmap_config.h. Fix the assembly cbfs walker
walkcbfs.S for fmap lacking a definition of the flash base.
Change-Id: I96b18f675e625abee503648ffdc6031978a4269a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Create the cappy variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:190515828
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Id5a3b0cb475ee77a9f62523d8322a5e4123ce3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
devfn_disable() function is used to disable a device based on
given bus, device function number. This function checks if the
device is at enable state and disables the device.
Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add camera support in devicetree.
BUG=b:190797339
BRANCH=None.
TEST=built pirika firmware and verified camera function is OK.
Change-Id: I66ded32105f3166e2faec3ea5dcfb93c29822366
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55450
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to meet timing requirement of WWAN reseting it in early GPIOs
and asserting Reset GPIO in ramstage
BUG=b:180166408
TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pmc_set_power_failure_state() is usually called twice, once upon boot
(with `target_on == true`) and once from SMM when the system is shut
down (with `target_on == false`). Assuming settings didn't change
between these calls, there is only one case where we actually need
to write the register value: when updating the state for the
MAINBOARD_POWER_STATE_PREVIOUS feature.
This suits us well as we want to avoid unnecessary writes so we
don't clobber the value set upon boot from within SMM. Due to
inaccessible option backends, SMM might not know the current
option state.
The assumption above, that the option value didn't change, may not
be true if the user changed the option on purpose. In the future,
one would have to reboot the machine for option changes to take
effect. However, this doesn't seem to make a huge difference: One
already needed a controlled shutdown for the update to take effect
before. A reboot doesn't seem much more expensive.
Change-Id: I58dd74b8b073f4f07db090bf7fddb14b5df8239a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55539
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch create separate helper functions to fill-in required
FSP-M UPDs as per IP initialization categories.
This would help to increase the code readability and in future
meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly.
TEST=FSP-M UPD dump shows no change without and with this code change.
Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55225
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating the APOB takes a considerable amount of time. I decided to be
granular and split out the operations so we know when we read vs read +
erase + write.
BUG=b:179092979
TEST=Boot guybrush and dump timestamps
3:after RAM initialization 3,025,425 (44)
920:starting APOB read 3,025,430 (5)
921:starting APOB erase 3,025,478 (48)
922:starting APOB write 3,027,727 (2,249)
923:finished APOB 3,210,965 (183,238)
4:end of romstage 3,210,971 (6)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I08e371873112e38f623f452af0eb946f5471c399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.
For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.
For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.
For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.
Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This a mainly a preparation for adding the MMIO UART devices to the
chipset devicetree.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In acpi_soc_get_bert_region after the bert_errors_region call is was
checked if the region parameter is NULL after the call; since region is
a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should
be checking here is if region points to a non-NULL pointer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Coverity (CID:1457506)
Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Even though the code is currently commented out, replace the magic
numbers with the existing defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0dbbadf71f2e5a4d23ee998e2aa0a8b67205845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Lynx Point PCH ACPI reference code version 1.9.1 has two additional
magic steps, which were already present in Broadwell. Add them.
Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The printed values are unsigned, and should be printed accordingly.
Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The typedef needlessly hides the actual type of the variables.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I58a58cd402ec679960f460e80b37ff2afb8e3974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This option is valid for Broadwell as well as Haswell.
Change-Id: I4f1e9663806bae279f6aca36f09a0c989c12e507
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Split up PCH Kconfig into a separate file. While we're at it, also sort
selected options alphabetically.
Tested with BUILD_TIMELESS=1, coreboot.rom for the Purism Librem 13 v1
remains identical when not adding the .config file in it.
Change-Id: Ic3ff982e7108bf2d25a22e56ac2fbb93070df164
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The BMC EEPROM layout has been updated to contain system and mainboard
serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables.
Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These macros were used to generate ACPI P-state entries, but Broadwell
now uses Haswell CPU code. These macros are unused and can be removed.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: Ib2baca2964d9177e7ab6630d4ced22c5d332fb6e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Keep deduplicating code. Have Broadwell PCH ASL borrow some equivalent
Lynx Point ASL files, and drop the now-unused files from Broadwell PCH.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: If5a8712a846bbf7c42db92167763935dee74c26f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use hostbridge.asl from Haswell instead of Broadwell. Both files are
equivalent. Then, drop the now-unused hostbridge.asl from Broadwell.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Include Haswell memmap.h from Broadwell iomap.h to deduplicate identical
definitions. This also prevents the definitions from falling out of sync
while the unification process is ongoing.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I850e5521effba3818f4e2a13b94281bf07857d50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move the inclusion of `pci_irqs.asl` into PCH scope in order to allow
deduplicating northbridge ACPI code.
Change-Id: I541913226b26662f3798ae9c25ab1ac33cf2ed45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Taken from Haswell code. These resources also exist on Broadwell and
should be reported to the OS.
Change-Id: I45f2a6a9140d72c1cc2ee8b72621dc16c815b621
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
GDXCBAR and EDRAMBAR are accounted for when reporting resources to the
allocator, but they are not present in the DSDT. In addition, coreboot
does not enable either range, but MRC.bin sets up GDXCBAR and does not
disable it afterwards. Not reporting GDXCBAR in the DSDT can result in
resource conflicts, and not enabling EDRAMBAR can cause issues on CPUs
with eDRAM.
Enable both GDXCBAR and EDRAMBAR in coreboot code, and report these
ranges in the DSDT. This matches what Broadwell does. The value for
the `GDXC_BASE_ADDRESS` macro matches what MRC.bin programs as well.
Tested on Asrock B85M Pro4 with an i7-4770S (no eDRAM):
- Still boots
- EDRAMBAR is now enabled with base address of 0xfed80000
- GDXCBAR is still mapped with base address of 0xfed84000
Change-Id: I5538873b30e3d02053e4ba125528d32453ef6572
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add defines for the sizes of northbridge MMIO windows and use them where
applicable. The macro names have been taken from Broadwell.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Mainboard information can be found in the included documentation.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55111
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is only called locally.
Change-Id: Ie3eaf659a2868eee1d4688885495c413f94f42e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
1) FSP-S should not run XIP
2) Overriding the FSP-T location conflicts with the location set in
drivers/intel/fsp2_0
This fixes a regression caused by commit
0f068a600e (drivers/intel/fsp2_0: Fix the FSP-T position)
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/G6WRFITANOS2JEYG3GKB2ZNVCLUZ6W7P/
Change-Id: I381781c1de7c6dad32d66b295c927419dea7d8be
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
One of the Memory32Fixed entries covers the TXT private and public
spaces, and another covers the TPM registers. Update the comments.
Change-Id: I261d74c113fabf1d152964efd8c91de85eba4179
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.
The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.
Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55098
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
TEST=Able to build and boot without any regression seen on ADL.
Change-Id: I92671992ec14fd2adca1635b0791ac8b456332e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55292
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on EHL.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iadf9145a11f27ff0e182f146b6fe5a01e6cf3ed8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on TGLRVP.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ic9d91b711bab83de1911e0b7ea876f2ad018c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55330
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on dedede
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4919a1ec02df50bc41fd66d5f3a352108a7aa04c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on CML.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib5df5fd32e2e2742d349754a942bf81ca505dd39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
TEST=Able to build and boot without any regression seen on Reef.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT,
specifically for (obsolete) Init Level De-assert.
Level LAPIC_INT_ASSERT is required to be set for all other delivery
modes other than LAPIC_DM_INIT.
This reverts the two above changes that X2APIC mode support introduced
to the IPI for LAPIC_DM_SMI.
Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Depending on how the "middle-end" (yes, the gcc developers are
serious about that) optimizer ends up mangling the code, there may
or may not be a complaint about x being used uninitialized when it's
clearly not used at all.
So instead, why keep x in the first place? memcpy(foo, NULL, 0) is
the same as memcpy(foo, some_uninitialized_variable, 0) in that it
does nothing.
Change-Id: Ib0a97c3e3fd1a2a6aff37da63376373c88ac595d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
CB:55356 removed static inline declarations from get_log_level(). This
commit puts them back. It also changes the method of accessing static
symbols in tests/console/routing-test to source file inclusion like
in CB:46458 to avoid changing tested source file.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iaa5dcbccb327f819374967be51ef642b1fb25e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55473
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the ThinkPad W541 based on Peter Lemenkov's initial W541
port. Compiled and tested with SeaBIOS and Tianocore booting into Arch
Linux 5.10.32-lts. The Haswell mrc.bin blob is required.
Tested working:
- SATA SSD
- SATA DVD drive
- M.2 SATA
- All USB ports
- SD card reader
- Speakers/headphone jack
- Keyboard/touchpad
- libgfxinit
- VGA
- mini DisplayPort (Thunderbolt untested)
- eDP laptop screen
- NVIDIA GPU in Linux
- Camera/Mic
- Smartcard reader
- Internal flashing when IFD is unlocked
- ThinkPad basic dock (VGA, USB, Ethernet)
- CMOS options
- WLAN
- Bluetooth
- Ethernet
- Using me_cleaner
- All DDR3 slots
Not working:
- Keyboard backlight
- First boot can take up to 20s (MRC.bin is slow)
Untested:
- Thunderbolt
- Internal flashing when IFD is locked
- Other ThinkPad docks (DisplayPort, DVI, Audio)
- ExpressCard slot
- Battery thresholds
- WWAN card
- Fingerprint reader
- USB Debug console
Signed-off-by: Justin Wu <amersel@runbox.me>
Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52659
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix compilation on x86_64 by using compatible types.
The MRC blob isn't supported yet as there's no x86_32 wrapper.
Tested on HP8200:
* Still boots on x86_32.
* Boots to payload in x86_64
Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In x86_64 code every function call consumes 32byte of stack with
no stack local variables being used. That limits the function call depth
in SMM to 32 or less.
Double the stack size to prevent overwriting the stack canary as seen
on HP8200 and x86_64 enabled.
Change-Id: Iee202ba2ae609a474d0eb3b06f49690f33f4eda8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This fixes a hard to debug hang that could occur in any stage, but in
the end it follows simple rules and is easy to fix.
In long mode the 32bit displacement addressing used on 'mov' and 'lea'
instructions is sign-extended. Those instructions can be found using
readelf on the stage and searching for relocation type R_X86_64_32S.
The sign extension is no issue when either running in protected mode or
the code module and thus the address is below 2GiB. If the address is
greater than 2GiB, as usually the case for code in TSEG, the higher
address bits [64:32] are all set to 1 and the effective address is
pointing to memory not paged. Accessing this memory will cause a page
fault, which isn't handled either.
To prevent such problems
- disable R_AMD64_32S relocations in rmodtool
- add comment explaining why it's not allowed
- use the pseudo op movabs, which doesn't use 32bit displacement addressing
- Print a useful error message if such a reloc is present in the code
Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge.
Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is most likely an oversight. Given that the coreboot project as a
whole is licensed as GPLv2, add a GPL-2.0-only SPDX license identifier.
Change-Id: I1acaf901e1426bd6747f8a772a498a0005b457fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
After ChromeOS NVS was moved to a separate allocation and the use
of multiple OperationRegions, maintaining the fixed offsets is not
necessary.
Use actual structure size for OperationRegions, but align the
allocations to 8 bytes or sizeof(uint64_t).
Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's helpful to know if it's the start or end of a step.
BUG=b:179092979
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I550e2535615ff7e92c7c8a68c8b149f0a3476d1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The system will hang when resuming from S3 if the SSD reset gpio is not
reset early enough.
Change GPP_A11 in baseboard to PLTRST to avoid an S3 resume hang.
BUG=b:174776411
BRANCH=none
TEST=none
Change-Id: Ia78d813cb6bc689b07e8d8ead1ade6e77f925ce1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Part of the soc/amd/stoneyridge code already uses the FCH_IOAPIC_ID and
GNB_IOAPIC_ID defines. Use those defines in the remaining location to
make sure that the IOAPIC IDs are always consistent between the hardware
register, the MADT and the IVRS ACPI tables.
TEST=Timeless build of amd/gardenia results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I410a6560de66889b153c8a66b8dc5474ac114ba7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Now that device NVS is no longer used as such, stop using it to store
ACPI device settings consumed by the SSDT generator. Instead, provide
the get_acpi_device_state() function to allow saving ACPI device BARs
and activation state from other compilation units. Also, introduce an
enum and a struct to ease handling device state.
Tested on out-of-tree Compal LA-A992P, SerialIO SSDT does not change.
Change-Id: I9e70bf71e808651cb504399dcee489a4d1a70e67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52521
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The same functionality can be provided through a runtime-generated SSDT.
The remaining parts of device NVS are removed in a follow-up.
Since the SSDTs are only loaded after the DSDT (if loaded at all), using
SSDT-provided objects outside method bodies is not possible: the objects
are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing
to this, the operation regions used by the _PS0 and _PS3 methods need to
be moved into the SSDT, as they depend on the SSDT-provided BAR1 values.
Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with
no errors and contains expected values. Linux does not complain either.
Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use the same code from Lynx Point on Broadwell, and adjust as needed.
Also add a config file to ensure the code gets build-tested.
Tested on out-of-tree Compal LA-A992P (Haswell ULT), UART 0 works.
Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In ACPI mode the device cannot be enumerated and thus the payload and
bootloader doesn't know about the active resources.
An ACPI aware OS can use the _CRS to determine the active MMIO window.
Mark the BAR0 as reserved if the device is in ACPI mode to make sure the
BAR is reserved in e820 tables.
Change-Id: I6079b1eb7b0c87c752515340aac8776244b30ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Many more asus boards using Panther Point PCH other than Z77 can be
added as variants of this series.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I3e0b5734658912a69ccde94d530399059502c4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Mainboard information can be found in the included documentation.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic56ac0e5f93a6e818ef0666e41996718471b1cf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set register "generic.stop_delay_ms" to 150 to reduce power resume time.
BUG=b:185308246
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idd90191ee7ecbbc544121dc0b93101bea64f0e5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54275
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD support to elemi for MT40A512M16TB-062E:R
BUG=b:190020997
TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-bootimage
Change-Id: I548ea2ec01dd0a43442a691cf870c2bc1b58bc74
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This is the same settings as voxel.
BUG=None
TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage
Verify that the image-trondo.bin is generated successfully.
Change-Id: I04df68ce1683fa32195df1a93f5bde2e3efe6090
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Create the gimble variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:190334274
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GIMBLE
Change-Id: If425571d95b3b20910f890428fb5726ebad2fdf4
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55300
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `location` member of `struct boot_state_callback` is conditionally
guarded depending on `CONFIG(DEBUG_BOOT_STATE)` using preprocessor. It
is probably intended to save some space when the `location` strings do
not get printed. However, directly using the `location` member without
any guards will cause a compile-time error. Plus, preprocessor-guarded
code gets nasty really quickly.
In order to minimise preprocessor usage, introduce the `bscb_location`
inline helper function, which transforms the compile-time error into a
link-time error. It is then possible to substitute preprocessor guards
with an ordinary C `if` statement.
Change-Id: I40b7f29f96ea96a5977b55760f0fcebf3a0df733
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Create the scout variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:187080143
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_SCOUT
Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I3be9d2d30821c2c9132ed94c9faf1f33b62bbc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Regenerate SPD for MT53E1G32D2NP-046 WT:B with correct value of ranks.
BUG=b:190692797
TEST=Build and boot to OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Icee095c7114f1d6dd960f2134db3816b367bf987
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We are not currently tracking how long it takes to load verstage. The
enum values already exist, they just weren't used.
BUG=b:179092979
TEST=Dump timestamps
501:starting to load verstage 2,280,656 (1)
502:finished loading verstage 2,340,845 (60,189)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2cde58cb8aa796829a4e054e6925e2394973484b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable generation of DMI Type 17 data on Cezanne.
BUG=b:184124605
TEST="dmidecode --type 17" in OS on Majolica
Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move dmi.c code to common/fsp to be shared among different SOCs.
BUG=b:184124605
Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
if VBOOT_STARTS_BEFORE_BOOTBLOCK is set, call boot_with_psp_timestamp to
migrate PSP timestamps into x86 timestamp table.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I4d51802145263145d40908889de29147af54f50f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The SKU ID for Cherry is retrieved via CBI interface.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Icefa016c2e5f68bd194f76d2252856835c65b8e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
volet don't support usb4, remove it to prevent USBC(P0) issue.
BUG=b:189740531
TEST=build and verify USB(P0) disaply out normal
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia78c7cee76ec2e3a5334ad8805a0d45616aade93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55344
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.
[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Order of bits in bitfields is implementation-defined. This makes them
non-portable, especially across systems using different endianness.
This change removes bitfields and uses masking and shifting instead.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: Ief7d87ddb25c9baa931f27dbd54a4ca730b6ece7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Restructuring opregion VBT related code to make it more generalize
for future revision of opregion spec.
Moved logic to locate VBT from different region (CBMEM, PCI option
ROM or VBIOS) into separate function.
Created a new function to check if extended VBT region is required.
This will be helpful in the subsequent changes to determine if
extended VBT region is needed and handle memory allocation
accordingly.
BUG=None
BRANCH=None
TEST=check the address of extended VBT region and address is coming
correctly.
Change-Id: I479d57cd326567192a3cd1969f8125ffe1934399
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On Linux, in order to set wake alarms >24 hours, the RTC Date Alarm
field must be set to a valid non-zero value. If not, there are two
consequences:
1. Alarms >24 hours don't work
2. The kernel will refuse to enter suspend because it can't resume as
expected to service the alarm.
Since the RTC Date Alarm and RTC AltCentury fields are supported on
Stoneyridge, set them.
This is a mirror of commit 041fcf5902
("soc/amd/picasso/acpi: Set missing RTC offsets") for picasso.
BUG=b:187516317
TEST=On a Chrome OS 'grunt' device, run
`time powerd_dbus_suspend --suspend_for_sec=172800`
and verify the system suspended and woke up after 48 hours
BRANCH=grunt
Signed-off-by: Anand K Mistry <amistry@google.com>
Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add EC_HOST_EVENT_HANG_DETECT to S3/S5/S0ix wake mask. This event is
sent when the EC detects the AP didn't fully enter a sleep state.
BUG=b:186571086
TEST=Trigger hang detect while AP is in S0ix, AP wakes from S0ix
Change-Id: I09ccf609fc453c19b4fb1ddaa5a0c86d7a85aad1
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add GPIO pin details specific to SC7280 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if
not updated.
coreboot logs appear as below with this patch:
On First boot after flashing the image:
coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
CPU: Genuine Intel(R) 0000
CPU: ID 906a0, Alderlake Platform, ucode: 0000001a
..
FMAP: Found "FLASH" version 1.1 at 0x1804000.
FMAP: base = 0x0 size = 0x2000000 #areas = 32
FMAP: area SI_DESC found @ 0 (4096 bytes)
SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Erasing flash addr 0 + 4 KiB
Update of PMC Descriptor successful, trigger GLOBAL RESET
Next boot after GLOBAL RESET:
coreboot-coreboot-unknown.9999.4589c0f Wed Jun 9 18:23:43 UTC 2021 bootblock starting (log level: 8)...
..
FMAP: area SI_DESC found @ 0 (4096 bytes)
SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
Update of PMC Descriptor is not required!
VBOOT: Loading verstage.
..
CBFS: Found 'fallback/verstage' @0x2264c0 size 0x16b08 in mcache @0xfef84d38
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6d9a2ce0f0b3e386eefa1962ce706b58f31a8576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since common CPU ID between ADL-P and ADL-M CPU IDs, the patch renames all
ADL-P and ADL-M Silicon CPUID macros and defines generic name
"Alderlake Platform" as macro value. Also, this will avoid log ADL-M for
ADL-P CPU and vice-versa. Although currently name field of "cpu_table"
points to only "Alderlake Platform, but it is retained asa placeholder in
future difference platforms.
Please refer EDS doc# 619501 for more details.
The macros are renamed as below:
CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0
CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_A1
CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_A2
TEST=Verify boot on Brya. After change, relevent coreboot logs appear as
below:
CPU: ID 906a1, Alderlake Platform, ucode: 00000119
CPU: AES supported, TXT supported, VT supported
MCH: device id 4601 (rev 03) is Alderlake-P
PCH: device id 5181 (rev 00) is Alderlake-P SKU
IGD: device id 46b0 (rev 04) is Alderlake P GT2
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Further add initial Silicon UPD settings for FuSa
(Functional Safety). Disable all by default, due to FSP binary
enable all by default.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.
Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Further add initial Silicon UPD settings for thermal and power
management stuffs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit adds support for the Chrome OS Zero-Touch Enrollment related
spaces. For TPM 2.0 devices which don't use Cr50, coreboot will define
the RMA+SN Bits, Board ID, and RMA Bytes counter spaces.
The RMA+SN Bits space is 16 bytes initialized to all 0xFFs.
The Board ID space is 12 bytes initialized to all 0xFFs.
The RMA Bytes counter space is 8 bytes intialized to 0.
BUG=b:184676425
BRANCH=None
TEST=Build and flash lalala, verify that the ZTE spaces are created
successfully by undefining the firmware antirollback space in the TPM
such that the TPM undergoes factory initialization in coreboot. Reboot
the DUT. Boot to CrOS and run `tpm_manager_client list_spaces` and
verify that the ZTE spaces are listed. Run `tpm_manager_client
read_space` with the various indices and verify that the sizes and
initial values of the spaces are correct.
TEST=Attempt to undefine the ZTE spaces and verify that it fails due to
the unsatisfiable policy.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55242
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for the TPM2_NV_SetBits command to the TLCL.
This command is used to set bits in an NV index that was created as a
bit field. Any number of bits from 0 to 64 may be set. The contents of
bits are ORed with the current contents of the NV index.
The following is an excerpt from lalala undergoing TPM factory
initialization which exercises this function in a child commit:
```
antirollback_read_space_firmware():566: TPM: Not initialized yet.
factory_initialize_tpm():530: TPM: factory initialization
tlcl_self_test_full: response is 0
tlcl_force_clear: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: kernel space already exists
tlcl_write: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: RO MRC Hash space already exists
tlcl_write: response is 0
tlcl_define_space: response is 14c
define_space():197: define_space: FWMP space already exists
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
tlcl_define_space: response is 0
tlcl_set_bits: response is 0
tlcl_define_space: response is 0
tlcl_write: response is 0
factory_initialize_tpm():553: TPM: factory initialization successful
```
BUG=b:184676425
BRANCH=None
TEST=With other changes, create a NVMEM space in a TPM 2.0 TPM with the
bits attribute. Issue the command and verify that the TPM command
succeeds.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55241
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently variant_has_fpmcu() is called very early in bootblock, before
eSPI is initialized. When checking CBI for its presence, that causes
an error and nothing else can be read from CBI in bootblock.
Moving it slightly later in bootblock doesn't hurt anything from a
timing standpoint, and allows CBI to be read.
BUG=None
TEST=See CBI get read and the FPMCU field read correctly.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch assings 2 to EC_EFS_BOOT_MODE_TRUSTED_RO to make coreboot
set VB2_CONTEXT_EC_TRUSTED when the GSC reports TRUSTED_RO.
Old GSC doesn't use 2. So, the new BIOS won't mistakenly set
VB2_CONTEXT_EC_TRUSTED.
BUG=b:180927027, b:187871195
BRANCH=none
TEST=build
Change-Id: I11a09d0035a4bd59f80018c647ca17e3318be81e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55373
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The loads of the FSPM and FSPS binaries are not insignificant amounts of
time, and without these timestamps, it's not clear what's going on in
those time blocks. For FSPM, the timestamps can run together to make it
look like that time is still part of the romstage init time.
Example:
6:end of verified boot 387,390 (5,402)
13:starting to load romstage 401,931 (14,541)
14:finished loading romstage 420,560 (18,629)
970:loading FSP-M 450,698 (30,138)
15:starting LZMA decompress (ignore for x86) 464,173 (13,475)
16:finished LZMA decompress (ignore for x86) 517,860 (53,687)
...
9:finished loading ramstage 737,191 (18,377)
10:start of ramstage 757,584 (20,393)
30:device enumeration 790,382 (32,798)
971:loading FSP-S 840,186 (49,804)
15:starting LZMA decompress (ignore for x86) 853,834 (13,648)
16:finished LZMA decompress (ignore for x86) 888,830 (34,996)
BUG=b:188981986
TEST=Build & Boot guybrush, look at timestamps.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Function is needed with PARALLEL_MP and excluding guard will
be added to the source file.
The incompatibilities with X2APIC_SUPPORT have been fixed
so the exclusion is removed here too.
Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
They are not __always_inline and specially enable_lapic()
will become more complex to support X2APIC state changes.
Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select 'HAVE_INTEL_FSP_REPO' so that the FSP binary from the FSP
repository is used by default. Also, use the FSP headers from the FSP
repository instead.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I0c1bcb07ed0f73e1d5ada5f6f16b84816c4ef3d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55229
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from Linux file `include/vdso/limits.h` with some adjustments.
Change-Id: I427d88b1d630fdc3c3e9c1b0e475adbf448d801a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55319
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `pnp_unset_and_set_config` function was only available when building
with `ENV_PNP_SIMPLE_DEVICE` set. Add the complementary definition using
device pointers, for the sake of completeness.
Change-Id: I2a21e635f41f3f786057500fa96a2b3116e30d76
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS
value within src/soc/intel/*/Kconfig.
Move the definition there for Tiger Lake and remove from the mainboard
Kconfig files.
Signed-off-by: Andy Pont <andy.pont@sdcsystems.com>
Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifd3e6a264131437c67d17ec80f37f5e8d0a03a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ptrdiff_t, wchar_t, and wint_t are all integer types built-in to the C
language (as opposed to being library-only types defined in a header).
In the past we had to define these typedefs ourselves because of romcc,
but now that it's gone we should use the GCC-provided macros to select
the types the compiler expects.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I0874eddf780b6e41ce773ad8b4faa595e4bbd8a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add Realtek audio codec ALC5682I and speaker L/R the same way as in waddledee
BUG=b:188446060
BRANCH=dedede
TEST=Boot to check ALC5682I and speaker L/R are functional
Change-Id: I8173ffbfb1a8f18978a5e35c69972d4a6d8cb04a
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54529
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select `HAVE_INTEL_FSP_REPO` so that the FSP binary from the FSP
repository is used by default. Also, use the FSP headers from the FSP
repository and adjust some UPD names so that coreboot is able to use
them.
Also added new config FSP_TYPE_CLIENT/IOT. Respective mainboard Kconfigs
to select right FSP_TYPE when using FSP repository.
BUG=b:175957775
BRANCH=none
Change-Id: I5e694b91be7734dd98665051a6a3d9eccab7dac7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Provide functions to allow for variants to override only a few pads from
the baseboard table.
BUG=b:189362981
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3ae6c11ca8614d523f3402f1c1abb7c82124e473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add lpddr4.c utility file with lpddr4_speed_mhz_to_reported_mts.
Fill in lpddr4_speeds using JDEC 209-4C table 210.
LPDDR4 SPD decoding utilities are not included since there isn't
a present need.
BUG=b:184124605
TEST=Build and run on guybrush
Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
is_devfn_enabled() function helps to check if a device
is enabled based on given device function number. This
function internally called is_dev_enabled() to check
device state.
Change-Id: I6aeba0da05b13b70155a991f69a6abf7eb48a78c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Derived from Broadwell and adapted to follow what soc/intel does. Note
that SERIALIO_UART_CONSOLE is meant to be selected from the mainboards
which expose a SerialIO UART. UART_FOR_CONSOLE also needs to be set in
mainboard Kconfig accordingly.
It is possible that some of the UART configuration steps in bootblock
are unnecessary. However, some of the steps turn off power management
features and others are undocumented: omitting them could cause weird
issues.
Finally, add a config file to ensure the code gets build-tested.
Tested on out-of-tree Compal LA-A992P, SerialIO UART 0 can be used to
receive coreboot and SeaBIOS logs.
Change-Id: Ifb3460dd50ed03421a38f03c80f91ae9fd604022
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52489
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add low_power_probe config to camera devices so that driver skips initial
probe during kernel boot and hence prevents privacy LED blink.
BUG=b:178060668
TEST=Build and boot to OS on Drawcia. Ensure no blink on privacy LED.
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I00dfe2ce0b57ff3eaa258204f49e79a280754dcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52190
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allows compile-time optimisation on platforms that do not wish
to enable runtime checking of X2APIC.
Legacy lapic_cpu_init() is incompatible so there is dependency
on PARALLEL_MP. Also stop_this_cpu() is incompatible, so there
is dependency on !AP_IN_SIPI_WAIT.
Since the code actually lacks enablement of X2APIC (apparently
assuming the blob has done it) and the other small flaws pointed
out in earlier reviews, X2APIC_RUNTIME is not selected per
default on any platform yet.
Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
For the purpose of LAPIC IPI messaging it is not required to
evaluate if IOAPIC is enabled. The necessary enable_lapic()
will still be called as part of setup_lapic() within cpu init.
Change-Id: I8b6a34e39f755452f0af63ae0ced7279747c28fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All functions in ec_skuid.c except google_chromeec_get_board_sku()
are for SMBIOS platforms. Move these functions to a new file to allow
non-SMBIOS platforms to use google_chromeec_get_board_sku() without
having to declare MAINBOARD_SMBIOS_MANUFACTURER.
BUG=none
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I8916223f5f04afe4761be4ad3313e900efae90d4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add function to force memory training and add VPD variable to operate
this function.
Tested=On OCP Delta Lake, memory training can be forced via VPD.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I53a923b51b36f9f5db491ef142109f58f9a4611d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Correct GPIO settings as below reason:
1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF.
2. GPP_B7 should configure as WWAN SAR detect ODL, but set to GPI
BUG=b:188956448
BRANCH=dedede
TEST=The LTE DPR pin can be pulled down normally when someone
get close to the P-sensor antenna.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Idc214fcd9c4631368a71f4d59bb644df739982ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
