Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus
KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC
bridge register 0x78 (particularly the 0x7b byte) to get to ramstage:
Assume that there's something about this register that adjusting it the
way we do for K8 is something that can/should be universally avoided on
all Fam10h systems with these chipsets.
Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10984
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Update the write protect GPIO reported in ACPI to be 71 which
is GPP_C23. Also update the controller id to INT344B:00 which
will point at the sunrisepoint device in /sys/class/gpio.
BUG=chrome-os-partner:42560
BRANCH=none
TEST=verify crossystem output with and without WP enabled
Change-Id: I625859bd8ac371a5c0cae18697dccf216c26a8b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fc5cb6b72dacd6aefe69fe8204f4e0d209ed8a4
Original-Change-Id: I04892e75f9bfe739c44eb40e7c6a969c33e157ca
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286842
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11035
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The FSP memory info hob does not return this data so we need
to supply it from the SPD included with the mainboard.
BUG=chrome-os-partner:42975, chrome-os-partner:42561
BRANCH=none
TEST=execute "mosys memory spd print all" on glados
Change-Id: Idfb71d36d1f8163d0daceb68675b10194db7cde7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7feece45900e5166864927047ad3ab7b997f8258
Original-Change-Id: Id2bc544ac5faf53f0f676fe132fea1db5640a401
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286877
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11034
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The write protect gpio is not added to the gpio map
so the structure is not valid for vboot to consume.
BUG=chrome-os-partner:42560
BRANCH=none
TEST=build and boot on glados, check basic crossytem output
CQ-DEPEND=CL:286911
Change-Id: I228d75049b919449072e395699c822203a08f1c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d15438c4bf56d92189f2f501a62b55b5d00ba461
Original-Change-Id: I3290c4b96e1cc675c618a983915b778f11175020
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286930
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11031
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No devices are connected to i2c4 bus on
both strago and cyan board.
Hence disabling the ALS platform data.
This will fix the i2c4 timeout issue and
also help in boot time optimization.
Removed unused macros.
BUG=None
BRANCH=chrome-os-partner:41934
TEST=After booting to kernel, i2c4 timeout
error message should not appear in dmesg.
Change-Id: Ib7ab4c95b0830a8d4e53c6c0ee919649ad1ed354
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c52b64037b46016fe01f1d55c4c58f7684eb778
Original-Change-Id: Ia7acdcef67a2f2837866f56aa0426a02ee05db46
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283608
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In BCRD2, RTEK audio codec is connected to I2C4.
Create a RTEK device entry on I2C4 to enable Audio
on BCRD2. In BCRD1, RTEK device is connected to I2C2.
Having two devices with same HID breaks the Audio
on BCRD2 even if I2C2.RTEK._STA returns 0. The Audio
codec driver in kernel is hard coded to use first
instance of the device (:00). When two devices are present
with same HID, first device gets an instance number :00
even though _STA returns 0. Second device which is on I2C4
and POR for BCRD2 assigned with instance number :01. The
device with :01 is not getting enabled since the Audio codec
driver supports only :00. This need a proper fix in kernel
which is in the pipeline. Audio on non BCRD2 platforms on
Strago build would be disabled since RTEK device is not present
on I2C2.
BRANCH=None
BUG=None
TEST=Build and boot the system
Change-Id: Ia97d011c951275e6179c8b79a22c496b8169356b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d71a41ee703e6f60299b9e31a408af2ca06d8e24
Original-Change-Id: I4b032e930e46da77474f8f5969e95f9560b3e905
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285193
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: http://review.coreboot.org/11003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I3cf6a579f4e62a59828e81aa63c3a1a020a15ea6
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10906
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=chrome-os-partner:42881
BRANCH=None
TEST=Using ctrl-d in recovery mode to switch to dev mode works.
Change-Id: Iefbd11d435c4beb570875d4835a085b194d1d1e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: be172409792a224855b1d31621f23d1969d319b9
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Change-Id: Icf57dfc4cc258aa2cba341f40d285f8c843aace5
Original-Reviewed-on: https://chromium-review.googlesource.com/286612
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11013
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GPIO mapping was incorrect for wpsw_cur.
The GPIOs for East community were in two ranges:
0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and
12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]
The discontinuity was not accounted for, hence the error.
The original offset was 0x16 whereas it should be 0x13
BUG=chrome-os-partner:42798
BRANCH=None
TEST=Run crossystem and test wpsw_cur entry. If screw is present,
it should be 1 and if not present, it should be 0
Change-Id: I2faea1fe1415c9d4cb23444d03c7c9d47c87e8e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 30ac96f606a5618e9ef12bac3f50fac433141acd
Original-Change-Id: I166a7c3e15a990b507ae3c13e15ab56bee7fb917
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286534
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/11010
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Document the lid open state and separate the routines with a single
blank line.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: I244f20c03bc7530ad8d140fba41dd97c12c079e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 57313253fdef3f2d3f0e16b8ab8aa91202d45b16
Original-Change-Id: I7b3bd9cf16e915d214eb2de0017a8d91a934b112
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286267
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11009
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove the address from the copyright notices.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: Ibe8196841d9e76c9ee3a3dbae802ecc63dc7904c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cc12d2658324a375d02748098f0a2f4b5d1b5615
Original-Change-Id: I81a71e4ad9b8a66ad0e9a93cbeb512d90eb35906
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286266
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11008
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: build bot (Jenkins)
Charger performance states table defines charger current limit for each
p state. Modify charger current control values for SANYO battery used
in Cyan.
BUG=None
BRANCH=None
TEST=System is charging battery, in shell window, issue command
"echo 0 > /sys/class/thermal/cooling_device4/cur_state",
"echo 1 > /sys/class/thermal/cooling_device4/cur_state",
"echo 2 > /sys/class/thermal/cooling_device4/cur_state",
"echo 3 > /sys/class/thermal/cooling_device4/cur_state", or
"echo 4 > /sys/class/thermal/cooling_device4/cur_state", will see EC
console show different charging current value.
Change-Id: Ie9bc78822a73de6bed338bfbcc5e9045653689dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3a6162151d1f9c756a13d2afc17f6b9c18608efc
Original-Change-Id: I71e8247d057e4728eedcd5e8a275b64428290d09
Original-Signed-off-by: li feng <li1.feng@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285605
Original-Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: http://review.coreboot.org/11004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch updates the Serial IO modes for UART2 to PCI mode
in devicetree for glados board.
Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit
legacy UART will stop working after devicetree change.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for glados and tested LPSS logs on glados.
CQ-DEPEND=CL:284881 CL:284882 CL:284883
Change-Id: I433979c852c80848c006ef089b43d75a17e761c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189
Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284826
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11002
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch updates the Serial IO modes for UART 1 and 2
in devicetree for kunimitsu boards.
UART1 are disabled and
UART2 is in PCI mode.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu and tested LPSS logs on Kunimitsu.
Change-Id: I5a46ab9e0b792478ee2e0845aeab1443423a2fac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 38c7b963a9d679ee5106c5343e1173d0b5056627
Original-Change-Id: I39cbb6bb0991e5f9b3365adaf6b24818d112cd1a
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284825
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11001
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch updates the Serial IO modes for UART 1 and 2
in devicetree for sklrvp boards.
UART1 is disabled and
UART2 is in PCI mode.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp and tested LPSS logs on RVP3.
Change-Id: I59a657d6a3744040ec6be290ba966672e0e5f17e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a20a70801d66abd87d4214e1ef187b86eed99da
Original-Change-Id: I381374272e1824ca8887ea5c5662215dde2c0a56
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284824
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.
BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2
Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Disabling the wwan gpio line
since wwan is not used.
BRANCH=none
BUG=none
TEST=wwan should not connect to network on cyan/strago.
Change-Id: I9d2e5d5b185a4622218e894d3b092afe15e09289
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a20c602b3bb768baa38b17e21cb4e5b0d9249ef
Original-Change-Id: Ib8d5fd15a172ef898ce675a85c2ea3e5f5c79144
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285304
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10992
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
BUG=chrome-os-partner:40526
BRANCH=None
TEST=Verify that system boots when used with coreboot and EC
versions that also have Software Sync enabled.
Change-Id: I6ed562fa51d83ddf16fc74d35db7c0004f57c79e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 090a66c50fac21808c4721a32b1728cc904f1b00
Original-Change-Id: Ia4d87d9a177c579567c03ae113889a277ffecee0
Original-Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283573
Original-Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
Original-Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/10985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BOOT_MEDIA_SPI_BUS is int, not hex.
Change-Id: I5cbcc3889a025caab921208037c8a61d224078a7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10973
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add initial files for the cyan board.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build
without the FspUpdVpd.h file.
BRANCH=none
BUG=None
Test=Build and run on cyan
Change-Id: I935839be033c25e197e78fbee306104b4162a99a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10182
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Initial files to support the Kunimitsu board.
Matches chromium tree at 927026db
This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on kunimitsu
Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Initial files to support the Intel Skylake RVP3
Matches chromium tree at 927026db
This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run on sklrvp
Change-Id: I5e7fff8f62a737e627e25c1e03e343d6167041ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the initial files to support the Intel RVP for Braswell.
Matches chromium tree at 927026db
This board uses the Braswell FSP 1.1 image and does not build without
the FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on strago
Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10052
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
So odmdata has the correct UART port of 0
BUG=chrome-os-partner:40741
BRANCH=None
TEST=build Foster ok; and check scratch20 register
Change-Id: I2c203317e6305214b74430780f2fe7b15652873a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0a0a99ac9c7db267129e4bc3478f9bb1ece08507
Original-Change-Id: I7be10d5deb5118f1cf3e339afca94893610437f2
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280291
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10955
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
So odmdata has the correct UART port of 0.
BUG=chrome-os-partner:40741
BRANCH=None
TEST=build Smaug ok; and check scratch20 register
Change-Id: I59154daa5b5627d3b594ff9505e4f02de0d4d7aa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 814cd164ab9ed9bf2e072f3728e89ea8d7cf0343
Original-Change-Id: I2252b728775cf2550d666ead0085c0ab3b72e40b
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277024
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10954
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add sdram_configs.c to both romstage and ramstage.
BUG=chrome-os-partner:40741
BRANCH=None
TEST=Build ok on Foster
Signed-off-by: Yen Lin <yelin@nvidi.com>
Change-Id: Ib270c837ebe355c8d16072186c2b27d1c469fd48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 73bc1abf2821176c21179880774887eec7c858b1
Original-Change-Id: Ia80a57a81e44542ee3d5437866071d50c8c5b8cb
Original-Reviewed-on: https://chromium-review.googlesource.com/280290
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
Reviewed-on: http://review.coreboot.org/10951
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
get_sdram_config() (in sdram_configs.c) will be needed in ramstage.
BUG=chrome-os-partner:40741
BRANCH=None
TEST=Build ok on Smaug
Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed
Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277373
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10950
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is a result of the Silcon Observation. On warm reset, the BIST
is 0x80000000, which causes BIST error. We skip checking this bit.
The update will be in CZ BKDG 1.05.
The code is tested on AMD/bettong.
Change-Id: I51c3f3567f758766079f7c8789f1ff072e1a7c53
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Should fix regression in HDA verb setup on nvidia mcp55 and intel sch
southbridges. The mcp55 code could not find the mainboard's verb table
because the table was not even being compiled in. The sch boards appeared
to have the same issue.
Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate
shrink, so apply it to those too.
Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078
(azalia: Shrink boilerplate)
Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10826
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It never made sense to have bootblock_* in init, but
pirq_routing.c in boot, and some ld scripts on the main
level while others live in subdirectories.
This patch flattens the directory hierarchy and makes
x86 more similar to the other architectures.
Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10901
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
LDO2 regulator is used as an always-on reference for the droop alert
circuit. Set output voltage to match kernel settings.
CQ-DEPEND=CL:284649
BUG=chrome-os-partner:42305
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c
Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284879
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10900
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:42220
BRANCH=veyron
TEST=Used physical recovery button to enter dev mode on mickey
Change-Id: I78332f516b042be9c0cef6d8a59af44b670fc260
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fcd79a133dc750dffd5d23e0b84a109e7b7cb8d
Original-Change-Id: I8d8dc0c0b98bbd194095d47047c8c5199ce17769
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283546
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Danger has a physical developer mode switch, it was just never
set up. This patch defines it, sets it up in fill_lb_gpios(),
and disables VIRTUAL_DEV_SWITCH.
Note: For now at least, dev mode is a bit wonky on Danger. It's
connected to both a DIP switch and a button. The button is normally
open, pulling dev mode high (defaulting to ON). The switch's "ON"
position will pull the value low, so we invert the value in coreboot
to see the expected behavior. Dev mode is enabled by holding the
button down during boot or by setting switch 2 in the DIP bank to
the ON position.
BUG=none
BRANCH=none
TEST=toggled dev switch on Danger and saw dev screen show up (or
not) as expected
Change-Id: I9369b96b6c9b54553d969b919ed663abdc704dd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dce53f1a31919f15f6e46c4a7d1c5ce541c2b318
Original-Change-Id: I737f165d7704e2f73375099367f012b365e3e77d
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280852
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No need to repeat this in the mainboard code (even if there's only one right
now).
Change-Id: Iaa3508c27f8c38cfa343ab1d8a094ce922dec157
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/10825
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix up all the code that is using / to use >> for divisions instead.
Change-Id: I8a6deb0aa090e0df71d90a5509c911b295833cea
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10819
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This value is overwritten in the next line.
Change-Id: I622c35b8d78f6b01f2532dd8b40db15b2e888f58
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Stops Linux from complaining:
[0.097286] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0
[0.100005] ..MP-BIOS bug: 8254 timer not connected to IO-APIC
[0.100005] ...trying to set up timer (IRQ0) through the 8259A ...
[0.100005] ..... (found apic 0 pin 0) ...
[0.143507] ....... works.
Change-Id: Ic09a6940f80e3da2c1f3c0ef04fb50a4096b7943
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10642
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that we have functioning display code for all platforms,
we can just get rid of this ugly hack used on non-Chromebook
veyrons.
BUG=none
BRANCH=none
TEST=built for Brain, Rialto, Mickey, Romy
Change-Id: Ibe248c7cc74940811345c249d66992d74fe85fe5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c627b087ba9fc07b4ec4a6d55d2e0203bdd4ff5
Original-Change-Id: I946eddb4e8ce1dbaa20212a2bb417e71a31b2ba3
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282049
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This uses VOP_MODE_NONE for display init on veyron_rialto and
adds a mainboard_power_on_backlight() stub so that we can finally
get rid of SKIP_DISPLAY_INIT_HACK.
BUG=none
BRANCH=none
TEST=built for veyron_rialto
Change-Id: Ia6b420a962fe266e773c804b8e5c68da35848753
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a290c938c163759a3672c07d8ec7c0a38057b13d
Original-Change-Id: Iec2d7f03857198a4d6f7490db1e3e19c74f18c43
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282048
Reviewed-on: http://review.coreboot.org/10784
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux. Calls to PMIC
functions to enable HDMI power are moved here as well.
BUG=none
BRANCH=none
TEST=with follow-up patches, we now get a dev screen on Brain.
Change-Id: Ifd2648376c789fb29c9e2e4ab6bdb10ca439e4a2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91ec6a96edaf2042236aee0383e18715014f1013
Original-Change-Id: I0c6e9f8fc5e06f53a1a160d8ab2e32447168139e
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282046
Reviewed-on: http://review.coreboot.org/10778
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This avoids any ambiguity or breakage in case the vop_modes get
shuffled around or changed in some future patch or copy+paste job.
Brain and Rialto need some more work done so their devicetree.cb
files will be updated in follow-up patches.
BUG=none
BRANCH=none
TEST=compiled only (for danger, jerry, mickey, romy, speedy)
Change-Id: I4fd549c82c8a5c31525c4e485fa8df73f33f2049
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd88973b53949058331613c7582650fbd4ea48db
Original-Change-Id: I47da45c5fd9648544392de8d76f86af812de9093
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282610
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10776
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
EDP-related hardware modifications for v2:
- BL_EN moved from GPIO7_A3 to GPIO7_A2
- EDP_HPD added to GPIO7_B3
BUG=none
BRANCH=none
TEST=built and booted Danger v2 with EDP panel attached, saw dev
mode screen come up
Change-Id: I47383610082b371a612aced656e56f1bd1cfa098
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb939ff17cca7bbd24aabfdb3cbd444696a5a845
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id271cdcfcde6fa84c1bb707b9842bddd77a7121b
Original-Reviewed-on: https://chromium-review.googlesource.com/280855
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are all Kconfig symbols that have been removed or renamed.
USE_PRINTK_IN_CAR was removed in commit 8c4f31b3
Drop the USE_PRINTK_IN_CAR option. It's a bogus decision...
DYNAMIC_CBMEM was removed in commit e2b0affd
Remove Kconfig variable that has no effect
MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc
Remove Kconfig variable that has no effect
CACHE_ROM was removed in commit 4337020b
Remove CACHE_ROM.
SMM_MODULES was removed in commit 44cbe10f
smm: Merge configs SMM_MODULES and SMM_TSEG
INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218
soc/fsp_baytrail: Fix use of microcode-related Kconfig variables
CAR_MIGRATION was removed in commit cbf5bdfe
CBMEM: Always select CAR_MIGRATION
REQUIRES_BLOB was removed in commit 70c85eab
build system: Retire REQUIRES_BLOB
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b
uart: Redefine Kconfig options
CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit
afa7b13b - uart: Redefine Kconfig options
Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10766
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since USBDEBUG is not selected by this platform, there is no
benefit to selecting USBDEBUG_IN_ROMSTAGE in the mainboard
Kconfig. Further, using a 'select' for USBDEBUG_IN_ROMSTAGE
prevents the value from being modified by a user in menuconfig.
Change-Id: I67b71a724a8614882cff4bb43b042f0c092d11d2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/10671
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10764
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This fixes the build with CONSOLE_CBMEM_DUMP_TO_UART.
Change-Id: Ibe79239c5799a5c4a08ed195fce4d0c63d629ca4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10769
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch fixes up verified boot (vboot2) configuration of all
tegra 124 bases boards in the tree.
Change-Id: I81f2e83821cbfdbe2a55095543e7447efdde494e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10761
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Otherwise the Chrome OS build won't succeed.
Change-Id: Idf93a09f53d08b6c201f1de140f0fff35f928dcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10760
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
- Add the common/firmware subdir to the baytrail & fsp_baytrail
makefiles and remove the code it replaces.
- Update baytrail & fsp_baytrail Kconfigs to use the common code.
- Update the IFD Kconfig help and prompts for the TXE vs ME.
- Whittle away at the CBFS_SIZE defaults. All the fsp_baytrail
platforms have their own defaults.
Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10647
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Copied from speedy, with changes to mainboard.c (and speedy -> minnie renames
across the directory)
Change-Id: Ib38f0b15da8306984869e7ee7b4ddf366b0df82c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10757
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is an nvidia t210 based board.
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I8630e86a4b0e8756693f8989ce147d6d762cefe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Exynos SoC code and vboot really don't get along and things are not even
in a good shape in Chrome OS' top of tree. Disable but don't rip out the
support functions, so it could be revived.
Change-Id: I982c5a3731b527fd1f1579e9de353819da656452
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10730
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Initializing timestamps and writing the "start romstage" timestamp already
happens earlier.
One question to sort out is what to do about the migration into cbmem, but at
least this compiles again.
Change-Id: Ie8a0b7998c6c9da71f036857987f3c781385034f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: Ie3b49aa716d9711223ec71a142878e847eedfe4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10726
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Current vboot wants that function.
Change-Id: I08590739112a7fcce7a983b6d77ff500692ef7d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
A lot changed here between Chrome OS and upstream, and these changes are
needed to reflect that.
Change-Id: I7195861465388d0f6a7cb540ebf4e410e38c260a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10723
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.
Change-Id: Iecfd37e79883d826e15c474d77095fbbbb2b7cea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10705
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In Chrome OS mode, the romstage tries to interpret the various buttons on the
device, so it needs access to the accessor functions.
Change-Id: I59a4f892ca84d475d8f46c8f8c1906dae10ad32d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
vboot configuration (separate stage or not, which stage loads romstage)
depends on SoC properties (eg. amount of SRAM), not on board specifics, so
move this part of the configuration to the SoC.
Change-Id: I70b4cd1794ddf2aba7cdae94859ea1d76ae019f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
romstage requires some button accessor functions for the Chrome OS boot flow.
Change-Id: I3f90d66b103e0610931c183dd5f5679ca6f910f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10697
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds the Veyron_Shark mainboard as a clean copy of Veyron_Speedy.
- board-ID differentiation removed, see mainboard.c
- speedy -> shark rename
BRANCH=None
BUG=None
TEST=Compiled.
Change-Id: I3b743a97f152f49647eee87be8f1497377ccacb4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac2ca328adf7e0dd879f51bbeae3cc11bceebf86
Original-Change-Id: I8a7cc9acb199ecf23b388c66f6885931ea3ec219
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/276490
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/10699
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Not all devices have a lid switch, so we need to state this
somehow. Since the alternative would be to extend get_lid_switch()'s
semantics to become a tri-state (open, closed, N/A), do this
through Kconfig.
BRANCH=none
BUG=chromium:446945
TEST=none
Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273850
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The function was used locally and in ramstage to set some
coreboot tables. It's also needed in romstage to deal with
"lid closed" behaviour.
BRANCH=none
BUG=chromium:446945
TEST=none
Change-Id: I8ad7061328c45803699321aa9f5edb0ed2288a8d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 78281a104fb9d79696a6ceb2a9a89a391146a424
Original-Change-Id: I56314b9dc9062dd61671982e7ec0ff15d7eb1bae
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273609
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This re-factors SDMMC power on/off to make corrections and take
differences between board versions into account. To avoid similar-
but-different case switch statements in romstage.c and mainboard.c,
power on/off functions for SDMMC are split into their own .c file.
BUG=none
BRANCH=none
TEST=built and booted of micro-SD card on Danger v2
Change-Id: Ib3069c35ceff1ff98b49579a6298681c1390beee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eecfee4a5dd39073b5f966a25991a594b3c4b519
Original-Change-Id: Id86ae7f40687e843ffc4e7769309d4678ad54f49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280853
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a configure_hdmi() function that drives the HDMI
enable output high and configures the iomux.
We'll add EDP/HDMI auto-detection in an upcoming patch.
BUG=none
BRANCH=none
TEST=set vop_mode to 1 in Danger's devicetree.cb and saw
dev mode screen output to HDMI display.
Change-Id: I2a208059fee74d436b5a5bedbc677bc59525f935
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 721f326319f727afcf73a0c21d20d26cb463ad71
Original-Change-Id: I139d39749963d4121aaeec0c3da37d825ffa94ac
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/280849
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested with interrupting AGP card in AGR slot.
PCI slots tested with 3-function OHCI/EHCI USB 2.0 card,
covering the INTA-INTC lines in each.
Change-Id: I0f8aeba90890a76a7cf9cbee9be7bcf919d1e39a
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10644
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ASUS KFSN4-DRE has full native VGA support, enable support for the
VGA device by default in the Kconfig file.
Change-Id: I09fc8845a30f26ca49f3547812f9784621ff4b5e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10673
Tested-by: build bot (Jenkins)
Reviewed-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Add the System Board Hardware ID to fix the warning:
dsdt.aml 88: Device (MB) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
Change-Id: Ie97b1e6792c8d4c8db2500cef6a79881b7ff94c8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10669
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the System Board Hardware ID to fix the warning:
dsdt.aml 88: Device (MB) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
Change-Id: I063580142ae8053fdc05e165c01e86b8b7cd5ca6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10668
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because of a misunderstanding of how Kconfig files are parsed, the
OVERRIDE_MRC_CACHE_LOC symbol was added to make sure that the value
was correctly set. This is not needed unless for some reason the
Kconfig parser is suddenly rewritten to parse everything differently.
At some point, the value in the FSP's Kconfig file was updated to
OVERRIDE_CACHE_CACHE_LOC, while the entries in the mainboard
Kconfig files were not updated. This resulted in the default values
not getting set correctly by default on the FSP Bay Trail boards.
This removes the whole bunch of incorrect and unnecessary symbols and
just sets the default for the MRC cache location directly.
Change-Id: I1cec758576866b7e0677272b8309bfde8d4a1ee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10611
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Where vboot verification can start, and how the code flow looks like is more a
property of the SoC (and its properties, like amount of SRAM) rather than the
board.
Change-Id: I610153ea4ceddc226d8cc3e17a515e41fc0479cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10662
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
vboot requires it.
Change-Id: Iae2310c9b9c311c3f64b8417295685261ba404b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: Icf83d5e2a3daea385af3572e9eac6b2431652c28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10640
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CAR_MIGRATION was removed in commit:
cbf5bdfe - CBMEM: Always select CAR_MIGRATION
ALT_CBFS_LOAD_PAYLOAD was removed in commit:
cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD
MARK_GRAPHICS_MEM_WRCOMB was removed in commit:
30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB.
EXTERNAL_MRC_BLOB was removed in commit:
0aede118 - Drop unused EXTERNAL_MRC_BLOB
CACHE_ROM is only in Google's codebase.
LID_SWITCH is only in Google's codebase.
DEFAULT_POST_DEVICE_LPC is only in Sage's codebase.
ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used.
HUDSON_NOT_LEGACY_FREE never existed as far as I can tell.
MAINBOARD_DO_EDID never existed as far as I can tell.
Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10616
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.
Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I0796b6e7adad0151c5aa6271d62a2cf4abeedb1e
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC.
This is the start of creating a common interface for all of them.
This also allows us to reduce the chipset dependencies for CBFS_SIZE.
Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10613
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is only needed on boards that still provide old style PIRQ
tables.
Change-Id: Ie299de2937e5b91b7b3e1d1110e40be23c6d9f52
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10508
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The CBFS size is really mainboard specific, since it really depends on
size of the chip on the mainboard, so it makes sense to have it in
the mainboard menu along with the ROM-chip size.
- Move the CBFS_SIZE definition up in src/kconfig
- Move the Mainboard Menu markers out of src/mainboard/kconfig into
src/Kconfig so CBFS_SIZE can live in the mainboard menu.
- Add a long list setting default values to do what the chipset
directories were previously defaulting the values to. This will
be trimmed down in a following patch that creates a common set of
IFD routines. (Who knew that kconfig supported line wrapping?)
- Update the help text.
Change-Id: I2b9eb5a6f7d543f57d9f3b9d0aa44a5462e8b718
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10610
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mickey:
- Does not have power key
- Does not have an audio codec(all audio goes thru HDMI)
- VCC18_LCD moved to VLDO8 and needs to be turned on (was
connected to VSWOUT2 earlier)
BUG=none
BRANCH=none
TEST=Boot from mickey board, and hdmi work normal
Change-Id: I88cdc41ce8bb96a6b17aeb7f24b1c5619471b24e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c966edfa29df1049c469442dc3ad8bf8b4197b1
Original-Change-Id: I3d98203185f52ed751a5d3045a0ee8f9b4dfbc71
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274876
Reviewed-on: http://review.coreboot.org/10630
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Bettong, Lamar and Olivehill Plus have many same Kconfigs.
Move them to northbridge/amd/pi/Kconfig.
Change-Id: I758d5a09f27eee7a7bd60268a2aaed6f16fd0294
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10421
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a new mainboard based on AMD's Family 15h Model 60h processor.
TEST: Bettong can boot Ubuntu 14.10, Windows 7 and Windows 8.
Change-Id: Id807369ff0f04ba303383c65ddd1bd512f184e6a
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10420
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
At present, no option exists for "Keep VESA framebuffer", which
means that text-mode will be used. Add the appropriate Kconfig
option.
Change-Id: Iaed07eba6d9288c857f7e7a0b0be1107071e49e5
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/10553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
On i945 legacy brightness control is enabled by a single
bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
reverses polarity). Set the bit to enable brightness
controls.
Change-Id: Id855c4e91fe71fb489739e62fbe99ca22841acd2
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/7048
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The EARLY_CONSOLE Kconfig symbol was removed in
commit 48713a1b - console: Drop EARLY_CONSOLE option
The arm64 and mips directories don't even have early_console.c
to include.
Change-Id: Idc60ffb2bac2b180f4fdd0adf5c411e1f692a846
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10615
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit
Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Provide ACPI devices with devicetree-compatible annotations for the
three leds and the button of the APU1, as well as the GPIO driver.
This will cause the Linux kernel to automatically load the following
modules:
leds_gpio (CONFIG_LEDS_GPIO)
gpio_keys_polled (CONFIG_KEYBOARD_GPIO_POLLED)
gpio_sb8xx (CONFIG_GPIO_SB8XX)
See
http://events.linuxfoundation.org/sites/events/files/slides/ACPI_vs_DT.pdf
and https://lwn.net/Articles/612062/ for some more information on how
the PRP0001 HID works.
To make this usable a Linux GPIO driver for the AMD chipset is also
required, which I am currently working on, but have not submitted
upstream yet.
Leds have been named after the convention in
Documentation/leds/leds-class.txt:
LED Device Naming
=================
Is currently of the form:
"devicename:colour:function"
For comparison, on an OpenWRT device:
GPIOs 0-21, ath79:
gpio-1 (tp-link:green:usb ) out hi
gpio-2 (tp-link:green:system) out lo
gpio-3 (reset ) in hi
gpio-5 (tp-link:green:qss ) out lo
gpio-7 (qss ) in hi
gpio-9 (tp-link:green:wlan ) out lo
gpio-18 (rtl8366rb ) in hi
gpio-19 (rtl8366rb ) in hi
On the apu1:
GPIOs 288-511, platform/PRP0001:00, AMD SB8XX/SB9XX/A5X/A8X GPIO driver:
gpio-475 (switch1 ) in hi
gpio-477 (apu1:green:led1 ) out hi
gpio-478 (apu1:green:led2 ) out hi
gpio-479 (apu1:green:led3 ) out hi
Change-Id: I956ee92d9d98ef27a83ccb30d314543bd8634f2c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10540
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The smbus.asl operation regions prevent the Linux i2c driver (i2c_piix4)
for this chipset from claiming the ioport ranges and thus it fails to
load.
The methods defined in smbus.asl are not used in the DSDT and also don't
exist in the DSDT of the vendor firmware.
In particular due to the following check in i2c-piix4.c will fail unless
acpi_enforce_resources=no is explicitly set on the Linux kernel
parameters:
if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
return -ENODEV;
Depending on kernel options the only error message printed is
ACPI Warning: SystemIO range 0x0000000000000B00-0x0000000000000B07 conflicts with OpRegion 0x0000000000000B00-0x0000000000000B0B (\SMB0) (20150410/utaddress-254)
ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
However since it does not implement a standard interface there is no
native ACPI driver for smbus.asl.
Change-Id: Id8401e8b36f0e2412d490a92c20540a04d853125
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10539
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The same values are used on my Lenovo R400 as reported by Francis Rowe
from his T400 and T500.
TEST: Read /proc/asound/card0/codec#0, see that the jack locations
correspond to the board layout, e.g. headphone and microphone
connectors are on front of the laptop, not right. Read
/sys/class/sound/hwC0D0/init_pin_configs, see that it has the same
content as with factory firmware.
Change-Id: I60e914ca9fab4bb2c99b4ed9e6d81a0580a88b18
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/10431
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Commit 8d80a3fb (ASRock DSDT: Split the ASRock DSDT) creates the file
`acpi/smbus.asl` in the board directory, but includes the identical
southbridge file in `dsdt.asl`.
So, the file is actually unused. Therefore remove it.
Change-Id: I26c5a2eaf3822d37da2402da65b278a3ee6d42f0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10544
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit: d20a1d1a22d64546a5d8761b18ab29732ec0b848
Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix by checking the actual function return value (the search
address pointer), rather than the search length value (which isn't
guaranteed to be sane or useful).
Change-Id: I226c635ddbbc916b02494fcd97df27d141cc2c7f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10516
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Commit 899d13d (cbfs: new API and better program loading) broke
panther's lan init when no vpd.bin present from which to read
the MAC address. Fix this by checking the validity of the search
address pointer, rather than the search length.
Change-Id: I8c7ca410d8ce5c5d92242a21c4c2ff4c001a68bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10509
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
sata.asl and superio.asl are empty files. Remove them.
Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Copy the Peppy directory. No changes.
Change-Id: I3fa382eaa40f642df8bc09ab69be67cbe9f3671a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10499
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No board in the tree selects this and it looks like the implementation
was done at chipset level while it should be part of PCI subsystem.
When enabled, at least AMD K8 and f14, f15tn and f16kb fail build test.
Feature of placing prefetchable PCI memory above 4GB may not work if
there is any 32-bit only prefetchable PCI BARs in the system.
Change-Id: I40ded2c7d6d05f461423721aa5d78a78f9f9ce1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Taken from CrOS, including everything up to commit da4c33913.
Adapted to upstream.
Change-Id: I095e6726a220200ba17719fc05fcdc521da484e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mimic vendor BIOS in switching off the led once coreboot has booted
successfully. Currently the led behavior is inconsistent. The led turns on
during poweron and stays on forever. When entering S3 and during S3 it
blinks and turns off after wake from S3. The behavior associated with S3
is the same under vendor BIOS and under coreboot. Switching off the led
before jumping to the payload makes the led behavior consistent within
coreboot before S3 and after wake from S3 and it makes the led behavior
consistent to vendor BIOS.
Change-Id: I0dec10b842b83dfc8054cd56d2750b724c4e8576
Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Reviewed-on: http://review.coreboot.org/10454
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Change the Kconfig board name symbol to uppercase to match
other symbols and to match the capitalization in the Kconfig
file where it's used in an expression.
Change-Id: I04ccb57cc15a6d7430f8d04136beb8384caa6c04
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10440
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Cleaning up unused Kconfig symbols. These symbols are not used anywhere
in the coreboot tree as far as I can tell.
Change-Id: I4d0b9512a784083dd134a8706b3bd8eca2a3a909
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10439
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.
Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9599
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.
Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.
Change-Id: I3fc8e0339fa46fe92cc39f7afa896ffd38c26c8d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9597
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This simply copies veyron_brain to veyron_mickey and makes the
minimal set of changes (s/brain/mickey) to make it compile. The
follow-up patch will take into account board differences.
BUG=none
BRANCH=none
TEST="emerge-veyron_mickey coreboot" doesn't fail
Change-Id: I7d029b36d2fb865446490b896117ade632325a52
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34f6b391290f99caf517d7e98c31c89dc57309be
Original-Change-Id: I03a2b80eb441384f363910467180479521765431
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271360
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10408
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This simply copies veyron_brain to veyron_romy and makes the
minimal set of changes (s/brain/romy) to make it compile. The
follow-up patch will take into account board differences.
BUG=none
BRANCH=none
TEST="emerge-veyron_romy coreboot" doesn't fail
Change-Id: Ice1bc012bddd6c51b43944747e0df3ffa34207fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ab849178b69cf2323f126e503bd61080048240a
Original-Change-Id: I0516ce94fd3c6a38170fae221a070f503ccfaf0f
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271345
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10407
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Every Lenovo Thinkpad includes a Trusted Platform Module, so we can enable
it for the sandy-/ivybridge platforms.
Change-Id: Icda443ba88c2a49a0033014ce7710dd607fa15dc
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/10411
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus
is the first to scan and it will be assigned with bus number 0.
If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range
of bus numbers instead of assigning consecutive numbers across all the links.
All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge.
Follow-up can easily drop this if we find this is dictated by architecture.
Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8366
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Define the default value under northbridge. The list of boards this
patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with
follow-up patch.
Based on code analysis, these boards already scan system bus
as the first (active) HT chain, so it is placed as bus 0
even when this option was not explicitly selected.
Change-Id: I5a00d6372cb89151940aeee517ea613398825c78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8353
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The input/output value max is no longer used for tracking the
bus enumeration sequence, everything is handled in the context
of devicetree bus objects.
Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The actual use of the parameter max is to keep track of PCI bus
number while recursively scanning PCI bridges or PCI-e rootports.
Neither CPU, SMBus, LPC or other static buses are involved in this
enumeration, but the way bridge operations were originally designed
forced to pass this argument thru unrelated functions.
Follow-up removes these once the function prototype gets fixed.
Change-Id: Idbc9c515a362c571a1798bb36972058b309c2774
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8535
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.
For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.
Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
cbfs_get_file_content was replaced with cbfs_boot_map_with_leak but
36f8d27ea9 failed to get it into account.
Change-Id: I0c7840043b2ea6abaf8e70f4bf1a63c96aedebc1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10403
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Makes it cleaner by putting AML into separate file rather than having
an array in C code.
Change-Id: Ia5d6b50ad9dabdb97ed05c837dc3ccc48b8f490f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10385
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A new CBFS API is introduced to allow making CBFS access
easier for providing multiple CBFS sources. That is achieved
by decoupling the cbfs source from a CBFS file. A CBFS
source is described by a descriptor. It contains the necessary
properties for walking a CBFS to locate a file. The CBFS
file is then decoupled from the CBFS descriptor in that it's
no longer needed to access the contents of the file.
All of this is accomplished using the regions infrastructure
by repsenting CBFS sources and files as region_devices. Because
region_devices can be chained together forming subregions this
allows one to decouple a CBFS source from a file. This also allows
one to provide CBFS files that came from other sources for
payload and/or stage loading.
The program loading takes advantage of those very properties
by allowing multiple sources for locating a program. Because of
this we can reduce the overhead of loading programs because
it's all done in the common code paths. Only locating the
program is per source.
Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9134
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
They're not referenced in the code anywhere.
Change-Id: I4805e11523ca7d3cffb484c719f479b7a6ba3e15
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Remove dead code and dead includes.
Change-Id: I5564ebfbbef6f65c275c2f94f75724f4e36472db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10349
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
PS/2 emulation is part of H8, so should be inited in relevant files.
Change-Id: Ie873ea7f6f88f68f622351799462d0b000d17585
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Previously only internal mic really worked but since it's of good quality
it's not really noticeable.
Change-Id: Ie14c377b0370302d97e1f89eae5787e05e73b7d2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10286
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Not used anywhere.
Change-Id: I9bab092d285aaebdf9283ba08e23197f9785b3a6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.
Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This allows to deactivate TPM on X201.
Change-Id: Ic085db6cc2c57668e7a4fdbc7440735c806cc256
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10278
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
This allows to deactivate TPM on X230.
Change-Id: I73d4272da62335ec3766ce4814d5b46538b190fe
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10273
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
This code is not specific to ChromeOS and is useful outside of it.
Like with small modifications it can be used to disable TPM altogether.
Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10269
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Brain doesn't have HOST1_PWR_EN (GPIO0_B3) and 5V_DRV (GPIO7_C5).
The only USB power enable pin connected to the AP is USB2_PWR_EN
(GPIO0_B4) which controls power for both the physical type-A ports.
BUG=none
BRANCH=none
TEST=built and booted on Brain, both USB host mode ports work
Change-Id: Iea371926c7dcd111aa2e671a15fe97a3519bfc04
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4db71095a5116666cd27aedb09b4f02557362346
Original-Change-Id: Ibbb4b9b424156eb3db1ccfdd948050c1c067ad3c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271309
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@google.com>
Instead of being pointer based use the region infrastrucutre.
Additionally, this removes the need for arch-specific compilation
paths. The users of the new API can use the region APIs to memory
map or read the region provided by the new fmap API.
Change-Id: Ie36e9ff9cb554234ec394b921f029eeed6845aee
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The CBFS_HEADER_ROM_OFFSET went away. Remove remaining
defintions that are not used.
Change-Id: Ibedce988143f0b7167cea1b27de5b33698b5d82b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The boot_device is a region_device that represents the
device from which coreboot retrieves and boots its stages.
The existing cbfs implementations use the boot_device as
the intermediary for accessing the CBFS region. Also,
there's currently only support for a read-only view of
the boot_device. i.e. one cannot write to the boot_device
using this view. However, a writable boot_device could
be added in the future.
Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10216
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Note: apu1c models do not support this. That we expose S3 in
ACPI table while it is not available, is a wider issue to solve.
Change-Id: I9b07550d0523593f51c1882a40cccd783115057b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10315
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This should be overriden by mobo even if it's no-op override.
weak function in this case would only hide real problems.
Change-Id: I30dd671eb605b490a51153d00ae308c4bdef3d05
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Export SLIC table from file in CBFS.
Change-Id: Id0e7fe0a49b9cd50b5e43cd15030e1c2098728ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7202
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
The comment about necessity of include isn't true anymore as get_cst_entries
is not weak anymore so if it's not found, the linking would fail.
Change-Id: I4bf88208d63ac3e625f464c3907e2e1ea575dd9f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7375
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
All boards now use per-device ACPI. This patch finishes migration
by removing transitional kludges.
Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7372
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This code in reality just describes the southbridge features, don't put a copy
in every mainboard.
Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10231
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Some missing static declarations and whitespace on the console.
Change-Id: I1af59dbfb1396297bd671b43d9326dffdd7f59d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10284
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Same comments were already removed for the latest board, the amd/lamar.
Change-Id: Ie244f838409c567c11f7444c9cf17de72e49dbb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10283
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Implementation corrupts low-memory on S3 resume path, rendering
OS unstable. AMD was never able to pinpoint a revision that did
not have the issue.
Change-Id: I9656ac1bfe1412775a6152b9f995c4d4ebf57159
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10285
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
acpi_fill_slit and acpi_fill_srat were removed in commit 5e597572e.
Take care of the boards that were added in the mean time.
Change-Id: I907e51de5d4ce9acfcce82e6bb30eefff312d35d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
SLIT and SRAT are created this way only on amdk8 and amdfam10.
This saves the need of having a lot of dummies.
Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I9c938b8a69479fae6b0eb99d1135f1caaf26d0e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10227
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The variable was set on all haswell boards, so we can do it like on
broadwell where the MSR based timer is assumed to be around, too.
Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10256
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
MAINBOARD_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere
(with no overlap), and never read. Remove it.
Change-Id: Ica1f16182b556dbf4a3b747237af74bcc4c0608c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Rename Kconfig options for secmon and spintable to be prefixed with
ARM64_ instead of ARCH_, which seems to be the standard throughout the
rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this
provides a clearer separation between generic options that are selected
by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to
some of the MAINBOARD_HAS_... we have) and options that only make sense
in the context of a single architecture.
Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10242
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sample code belongs to documentation, not copied 100x over prodcution code.
Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These are alternative customer options connected to J19 header.
We need to avoid modifying devicetree.cb, so we fix devicetree
for the super-io device-enables at runtime instead.
Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch is based on commit f2b3cd63
(lenovo/x60: Support digitizer on X60t and X201t)
Tested on Thinkpad X200 Tablet (7450): all pen functionallity
works (i.e. movements, presure sensitivity and buttons)
Change-Id: I9bd18642a6ea4211dc3be065456a507fc0b72561
Signed-off-by: Alex David <opdecirkel@gmail.com>
Reviewed-on: http://review.coreboot.org/10208
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
We already have APM_CNT_FINALIZE defined to the same value. Just use it
thoughout.
Change-Id: Ife94ec7a34da27d3a720bda7337c02e41f18ac72
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10226
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
These boards are not ThinkPads. Furthermore, autogenerated build.h
might not be generated yet to be included.
Change-Id: I084f632d45477abf5e3cb1b734e8048f554423ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10213
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Without this some radios may remain operational. They may consume power but
the immediate demonstrable effect is wireless LED still being on.
Coreboot will reenable radios on resume or poweron.
Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10190
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
vboot_verify_firmware() was only defined to ease upstreaming.
It was only an empty inline as it is so remove it. Additionally,
vboot2 does not require romstage_handoff so there's no need in
adding it for the nyan boards.
Change-Id: I4d84ac9fb60c756cf10742f26503f7f11af5f57b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These tables are not referenced anywhere, thus all
comments about adjustments are void.
Also drop stub AgesaReadSpd that is all commented out.
Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10143
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
There's now room for other repositories under 3rdparty.
Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.
Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The vboot mechanism will be implemented within the program loader
subsystem to make it transparent to mainboards and chipsets.
Change-Id: Icd0bdcba06cdc30591f9b25068b3fa3a112e58fb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10094
Tested-by: build bot (Jenkins)
On current Danger boards, VCC_LCD is gated by BL_EN. Thus we
need to enable BL_EN in order to power on the display so that
we can read the EDID and set things up.
Later board revisions may change this ordering, but for now it
doesn't seem to be causing a significant issues (no noticable
"snow" or other corruption using Pepto display).
BUG=none
BRANCH=none
TEST=booted on Danger, saw dev mode screen come up
Change-Id: I70aab8c1f6da2d0fce310d59073026eef0f67821
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a918824e747600a2f3a88602320f4f563ce17b7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iaf17cc4682bd3c46f62cba789e3ecf8d5a474362
Original-Reviewed-on: https://chromium-review.googlesource.com/266913
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10089
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This patch initializes the GPIO for the Chrome EC interrupt line on
Veyron boards and passes its description through the coreboot table, so
that payloads with keyboard support can use it to detect pending key
presses.
BRANCH=none
BUG=chrome-os-partner:39514
TEST=Booted Jerry, confirmed that it could still detect keypresses.
Confirmed that EC log does not show a huge amount of MKBP polls.
Change-Id: I4de35ef411c3acc02282ebf8e764785a1e7bf6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ad95d667ef3af3fb217e3c370468dc1d6ec36c9
Original-Change-Id: I8b426621af088460929cfff0a4b46618e2a86725
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/267344
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10088
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I19af5f36a55d6c2906d603e940b3aadd2ca97140
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8317
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
