Commit graph

1259 commits

Author SHA1 Message Date
Elyes HAOUAS
f8d399904c northbridge/amd/agesa/family14: Remove commented code
Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16895
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:36:18 +02:00
Elyes HAOUAS
4da1aa8561 northbridge/amd/amdk8: Remove commented code
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16893
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:36:06 +02:00
Elyes HAOUAS
1a77fd3e36 northbridge/amd/lx: Remove commented code
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16891
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:31:11 +02:00
Elyes HAOUAS
e809dd3a84 northbridge/amd/pi/00730F01: Remove commented code
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16890
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:58 +02:00
Elyes HAOUAS
6bc3b96831 northbridge/amd/amdmct/mct_ddr3: Remove commented code
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16889
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:46 +02:00
Elyes HAOUAS
59840d1dee northbridge/amd/agesa/family16kb: Remove commented code
Change-Id: Ic22f8a00e6009e104df8c4374067369ebbf90ee2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16888
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:35 +02:00
Elyes HAOUAS
decf90e4eb northbridge/amd/agesa/family15rl: Remove commented code
Change-Id: I5f45a4cd5661140f57aa37e86cc8a34622da3de5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:23 +02:00
Elyes HAOUAS
d13b147235 northbridge/amd/agesa/family10: Remove commented code
Change-Id: I7966f996a4291cc6b97b53aba59b43358de94e45
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16886
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:14 +02:00
Elyes HAOUAS
e0ee4c87e8 northbridge/amd/amdfam10: Remove commented code
Change-Id: I63fee62253cb0488a041c9985a646102261b8c5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16880
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09 21:30:03 +02:00
Elyes HAOUAS
7db506c3dd src/northbridge: Remove unnecessary whitespace
Change-Id: Ib06ecd083f00c74f1d227368811729d2944dd1ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16851
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04 19:15:55 +02:00
Elyes HAOUAS
0d4b11a4f8 src/northbridge: Remove whitespace after sizeof
Change-Id: Iea0352f85f4d5f47fc906edbe625e7bbf3f03afd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16863
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-10-04 14:31:53 +02:00
Elyes HAOUAS
b6a6bb5393 northbridge/amdk8: Improve code formatting
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16644
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-21 16:49:34 +02:00
Elyes HAOUAS
e1606731b6 northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 16:49:15 +02:00
Elyes HAOUAS
a813160fbc northbridge/amd: Improve code formatting
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 11:04:45 +02:00
Elyes HAOUAS
04f8fd981f northbridge/amd/amdfam10: Improve code formatting
Change-Id: I86a252598666af635281eaa467020acb53d71c77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:53:57 +02:00
Elyes HAOUAS
1d8daa66ee northbridge/amd/agesa: Improve code formatting
Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 17:42:03 +02:00
Elyes HAOUAS
705a063e65 northbridge/amd/amdk8/raminit_f_dqs.c: Improve code formatting
Change-Id: Ib1f9926ced1fd382c782f5098eb1ad98330cf655
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16600
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15 02:30:30 +02:00
Elyes HAOUAS
7a3a8a5f85 northbridge/amd/amdk8/coherent_ht.c: Improve code formatting
Change-Id: I296254d61fdc5c120e1e2abcbecb4677f3216d26
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16598
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15 02:29:22 +02:00
Antonello Dettori
b0a60e5b21 northbridge/amd/amdht: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdht.

Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16468
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:17:31 +02:00
Antonello Dettori
0501ece181 northbridge/amd/amdk8: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdk8.

Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16467
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:17:17 +02:00
Antonello Dettori
f65ccb2cd6 northbridge/amd/amdfam10: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/amd/amdfam10.

Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16466
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:17:02 +02:00
Elyes HAOUAS
6e8b3c1110 src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12 20:08:19 +02:00
Rizwan Qureshi
8453c4f2fb cpu/x86: Move fls() and fms() to mtrr.h
Move the funtion to find most significant bit set(fms)
and function to find least significant bit set(fls) to a common
place. And remove the duplicates.

Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:51:36 +02:00
Antonello Dettori
587f9cb6ce northbridge/amd/lx: remove unused function declaration
Remove an unusued function declaration that caused problems while
compiling the target.

Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16435
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07 18:34:47 +02:00
Elyes HAOUAS
5a7e72f1ae northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31 20:28:51 +02:00
Elyes HAOUAS
38424987c6 src/northbridge: Remove unnecessary whitespace before "\n" and "\t"
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16280
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
2016-08-23 15:43:27 +02:00
Patrick Georgi
47f7b0e196 amd/amdfam10: eliminate dead code
if (gart) { foo = gart?a:b; } never evaluates to foo=b.

Change-Id: Ibc7376687374065585b125a670dea5fe46bda97a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347365
Reviewed-on: https://review.coreboot.org/16008
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-02 14:02:51 +02:00
Martin Roth
0cd338e6e4 Remove non-ascii & unprintable characters
These non-ascii & unprintable characters aren't needed.

Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01 21:44:45 +02:00
Martin Roth
bb9722bd77 Add newlines at the end of all coreboot files
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01 21:43:56 +02:00
Elyes HAOUAS
15279a9696 src/northbridge: Capitalize CPU, RAM and ROM
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 18:28:48 +02:00
Kyösti Mälkki
bce9bbdfd4 AGESA: Use common romstage ram stack
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15 12:18:54 +02:00
Kyösti Mälkki
5003632407 AGESA: Fix invalid use of CFG_ declarations
The declarations of CFG_ evaluate to correct values only when
included after the definitions of BLDCFG_ in buildOpts.c.
So we never have CFG_PLAT_NUM_IO_APICS defined here.

Change-Id: I94b3dee5a3207b37921eb24a0bcd73b5a217b2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04 11:09:22 +02:00
Timothy Pearson
84da72c988 nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure
The existing DIMM size calculation for DDR3 was incorrect.  Use
the recommended calculation from the DDR3 SPD specification.

Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14739
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 20:44:11 +02:00
Timothy Pearson
d112f46bed nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h
While some stubs existed before this patch to handle non-ECC
memory initialization, there were a number of ECC detect unaware
sections of code.  Add ECC support detection to those sections.

Change-Id: I56dad8a0f6833b2f42796212afb9777e9cc73d6d
Tested-On: ASUS KGPE-D16
Tested-With: 1x Opteron 6262
Tested-With: 1x SuperTalent 4G non-ECC DIMM in slot A2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14737
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 20:43:29 +02:00
Stefan Reinauer
617536e580 amd/gx2 + amd/lx: Fix shift overflow issue
gcc 6.1 complains that SMM_OFFSET << 8 is larger than the register
it is assigned to (rightly so):

src/northbridge/amd/gx2/northbridgeinit.c:196:23: error: result of
    '1077936128 << 8' requires 40 bits to represent, but 'int' only
    has 32 bits [-Werror=shift-overflow=]
  msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
                       ^~

Change-Id: Ib0d669268202d222574abee335a6a65c8a255cc7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14617
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-06 19:04:51 +02:00
Timothy Pearson
394041b149 nb/amd/mct_ddr3: Only initialize ECC bits once
The ECC check bits of all ECC DIMMS were inadvertently initialized
twice in the same routine, significantly delaying startup.  Part
of this was related to an obsolete MCA workaround that has been
fixed through multiple commits, therefore the workaround is no
longer needed.

Only initialize the ECC check bits once.

Change-Id: I90ac1147d9b006794d29b866a9cb5b7ead8f01e7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14503
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-02 16:17:52 +02:00
Timothy Pearson
ac6bd5b037 nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h
Change-Id: Idb948acd1a508379f600fbd2fd40fb26b7571d7c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14545
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:50:47 +02:00
Timothy Pearson
2bb1d30d69 nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
During receiver enable cycle training on Family 15h the entire range
of possible delays is searched, even though the single passing window
is often found nearly immediately.  Skip the remainder of the delay
range after the passing window has been located.

Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14544
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:50:21 +02:00
Timothy Pearson
29dd5da1dc nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
During DQS receiver enable cycle training on Family 15h platforms the
read data timing registers were inadvertently set to zero on every
lane training attempt.

Ensure that the read data timing registers are correctly set after
each lane is trained in receiver enable cycle training.  This allows
more than one RDIMM to function on a given DCT channel.

Change-Id: I87d732f0383e9785a73b57e6f48855f3e872f1f9
Tested-On: ASUS KGPE-D16
Tested-With: 1x Opteron 6262HE
Tested-With: 4x Crucial 36KSF1G72PZ-1G6M1 (slots A2 / A1 / B2 / B1)
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14543
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:50:05 +02:00
Timothy Pearson
263c679075 nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14542
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:49:40 +02:00
Timothy Pearson
7f731f8d4f nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
The existing Family 15h receiver enable training code stored
temporary delay values in the wrong variables, leading to
the requisite averaging of delays across nibbles not being
applied.  This in turn made x4 DIMMs less stable than they
should have been.

Store temporary nibble delay values in a dedicated array.

Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01 00:49:24 +02:00
Timothy Pearson
09e3bfbd8b nb/amd/mct_ddr3: Restart system on training failure instead of using die()
DIMM training can sporadically fail due to external influences or various
errata.  In these cases, restarting to retry training is a more appropriate
response than halting the system and requiring manual intervention.

Change-Id: Id49f7419f56e0640a84448cc06ecbaf62bed145e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14529
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-28 20:04:54 +02:00
Timothy Pearson
0739b9fe85 nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines
The wrong DIMM number was used in the initial non-target MRS
setup routines.  This had no functional impact other than to
print the wrong DIMM number in the DDR3 verbose debug output.

Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14501
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-26 16:54:04 +02:00
Timothy Pearson
3242bcfa0f nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup
The existing RDIMM RC control word send routines were a hodgepodge
of various AGESA chunks with different ways of handling the same
task.  Unify the control word chip select setup, use precise timing
routines on Family 15h, fix a couple of incorrect masks, and add
additional debugging statements.

It is believed that this patch is cosmetic and does not significantly
alter existing functionality.

Change-Id: Ie4ec7b6a7be7fce09e89f9eec146cc98b15b6160
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14500
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-26 16:53:42 +02:00
Timothy Pearson
4488d7371a nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change
When more than one DIMM is installed on a DCT, only the first DIMM
delay values are scaled to the new memory clock frequency after a
memory clock change during write leveling.

Store the previous memory clock of each DIMM during write leveling
to ensure that every DIMM has its delay values rescaled.

Change-Id: I56e816d3d3256925598219d92783246f5f4ab567
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14479
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-25 19:51:55 +02:00
Timothy Pearson
8b9c807d72 Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
After substantial testing it has been determined that it is neither
required nor safe to disable the DRAM MCA during initial startup.

This (mostly) reverts commit c094d99611.
The minor debugging enhancements from that commit were left in place.
Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Config-RAM: 1x Kingston 9965516-483.A00LF
Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14446
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:32:20 +02:00
Timothy Pearson
5a359365b9 nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14447
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:31:42 +02:00
Timothy Pearson
490160140a nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
Certain RDIMMs have inherently large write levelling delays,
in some cases exceeding 1.5 MEMCLK.  When these DIMMs are
utilized, the phase recovery system requires special handling
due to the resultant offset exceeding the phase recovery reporting
capabilities.

Fix an old error where delays > 1.5 MEMCLK were not being programmed
(gross delay high bit was not in set range), and restore special
delay handling for delays greater than 1.5 MEMCLK.

Also enhance debugging for x4 DIMMs around the affected code.

Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14441
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:29:22 +02:00
Timothy Pearson
b474afdd21 nb/amd/mct_ddr3: Run fence training on each node after memory clock change
The BKDG requires phy fences to be re-trained after a memory clock change.
Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked
 -- without actually following this requirement -- !

Fix the single typo that caused several weeks of delay in putting
servers with Kingston RAM (and others) into production...

Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14445
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-22 17:29:01 +02:00
Kyösti Mälkki
318e2ac974 AMD CIMX: Drop unused code
We never define B1_IMAGE or B2_IMAGE. These are about building
CIMx as separate binary modules, while coreboot builds these into
same romstage or ramstage module.

Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-04-20 15:31:18 +02:00
Patrick Georgi
59493717ad northbridge/amd/{lx,gx2}: remove immediate accesses of 0
gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.

Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.

Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-04-16 01:50:55 +02:00
Edward O'Callaghan
46f8bd70ef amd/agesa/family12/dimmSpd.c: Indent (tab) fix
Trivial; Use tab over space for indent. Clean up some ASCII art
while here.

Change-Id: Id2478d140a98596c5eeefdf5b047c1ca23203909
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-13 21:16:18 +02:00
Timothy Pearson
186b9de95d and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignment
Two of the MCT data structures passed as substructures to ramstage were
not packed, and additionally no alignment was specified.  On at least
SP5100-based platforms, specifying packed with no alignment caused boot
failure dependent on the exact compiled binary layout (LPC hang).

Specifying the alignment and packing the remaining structures appears to
have resolved the remaining LPC hang issues on the KGPE-D16.  Note that
packing the remaining structures alone was not sufficient to eliminate
the hang, however removing the packed attribute entirely (during debugging)
did resolve the hang at the expense of potential problems in ramstage.

Change-Id: If3a7509ed438870d4d05caaaaa091e1c47bf9b97
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14303
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-04-11 18:19:13 +02:00
Timothy Pearson
54e055179d nb/amd/amdfam10: Write MCT variables to flash after PCI configuration
The SPI controller needs to be set up on devices such as the SP5100
before it can be accessed to write MCT backup data.  Move the backup
data write after PCI configuration has been completed.

Change-Id: Ibcf31755242ac058407a422ce8aa33d6b0b293c7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14305
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11 17:29:58 +02:00
Timothy Pearson
5a57725126 Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
This reverts commit f961becc43.

On studying the BKDG more closely this is not the correct place
to enable DIMM parity.  Further patches to clarify the parity
setup process on Family 15h are forthcoming.

Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebecd
Reviewed-on: https://review.coreboot.org/14271
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08 17:21:21 +02:00
Timothy Pearson
ba817d0931 nb/amd/mct_ddr3: Reenable sync flood after ECC init
The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
and related changes have made it possible to move the sync flood enable statements
back into romstage.

Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14270
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08 17:21:09 +02:00
Timothy Pearson
1d9370b3a5 nb/amd/mct_ddr3: Add MCE reporting logic
When a fatal error and subsequent sync flood / reset occurs,
the MCA status registers may contain valuable information on
the cause of the fatal error.  Add functions to report MCEs and
reset the MCA status registers early in the boot process.

Change-Id: Icde1051ac22f93688de1330f5e2c9ce28b14b59a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14265
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08 16:43:53 +02:00
Timothy Pearson
49e917bffd nb/amd/amdfam10: Only flag machine check exception if valid bit is set
Change-Id: I42d901ae9445943a863fb3ba9bda5a915f255e02
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14264
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08 16:43:35 +02:00
Timothy Pearson
c5c3d76127 nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level
Certain AMD platforms, such as those using the SP5100 southbridge,
contain a very poorly documented bug related to LPC ROM access,
which is triggered by repeated (hundreds or more) rapid calls to
get_option().  This bug manifests as a complete system deadlock
in ramstage device configuration, requiring standby power to be
removed from the system to release the deadlock.

Cache the platform ECC status to avoid repeated calls to get_option()
in the lane count detection logic.

Change-Id: I8b48c523218ccc8c113319957d6eca2d15e1070f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14273
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-08 16:43:11 +02:00
Timothy Pearson
7123e2e9b6 nb/amd/mct_ddr3: Fix revision mask for DR processors
The revision mask for all DR-* series processors was incorrectly
set to only include the DR-B revision mask.  Include all DR-*
series prcessors in the DR_ALL revision mask.

Change-Id: Iceda96aa6267b24abcbf78d39f4848d2be8053b8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Found-by: Coverity, CID 1229627 (#1 of 1): Logically dead code (DEADCODE)
Reviewed-on: https://review.coreboot.org/14216
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-04-01 22:31:09 +02:00
Timothy Pearson
b3ddf83a11 nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
Enabling sync flood on DRAM MCE directly after ECC clear can
lead to a system hang with no way to determine the offending
DRAM module.  Clear MCEs after ECC setup, but do not enable
sync flood until NB setup in ramstage to allow time for any
MCEs to accumulate in the status registers.  Before enabling
sync flood on MCE, determine if any MCEs were logged during
ramstage execution and display them on the serial console.

Also clear the DRAM ECC sync flood bits during DRAM training
and initial ramstage execution.

Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14192
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-31 23:09:29 +02:00
Timothy Pearson
c00f4d669d nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
During power on from cold (S5) state, numerous MCEs are generated
before DRAM training starts, e.g. during HT link training.  Clear
these MCEs before DRAM training start, and report any MCEs generated
during DRAM training.

Change-Id: I7d047571242e5bd041e4aac22c1ec1d7d26ef0e6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14191
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-31 20:54:56 +02:00
Timothy Pearson
c094d99611 nb/amd/mct_ddr3: Disable MCE framework during DRAM training
On Family 15h processors, with certain RDIMMs, MCEs are generated
as a normal part of DCT startup / DRAM training.  Disable sync
flood on parity or UC data error until ECC has been enabled.

Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14186
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-31 20:00:34 +02:00
Timothy Pearson
f961becc43 nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
This resolves a long-standing issue with RDIMM control word
configuration failure, likely due to random parity failure.

Change-Id: If8b8dc5b8b99f4c2fe29b3a133b064631e4693be
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14184
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30 20:23:34 +02:00
Damien Zammit
33aaa921f7 northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
Change-Id: I96d695ed10176276116fcf3a2b77605fb3f2d5db
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13710
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30 16:23:07 +02:00
Timothy Pearson
e2e0057ee7 nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
Replace open coded memset() functions with calls to the library function.
The new code also explicitly backs up and restores the data structures
that are preserved across calls to mct_ResetDataStruct_D(), and no longer
relies on structure member order to function correctly.

Change-Id: I6dd6377deda0087cd1b65f7555588978657d6516
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-28 18:20:59 +02:00
Damien Zammit
ec38c3d956 nb/amd/amdmct: Select max_lanes based on ECC presence or absence
Change-Id: Ic5482dc13ab7b53ec4df408bbe32d20888ae2e12
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13725
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-26 22:40:56 +01:00
Timothy Pearson
54accfe0d6 nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
During maximum read latency training on Family 15h processors,
the maximum read latency was incorrectly set from the NBP1
value instead of the correct NBP0 value.

Modify maximimum read latency training to explicitly operate
on the NBP0 value, and store the previously calculated NBP1
value for reference by other portions of the training algorithm.

Change-Id: I5d4a6c2def83df3e23f1a4c598314c31a0172cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14150
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-03-24 22:24:11 +01:00
Timothy Pearson
f1d807c5c6 nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_SW_Fam15()
Change-Id: Ic3f636983cf6ba2796ee56e2a25b56513a4343c1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14148
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-23 22:14:00 +01:00
Timothy Pearson
f7d4f73053 nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Under certain conditions (training abort) BlockRxDqsLock could
remain set in violation of the BKDG.  Ensure BlockRxDqsLock is
reset to 0 after a lane training abort.

Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b
Reviewed-on: https://review.coreboot.org/14144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21 20:30:30 +01:00
Timothy Pearson
bc5ad1087b nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
Rebasing change I3be808db5d15ceec4c36d17582756b01425df09a
did not take into account the default UI setting introduced in
change I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 , causing DRAM
instability and occassional failure to boot.

Use the correct 1UI value for the modified function semantics.

Change-Id: I9fd24cf83e4c4083c6e467d49021c98e5f5f2c53
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14073
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13 23:42:41 +01:00
Timothy Pearson
2d987fe0fb nb/amd/mct_ddr3: Consolidate duplicated code
read_dqs_read_data_timing_registers() and
read_read_dqs_timing_control_registers() served essentially
the same function but had slightly different semantics,
causing confusion and needlessly complex Family15h code.

Consolidate both into read_dqs_read_data_timing_registers()
and adjust surrounding code to match new semantics.

Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13994
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12 20:27:48 +01:00
Timothy Pearson
10d6fceaa0 nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13932
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 18:53:32 +01:00
Timothy Pearson
ed85f614b0 nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
Change-Id: I4497b0be6ed6c90dbb31e89013feed8ff5ff9071
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13885
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11 18:48:38 +01:00
Timothy Pearson
2e1f73181a nb/amd/mct_ddr3: Require minumum training quality for both read and write
The existing MCT code proceeded to the next DRAM training phase if
the minimum lane quality standard passed for either the read or
write direction.  Ensure that both pass for a given set of delay
values before proceeding to the next training phase.

Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13993
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:58:55 +01:00
Timothy Pearson
50583f0e1f nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency
must be calculated prior to DQS position training, however the read
latency calculations use read DQS delay values that have not been
set prior to DQS position training.

Set the read DQS delay values to 1UI (i.e worst case) before calculating
the read latency prior to DQS position training.

Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13995
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:57:49 +01:00
Timothy Pearson
8eb221deaf nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
A couple of arrays were not properly initialized.  This
did not appear to affect operation of the codebase however
it led to some ugly values being displayed when debugging
was turned on.

Also bounds check an array index; as before this did not
appear to affect operation but was a potential point of
failure.

Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13934
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:56:56 +01:00
Timothy Pearson
bbfcf62512 nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13931
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:56:17 +01:00
Damien Zammit
41462bd0c3 nb/amd/amdmct: Add socket specific configuration for FM2
Change-Id: I1088064e5f84fcabcd51e0eaaedfb5074f7fb2b5
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13709
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-02-19 21:27:35 +01:00
Timothy Pearson
fec8872c9d nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
Certain registered DIMMs failed training due to an error
likely introduced during historical rebase.  Ensure that
the SubMemclkRegDly bit is set according to BKDG
recommendations on Family 15 processors.

Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13148
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:26:54 +01:00
Timothy Pearson
31682364ba nb/amd/mct_ddr3: Work around RDIMM training failure
Under certain conditions, not elucidated in the BKDG,
an extra memclock of CAS write latency is required.

The only reliable way I have found to detect when this
is required is to try training without the delay, and
if DQS position training fails, adding the delay and
retraining.

This is probably related in some form or another to
the badly broken DQS Write Early algorithm given
in the BKDG.

Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13531
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:26:31 +01:00
Martin Roth
2f91403303 src: Fix various spelling and whitespace issues.
This fixes some spelling and whitespace issues that I came across
while working on various things in the tree.

There are no functional changes.

Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-02 14:37:09 +01:00
Timothy Pearson
b410d267e3 nb/amd/amdmct/mct_ddr3: Save and restore SkewMemClk for S3 resume
Change-Id: Ib331bd330530d4d6be5eb7351d9f9b15c135dd63
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13167
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-01 22:56:33 +01:00
Timothy Pearson
8e9106db20 nb/amdmct/mct_ddr3: Enable mainboard voltage set
The existing code used an incorrect macro name to check for mainboard
DRAM voltage set support, and as a result no voltages were actually
set.  Furthermore, the existing code did not contain a centralized
voltage assumption for boards that did not have a DIMM voltage set
implementation.

Use the correct macro name to test for boards with voltage set
implementation, and provide a basic fallback to 1.5V operation
for boards without a voltage set implementation.

Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13150
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 00:42:30 +01:00
Timothy Pearson
71f864191f cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems
The existing code generated an incorrect boot APIC ID from node and
core number for single node packages, leading to a boot failure when
the second node was installed.

Properly generate the boot APIC ID from node and core number.

Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13149
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-29 00:42:21 +01:00
Timothy Pearson
db84a99011 nb/amd/mct_ddr3: Properly set MR0 WR value
The existing code accidentally truncated the MSB from the MR0
WR value.  While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.

Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-24 23:26:59 +01:00
Timothy Pearson
ad9a2bb0de nb/amd/mct_ddr3: Add additional verbose-level debug statements
Change-Id: Ie91c990d9c2bcab8292a75d87523a46d5694a34a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13146
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:26:13 +01:00
Timothy Pearson
2d500ba598 nb/amd/mct_ddr3: Update drive strength configuration
The existing drive strength calibration code did not strictly
follow the BKDG-defined setup process.  Bring the calibration
code in line with the BKDG recommendations.

Change-Id: I122eeb93958d88de59d0c3b2979f607afa2c52c3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13145
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:25:18 +01:00
Timothy Pearson
a2df081d44 northbridge/amd/amdmct/mct_ddr3: Enable fast refresh on ETR devices
When an Extended Temperature Range DIMM is installed on a channel
the refresh rate should be increased per the BKDG recommendations
to allow correct operation at higher temperature ranges.

Set fast refresh on a channel if an ETR DIMM is installed on that
channel.

Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:24:33 +01:00
Timothy Pearson
6aa6eab98b northbridge/amd/amdmct: Add termination and timing values for C32 sockets
The existing MCT initialization code was largely missing C32 socket-
specific configuration data.  Add C32 socket-specific timing and ODT
values as specified in the BKDG.

Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13141
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:20:31 +01:00
Timothy Pearson
19ce16ae69 northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
The existing code applied G34-specific speed limits to all socket
types.  Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.

Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-24 23:20:02 +01:00
Martin Roth
fd277d8f94 header files: Fix guard name comments to match guard names
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.

Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-18 04:07:53 +01:00
Martin Roth
a20ac2f7b3 tree: drop last paragraph of GPL copyright header from new files
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)

Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13 20:35:40 +01:00
Martin Roth
2ed0aa258f Correct some common spelling mistakes
- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller

Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07 22:57:02 +01:00
Kyösti Mälkki
bb85f9eb73 Revert "AMD OemS3Save: refactor for Merlin Falcon"
This reverts commit d3deecdd9c.

Do not mix open-source AGESA and binary PI trees. Once you have
working S3 support for binaryPI platforms, add the adapted
oem_s3.c file as northbridge/amd/pi/oem_s3.c instead.

Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/12282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04 11:18:04 +01:00
Timothy Pearson
1eaaa0e446 southbridge/amd/sr5650: Add MCFG ACPI table support
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.

Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-18 19:51:44 +01:00
Timothy Pearson
16ff807ba6 amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes
Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12712
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-13 02:20:12 +01:00
Martin Roth
6215b88aee northbridge/amd/agesa/agesawrapper.c: Fix Kconfig symbols
The Kconfig symbols were missing an underscore, so were not getting
evaluated properly.

Change-Id: I619cf3f44f44f9c9699482d64164d3db28cd4c8f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12559
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-08 00:11:18 +01:00
Martin Roth
7c38e1e8bc Remove #ifdef checks on Kconfig symbols
In coreboot, bool, hex, and int type symbols are ALWAYS defined.

Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:46:12 +01:00
Martin Roth
19fbdcc828 amd/pi/00660F01: Remove 'PER_DEVICE_ACPI_TABLES'
The PER_DEVICE_ACPI_TABLES Kconfig symbol is no longer used as it was
removed in commit 83f81cad (acpi: Remove monolithic ACPI)

Change-Id: Ie6ba252f6e7d33da9d4500f1201367f116e4c505
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12554
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-06 18:45:02 +01:00
Timothy Pearson
69056d9452 northbridge/amd/amdht: Reduce excessive romstage array size
Change-Id: Ibcdf5d3927375da5cb72987ae83eaaa789ab9a70
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12573
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 18:45:00 +01:00
Timothy Pearson
09830faa8d nb/amd/amdht: Fix XCS buffer count setup on AMD Family 15h CPUs
The existing code re-used the Family 10h XCS buffer setup on
Family 15h CPUs, which set incorrect values leading to random
system lockups.

Use the Family 15h XCS buffer setup shown in the BKDG.

Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:56:31 +01:00
Timothy Pearson
93107bebf6 nb/amd/amdfam10: Fix incorrect channel buffer count configuration
The secondary bus number set code incorrectly overwrote the link
buffer settings in F0x[F4,D4,B4,94].  Constrain the secondary
bus number set to the appropriate bits of the registers.

Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-01 16:32:25 +01:00
Timothy Pearson
5edc6695f8 nb/amd/mct_ddr3: Add Family 15h tristate enable codes
The Family 15h DRAM initialization did not set up the various
tristate enable codes in the MCT.

Add Family 15h tristate enable setup.  This fixes multiple
DIMMs on a single channel.

Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-12-01 16:31:02 +01:00
Martin Roth
d45a3477b7 amd/pi/00630F01: Drop HT3_SUPPORT
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented.

This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT)

Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12556
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-01 16:28:07 +01:00
Timothy Pearson
309303884c nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time
There is no need to continue testing a DCT configuration after
data errors have already been detected; this just wastes time
during boot.

Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 19:39:31 +01:00
Timothy Pearson
16a3a7515a cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes
Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12065
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
2015-11-30 05:21:24 +01:00
Timothy Pearson
01b9f8e4c2 nb/amd/mct_ddr3: Use antiphase to better center DQS window
The BKDG recommends the use of an antiphase window detection
algorithm to ensure that the DQS data eye is properly centered.

TEST: Booted both with DIMMs known to move the data eye into the
prior clock phase and DIMMs known to keep the data eye in the
current clock phase.

Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12059
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 05:19:19 +01:00
Timothy Pearson
4502df12aa nb/amd/mct_ddr3: Fix odd rank data corruption
The odd rank of each DIMM could experience data corruption due to
incorrect DQS training.  Fix the DQS training algorithm by executing
the relevant portions of the training algorithm on the odd ranks.

Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:38:13 +01:00
Timothy Pearson
df499b53c3 nb/amd/amdmct/mct_ddr3: Fix a minor RDIMM CS select error
Change-Id: I4cdfeec887813c17edcdee8858222414fb19b72c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12057
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:37:08 +01:00
Timothy Pearson
0eb163d5d3 nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set
Also fix incorrect Trfc[0-3] value on Family 15h.

Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-29 19:36:34 +01:00
Timothy Pearson
8528e39fba nb/amd/amdfam10: Work around sporadic lockups when CC6 enabled
The silicon in control of CC6 appears to contain minor bugs
and / or deviations from the BKDG; through trial and error
it was found that these issues can be worked around by reserving
the entire possible CC6 save region, regardless of currently
installed node count.

Change-Id: If31140651f25f9c524a824b2da552ce3690eae18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-28 19:21:18 +01:00
Timothy Pearson
ab1e77fb01 northbridge/amd/amdmct/mct_ddr3: Add CC6 setup information messages
Change-Id: I17660ce5429431e08476b7bba15e381636b64c7d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12053
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-24 19:50:11 +01:00
Timothy Pearson
c8e1073359 northbridge/amd/amdmct/mct_ddr3: Add DDR3 termination debug output
Change-Id: Iabd2e3e20b0e9719080f6bd7be2032c1749994dc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12056
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:48:43 +01:00
Timothy Pearson
ce3456dacd nb/amd/amdfam10: Fix gart setup not working on Fam15h processors
Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12047
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-24 19:28:51 +01:00
Timothy Pearson
50001b80f5 northbridge/amd/amdht: Add isochronous setup support
The coherent fabric on all Family 10h/15h devices supports
isochronous mode, which is required for IOMMU operation.

Add initial support for isochronous operation.

Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:28:00 +01:00
Timothy Pearson
68130f506d amd/amdfam10: Control Fam15h cache partitioning via nvram
Add options to control cache partitioning and overall memory
performance via nvram.

Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:27:43 +01:00
Timothy Pearson
b174667534 northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart
Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12046
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:03:24 +01:00
Timothy Pearson
5a0375a2f6 northbridge/amd/amdfam10: Add Family 15h cache partitioning support
Certain workloads may evict too many lines of other cores from the
L3 cache if configured as one monolithic shared cache region.

Forcibly partition L3 cache to improve performance.

Change-Id: Ie4e28dd886aaa1c586b0919c5fe87ef1696f47e9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12036
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-23 22:55:28 +01:00
Timothy Pearson
121ef60666 northbridge/amd/amdfam10: Fix invalid NUMA table
The existing code generated an invalid NUMA table
that was rejected by Linux, leading to poor resource
allocation.  This was due to system MMIO resources
being inserted into the table when the table should
only contain DRAM resources.

Do not include system MMIO resources (i.e. resources
with an index less than 0x10) in the NUMA table.

Change-Id: I99c200382b52a99687daf266a84873d9ae2df025
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12035
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-23 22:54:19 +01:00
Timothy Pearson
845b00ce33 amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
Change-Id: Ib6bc197e43e40ba2b923b1eb1229bacafc8be360
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 18:36:44 +01:00
Stefan Reinauer
991f18475c cpu/amd: de-duplicate MSR include files
Change-Id: I8e01a4ab68b463efe02c27f589e0b4b719532eb5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12510
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-23 17:16:45 +01:00
Timothy Pearson
0d2fdeb36a amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance
Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12037
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:10:12 +01:00
Timothy Pearson
eb295a3e69 nb/amd/amdmct/mct_ddr3: Force DRAM retraining on every boot
Stability issues have arisen on multiple Family 15h systems
when configuration restoration is enabled.  In all cases these
stability issues resolved by allowing the RAM to go through a
full training cycle.

Change-Id: I017e0dd5120110124d5b5d5276befef6f7740614
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12034
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:09:35 +01:00
Timothy Pearson
4dc6cabd36 northbridge/amd/amdfam10: Fix poor performance on Family 15h CPUs
Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12031
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-11-22 23:09:01 +01:00
Timothy Pearson
fdf31cb9d9 northbridge/amd/amdht: Add comment for HT Freq write ordering
The BKDG is not correct regarding HT Freq write ordering;
indicate this in a comment to avoid confusion.

Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 23:54:40 +01:00
Timothy Pearson
7c55f374d1 northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12027
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 23:49:38 +01:00
Timothy Pearson
0f1553b89a nb/amd/amdfam10: Add HyperTransport probe filter support
All modern Opteron processors support the HT probe filter,
which helps to increase coherent fabric performance by
reducing the number of HT transactions per cache probe.

AMD recommends that the probe filter be enabled on all
systems with more than two nodes, and it does not hurt
to enable it on systems with 2 nodes.

Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12021
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 20:32:19 +01:00
Timothy Pearson
4530df431e northbridge/amd/amdmct/mct_ddr3: Move K10D configuration into separate file
Change-Id: Id45888f266fac7810a63fef43b8d7a0ee40cbf70
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12023
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19 20:22:56 +01:00
Timothy Pearson
0122afb609 cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
This fixes Family 15h multiple package support; the previous code
hung in CAR setup and romstage when more than one CPU package was
installed for a variety of loosely related reasons.

TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
and several different RDIMM configurations.

Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12020
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18 17:14:48 +01:00
Timothy Pearson
29016ea3b4 northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15h
The existing MCT support code did not perform any of the requisite
configuration to support registered or x4 DIMMs.  Add the needed
configuration per the BKDG for Family 15h.

Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12019
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16 18:04:59 +01:00
Timothy Pearson
f682d0028c amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10h
Sufficient support has been added to allow booting with registered
DIMMs on the KGPE-D16 in certain slots.  ECC support needs additional
work; the ECC data lanes appear to cause boot failures in some slots.

Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12017
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16 17:55:57 +01:00
Timothy Pearson
dc4cb05763 nb/amd/mct_ddr3: Fix RDIMM errors due to undefined number of slots
The current code did not define the number of DIMM slots on the
mainboard, which lead to incorrect configuration values and
occassional training failure.

Add preliminary support for DIMM slot count configuration.

Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12016
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-16 17:31:48 +01:00
Timothy Pearson
9597790571 northbridge/amd/amdmct: Reduce maximum number of DDR3 DIMMs
CAR space on certain platforms is nearly full.  This prevents the
addition of necessary RAM initialization features such as x4 DIMM
support.  As the DIMM SPD cache uses a sizeable amount of CAR RAM,
reducing it would free up a significant amount of CAR RAM.

DDR3-based AMD platforms only support up to 3 physical DIMMs on
each channel (6 per node).  Reduce the maximum number of DIMMs
on a node from 8 to 6 accordingly.

Change-Id: I38def86da76fc622785318c825670209b2ac9017
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12107
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-15 02:59:44 +01:00
Timothy Pearson
a44daac7e6 northbridge/amd/amdmct/mct_ddr3: Fix Family 10h boot failure
In the course of adding full Family 15h MCT support some Family
15h specific settings were inadvertently applied to Family 10h
processors.

Only apply Family15h specific settings to Family 15h processors.

Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12013
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:45:37 +01:00
Timothy Pearson
4ef4fc6c3b northbridge/amd/amdmct/mct_ddr3: Properly indicate clobbered registers
Change-Id: Icb2754143762bd64ee1df5674fa071de1c595eaf
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12012
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:45:24 +01:00
Timothy Pearson
dee6b1ff39 northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in use
When both DCTs of a node are in use the DRAM clocks should be skewed
with respect to one another in order to reduce cross-channel interference.

Set the clock skew bit according to the BKDG recommendations.

Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12011
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:45:13 +01:00
Timothy Pearson
f3aa375f44 northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
The existing code did not set Rtt timing parameters when registered
DIMMs were used with Family 15h processors.  Set the Rtt values
according to the BKDG recommendations.

Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:44:36 +01:00
Timothy Pearson
b7a8b8c6fb northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs
Change-Id: Iaf826b6a0c8e929372519f6d97933515a80f0b39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12009
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:44:20 +01:00
Timothy Pearson
11739a48ce northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
AMD Opteron processors contain a very fragile phy phase detection circuit.
Additionally, the algorithm given in the BKDG does not function as intended;
this was verified both on real hardware via execution trace and on paper
with values read back from multiple CPUs and DIMMs.

As a result, the phy training algorithm given in the BKDG has been
replaced with a phy training algorithm developed at Raptor Engineering.
This particular patch is the first part of that algorithm; the code
is updated in future patches but this should exist in the historical
record in case something breaks down in the later sections of code.

Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12007
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:44:10 +01:00
Timothy Pearson
9426e4fcf5 northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors
AMD's automatic phy phase detection hardware is very fragile and often
produces incorrect results.  Attempt to recover from obvious phase
locking errors by retrying phy training on the failing link.

Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:43:54 +01:00
Timothy Pearson
5288cedac1 amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values
The existing MCT code did not properly set up the On Die Termination
(ODT) or timing values for registered DIMMs.  Use the BKDG recommended
values when registered DIMMs are installed.

Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12005
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:43:42 +01:00
Timothy Pearson
38508a0ff1 cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
There were numerous issues surrounding AMD ECC initialization on
Family 15h processors due to the incomplete derivation from Family
10h MCT code.  Bring the Family 15h ECC initialization and supporting
setup code in line with the BKDG recommendations.

Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12003
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:43:30 +01:00
Timothy Pearson
eb2f6fff32 northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init
The existing ECC initialization algorithm contained several bugs on both
Family 10h and Family 15h processors, including activation of ECC scrub
before DRAM setup was completed, in violation of both BKDG and errata
recommendations.

Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12002
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-15 02:43:22 +01:00
Timothy Pearson
0d0375b3c6 northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12008
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-14 23:44:08 +01:00
Timothy Pearson
0e545c66a3 northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables
Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-14 23:38:10 +01:00
Timothy Pearson
31ec0f3257 northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
The existing prefetcher configuration was incorrect; use the correct
values from the AMD Family 10h and Family 15h BKDGs as appropriate.

Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12417
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 22:16:16 +01:00
Timothy Pearson
7fd3ef57cb northbridge/amd/amdmct: Clear memory before enabling ECC
The existing code enabled ECC before clearing memory.  As the
AMD CPUs will generate MCEs on any invalid check bits, this
resulted in random lockups during memory training due to the
uniniailized check bits.

Initialize ECC check bits before enabling ECC hardware.

Change-Id: I992e7040520570893ba6a213138dd57bfa14733b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11996
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12 22:16:09 +01:00
Timothy Pearson
f3b9fd3265 src/northbridge/amd/amdmct: Add option to override bad SPD checksum
Certain DIMMs, for example DIMMs on which the EEPROM has been modified
by the end user, may not contain a valid SPD checksum.  While this is
not a normal condition, it may be useful to allow a checksum override
while memory timing parameters are being altered, e.g. in the course
of overclocking or underclocking, or when recovering from a bad SPD
write.

This is an advanced level feature primarily useful for debugging
and development.

Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-12 21:11:47 +01:00
Timothy Pearson
f70946ff4d northbridge/amd/amdmct: Verify MCT NVRAM options before skipping training
Change-Id: If26e5d148a906d63bd1407b8ffa58f08ae6b4275
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11986
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 00:51:23 +01:00