This makes it easier to have common code for MP init on AMD systems.
Change-Id: Icb6808edf96a17ec0b3073ba2486b3345a4a66ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This avoids searching the HOB output multiple times when calling
smm_region().
Change-Id: Iad09c3aa3298745ba3ba7012e6bb8cfb8785d525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here.
BUG=b:218709292
TEST=Set serial soft fuse, boot to kernel, check logs
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.
Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reverting commit 1e25fd426a ("soc/amd/common/block/psp: introduce
AMD_SOC_SEPARATE_EFS_SECTION").
A better solution was used in commit c17330c1dd ("mb/amd/chausie: Add
EC blob into CBFS"), and this is no longer necessary.
TEST: Boot chausie
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I27a8622a1f0d871690b181a79adca225a20996ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Return the correct processor family code for smbios per System
Management BIOS (SMBIOS) Reference Specification DSP0134 revision 3.5.0.
BUG=b:234409052
TEST=Boot chausie to chromeos and verify "dmidecode -t processor"
outputs the correct processor family.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I617ce3e23f4b28a197034756d285339595d3b53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65364
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of the src/soc/Kconfig files are only there for AMD and Intel to
load the main SoC Kconfig files before any common files. That can be
done in src/Kconfig instead. Moving the loads to the lower level allows
the removal of all but the Intel soc/Kconfig file, which can be removed
in a follow-on patch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The common AMD ACPI GPIO access code is verified to be correct for
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I834076c0a1d1784a272896f2d8f082ebfb86a383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The MCA banks were updated in commit 736d68c0b3 ("soc/amd/sabrina/mca:
update MCA bank names to match the hardware"), but seems that I forgot
to remove the TODO about checking if this is still correct for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd86113ccb9eeab704679afab0b985f9febed13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The common microcode update mechanism is verified to be correct and work
on Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5c41674299a829507438beb3ea597a71a0c5a972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Both UART and DMA MMIO regions for each UART are mapped by the
UEFI reference code, so do the same here.
Without these defined, UART-attached devices fail to correctly
initialize under Windows.
Change-Id: I0e1af9028c7c1746407e923cebe824a15aeb565e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65233
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 96f7b96866 (soc/amd/common/block/
cpu/: Make ucode update more generic) removed the code that used the
SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused
Kconfig option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Without this, calls to i2c_link() and runtime i2c detection fails on
AMD common platform boards.
Test: Runtime i2c detection of correct touchpad model succeeds on
google/zork.
Change-Id: I238b680b2afb4b9d3e5ac75fe9e630b2adc74860
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select
DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the
selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding
the Designware I2C bus ops handler in a subsequent commit.
Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The CPUID function to get the number of cores on a package is common
across multiple generations of AMD cpus.
Change-Id: I28bff875ea2df7837e4495787cf8a4c2d522d43d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64869
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.
Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
TSEG does not need to be aligned to 128KiB but to its size, as the MSR
works like an MTRR. 128KiB is a minimum TSEG size however.
TESTED on google/vilboz.
Change-Id: I30854111bb47f0cb14b07f71cedacd629432e0f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64865
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Make the config file reflect reality instead of using the old cezanne
copy.
TEST=Build chausie
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I8362bc19875ae152e0deab7f64d5b1c50929b95b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify the config file, consumed by amdfwtool, to use "sabrina" and
"SBR" named files.
TEST=build chausie using updated amd_blobs
BUG=b:220848549
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ia993644e67d14792d753cc74a957529d15be18f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Sabrina APU has a maximum configuration of 4 physical cores with 2
threads each, so a total of 8 CPU cores.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MCA bank names were checked against PPR #57243 Rev 1.53.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b947e686a0306d4468203103f91107c15ececc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina slightly changed the names of microcode patches. Adding a
wildcard to support the new name without breaking current builds that
are using the placeholder CZN binaries.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I86caf0ba5c15f64a9a1f0e76a3186919e5e761a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65069
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina uses the SVI3 spec for VID tables which is incompatible with the
SVI2 spec used on PCO/CZN. Move the defines from common to soc and
update the decoding for sabrina.
See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables
TEST=timeless builds on mandolin/majolica for PCO/CZN
build chausie and verify pstate power is correct in ACPI tables
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I915e962f11615246690c6be1bee3533336a808f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Use the equivalent cpuid in the microcode header to name the update file
in cbfs. This allows the SOC to directly locate its microcode file when
there are multiple processor revisions.
TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode
files and booted. Verified that only the sabrina microcode file was
successfully loaded
Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Now that the FSP provides the ALIB ACPI table via a HOB, the PNOT power
notify method can call WAL1 which will then call ALIB to communicate the
current AC/DC state to the SMU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic966b73aa28f329207f8d840ca5fb5f2bf6ec9b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64667
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All targets now use cbmem for the BERT region, so the implementation can
be common.
This also drops the obsolete comment about the need to have bert in a
reserved region (cbmem gets fixed to be in a reserved region).
Change-Id: I6f33d9e05a02492a1c91fb7af94aadaa9acd2931
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This removes the need to align BERT so that TSEG remains aligned.
Change-Id: I21b55a87838dcb4bd4099f051ba0a011a4d41eea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On platforms where the bootblock is not included in CBFS anymore
(because it is part of another firmware section (IFWI or a different
CBFS), the CRTM measurement fails.
This patch adds a new function to provide a way at SoC level to measure
the bootblock. Following patches will add functionality to retrieve the
bootblock from the SoC related location and measure it from there.
In this way the really executed code will be measured.
Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There are efforts to have bootflows that do not follow a traditional
bootblock-romstage-postcar-ramstage model. As part of that CBMEM
initialisation hooks will need to move from romstage to bootblock.
The interface towards platforms and drivers will change to use one of
CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called
in the first stage with CBMEM available.
Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The psp_notify_boot_done call is done at the entry of BS_PAYLOAD_BOOT,
so it's not guaranteed that the psp_set_spl_fuse call is done before the
psp_notify_boot_done call. Moving the psp_set_spl_fuse call makes sure
that it's done before the psp_notify_boot_done call. This also brings
the psp_set_spl_fuse call in line with the enable_secure_boot call that
sends the PSB fusing command to the PSP.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id76b462608c3d788cd90e73a64d18c8e8b89dbfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is
constant. Changing a constant is undefined behavior, so create a local
static instance of usb_phy_config that can be modified safely.
Change-Id: If9b76b869a5b0581f979432ce57cc40f1c253880
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add and use defines instead of magic values in fsp_m_params.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e33eb0af5310ab4610ea8951688464c4960260
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85dc2fce11d9a670b2037d8a6a694177cfaa2177
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The MP_IRQ flags can be used in the MP table and the ACPI MADT table.
Move them into acpi.h to avoid pulling in the full mpspec.h which is
only available on x86.
BUG=b:218874489, b:160595155
TEST=Build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f1091b7629a6446fa399720b0270556a926401a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Platform Secure Boot (PSB) enablement via the PSP if it is not
already enabled. Upon receiving psb command, PSP will program PSB fuses
as long as BIOS signing key token is valid.
Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
only available with NDA customers.
Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The postcar frame can now be a local variable to that function.
Change-Id: I873298970fff76b9ee1cae7da156613eb557ffbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Setting up postcar MTRRs is done when invd is already called so there
is no reason to do this in assembly anymore.
This also drops the custom code for Quark to set up MTRRs.
TESTED on foxconn/g41m and hermes/prodrive that MTRR are properly set
in postcar & ramstage.
Change-Id: I5ec10e84118197a04de0a5194336ef8bb049bba4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54299
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change matches what we already do for cezanne. It will allow the
GPIO controller to work correctly in windows.
BUG=b:175146875
TEST=Boot windows and verify GPIO controller binds correctly and touch
screen works. Also boot linux and verify touchpad still works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
mcfg->usb_phy is a pointer to a struct usb_phy_config. The config is
constant. Changing a constant is undefined behavior, so create a local
static instance of usb_phy_config that can be modified safely.
Change-Id: Iedbc49109dcd1da9198fcb2a8f84e2b567cd8f86
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64130
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add and use defines instead of magic values in fsp_m_params.c. The
values will be updated to match the Sabrina FSP in a follow-up commit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I91da9e9d2b95e169dd73153766f24cf8afbfa4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64128
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use sizeof instead of having a hard-coded struct length.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3c39d770a7719e30572e71b6a6c24fa2ad4a9426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The bootblock.elf file gets embedded in the BIOSPSP part and loaded by
the PSP in dram. The top aligned bootblock in cbfs is unused.
Tested on Cezanne/Guybrush.
Change-Id: I72f0092e0e3628b388f6da6a417c2857a510b187
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The first target for the add_intermediate targets is always
$(obj)/coreboot.pre.
Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This avoids compiler warnings on 64bit builds that complains about
casting pointer to non matching integer size.
Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 198cc26e49 (soc/amd/common/block/
psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are
accessed. Since the new method doesn't need to rely on a MMIO base
address to be configured, the read will always be successful and so
soc_read_c2p38 doesn't need to return an error status and can directly
return the value instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The eSPI decode range defines aren't and shouldn't be used directly from
outside of the common AMD eSPI code which provides functions to abstract
the register access, so move the defines from amdblocks/espi.h to
espi_def.h inside the common AMD LPC/eSPI support directory to limit the
visibility. The special I/O range decode bits need to stay in
amdblocks/espi.h since those are used in the devicetree. Also update the
indentation in espi_def.h so that the defines line up properly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64053
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those
registers are however not in one block where it's easy to calculate the
addresses of a register from the index of the decode range. Within one
group of decode range registers it's still easy to calculate the
register address, so move the base address from within the macro to the
instantiation of the macro as a preparation for adding the support for
the additional ranges.
TEST=Timeless build results in identical binary for Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id309d955fa3558d660db37a2075240f938361e83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to
access the PSP mailbox registers, switch to using the SMN mapping of the
PSP mailbox registers. The PSP SMN base address is taken from the amdgpu
driver in the Linux kernel.
BUG=b:229779018
TEST=Mandolin still boots successfully and there are no errors/warnings
about possibly PSP-related things.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CORE_2_PSP_MSG_38_OFFSET and CORE_2_PSP_MSG_38_FUSE_SPL are only used in
psp_gen2.c, so move them into this file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
I find it difficult to constantly decode the registers when reading
them. Let's print out something that's easier to parse.
BUG=b:228289365
TEST=boot guybrush and see status codes printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Silently failing makes it hard to debug when something goes wrong.
BUG=b:228289365
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Drop struct pspv2_mbox and access the PSP mailbox via their offsets into
PSP MMIO region.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib665d7ae19deae07d6a69c11ba8cf44e45ea4e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63966
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't use unnamed redefinitions of the pspv2_mbox_command union when the
union definition can be used instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3757db45272f11bb47e5106ad9054c0a9ca0cd52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The pspv2_mbox struct contained an unnamed union that covered the 32
bits of the command register of the PSP v2 mailbox. Since the pspv2_mbox
struct is mainly used for hardware register accesses and the union part
is mostly used to access the different bits before/after writing/reading
the command register, split this functionality. For the register access
a command field is added to the pspv2_mbox struct instead of the unnamed
union and for accessing the separate bits of the command register a new
named union is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3f00b6fd73c3f749154b77b940e6d5aa385ec49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The cmd_response field in the pspv2_mbox struct is the buffer used to
pass data to the PSP and back to the x86 side, so rename it to buffer.
This also aligns the code a bit more with the reference code. Also
rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those
definitions from the common psp_def.h to the specific psp_gen[1,2].c
files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Sabrina added the ALERT_ENABLE bit. Set it to enable the eSPI_ALERT#
line.
BUG=b:227282870
TEST=Boot skyrim and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2a193ca454692bf13b707401079bd9edf026ef5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This bit is new on sabrina. We need to enable it after initialization
has completed.
BUG=b:227282870
TEST=Boot skyrim to OS and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I795275993589e20c1d09674232ecff782c491335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We don't currently have ALIB plumbed through. Disable the ALIB call to
remove ACPI errors during boot.
BUG=b:228496169
TEST=Boot skyrim and no longer see ALIB errors
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad45bcda326597ebfc8b9c403de5b4a934b0bbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63841
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.
Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PSP verstage can start at address 0 and use 200KB of PSP SRAM for
execution. Modify both the PSP SRAM start address and size for use by
PSP verstage.
BUG=b:220848544
TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands.
Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command
ID) with individual subcommands and the corresponding parameters.
BUG=b:220848545, b:217414563
TEST=Build the Skyrim BIOS image with PSP verstage enabled.
Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Commit 3e1943ec46 (soc/amd/cezanne: Force
resets to be cold) forced all resets on Cezanne to be cold resets to
work around a bug. Since the bug is fixed on Sabrina, this workaround
copied over from the Cezanne code isn't needed here, so sort-of revert
what the patch referenced above changed for Cezanne in the Sabrina code.
BUG=b:229105416
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I785e43124a9a969eeb129454e6e15dc245625250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
PSP needs SPL file to boot. Introduce the support to add SPL file.
Currently Sabrina does not have a specific SPL file. Use Cezanne SPL
file as a placeholder.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL
file.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63313
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Chause doesn't get to x86 bootblock without the SPL table binary in the
PSP directory table, so I assume that Majolica won't get to x86
bootblock either, since the Cezanne SoC default is not to include any
SPL table binary. This was caused by a combination of
commit 6c5ec8e31c (amdfwtool: Add options
to support mainboard specific SPL table) that caused a regression in
amdfwtool and commit c5b912f788
(soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that
removed the default for the Cezanne SoC. Fix this by adding the default
SPL table file back to the fw.cfg file which will get ignored by
amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another
SPL table binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since Sabrina uses the image slot header (ISH) that depends on the AMD
A/B recovery scheme that depends on the multi-level PSP directory
support, the multi-level support gets automatically selected by passing
Sabrina as SoC name to amdfwtool, so passing the --multilevel command
line switch to amdfwtool isn't needed.
TEST=Timeless build results in identical binary for chausie
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The fch_i23c_pad_init implementation was written without looking at any
reference code and turned out to not work properly on hardware. Before
this function writes to the MISC_I23C_PAD_CTRL registers, the value read
back is 0x3000003c which results in the I2C bus communication to work
while the 0x300003fc the code writes to the register breaks the I2C
communication. Removing the code that sets bits 6..9 fixes the I2C bus
communication.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Contradicting the PPR #57243 version 1.56, the I2C3 pad control register
in the MISC ACPIMMIO region is the same new I23C pad type as the
corresponding registers for I2C0..2 and not the older I2C pad control
register type used on Picasso and Cezanne. All I2C pads being of the new
I23C type is in line with the GPIOMUX settings for the pins used by
I2C0..3 that can alternatively connect the pins to an I3C controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19
and 20 is the I3C3 controller and not the I2C3 controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9688f1816aa840c64441495ed451997a474b306f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When masking out bits with an and mask, the bit mask needs to be
inverted.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63222
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the
PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers
both bits 6 and 7.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86 ramstage is always relocated at runtime in cbmem so there is no
need to have this configurable in Kconfig.
Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the amdfwtool support for Sabrina is in place, change the
SoC name parameter passed to amdfwtool from Cezanne to Sabrina.
The fw.cfg file still points to the Cezanne binaries, but since
commit 9cb0a05dfb (soc/amd/sabrina: Add
prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig
config file in the build. As soon as the Sabrina PSP binaries are
available in 3rparty/amd_blobs, the fw.cfg file will be updated to use
the correct ones for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the
Cezanne Kconfig, so drop this from the Sabrina makefile.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The way to select the pads has changed from Cezanne.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI
Decode register. Add a config to choose between clearing the entire ESPI
Decode Register vs retaining the port80 enable bit.
BUG=None
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The Sabrina microcode update files are 3200 bytes large and not 5568
like it is the case on Cezanne where this file was originally copied
from.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Fixes building with clang.
Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
TEST=builds
Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SMMINFO is already set up in S5, so it should be skipped in S3 resume
BUG=b:194990818
TEST=Build guybrush
Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This will allow configuring the concerned config through an external
defconfig file.
BUG=None
TEST=Ensure that AMDFW_CONFIG_FILE is configurable.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.
The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.
Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B
recovery. Both bootloader can be put in the fw.cfg. The amdfwtool
decides which booloader is dropped in the directory.
Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
On boards where PSP uses ESPI to write postcodes, update the verstage to
do it after ESPI initialization.
BUG=b:224543620
TEST=Build and boot to OS in Nipperkin. Ensure that there are no
attempts to write the post code from PSP verstage before ESPI
initialization.
Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mohan Viswanathan
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Despite the SMBus device being function 0 of the FCH PCI device, the
MMIO resource of the FCH IOAPIC is on the LPC device which is function 3
of the same PCI device, so move the FCH IOAPIC initialization code to
the LPC device. Since the HPET was enabled in the same function, also
move it to the LPC device initialization.
TEST=On Mandolin both IOAPICs are still correctly detected by Linux.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Some counters are not being initialized and are relying on mainboards to
set their values. If the mainboards have not implemented these
functions it leads to indeterminate behavior.
BUG=b:224987813
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The current SMM framework only allows the mainboard code to handle GPEs.
i.e., Events 0 - 23. This change allows the mainboard code to handle any
SMI events not handled by the SoC code. This will allow the mainboard
code to handle `SMITYPE_ESPI_SMI`.
BUG=b:222694093
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.
replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.
I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.
BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Log the platform boot mode reported by PSP verstage to PSP stage 1
bootloader. This helps to improve the debuggability.
BUG=b:193050286
TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot
mode is logged in the verstage logs.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I752ee56f2af48215a770d799432d02f0609757cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to
clarify that this isn't the address the SPI flash gets mapped, but the
address of the SPI controller MMIO region. This also aligns the register
name with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In the northbridge's and root complex' read_resources function, the
GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index
which might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed)
After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8061364879d772469882fc060f92676de6f600a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In the northbridge's and root complex' read_resources function, the
mmconf resource used the number of the MMIO_CONF_BASE MSR as index which
might be misleading. Instead use idx++ as a unique index for this
resource.
TEST=Resource allocator doesn't complain and no related warnings or
errors in dmesg. The update_constraints console output changes like
expected:
Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed)
After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Picasso with Cezanne and Sabrina. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=Mandolin still boots successfully to Linux desktop and dmesg
doesn't show any any possibly related problems.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since we want to read the non-x86 CBMEMC from SMM we need to be stricter
on where we read from. This change forces the verstage binary and x86
code to agree on the CBMEMC transfer buffer location and size.
BUG=b:221231786
TEST=Boot guybrush and verify verstage transfer buffer still ends up in
cbmem
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We don't need to force the caller to look up and cast the transfer
region. We can do it in the function.
BUG=b:221231786
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
I want to reuse the transfer buffer methods in SMM, so I need to add
them into their own file. I renamed `setup_cbmem_console` to
`replay_transfer_buffer_cbmemc` so it has a more descriptive name. I
also fixed the comment on `verify_psp_transfer_buf`.
BUG=b:221231786
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We need to save the transfer buffer so we can transfer the cbmem
console and timestamps into x86 DRAM.
BUG=b:221231786
TEST=Boot guybrush and verify S0i3 resume works. Also dumped the
transfer buffer from the OS and verified the console contents got
transferred.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
If an AMD FSP binary has no valid image revision information, print a
warning instead of an error.
Change-Id: Ie9c5a387b81205fe93382778090260e41e261776
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We print these out in the normal flow, so lets add them for S0i3 resume
as well.
BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This feature was never used. Let's remove it to keep things simple.
BUG=221231786
TEST=Boot test guybrush and morphius and verify transfer buffer is
correctly passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000,
so define this once in arch/x86 and include this wherever needed. The
old AMD AGESA code in vendorcode that has its own definition is left
unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common
definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0".
So set it correctly for treewide.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Lance Zhao
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't
set so that the HPET_ADDRESS Kconfig option will have the right default
value. Instead check if the HPET_ADDRESS Kconfig value matches the
HPET_BASE_ADDRESS define in the SoC code which is the case if
HPET_ADDRESS_OVERRIDE isn't selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC-specific I2C code and header file have been verified some time
ago, but it seems that I forgot to remove the corresponding TODOs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.
Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.
For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.
Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
Additionally, fixed SoC configs inclusion order alphabetically.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Compiling efs_fmap_check.c depends on fmap_config.h already being
generated, so add this dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Also add the Makefile dependency on the fmap_config.h file to make sure
that this file already exists when it's included.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP. An example of
implementation within Linux kernel is available [1].
There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated
driver on OS side can bind to it and handle this special setup. Since
PSP takes care of I2C controller power management, we need to remove
PowerResource object from DSDT.
BUG=b:204508404
BRANCH=guybrush
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The and-mask passed to the gpio_update32 call needs all 32 bits to be
set to ones. When building as 32 bit binary the -1UL will result in the
needed bit mask, but for a 64 bit build the constant would have 64 bits
set to ones which then gets truncated to 32 bits causing a compiler
error. Use 0xffffffff as bit mask instead which behaves correctly in
both cases and also clarifies what this is doing.
TEST=Timeless build for Chausie results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes a build failure when trying to build the code in 64 bit mode.
TEST=Timeless build for Chausie results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add PSP command to send SPL fuse command if PSP indicates SPL fusing
is required. Also add Kconfig option to enable sending message.
BUG=b:180701885
TEST=On a platform that supports SPL fusing. Build an image with an SPL
table indicating fusing is required, confirm that PSP indicates fusing
required and coreboot sends the appropriate command. A message indicating
PSP requested fusing will appear in the log: "PSP: Fuse SPL requested"
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
The gen2 ACP register definitions and locations are different from
previous models. Specific code is refactored into acp_gen1 and acp_gen2.
Update ACP register locations and definitions for gen2.
Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC
talk to each other via the system bus, there is no longer the
requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that
start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2
as the IOAPIC ID while most of their CPUs have more than 2 logical cores
resulting in the IOAPIC having the same ID as one of the LAPICs.
All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and
GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT
and IVRS ACPI tables and there's no MPTable support for those SoCs that
might also rely on those IDs being consistent.
This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID
from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes
sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a
CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4
bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of
IOAPIC IDs, this is non-standard.
TEST=AMD Mandolin and Google Liara still work.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
FCH_UART_ID_MAX == 2, and there are 2 UARTS, so we don't need the -1.
BUG=b:215599230
TEST=Build guybrush
Found-by: Coverity CID 1469611
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5f0171ed2d3da7f86ba3cfd0457f60d2d5722625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61869
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor existing acp code into acp_gen1 variant as preparation for gen2
variant in sabrina.
Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Check if FSP binary and coreboot FSP structures (fspmupd.h) match
sufficiently.
A change in minor number denotes less critical changes or additions
to the FSP API that still allow for the boot process to proceed.
A change of the AMD image revision major number will halt boot.
The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD
Picasso, Cezanne and Sabrina APUs.
BUG=b:184650244
TEST=build, boot and check fsp image revision info. Example:
FSP major = 1
FSP minor = 0
FSP revision = 5
FSP build = 0
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Introduce and use functions to translate eSPI IO/MMIO decode range IDs
into the corresponding register bits and the IO/MMIO range and size
register IDs into register offsets. This is a preparation to support the
additional eSPI decode ranges on Sabrina where not all enable bits and
base/size registers for one type of decode ranges are consecutive.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This aligns the register names more with the PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On systems that use the first 128kByte of the SPI flash for the EC
firmware, it is not possible to place the EFS/amdfw part at the lowest
location in flash where the on-chip PSP firmware will look for the EFS,
since this is at an offset of 128kByte into the flash which is where the
cbfs master header resides when the main CBFS is placed right after the
EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION
option that allows putting the EFS in a separate FMAP section that can
be located right after the EC firmware FMAP section. The EFS FMAP
partition is checked to ensure it begins at the expected location.
Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to
configure the PCI MMCONF base address.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Now that PSP verstage can directly write to the UART, we no longer need
to manually dump the cbmem contents.
Ideally if we can get picasso to add support for mapping the UART, or
if we implement bit banging we can delete this functionality
completely.
BUG=b:215599230
TEST=Boot guybrush and verify verstage logs aren't printed twice
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id70b24625c3b2f3d6fe470cf227a0083f5b974f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This will allow PSP verstage to write logs to the serial console. We
are no longer dependent on using a serial enabled PSP boot loader.
Ideally we would delete this psp printk and use the standard printk.
Since picasso doesn't currently support mapping the UART though, I'll
keep it for now.
BUG=b:215599230
TEST=Boot guybrush and verify PSP logs are output on serial console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The Sabrina PSP doesn't support mapping the UART, so add a dummy
function to return NULL.
BUG=b:215599230
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The Picasso PSP doesn't support mapping the UART, so add a dummy
function to return NULL.
BUG=b:215599230
TEST=Build and boot morphius
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This will allow directly using the UART console. On PSP releases that
don't support mapping the UART, we will just return NULL which is
perfectly acceptable.
BUG=b:215599230
TEST=Boot guybrush and verify verstage can print to the console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic8d7f0fe00794a715756f92e3fb32c6b512cb8aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61607
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the console system itself will clearly differentiate loglevels,
it is no longer necessary to explicitly add "ERROR: " in front of every
BIOS_ERR message to help it stand out more (and allow automated tooling
to grep for it). Removing all these extra .rodata characters should save
us a nice little amount of binary size.
This patch was created by running
find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';'
and doing some cursory review/cleanup on the result. Then doing the same
thing for BIOS_WARN with
's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi'
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.
BUG=b:216096562
Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina is compatible with the common AMD UART block and also with the
DRIVERS_UART_8250MEM_32 driver it selects.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU
code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This comment was added with the AMD family 15h Trinity IOMMU support in
commit 88ebbeb7e2 and looks like a copy of
the comment about the subtractive decode ranges in the LPC device. The
IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this
is also not what the code does. This resource is the MMIO region to
configure the IOMMU instead, so fix the comment in all copies of the
IOMMU support code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina is compatible with the common AMD ACPIMMIO function block
mapping and access functions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I890375654a9cb1156e481c5586007ac81ab84120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The PM2 ACPIMMIO region should only be accessed with 8 bit accesses.
Using 16 or 32 bit read accesses will return the data from the first
byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in
only the first byte being written which is both unexpected behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge
and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on
Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is
only defined for Sabrina. Since the default value of undefined bits is 0
it isn't a problem to have descriptions for reserved reset status bits
on some SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sabrina has no SATA controller, so remove the corresponding PIRQ
mapping. This was verified with PPR #57243 Rev 1.53.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The common AMD data fabric register access code is valid for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97fb2c6006c09297584845a83342e75058d35713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The common AMD SMU code and the common AMD SMN access code that gets
selected by the common SMU code are valid for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The common AMD FCH AOAC bit definitions and helper functions are correct
for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Sabrina uses an identical I2C controller as Picasso and Cezanne. Also
both the type and version read-only register of the I2C controller
contain identical values.
The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are
defined in the dw_i2c_regs struct in the common Designware I2C code
aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since
common DW I2C code doesn't access those, this is no problem.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V
and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the
existing I2C pad control registers the bit definitions are different, so
add a separate function to configure those pads which however still has
the same function signature and is compatible with same data structs
used for the devicetree settings. PPR #57243 Rev 1.50 was used as a
reference.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The I2C pad control registers of Picasso and Cezanne are identical and
the one of Sabrina is a superset of it, so factor out the functionality.
To avoid having devicetree settings that contain raw register bits, the
i2c_pad_control struct is introduced and used. The old Picasso code for
this had the RX level hard-coded for 3.3V I2C interfaces, so keep it
this way in this patch but add a TODO for future improvements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
No mainboard in the current tree implements mainboard_i2c_override. In a
follow-up commit the i2c_pad_control struct is introduced to be able to
make more parameters controllable by devicetree settings in the future.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This flag only controls eSPI init in the PSP Stage 2 Boot Loader. It
doesn't control if port 80s are written. This flag also doesn't
currently control LPC init. The PSP is currently hard coded to remove
any LPC init.
BUG=b:215425753
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idf3f0dcc216df2fd15b016f9458a208b7e15c720
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add platform_report_mode function which report current developer mode
status to the PSP. L1 widevine app in the PSP will use this information
to select key box.
BUG=b:211058864
TEST=build and boot guybrush
TEST=build picasso chrome os boards
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Commit 86302a806c (soc/amd/{common,
cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig
option before the initial commit that added soc/amd/sabrina as copy of
soc/amd/cezanne landed in the tree, so port the change forward to
Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding mainboard design guide was used as a reference here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SMU message response register was moved compared to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie384de52b1efb1d52f9018315a4b72916a4c9cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The Sabrina SoC doesn't have the PM_ESPI_CS_USE_DATA2 bit defined in the
PM_SPI_PAD_PU_PD register. It also doesn't have a physical LPC interface
any more, so there are no LPC pins that can be reconfigured as eSPI
interface.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I02bc8d007901c71942475fe707637c5da7227230
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The CPPC feature isn't available on the Sabrina SoC, so drop the
corresponding code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71a1b0717571729ebca3600ac433e621cafc4e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There are no SATA controllers on the Sabrina SoC. The UPD field will be
removed later as a part of the initial UPD header update.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Some of the names have slightly changed in the PPR, but I kept the
current names for consistency across all AMD SoCs in coreboot. Revision
1.50 of the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bda656015858a57e221b8d7819f944c21564a39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0
fabric ID than Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Since we don't need to support PCI ID remapping for finding the correct
VBIOS binary for the integrated GPU, graphics.c can be dropped for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd5b678f472b3b5888353efd057203eb641be874
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Sabrina is family 17h model A0h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I01e02e3491fb90941c767058986da876bdf7ca1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of
the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The GPIO and GPIO MUX mapping as well as some GPIO to GEVENT mappings
have changed compared to Cezanne. Sabrina also doesn't have a remote
GPIO bank. Revision 1.50 of PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabb85a3d24c881055e94400d08d01505df44a07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This code is common to at least all Zen-based APUs (Picasso, Cezanne,
Sabrina) and is also useful outside of the SoC-specific dynamic ACPI
table generation code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-by: Eric Peers <epeers@google.com>
The VERSTAGE region is only needed when running verstage in the x86.
This change reduces the early ram size by 512 KiB when using PSP
verstage.
BUG=none
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I45ce421397807dbb1eb48aedd05209b91e89aa4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The FSP gets these values from the UPD and sets the internal values.
The document about eDP tuning is attached in issue tracker of this
ticket, at the issue tracker b/203061533#comment6.
BUG=b:203061533
Cq-Depend: chrome-internal:4303901
Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Compared to Cezanne there are 3 more UARTs controllers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Compared to Cezanne there are 3 more UARTs with DMA controllers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a3d255bb4976a55623f3a161e791e80f1d01c69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Let's increase this to avoid losing any logs.
BUG=b:213828947
TEST=Boot guybrush and no longer see
*** Pre-CBMEM romstage console overflowed, log truncated!
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3258145e352af3a75893c7cc96f36eb238c99abb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added
in commit 27b02c2eee (include/device/
pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC).
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Document #55758 Rev. 1.13 says that family 17h models 30h-3Fh and later
use the spi_readmode_f17_mod_30_3f struct element for SPI_MODE_FIELD and
spi_fastspeed_f17_mod_30_3f for SPI_SPEED_FIELD, so also use this for
The AMD Sabrina SoC which is family 17h models A0h-AFh.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I336f9ea4a0defdf34e1af4b6d568cfe46488f75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The Cezanne SoC code was initially started as a copy of example/min86
which only provides enough code to make the SoC code build. Then the
different parts of the real SoC support was brought in patch by patch
which also helped cleaning up and untangling the code. Since the Cezanne
SoC code is now in a rather good shape and the Sabrina SoC is similar to
the Cezanne SoC from the coreboot side, the new SoC support is started
with a copy of the Cezanne code and all the needed changes will be
applied on top of that. In order for the build not to fail due to
duplicate files, this patch does not only copy the directory, but also
replaces most instances of the Cezanne name with Sabrina. Since the
needed blobs aren't available in the 3rdparty/amd_blobs repository yet,
the Cezanne blobs are used for now so that the build will succeed. As
soon as the proper blobs will be available in that repository, the code
will be switched over to use them.
As suggested by Nico, I added a "TODO: Check if this is still correct"
comment to the beginning of every copied file and all SOC_AMD_COMMON_*
Kconfig option selects which will be removed after re-verifying that
each file and each selected common code block is still correct for the
new SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change splits the size of the console transfer region and size of
the bootblock/romstage Pre-RAM console region. This allows having a
larger Pre-RAM console while not impacting the size of the PSP verstage
console.
Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in
`setup_cbmem_console`, I chose to use the offsets provided in the
transfer buffer. It would be nice to eventually do this for all the
fields in the transfer buffer.
BUG=b:213828947
TEST=Boot guybrush and verify verstage logs are no longer truncated
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This implementation is the same for all SoC that select
SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR
CPU support code folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will verify that signed verstage binaries and the bootblock code
executing agree on the transfer buffer struct size.
BUG=b:213828947
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I597e38fe0a37416ffd3bc01fd974fa8f6610a88c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses
some of the registers directly.
BUG=b:183149183
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since we need the GPIO defines in the devicetree settings, include
gpio.h in each SoC's chip.h file which will indirectly include the
soc-specific soc/gpio.h header instead of having it indirectly included
via soc/i2c.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The existing common AMD SoC code supports some of AMD Family 17h Model
A0h SoC's PCI devices that however have different PCI IDs. Add the new
PCI ID defines to the PCI ID lists of the common PCI drivers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
uintptr_t is defined in stdint.h which gets included by types.h. I use
types.h instead of stdint.h, since that's also what the Picasso code
does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id3d0811d831b5acc9343398f4d28c73467c0a429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Define the register offsets and bits in a separate header file instead
of in the middle of the .c file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In espi_wait_channel_ready the return value of espi_get_configuration
didn't get checked before. In the case of the espi_send_command call in
espi_get_configuration returning CB_ERR, espi_get_configuration didn't
write to the local config variable, so if this happens in the first pass
of the do-while loop, the following espi_slave_is_channel_ready call
would use the uninitialized local config variable as parameter. Fix this
by checking the return value of espi_get_configuration.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use enum cb_err as return type of all remaining functions that only
return success or failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Use enum cb_err as return type of all functions that aren't exposed
outside of this compilation unit. The checks if a function has returned
a failure are replaced with checks if the return value isn't CB_SUCCESS
which is equivalent if only those two values are used, but also detects
a failure if any unexpected value would be returned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The intermediate ret variable isn't needed. espi_open_generic_io_window
only returns 0 or -1, so if ret is != 0, it has to be -1. This is a
preparation to use the enum cb_err type for the return values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
