- Add support for ME Soft Temporary Disable Mode. In this mode, ME
doesn't load its kernel and freezes at Bring UP (BUP) phase. This mode
is saved in ME NVRAM (and thus will remain for next reboots and
poweroffs).
- Add support of new CMOS option for Sandy Bridge and Ivy Bridge
ThinkPads.
HOW TO USE
To disable ME:
1. nvramtool -w me_state=Disabled
2. reboot
To enable it back:
1. nvramtool -w me_state=Normal
2. reboot
To check current status:
intelmetool -m
Tested on ThinkPad X230 and ThinkPad X220.
BACKGROUND
There's no Intel documentation that would explain how this should be
implemented, in public. Working binary sequence for MKHI command to put
ME in Soft Temporary Disable Mode, as well as a way to bring ME out of
it (by writing to H_GS register), was found and published by researchers
from PT Security:
1. To disable ME, BIOS issues the disable command (before End of Post)
and reboots. ME is supposed to be disabled on the next boot after
DID (DRAM Init Done).
My numerous tests show that issuing the command and rebooting is not
enough. If we reboot too early, ME will not be disabled. Apparently,
it is doing something in background after receiving the command. It
works with a delay of 500-1000 ms.
I also tried to dump all known (documented) registers, such as GMES
and HFS, before and during the next 2 seconds after execution of the
disable command to find a possible indication that something's
changed in ME and we're ready to reboot. Found nothing
unfortunately.
2. To enable ME back, host writes value 0x20000000 to H_GS.
PT slides don't contain any more information on it, but my tests
show, that after writing this value, GMES[31:28] is changing from
0x01 (BUP phase) to 0x03 (Policy Module) to 0x06 (Host
Communication). Then, after some more time, fw_init_complete bit of
HFS becomes 1.
This means that ME starts loading its kernel immediately, without
reboot.
On the other hand, Lenovo BIOS clearly perform a reboot after
enabling it (one reboot after saving the settings, then ThinkPad
logo appears, and then one more reboot). I'm assuming we have to
reset too.
Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These accessors can be reused for several other northbridges.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ia16ccc63dddebf938f4e9a7f5518e4d25d3e7e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49748
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Add Kconfig option to hide the Management Engine Interface device so
the OS doesn't try to access it, if the Management Engine is in an
inoperable mode, e.g. if me_cleaner is used.
- Also hide the MEI if the ME is in Soft Temp Disable mode.
Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e
Signed-off-by: James Ye <jye836@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.
They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.
It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.
Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is the same for all three mainboards.
Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Was copied from bd82x6x and none of the PCI IDs matches that of Ibex
Peak (PCI_DID_INTEL_IBEXPEAK_HECI1 = 0x3b64). Remove the code. This
allows dropping the me_8.x.c dependency, which never made sense.
Change-Id: I54df1e080048c0599dbee687ec617fb724cb6634
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use proper types in readXp functions, define `PCH_THERMAL_DEV`, clean up
comments a bit, and use `RCBA32_AND_OR` instead of read32/write32.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I95e054d6e52706e06e313068e61484f6cb9a64e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50038
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch defines default value for ME_REGION_ALLOW_CPU_READ_ACCESS config.
It sets value 'y' if CSE Lite SKU is integrated, otherwise value 'n'. The
config ME_REGION_ALLOW_CPU_READ_ACCESS ensures host has read access to ME
region when the LOCK_MANAGEMENT_ENGINE is enabled and CSE Lite SKU is
integrated.
TEST=Verified build for JSL
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I680a23e27ae2bf4d85bf919134c47882f308af56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.
More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a common place where acpigen generates these,
so the declarations for the OperationRegions should be
centralized too.
Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
APIC was not referenced anywhere in ASL.
MPEN has references under boards:
getac/p470, roda/rk9, roda/rk886ex.
MPEN has reference also in Intel SpeedStep ASL.
Replace static MPEN with detection of multiple CPUs
installed.
Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.
Remove the PCNT name from GNVS OperationRegion elsewhere.
Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
They all operate on that file, so just add it globally.
Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that intermediate coreboot.pre manipulation is serialized within
the build system, remove the flock calls.
Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To allow other platforms to reuse this code, extract it into a separate
compilation unit. Since HPET is enabled through the southbridge, place
the code in the southbridge scope. Finally, select the newly-added
Kconfig option from i82801gx and replace lpc.c `enable_hpet` function.
Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying
the file in some way. When running them in parallel, coreboot.pre can be
read from and written to in parallel which can corrupt the result.
Add a function to create those rules that also adds existing
INTERMEDIATE targets to enforce an order (as established by evaluation
order of Makefile.inc files).
While at it, also add the addition to the PHONY target so we don't
forget it.
BUG=chromium:1154313, b:174585424
TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2
timeout and sercon) and saw that they were executed.
Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While unused, this allows use of a common initialisation
code for GNVS allocation.
Change-Id: Ie84b5a3e16d3baa12bcd5dadac0b1f7edb323272
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The S3/S4 workaround is specific to Panther Point stepping A0, and it is
wrongly implemented. Rewrite the whole function as per reference code.
Since this runs in SMM, be overly cautious and double-check everything.
Do not rely on GNVS to determine if xHCI is enabled. Instead, check
whether the corresponding bit in the Function Disable register is set.
Only Panther Point has xHCI, so exit early if this is not the case.
Change-Id: Iabce6c52fac781dc694f5b589fab2e9fe438f3f5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.
Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a small change to follow the code style.
Change-Id: Ie838b82e12627478ea721f426efc4d557feb6ae3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49166
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Trying to do multiple operations on the same CBFS image at the same time
likely leads to data corruption. For this reason, add BSD advisory file
locking (flock()) to cbfstool (and ifittool which is using the same file
I/O library), so that only one process will operate on the same file at
the same time and the others will wait in line. This should help resolve
parallel build issues with the INTERMEDIATE target on certain platforms.
Unfortunately, some platforms use the INTERMEDIATE target to do a direct
dd into the CBFS image. This should generally be discouraged and future
platforms should aim to clearly deliminate regions that need to be
written directly by platform scripts with custom FMAP sections, so that
they can be written with `cbfstool write`. For the time being, update
the legacy platforms that do this with explicit calls to the `flock`
utility.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.
Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Structure with chromeos_acpi_t is expected to have size
0x1000. Only ones with device_nvs_t have size 0x2000.
Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The CHROMEOS option was never used with ibexpeak, code was copy-pasted
and forked from bd82x6x. Since a custom ibexpeak/nvs.h was already made,
an accompanying globalnvs.asl is added here too without chromeos_acpi_t.
Change-Id: I16406516b51c13d49593bc8a3e1e5b868eea6f24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is equivalent to `azalia_find_verb` in its current form,
so replace them. Also, adapt and move the function description comment.
Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Allow to specify which table should the verb list be read from.
Change-Id: Id1bc40c4364cda848f416bad9eeab1b8ca3e9512
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
To allow dropping copies of this function, make it non-static. Also,
rename it to `azalia_find_verb` as the function is now globally visible.
Finally, replace the copies in chipset code with `azalia_find_verb`.
Change-Id: Ie66323b2c62139e86d3d7e003f6653a3def7b5f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There's many copies of this function in the tree. Make the copy in
azalia_device.c non-static and rename it to `azalia_set_bits`, then
replace all other copies with it. Since azalia_device.c is only built
when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary.
This has the side-effect of building hda_verb.c from the mainboard
directory. If this patch happens to break audio on a mainboard, it's
because its hda_verb.c was always wrong but wasn't being compiled.
Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Using `pci_dev_read_resources` works just as well on bd82x6x (the
allocator does the same) and allows dropping the i82801gx check.
Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since common smbus.c gets built for romstage as well, create a new file
to hold this common code. Account for ICH7 not having a memory BAR, too.
Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48364
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Code was copy-pasted from older chips and has no effect on bd82x6x.
Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47099
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to make most things non-static so that the code builds. Also, we
need to update ibexpeak as well, because it borrows files from bd82x6x.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42019
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copy and paste the i82801gx code onto all newer southbridges. This will
be factored out into common code in a follow-up.
Change-Id: Ic4b7d657865f61703e4310423c565786badf6f40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is for consistency among the various southbridges.
Change-Id: Id0dcfeef6e220861212ce665201ce8cd31f3b054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The patch modifies KConfig behaviour if CSE Lite SKU is integrated into
the coreboot. When the CSE Lite SKU is integrated, the KConfig prevents
writing to ME region but keeps read access enabled. Since CSE Lite driver
checks the signature of RW partition to identify the interrupted CSE
firmware update, so host must have read access to the ME region. Also, the
patch modifies the KConfig's help text to reflect the change.
When CSE Lite SKU is integrated, master access permissions:
FLMSTR1: 0x002007ff (Host CPU/BIOS)
EC Region Write Access: disabled
Platform Data Region Write Access: disabled
GbE Region Write Access: disabled
Intel ME Region Write Access: disabled
Host CPU/BIOS Region Write Access: enabled
Flash Descriptor Write Access: disabled
EC Region Read Access: disabled
Platform Data Region Read Access: disabled
GbE Region Read Access: disabled
Intel ME Region Read Access: enabled
Host CPU/BIOS Region Read Access: enabled
Flash Descriptor Read Access: enabled
BUG=b:174118018
TEST=Built and verified the access permissions.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2f6677ab7b59ddce827d3fcaae61508a30dc1b28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Qemu i440fx does not support an smihandler at the moment.
Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a Kconfig symbol for including the PCIe MMCONF setup function in the
build and select it when SOC_AMD_COMMON_BLOCK_PCI is selected and in the
southbridges call enable_pci_mmconf(), but don't select
SOC_AMD_COMMON_BLOCK_PCI.
Change-Id: I32de7450bff5b231442f9f2094a18ebe01874ee7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47878
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Code was copy-pasted from older chips and has no effect on Lynxpoint.
Change-Id: I2c789ba48f175b3c9c9643118fc2209c94f24c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These two IDs are for Cougar Point and Panther Point, the previous
generation of Platform Controller Hubs. So, drop their device IDs.
Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.
Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
These Function Disable definitions have been copied from Cougar Point,
are not used by any mainboard, and may be incorrect. So, remove them.
Change-Id: I36f732bce22ec33aab42beababe54c4d88e0205b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46784
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to dynamically differentiate between traditional and Low
Power platforms at runtime, and doing so makes code reuse more complex.
Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 576b7c7 (broadwell: gpio.asl: Make GWAK method serialized) made
GWAK serialized for Broadwell. This commit follows suit on Lynx Point.
The reason to serialize this method is because it creates named objects
which depend on input parameters, and thus cannot be created elsewhere.
Change-Id: I892700df3bba079e3280008f619017e3954d5a06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46783
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: I0ce8f1e4aaa86d2f7607fec9214dc64d1f530c88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46782
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LynxPoint-LP handles GPIOs differently, and LynxPoint-H has the same
GPIO kind as previous-generation PCHs, such as Cougar Point. Remove some
unneeded logic from `_CRS` and declare the GPIOBASE resource statically.
The preprocessor allows later ACPI deduplication to remain reproducible.
Change-Id: If771d5b6c3a1623da7d015ed50199877615409b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46781
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order for ACPI deduplication to be reproducible, the `ISLP` method
needs to disappear. Replace the _PRW methods with a name and a macro.
Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46780
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use ASL 2.0 syntax where possible and uniformize code style to match the
IASL disassembly. Some `Store` in gpio.asl change the binary if touched.
Also remove outdated comment and remove `LynxPoint` from `serialio.asl`.
Tested with BUILD_TIMELESS=1, Google Panther does not change.
Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46777
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `sir_unset_and_set_mask` helper and update the one PCI
read-modify-write operation that is somehow not reproducible.
Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The other two modes are not used by any mainboard, and the code seems to
be copied from older southbridges. As the code looks incorrect, drop it.
Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and
setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF.
Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2.
However, current code doesn't account for this. The result is that
register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is
OBFF-capable but support is disabled, which makes no sense. Given that
reference code and Broadwell both disable OBFF, disable it here too.
Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Code does not match comment, but this time the comment is right.
Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47044
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Testing shows that these registers are backwards. Use the definitions
from Broadwell instead. All affected boards use the same value for both.
Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is already done once when enabling PMBASE in early init.
Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For all these southbridges, the lower nibble of PCICMD is read-only.
Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change.
Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.
Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Only LPT-LP includes this file, so `ISLP` is effectively constant. Thus,
eliminate some unnecessary if-blocks, since only one branch gets taken.
Change-Id: Ie8ba787bf5c021845e1e47256a6303697aa97fe1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46776
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `GWAK` method into the GPIO device, and have lpc.c include the
LP GPIO code. All usages of `GWAK` on mainboards need to be updated.
Change-Id: Id6a41f553d133f960de8b232205ed43b832a83d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46775
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename `lpt_lp.asl` and place all Lynxpoint-LP GPIO ASL there. It has
been named `gpio.asl` to ease diffs between Lynxpoint and Broadwell.
Tested with BUILD_TIMELESS=1, Google Panther does not change.
Change-Id: I7cc4ab3371014be783761f110542471a8c0157a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46774
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nothing should be using this offset.
Change-Id: Ia4736471e2ac53bec18bfe073f4aa49e3fc524a8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is merely to align ACPI files with Broadwell. It is unused.
Change-Id: I8aa297bd3c3734bbd438ff84742aadfc661adcf7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46764
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file is no longer specific to 6 and 7 series PCHs.
Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bus Master is not required and reference code does not set it.
Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore.
Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The `find_resource` function will never return null (will die instead).
Given that the existing code gracefully handles null pointers already,
it is reasonable to replace these function calls with `probe_resource`.
Change-Id: Ibd8f5ebd561cbde22ce5cd83de8270177bad1344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent.
Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46728
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of checking whether the return value equals -1, just check if it
is negative. Some Azalia implementations already do it, but most do not.
Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46727
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This sequence used to be an array of reg-and-or triplets, but can be
simplified. The resulting sequence is closer to what Broadwell does.
Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46725
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change.
Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to reinvent the wheel.
Change-Id: If6b90c9a7a00af0322c6dd15d2c4ecf2c513d0cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46977
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The last argument for acpi_fill_mcfg() is the last PCI bus, which is
an uint8_t, not the total number of busses, which overflows the
argument if CONFIG_MMCONF_BUS_NUMBER is 256.
Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.
BUG=b:154032833
TEST=Build & boot on mandolin
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.
Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45713
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Casts can be considered unary operators, so drop the space.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ib180c28ff1d7520c82d2b5a5ec79d288ac8b0cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested with BUILD_TIMELESS=1, Google Wolf does not change.
Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this
option with `EM100Pro`. Looks like it is not build-tested, however.
Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Also remove extra empty lines.
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1
Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45275
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several changes[1][2] to the Linux kernel now enable ASPM/AER for the
rt8169 network driver, for which it was previously disabled. This,
coupled with the southbridge enabling AER for all PCIe devices, has
resulted in a large amount of AER timeout errors in the kernel log for
boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino).
While performance is not impacted, the errors do accumulate.
To mitigate this, guard AER enablement via Kconfig, select it by default
(as to maintain current default behavior), and allow boards which need
to disable it to do so (implemented in subsequent commits).
This implementation is derived from that in soc/intel/broadwell.
Test: build/boot google/beltino variants with AER disabled (CB:46136),
verify dmesg log free of AER timeout errors.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=671646c151d492c3846e6e6797e72ff757b5d65e
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a99790bf5c7f3d68d8b01e015d3212a98ee7bd57
Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to make so much noise when writing IOBP registers.
Change-Id: I1fbb6e409375240544b9b5e810523f9471435f2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Broadwell does this, so do it on Lynx Point too.
Change-Id: I309f0cbf93e3f75b20cdd049d9437841ef61c03a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Both PCH types are very different, and mixing the code for both together
isn't useful. Make `ISLP` return a constant, so that IASL can fold it.
Change-Id: I6222d6661115d444d4dad0217c2d376dc551465c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45048
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both PCH types are very different, and mixing the code for both together
isn't useful. First of all, inline `pch_is_lp` to return a constant.
This allows the compiler to optimize out unused code, which results in
smaller executables. For the Asrock B85M Pro4, it's about 2.5 KiB less.
Subsequent commits will further split the southbridge code.
Change-Id: Iba904acf64096478d1b76ffd05a076f0203502f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45047
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
