This is only a qualifier between TSEG and ASEG.
Change-Id: I8051df92d9014e3574f6e7d5b6f1d6677fe77c82
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
When <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
The file and all of it's functions are unused. Drop the dead code.
Change-Id: Iaddd7a688d431d40f38293939e084d19b286aed4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enabling flashconsole on these platforms fails to build due to
spi.c not being compiled in prior to ramstage. Include in early stages
(bootblock/romstage/postcar) as needed to enable flashconsole support.
Early inclusion of monotonic_timer.c is needed for Broadwell as well.
Change-Id: Idae0578ca92939246021bb85e34b0dcbd41df3b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
With a separate verstage the romstage becomes an RW stage.
The mrc.bin however is only added to the RO COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The only functional difference is the use of stack guards.
Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As of CL:1605641, vboot2 code should be used for setting and
checking display init state. Remove all vboot1 OPROM-related
code, and use the vboot2 display init code which has already
been added in previous commits.
coreboot should not be reading vboot NVRAM flags directly.
Remove the function vboot_wants_oprom(), and instead rely on
display_init_required(), which uses the
VBOOT_WD_FLAG_DISPLAY_INIT value stored in
vboot_working_data.flags, initialized during verstage.
Note that this means in the case of CONFIG_VBOOT=y, the return
value of display_init_required() can only be trusted after
verstage has been executed. This should not be a problem
assuming that all display initialization occurs in ramstage.
BUG=b:124141368, b:124192753, chromium:948529
TEST=Build locally
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic8f9dc5a3c7f1546a8fed82bde02be4d04568f8d
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1605641, chromium:1605525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32723
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Call the raminit from a common location instead of from the mainboard
specific code.
Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To improve the bootflow, the scope of the pei_data needs to be
extended.
Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This also links the gpio configuration instead of including it as a
header.
Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name OPROM is somewhat inaccurate, since other steps to bring
up display and graphics are needed depending on mainboard/SoC.
This patch cleans up OPROM code nomenclature, and works towards
the goal of deprecating vboot1:
* Rename CONFIG_VBOOT_OPROM_MATTERS to
CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig
description
* Remove function vboot_handoff_skip_display_init
* Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY
* Add |flags| field to vboot_working_data struct
* Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff
BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
TEST=build and flash eve device; attempt loading dev/rec modes
BRANCH=none
Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch enables CONFIG_VBOOT_OPROM_MATTERS in a few more cases where
I think(?) it should be. Haswell, Broadwell and Baytrail Chromebooks
have this enabled in their old depthcharge firmware branches -- we
presumably just forgot to move it over when vboot2 migrated the option
to coreboot. Braswell didn't, but it seems like this requirement was
added when it was migrated to FSP 1.1...? (Not very sure about that one,
but it does call load_vbt() right now which executes things based on
display_init_required().) Additionally, it seems to make sense to enable
it whenever the user explicitly selects VGA_ROM_RUN in menuconfig (like
one of the Intel defconfigs does).
Once we have all this, one could take a step back and ask whether this
option still makes sense at all anymore. It's enabled for almost all
devices (that work with vboot at all), it will presumably be enabled for
all future devices, and it seems that most devices that don't enable it
use libgfxinit, which as far as I can tell isn't gated on
display_init_required() but probably should be. Realistically, whatever
kind of display init a board needs to do (native or option ROM), it's
probably expensive enough that it's worth skipping on a normal mode
vboot boot, and we'd want to have this enabled by default on everything
except boards that actually don't have a display. So maybe we should
flip it around to CONFIG_VBOOT_OPROM_DOESNT_MATTER, but doing that would
probably lead to nobody ever selecting it at all.
Not sure what the best solution there is yet, but I think this patch
at least moves things in the more correct direction.
Change-Id: Id96a88296ddb9cfbb58ea67d93e1638d95570e2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch removes all local definitions of sub_system functions and make
use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus
devices as well.
Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch removes local definitions of sub_system function and make use
of common function pci_dev_set_subsystem().
Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: Idca207b4f05d1844ce6612dbecaad6faeb68725a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Some similar calls to postcar_frame_add_mtrr() were added in the
meantime or were under review while postcar_frame_add_romcache()
was introduced.
Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some SPI controllers support both READ and WRITE protection
add a variable to the protect API for the callers to specify
the kind of protection they want (Read/Write/Both).
Also, update the callers and protect API implementation.
BUG=None
BRANCH=None
TEST=test that the mrc cache is protected as expected on soraka.
Also tried if the read protection is applied correctly.
Change-Id: I093884c4768b08a378f21242ac82e430ac013d15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.
Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently this needlessly initializes the hardware in the both the
romstage and the bootblock, but it works.
Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the
use better, related support files can be built to pre-ram stages
regardless of usbdebug being enabled or not.
Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK).
Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught
because files only build with __SIMPLE_DEVICE__ defined.
Remove cases of testing __SIMPLE_DEVICE__ in files that
are not build for ramstage.
Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The same file was replicated three times for certain
soc/intel bootblocks, yet there are no indications or need to do
chipset-specific initialisation.
There is no harm in storing the TSC values in MMX registers
even when they would not be used.
Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Platforms moved to POSTCAR_STAGE so these are no longer used.
Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).
This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.
Test: build/boot each affected platform, ensure no change in functionality
Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This does the following:
- Reuse the cpu/intel/car/non-evict CAR setup and exit.
- Use postcar_frame functions to set up the postcar frame
Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in
cpu/x86/smm.h
Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine is RAM must be reserved.
BUG=N/A
TEST=Intel BayTrail CRB
Change-Id: Ic1f5089227f802e2b2f62dc02fa0d1648c1855b5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag
- implement vboot_platform_is_resuming on platforms missing it
- add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges
[ originally https://review.coreboot.org/c/coreboot/+/28750 ]
BUG=b:114018226
TEST=compile coreboot
Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add definition for PCH_GPIO_PIRQ_INVERT, which is needed
for google/buddy, a to-be-merged variant of google/auron.
Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53]
Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.
Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.
Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.
Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190)
- Make function naming in gnvs.h consistent (start with "chromeos_")
BUG=b:112288216
TEST=compile and run on eve
Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use get_acpi_table_revision(HPET) to keep all table versions in sync.
Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in
soc, therefore just use the defaults in sb/intel/common/firmware.
Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28011
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures
Software Developer’s Manual.
The purpose is to differentiate with MSR_SMRR_PHYSx.
Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add DMAR RMRR table entry and helper functions, using the existing
DRHD functions as a model. As the DRHD device scope (DS) functions
aren't DRHD-specific, genericize them to be used with RMRR tables as
well. Correct DRHD bar size to match table entry in creator function,
as noted in comments from patchset below.
Adapted from/supersedes https://review.coreboot.org/25445
Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27269
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For cases with POSTCAR_STAGE=y this reference pulled
in the implementation of run_ramstage() which we would
not call.
Using _program results with the same region being marked
as WRPROT-cacheble.
Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26583
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent changes to field lengths in include/memory_info.h resulted in
a mismatch between the memory_info struct the MRC blob writes to and
the struct used by coreboot to parse out data for the SMBIOS tables.
This mismatch caused type 17 SMBIOS tables to be filled incorrectly.
The solution used here is to define the memory_info struct as expected
by MRC in the pei_data header, and manually copy the data field by field
into the coreboot memory_info struct, observing the more restrictive
lengths for the two structs.
Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly
populated.
Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/26598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
