They are used at most once. Use the actual values and drop the macros.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I9c1c3ebbbfa64a5eeea3bd5551c3d0068ac0dab2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55799
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Broadwell now uses the Lynx Point hda_verb.c and should thus use the
corresponding header as well.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I9b8ca91bed67be9c6850bd51f4c81e002a0f5aef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55797
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For some reason, this change makes ramstage slightly smaller.
Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55583
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These functions are never defined. Remove the unused declarations.
Change-Id: I4204265680d06bf83fc42f061fd7270ff8e3305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55798
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file only contains the `broadwell_run_reference_code()` function
prototype (either a declaration or an inline stub definition). Rename
this file to refcode.h and only include it where necessary.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55582
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
For now, the PCI devices with the ID 110a:403e and 110a:403f needs this
master bit to be set.
Change-Id: Id3f6bda97e5f47d0613a1db8f8adac0b158ab8b1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56632
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boards based on mc_ehl have, just like some mc_apl variants, legacy
devices on the PCI bus which take longer to boot. In order to ensure
that they will be enumerated correctly wait for them to come up before
PCI scan starts.
TEST=Checked that the new message is visible in the log.
Change-Id: If2f935b69ddaa9364566deacfada5e7d41fcdabd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56631
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GENMASK is defined in multiple files (with various names such as
MASKBIT), which sets certain consecutive bits to 1 and leaves the others
to 0. To avoid duplicate macros, add GENMASK macro to helpers.h.
GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For
example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000.
Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in
mmio.h.
BUG=none
TEST=make tests/commonlib/bsd/helpers-test
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
1. Replace OV5675 ACPI entries with IMX208
2. Replace FW_CONFIG name
3. Add support for NVM inside UFC
BUG=b:190674542
TEST=Build and boot to OS on Brya, raw capture on UFC
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
As per the schematics, UFC has on card oscillator so we donot need
H21 in NF1 that is IMGCLKOUT
H21 is used to enable this oscialltor so configuring it as 1
A17 is configured as high while _ON method is called by driver and
it is configured as low when _OFF method is called by driver.
Hence coreboot should configure it as low on boot.
BUG=b:190674542
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56655
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The cappy2 removed the anpec apw8738bqbi and "disable_external_bypass_vr" should be set to "1" to disable
BUG=b:194146867
BRANCH=dedede
TEST=VCCIN_AUX is disable
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ieb4182a989459db629e3b69757c293ca26e8b0cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Using Tpm2.0 device instead of the Cr50 in cappy2
BUG=b:191743435
BRANCH=dedede
TEST=tpm2.0 device function is ok
Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I216ceb6386ad57c9f1982187a4525d89869fa9c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56658
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For consistency with Haswell, rename this macro to `HOST_BRIDGE`.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Done for consistency with Haswell in order to ease unification.
Change-Id: I445f086cfcb65a6001ced3326fb9f25a4188b888
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55527
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future
commits will move the Broadwell MRC/refcode glue code to be in Haswell
northbridge scope, so plan in advance.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new IVRS kconfig option to control IVRS generation.
BUG=b:190515051
Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE.
BUG=b:194146863
BRANCH=none
TEST=check on evtest
type 4 (EV_MSC), code 4 (MSC_SCAN), value ab
type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1
type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b
type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Ic39ecb3118e885c9e6d84d7b78bf435cb903d17e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:187801363
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
A valid GEVENT number is never negative. The local variable in
set_single_gpio still needs to be a signed integer, since the return
value of get_gpio_gevent being -1 indicates that the GPIO can't generate
a GEVENT. The check for that makes the function return before calling
program_smi of program_sci, so the parameter of those functions can be
changed to unsigned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each bit in the GPIO wake status index registers is set to 1 when at
least one of 4 corresponding GPIO pins has its wake status register set.
Added the comment since the gpio_base + i * 4 in the next line looked as
if it calculates some absolute register value which is not what the code
does or should be doing.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the parameter the variable gets compared with is size_t type, use
size_t as type for that variable too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the addition of the remote GPIO support, the GPIO number won't fit
into 8 bit any more, so use the gpio_t type instead which is an uint32_t
typedef.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The offsets of all GPIOs in the up to four regular banks are all
calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the
unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO bank 3 isn't used in coreboot, but the existence is documented in
both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and
for those two SoCs all 4 banks are covered by the corresponding
Memory32Fixed region in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
WWAN (fibocom L850-GL) works in USB mode, so turn off PCIe 6.
BUG=b:194861116
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ie04a5bb2af9ce11f57339f460a7f880bfc14b688
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Sync the MemInfoHob.h with current FSP code.
BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Realtek speaker amplifiers under auto mode operation have Absolute Max
Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker
amplifier and program the VCCIOSEL accordingly.
BUG=b:194120188
TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616
Reviewed-by: Evan Green <evgreen@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Latency Tolerance Reporting is yet another PCIe power management feature
which can have a bad influence on realtime performance. Disable this
feature for all PCIe root ports.
Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
L1 substates of a PCIe link are meant to save some power when the link
is not active but have the drawback that the PCIe latency is increased
as PLLs are switched on and off as needed.
In order to get a better realtime performance, disable all substates for
every PCIe root port.
Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This variant uses I210 MACPHYs so enable the I210 driver in order to set
the needed MAC addresses. In addition add the function to retrieve a
valid MAC address for the given MACPHY.
Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All the boards based on the mc_ehl baseboard have the NC-FPGA available.
Enable the appropriate driver on baseboard level.
Change-Id: I40b76a837b7ddb70ceba3135996b1c1080170c4d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56566
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All variants based on mc_ehl will use the Siemens HWILIB. Select the
Kconfig switch on baseboard level.
Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable IBECC for mc_ehl1 to provide a memory failure protection.
Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In favor of better realtime performance disable dynamic frequency
support in the System Agent for mc_ehl1.
Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable measured boot for all boards based on mc_ehl baseboard.
Change-Id: I3aff943305c024d1f25d2127e6f60495828da3eb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
All the boards based on the mc_ehl baseboard have a TPM which is
connected to SPI but mapped into the address space of the x86 so that
it acts like a LPC attached TPM. Enable the TPM driver so that it will
be used. In addition add the needed entry in devicetree.
Change-Id: I301d0ed4a108bac45d95eced120e7ba280945d9c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
All the mainboards based on mc_ehl use the external RTC RX6110SA.
Enable the driver in Kconfig for all boards based on mc_ehl. In
addition, as mc_ehl1 has the RTC attached to the SMBus, add the
devicetree entry on behalf of the SMBus device 00:1f.4 for this variant.
Change-Id: Ie1f45d0e6f9063c00253fe58a6268d40de91cf63
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56523
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The x86 thread code is all x86_32 specific. It needs to be updated to
work with 64 bit. For now just throw an error when compiling.
BUG=b:179699789
TEST=none
Suggested-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I96187ad84bdec40c6883748afa41e217bc389b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:193898133
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
TEST=Refer to `cbmem -t` output below:
Without this code changes, timestamp ids 962 and 963 are listed as
`unknown`.
962:<unknown> 1,704,863 (157)
963:<unknown> 1,704,878 (14)
With this code changes, lists the timestamps along with the timestamp
strings.
962:calling FspMultiPhaseSiInit 1,704,863 (157)
963:returning from FspMultiPhaseSiInit 1,704,878 (14)
Change-Id: I528567e4cc630e15dffffd1c7684798fcdde4535
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56641
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure I2C high / low time in the device tree to ensure I2C
CLK runs accurately between 380 kHz and 400 kHz.
Audio codec:388.91 kHz
Touchpad:394.48 kHz
BUG=b:193864546
BRANCH=dedede
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Change-Id: Ia57c90ead44ceb0990878dc0566e595bae5a9099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56383
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
MT53E512M32D1NP-046 WT:B
MT53E1G32D2NP-046 WT:B
H54G46CYRBX267
H54G56CYRBX247
K4U6E3S4AB-MGCL
K4UBE3D4AB-MGCL
BUG=b:194766276 b:194686484 b:194765811
TEST=build
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iba019c50224be8322865eee7baf81e3a574ff9a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for ADL:
1. H54G46CYRBX267
2. H54G56CYRBX247
3. K4U6E3S4AB-MGCL
4. K4UBE3D4AB-MGCL
BUG=b:194686484 b:194765811
TEST=build.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add Charger Performance Control table TCHG for DPTF setting.
BUG=b:194256990
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.
Change-Id: I9dba3f0e75d07d8ee9656bd1ee8d6de2d3b8c152
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Paul F Yang <paul.f.yang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
According to the schematic diagram of proto, modify the clock of nvme
from the baseboard default to src0.
BUG=b:194487277
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I41be517b434513bca2332ec37e54f56910302bb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 4c569b52f6. This has
introduced a regression in mainboards using JSL SoC such that it
overrides the soft straps for all the GPIOs. This in turn has led to
some of the peripherals not working.
BUG=None
TEST=Build and boot to OS in Storo. Ensure that the regressed
peripherals are working back again.
Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit ce79ceec86. This has
introduced a regression in mainboards using JSL SoC such that it
overrides the soft straps for all the GPIOs. This in turn has led to
some of the peripherals not working.
Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use bit-wise and logical operators instead of their equivalent methods.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I30807e14b2a9a8203a76d418f586423bcaec2a3a
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use `FOOO[1337]` instead of `Index(FOOO, 1337)`.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I4f5d5cb8ce8c3ae37dc44ca87bd67596af9feee8
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The GPE offset of 16 is PCH specific.
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the
same.
Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add wifi sar for magister.
Due to fw-config cannot distinguish between magolor and magister.
Using sku_id to decide to load magister custom wifi sar.
BUG=b:192290227
TEST=build and test on magolor/magister
Cq-Depend: chrome-internal:3986580
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4510cc2ad42a11ec802ecd439b353f8e87d63868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake.
BUG=b:191691430
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch adds device tree settings to control pcie modphy tuning
FSP UPDs. With this patch, the pcie modphy can be tuned per board.
BUG=b:192716633
BRANCH=NONE
TEST=build dedede variant coreboot with fw_debug enable and check if
these settings have been changed successfully on fsp debug log.
Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
LTE module L850-GL may encounter U3 wakeup race condition with the host.
Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not
miss the device-initiated U3 wakeup thus avoid the race condition.
BUG=b:191426542
BRANCH=dedede
TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
This symbol is only used in generating a default fmap.
Change-Id: I8d92eba9978cdad5795b0f5755e1d75db7b3cb2d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the specification isn't very clear on this, add a comment about
the optional raw data part of a acpi_generic_error_status block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6df7d2f216fe0515e89d08c8ed01f06d19461429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since current AMD SoCs don't need some wait time between INIT and SIPI,
we can skip the 10ms wait there, which improves the boot time a bit.
before: CPU_CLUSTER: 0 init finished in 632 msecs
after: CPU_CLUSTER: 0 init finished in 619 msecs
mpinit still works on Mandolin and all CPU cores show up and are usable.
This also doesn't change the binary in a timeless build for boards/SoCs
that don't select X86_AMD_INIT_SIPI which I verified for lenovo/x230.
BUG=b:193885336
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e044776f45021742a88a5e369a74383c1baaab6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.
Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove redundant type, prompt and help text, and replace `depends on`
clause with conditional default to allow specifying a FMAP when vboot
is not selected.
Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to an issue in sconfig, move `chipset_lockdown` out of
`common_soc_config` and configure it separately in the baseboard's
devicetree since it might get overwritten if a variant configures
`common_soc_config`.
Also, deduplicate the configuration of `chipset_lockdown`.
Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.
Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change does the following:
* Pushes the cpu_info struct into the top of the stack (just like
c_start.S). This is required so the cpu_info function works correctly.
* Adds the thread.c to the romstage build.
I only enabled this for romstage since I haven't done any tests in other
stages, but in theory it should work for other stages.
BUG=b:179699789
TEST=Boot guybrush with threads enabled in romstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e32e1c54dea0d0c85dd6d6753147099aa54b9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The alignment for `struct cpu_info` is wrong on x86_64. c_start.S uses
the `push` instruction when setting up the cpu_info struct. This
instruction will push 8 bytes but `unsigned int` is 4 bytes. By making
it a `size_t` we get the correct size for both x86_32 and x86_64.
BUG=b:179699789
TEST=Boot guybrush to the OS
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ef311aaa8333ccf8a5b3f1f0e852bb26777671c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The structure and function are not currently used or implemented. x86 is
the only arch that currently implements it. It is currently used for
COOP_MULTITASKING and mp_init.
Keeping around the unused definitions leads to confusion.
BUG=b:179699789
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0775ef03168f7f9c41b1b05cb8f12724d0458ba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
By lazy initializing the threads, if a stage doesn't use them, they will
be garbage collected.
BUG=b:179699789
TEST=Boot guybrush to the OS and verify threads worked
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7208ffb5dcda63d916bc6cfdea28d92a62435da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56532
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no reason this needs to be done in asm. It also allows
different stages to use threads. If threads are no used in a specific
stage, the compiler will garbage collect the space.
BUG=b:179699789
TEST=Boot guybrush to the OS
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5a84a62fdc75db8ef0358ae16ff69c20cbafd5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56531
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It can be nice to update the TPM firmware without having to clear the
TPM owner. However, in order to do so would require platformHierarchy
to be enabled which would leave the kernel antirollback space a bit
vulnerable. To protect the kernel antirollback space from being written
to by the OS, we can use the WriteLock command. In order to do so we
need to add the WRITE_STCLEAR TPM attribute.
This commit adds the WRITE_STCLEAR TPM attribute to the rw antirollback
spaces. This includes the kernel antirollback space along with the MRC
space. When an STCLEAR attribute is set, this indicates that the TPM
object will need to be reloaded after any TPM Startup (CLEAR).
BUG=b:186029006
BRANCH=None
TEST=Build and flash a chromebook with no kernel antirollback space set
up, boot to Chrome OS, run `tpm_manager_client get_space_info
--index=0x1007` and verify that the WRITE_STCLEAR attribute is present.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I3181b4c18acd908e924ad858b677e891312423fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56358
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Realtek speaker amplifiers under auto mode operation have Absolute Max
Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker
amplifier and program the VCCIOSEL accordingly.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Ifa0b272c23bc70d9b0b23f9cc9222d875cd24921
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Jasperlake is one of the few SoCs that support programmable VCCIO
selection and this support is used by Dedede mainboard.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: I54def27a499ccba7fd25cab1048fdca06dbc535f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56536
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the Intel SoCs with more than 2 PAD configuration registers
support programming VCCIO selection. Add a pad configuration macro to
program VCCIO selection when the GPIO is an output pin.
BUG=b:194120188
TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is
configured as expected and probing the GPIO reads the configured
voltage.
Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Verstage even fits in 44K so one can comfortably increase the
bootblock size. This is need for the followup patches that turn
console methods into drivers, which increase the bootblock a little,
but still too much for the the bootblock to fit in the alloted size on
this platform.
Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch moves the common config to the Kconfig under
BOARD_GOOGLE_BASEBOARD_BRYA and removes the redundant config.
BUG=b:191472401
BRANCH=None
TEST=build pass
Change-Id: Ie59299dfaba6bb23758d4a4c22a6dbbb4ba6520e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56387
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, BT offload is disabled/enabled unconditionally based on the
devicetree settings. BT offload uses I2S lines and cannot be enabled
when a I2S based audio daughter card is active. So we need to enable
BT offload only while using soundwire based audio daugther card.
BUG=b:175701262
TEST=Verified BT offload on brya with soundwire audio daughter card
BT offload enabled
Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
`cpu_info()` requires that stacks be STACK_SIZE aligned and a power of 2.
BUG=b:179699789
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I615623f05bfbe2861dcefe5cae66899aec306ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
thread_run_until is a ramstage specific API. This change guards the API
by checking ENV_RAMSTAGE.
BUG=b:179699789
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4784942070fd352a48c349f3b65f5a299abf2800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56529
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
- The WWAN card was being disabled later than desired.
- The SD card was never being placed into reset on BoardID 1.
- Enable Touchscreen power
- Enable PCIe_RST1 at the same points as PCIe_RST
- Remove Redundant Bootblock settings
BUG=b:193036827
TEST=Build & Boot, look at GPIO states through boot process
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This is in preparation for migrating EDK2 to more recent version(s). In
EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0
header (FspMultiPhaseSiInitEntryOffset). This increases the length of
the header from 72 to 76. Instead of checking for exact length check
reported header length against known minimum length for a given FSP
version.
BUG=b:180186886
TEST=build/boot with both header flavors
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sb_clk_output_48Mhz is only used in fch.c where it is also implemented,
so no need to have it visible outside of that compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Getting boardid information for the different SKU variants
BUG=b:182963902, b:193807794
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide a valid GPIO configuration based on the mainboard wiring.
Change-Id: I36f0e8292a405b4bac74fbc5fde62e5e414387e7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56519
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there is no SD card interface on this mainboard do not set the
card detect GPIO.
Change-Id: Ibe6799c5c540538f97d1726ec16e79f3edbb16fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56489
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE instead of
PCI_ALLOW_BUS_MASTER to enable PCIe bus master bit as requested in
CB:56441 during review.
Change-Id: I433dbae0d9b15e41d1d0750298868341ce3d6b46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Set the bus master bit only if the global Kconfig switch
PCI_ALLOW_BUS_MASTER_ANY_DEVICE is enabled. For now the bus master bit
is needed for i210 because of some old OS drivers that do not set it
and won't work properly without it.
Change-Id: I6f727e7f513f4320740fbf49e741cea86edb3247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a new configuration option with more density for
8GB variants of the up squared board.
Settings are taken from slimbootloader.
Signed-off-by: Florian Laufenböck <florian@laufenbock.de>
Change-Id: I217b04be94e913b75e2bac0a4ae1c43f2411a044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This legacy alt-century byte sits amidst CMOS and conflicts many option
tables. It usually has no meaning to the hardware and needs to be main-
tained manually. Let's disable its usage by default if the CMOS option
table is enabled.
Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Chrome EC is relatively quick with retiring "old" boards from their
tree so when upreving it, the last veyron in that list that wasn't
commented out is gone as well.
Change-Id: Ie1ef693c8d0947396ee01e5aa5f40ef36c8a317a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56430
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When accessing I2C, we should use the official names (I2Cx)
instead of magic numbers.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I17cc4c87f5ad26deeb5e529d1c106b697a53591b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56504
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EC_IN_RW_OD signal is routed from Google Security Chip to GPIO_91 in the
upcoming hardware build. The existing SD_EX_PRSNT signal is dropped in
the upcoming hardware build because SD7 support is dropped. Export the
EC_IN_RW GPIO for use by payload.
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the device can boot
successfully in both recovery and normal mode.
Cq-Depend: chromium:3043702
Change-Id: I8986ba007a2d899c510be61664d90430b8d2d384
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56493
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update proper number of sectors info for winbond W25Q512NW-IM chip
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: I12a22321bb9180e32cd47faa6ac3960ba5b2dfb8
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56038
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since this mainboard does not use GSPI at all, disable all GSPI ports.
Change-Id: I60254e9f4047537d86c972151ec9e33552332959
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard uses I2C1 and I2C4 buses only. Disable all the others as
they are not connected at all.
Change-Id: I4743f6ea6b9a9987ad63b60f56ee9a597a08284b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Features like DevSLP and Aggressive Link Power Management are not
supported on this mainboard and are therefore disabled.
Change-Id: I3bc650ea78be8587889fb7abfe7075cd9a122198
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board does not use CLKREQ-signaling for PCIe, so disable the pin
assignments. In addition only three clock outputs are used for PCIe,
therefore disable all others to improve EMI.
Change-Id: I545f890fa55a109df7f44d2c82170874fb769009
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are in total three USB ports that are used on mc_ehl1:
- Port 1: Type A connector connected to USB2/USB3 port 0
- Port 2: Type A connector connected to USB2/USB3 port 1
- Onboard: connected to USB2 port 2
None of the ports supports overcurrent reporting.
Adjust the appropriate UPDs in devicetree to match the hardware
configuration.
Change-Id: I220637b8e9f03efccacd0955e82cfc0c7a6f53ee
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56454
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mc_ehl1 does not have a display attached nor have a display
connector available (pure headless design), remove display related
settings from the devicetree.
Change-Id: Id31c09fcfba15f55eed19134bd0c2fb887bd2478
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56453
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without this configuration, even though there is no SD card it shows as
SD card is present and host controller waits for card to respond.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board with SD card and
without SD card, make sure if SD card not present then host controller
should not wait for card to respond.
Change-Id: I5dc5ba10c98d606d98e7d4f4c41c3e4f45e94452
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
The common gpio driver can be re-used for SC7180,
thus remove the existing gpio driver support and
also clean up the common macro definitions.
Add GPIO pin details specific to SC7180 chipset
for the consumers to be able to request for the
gpio functionality as per their requirement.
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This enables the MCAX checking and BERT entry generation for Cezanne.
TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706
Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Move M2_SSD_PLN_L to GPP_D3 for power loss notify function.
2. Set GPP_E21 as NC to remove LCLW_DET function
BUG=b:190643562
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id3c60adeb5d35c79a1c700937f93a80ad3587c5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56420
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This allows keeping track of how long it takes to load the microcode.
BUG=b:179699789
TEST=Boot guybrush
112:started reading uCode 990,448 (10,615)
113:finished reading uCode 991,722 (1,274)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use the gpio offset macro instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Program unused Cnvi BT UART GPIOs as NC since we are using
Bluetooth over USB mode for Brya.
Change-Id: I33a37ceb8a91603d2a193de5bdd1b6885eb3c319
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55317
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the taeko variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:193685558
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TAEKO
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: If738849bc3103c52a4c4d8a8aaef3f90a62ad5c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56385
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR.
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56329
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Take Kconfig switch PCI_ALLOW_BUS_MASTER into account and set the PCI
bus master bit for legacy devices only if it is allowed.
Change-Id: I7798a767d528419bb093f301140ab68cc8b9c5ae
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch adds support for variant specific soc chip config update
function.
Change-Id: Ic3a3ae0b409433e6dfa102c5e7a6322d4f78f730
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch makes Ampton EC wake up AP from s0ix when the state of
charge drops to 2%.
Demonstrated as follows:
1. Boot Ampton.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 2.
4. System resumes.
BUG=b:189540432
BRANCH=Octopus
TEST=Verified on Ampton.
Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350
Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56341
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_parts_uesd.txt that contains the new
memory parts used by primus and Makefile.inc generated by
gen_part_id.go using mem_parts_used.txt.
BUG=b:193813079
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I6aa37114f3a164a4f3c35dfc9b43e1106b825bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
As part of GPIO driver cleanup across qcom chipsets,
GPIO_OUTPUT_ENABLE has been renamed to GPIO_OUTPUT.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Defining a macro for the gpio offset instead of a constant value.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
For new MT8195 devices we will control mt6360 via EC,
so we have to add ec function of controlling MT6360 and
add CONFIG to separate them.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic2228f5b45173f0905ea66a3a1f00ec820e0f855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch sets the optimized FIVR configs for ehlcrb customized
based on the performance measurements to achieve the better power
savings in sleep states.
- Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5
states.
- Update the supported voltage states.
- Update max supported current, voltage transition time and RFI
spread spectrum.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the new definition of mt6360_regulator_id,
merge the MT6360 LDO and PMIC interfaces into one.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7ccc32cb0a9481d5f55349c152267a44fe09d20a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On MT8195 platforms with BC1.2, we have to use EC to control
MT6360 so the mt6360_regulator_id is redefined to match the
numbers defined in EC driver.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I9437edb9776442759ce04c31d315c3760078ffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56434
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No reason to use the preprocessor for this.
BUG=none
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I920dfa2d27c2eb27e8bc50c615ccd13601610fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These methods are oprom specific. Move them out of CBFS. I also deleted
the tohex methods and replaced them with snprintf.
BUG=b:179699789
TEST=Boot guybrush and see oprom still loads
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As per the EDS revision 1.3 add support for I2C6 and I2C7.
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Id918d55e48b91993af9de8381995917aef55edc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the variants can have different memory move the SPD related
content to the variant directory.
Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56036
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we don't escape the $ then the actual $(obj) path will be written
into the .config file. With this change `$(obj)` is written into the
.config file. The Makefile then does:
PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
Since this is a recursive assignment the $(obj) will be expanded at that
point.
This change makes it easier to compare full .config files.
BUG=none
TEST=Build ezkinil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This method will allow the SoC code to start loading the payload before
it is required.
BUG=b:177909625
TEST=Boot guybrush and see read/decompress drop by 23 ms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifa8f30a0f4f931ece803c2e8e022e4d33d3fe581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.
BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will cause a linker error if these methods are used outside
ramstage.
BUG=b:179699789
TEST=compile guybrush w/ and w/o COOP_MULTITASKING
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9983fca939c8a15fa570481bfe016a388458830
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56352
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a thread wants to block a state transition it can use
thread_run_until. Otherwise just let the thread run. `thread_join` can
be used to block on the thread. Boot states are also a ramstage concept.
If we want to use this API in any other stage, we need a way of starting
a thread without talking about stages.
BUG=b:179699789
TEST=verify thread_run no longer blocks the current state
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3e5b0aed70385ddcd23ffcf7b063f8ccb547fc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56351
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The thread_handle can be used to wait for a thread to exit. I also added
a return value to the thread function that will be stored on the handle
after it completes. This makes it easy for the callers to check if the
thread completed successfully or had an error. The thread_join
method uses the handle to block until the thread completes.
BUG=b:179699789
TEST=See thread_handle state update and see error code set correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56229
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.
BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.
BUG=b:179699789
TEST=Boot guybrush with APOB patches.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need a way to protect shared resources. Since we are using
cooperative multitasking the mutex implementation is pretty trivial.
BUG=b:179699789
TEST=Verify thread lock and unlock.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56230
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switching threads while holding a spinlock can lead to a deadlock. This
happens if you have two thread trying to print to the serial console
because the uart code uses udelay.
BUG=b:179699789
TEST=Boot guybrush and no longer see a deadlock when printing to
console from a second thread.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b929070b7f175965d4f37be693462fef26be052
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Renaming them to thread_coop_disable()/thread_coop_enable() makes them
sound like a pair.
BUG=b:179699789
TEST=Boot guybrush to OS
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56357
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows nesting critical sections, and frees the caller from
having to keep track of whether the thread has coop enabled.
BUG=b:179699789
TEST=Boot guybrush with SPI DMA
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I325ab6181b17c5c084ca1e2c181b4df235020557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56350
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
idle_thread_init was actually configuring the BSP thread at the end.
We can instead do this in threads_initialize. This now lets us set
initialized after the idle thread has been set up.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1d6afac3b0622612565b37c61fbd2cd2481552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56356
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This helper method is just a shorthand for
`thread_yield_microseconds(0)`. I think it makes it clear that we want
to yield a thread without delaying.
BUG=b:179699789
TEST=build test
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id8b60c35b183cff6871d7ba70b36eb33b136c735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56349
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.
BUG=b:193888172
Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Define new configs for Opregion versions.
2. Assign RVDA to relative address of the Opregion buffer
in case of opregion 2.1+.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I95a9f3df185002a4e38faa910f867ace0b97ac2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Elkhart Lake provides option to configure FIVR (Fully Integrated
Voltage Regulators) via parameters in FSP-S.
This CL removes fixed FIVR config values and expose these parameters
to the devicetree so that they can be configured on mainboard level
as needed.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B.
BUG=b:193732051
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory MT40A1G16RC-062E:B
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch removes all local `CPUID_` macros from SoC directories and
creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC
users are expected to add any new CPUID support into cpu_ids.h and
include 'cpu/intel/cpu_ids.h' into respective files that look for
`CPUID_` macro.
Note: CPUIDs for HSW, BDW and Quark are still inside the respective
directory.
Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.
Built google/delbin with `BUILD_TIMELESS=1` and coreboot.rom
remains the same.
Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56199
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The configuration of the setting `chipset_lockdown` doesn't have any
effect for most of the variants since their configuration of
`common_soc_config` overwrites the configuration of the baseboard's
devicetree. If `chipset_lockdown` is configured separately in the
baseboard devicetree, the variant overridetrees reuse its
configuration.
Thus, move `chipset_lockdown` out of `common_soc_config` in the
baseboard devicetree and configure it separately.
Change-Id: I595c042cf62680d61f60965710d382bfdcd81671
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56209
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the part number for all boards was "Grunt". This patch adds the
correct part number/name for all variants.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If506df0b1027fb09f5027d8b9653b776fe3bdc75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55681
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure GPIO DGI_D4 (AP_XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:193499785
TEST=emerge-cherry coreboot
BRANCH=none
Change-Id: I21b7b811b8138cb3f71efecb0a0a886905c65a9c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
The patch adds an interface for configuring GPIOs inside the Kontron
CPLD/EC. This allows to statically define the mode for each GPIO pin
in devicetree.cb of the motherboard or carrier board. For example:
chip ec/kontron/kempld
device gpio 0 on
register "gpio[0]" = "KEMPLD_GPIO_INPUT"
register "gpio[4]" = "KEMPLD_GPIO_OUTPUT_LOW"
register "gpio[5]" = "KEMPLD_GPIO_OUTPUT_HIGH"
register "gpio[11]" = "KEMPLD_GPIO_DEFAULT"
end
end
In this case, <device gpio 0>, like all other devices, is not a real
device inside the EC. These definitions are used to understand the EC
resources and systematize configuration options, but if mark this as
<off>, the initialization step will be skipped in the driver code.
Use KEMPLD_GPIO_DEFAULT or skip it in devicetree.cb to not configure
the GPIO and keep the default mode after CPLD reset.
This work is based on code from the drivers/gpio/gpio-kempld.c linux
driver. Tested on Kontron mAL-10 COMe module [1].
[1] CB:54380 , Change-Id: I7d354aa32ac8c64f54b2bcbdb4f1b8915f55264e
Change-Id: Id767aa451fbf2ca1c0dccfc9aa2c024c6f37c1bb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In hardwaremain.c we call console_init before threads_initialize. Part
of setting up the uart requires calling udelay which then calls
thread_yield_microseconds. Since threads have not been set up, trying to
yield will result in bad things happening. This change guards the thread
methods by making current_thread return NULL if the structures have not
been initialized.
BUG=b:179699789
TEST=Ramstage no longer hangs with serial enabled
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56318
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also move the registers in the order they are in the hardware.
Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only when ACPI_BERT is selected the BERT functionality needs to be
included in the build.
Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we don't need to skip the MCA check on cold boot on MCAX capable
systems, add a mca_skip_check implementation that always returns false.
Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This will allow moving mca_check_all_banks to mca_common.c.
Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.
Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.
Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.
Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.
Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alder Lake SoC has virtual GPIOs for community 1 which was being
programmed by FSP and hence was skipped by coreboot. As part of
moving most of the GPIO programming to coreboot, we're skipping this
programming in FSP now.
TEST=Check register offset to see if programming is correct.
Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Fast Read Dual Output and Fast Read Dual I/O commands are
practically identical, the only difference being how the read address is
transferred (saving a whooping 2 bytes which is totally irrelevant for
the amounts of data coreboot tends to read). We originally implemented
Fast Read Dual Output since it's the older command and some older
Winbond chips only supported that one... but it seems that some older
Macronix parts for whatever reason chose to only support Fast Read Dual
I/O instead. So in order to make this work for as many parts as
possible, I guess we'll have to implement both. (Also, the Macronix
device ID situation is utter madness with different chips with different
capabilities often having the same ID, so we basically have to make a
best-effort guess to strike a trade-off between fast speeds and best
chance at supporting all chips. If this turns out to be a problem later,
we may have to add Kconfig overrides for this or resort to SFDP parsing,
although that would defeat the whole point of trying to be fast.)
BUG=b:193486682
TEST=Booted CoachZ (with Dual I/O)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We may want to use that flash vendor on future variants.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To be able to enable & disable PSP_verstage in the saved .config file,
the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a
select to a default with a prompt.
BUG=182477057
TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK,
verify that VBOOT_STARTS_IN_BOOTBLOCK is set.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will allow factoring out and moving check_mca() to soc/amd/common.
Change-Id: I92c7657baef17c248a5aef1eda268e9647502837
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the way how the not implemented MCA bank 3 gets
skipped. For the not implemented bank 3 the name gets set to NULL
resulting in mca_is_valid_bank returning false causing the bank to get
skipped. This is a preparation for commonizing the MCA(X) handing in the
soc/amd sub-tree.
Change-Id: I40d6a6752504d804c45b445fce7e763e80161211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
In mca_check_all_banks only check valid MCA banks for errors. This
aligns the Picasso code a bit more with the Stoneyridge code base which
will be updated in a follow-up patch. This is a preparation for
commonizing the MCA(X) handing in the soc/amd sub-tree.
Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The length of mca_bank_name should match the return value of
mca_get_bank_count which gets the number of MCA banks from an MSR.
TEST=No error message on serial console on amd/mandolin
Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also use array indices for the initialization.
TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16
Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
