Commit graph

541 commits

Author SHA1 Message Date
Jeremy Soller
21d7c477a4 soc/intel/tigerlake: Add PCH-H GPIO definitions
Add TGL-H GPIO definitions, based on existing TGL definitions and how
CNP/CNP-H handles the split.

Reference:
- Intel doc 619207
- TigerLake FSP
- linux/drivers/pinctrl/intel/pinctrl-tigerlake.c

Change-Id: If9a0fd1691fc1143b5c214a2613d270199367659
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24 14:48:12 +00:00
Jeremy Soller
657f7db769 soc/intel/tigerlake: Add PCH-H PMC GPE group definitions
Reference:
- TigerLake FSP

Change-Id: I666eb710762f6b00d173ee1a473f1f5a612953a6
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24 14:47:07 +00:00
Jeremy Soller
6b1b9ad835 soc/intel/tigerlake: Add PCH-H chipset devicetree
Based on the base TGL devicetree, add one specific to TGL-H that adds
the additional supported devices.

Introduces a new Kconfig for selecting the PCH support.

Reference:
- Intel doc 615985

Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24 14:46:16 +00:00
Jeremy Soller
301b09b3e6 soc/intel/tigerlake: Add TGL-H power limits
Convert the power limit defines to an enum and add TGL-H entries.

Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24 14:45:36 +00:00
Jeremy Soller
49759f6025 soc/intel: Add TGL-H CPUID
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-24 14:13:57 +00:00
Jeremy Soller
191a8d7d2e soc/intel/common: Add TGL-H PCI IDs
Add TGL-H PCI IDs from the Processor and PCH EDS docs.

Reference:
- Intel doc 615985
- Intel doc 575683

Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19 13:51:59 +00:00
MAULIK V VAGHELA
39a37bcdbe mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.

BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.

Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16 15:01:11 +00:00
Subrata Banik
ad08265740 soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable
As per TGL EDS doc:575681, two ways will be controlled with one bit
of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT
for TGL SoC.

Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15 07:12:41 +00:00
Tim Crawford
ebf8a41b05 soc/intel/tgl: Hook up ucode for TGL-U and TGL-R
Hook up microcode from 3rdparty repo for:

- TGL-U: 06-8c-01 (CPUID signature: 0x806c1)
- TGL-R: 06-8c-02 (CPUID signature: 0x806c2)

Verified microcode blob was found in CBFS on system76/darp7 (TGL-U).

    CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac
    microcode: sig=0x806c1 pf=0x80 revision=0x88

coreboot reports the correct revision for the microcode.

Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13 18:07:22 +00:00
Felix Singer
673e6d1c67 soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
Use a variable to store if the FSP should be responsible for the chipset
lockdown and use it for setting related configuration options. Thus, get
rid of that if-else-clause.

Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12 21:42:01 +00:00
Tim Crawford
f3c4f29ddd soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S
Prevent the FSP from writing its default SVID SDID values of 8086:7270
for internal devices as this locks most of the registers. Allows the
subsystemid values set in devicetree to be used.

A description of this SSID table override behavior, along with example
code, is provided in the TigerLake FSP Integration Guide, section
15.178 ("SI_CONFIG Struct Reference").

The xHCI and HDA devices have RW/L registers rather than RW/O registers.
They can be written to multiple times but cannot be modified after
being locked, which happens during FspSiliconInit. Because coreboot
populates subsystem IDs after SiliconInit, these devices specifically
must be written beforehand or will otherwise be locked with their
default values of 0:0.

TGL also introduces parameters for customizing the default SVID:SSID.
These must be set or it will still use the FSP defaults.

Tested by checking lspci output on System76 darp7 (TGL-U).

References:
- b1fa231d76 ("soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-S")
- TigerLake FSP Integration Guide
- Intel Document #631120-001

Change-Id: I391b9fd0dc9dda925c1c8fe52bff153fe044d73e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-12 17:53:27 +00:00
Ricardo Quesada
470ca5714f Move post_codes.h to commonlib/console/
Move post_codes.h from include/console to
commonlib/include/commonlib/console.

This is because post_codes.h is needed by code from util/
(util/ code in different commit).

Also, it sorts the #include statements in the files that were
modified.

BUG=b:172210863

Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-04 15:15:51 +00:00
Sean Rhodes
bc35bed18e soc/intel/*: Allow configuring 8254 timer via CMOS
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-03 15:21:04 +00:00
Angel Pons
ac90f593f8 src/*: Specify type of CBFS_SIZE once
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.

Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26 14:02:57 +00:00
Lean Sheng Tan
750200020a soc/intel/common: Rename kconfig PMC_EPOC
Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain
common naming convention.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-19 06:33:18 +00:00
Subrata Banik
aec071661c soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated
cpu_ids.h file in SoC directory.

Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-17 09:50:32 +00:00
Subrata Banik
7d3e57d7a3 soc/intel/tigerlake: Use is_devfn_enabled() for Crashlog UPDs
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and
SOC_INTEL_CRASHLOG is selected by the SoC user.

Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15 14:03:57 +00:00
Angel Pons
6f5a6581a6 src: Introduce ARCH_ALL_STAGES_X86
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically
select the per-stage arch options. Subsequent commits will leverage
this to allow choosing between 32-bit and 64-bit coreboot where all
stages are x86. AMD Picasso and AMD Cezanne are the only exceptions
to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set
the per-stage arch options accordingly.

Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02 08:19:10 +00:00
Angel Pons
c7cfe0ba54 soc/intel: Refactor xdci_can_enable() function
The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.

Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01 12:14:02 +00:00
Tim Wawrzynczak
25d2452388 soc/intel/tigerlake: Send End-of-Post message to CSE
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#612229

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30 22:20:06 +00:00
Lean Sheng Tan
508dc163f1 soc/intel/common: Move PMC EPOC related code to Intel common code
Move PMC EPOC related code to intel/common/block because it is
generic for most Intel platforms and ADL, TGL & EHL use it.

Add a kconfig 'PMC_EPOC' to guard this common EPOC code.

The PMC EPOC register indicates which external crystal oscillator is
connected to the PCH.  This frequency is important for determining the
IP clock of internal PCH devices.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30 07:34:44 +00:00
Angel Pons
8e035e3c13 src: Move select ARCH_X86 to platforms
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware,
have platforms select `ARCH_X86` directly instead of through per-stage
Kconfig options, effectively reversing the dependency order.

Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30 04:48:59 +00:00
Tim Wawrzynczak
ed042a9687 soc/intel/tigerlake: Enable support for common IRQ block
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows tigerlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.

BUG=b:171580862
TEST=on delbin, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:     6     0     0   0  IO-APIC    2-edge      timer
   1:     0    35     0   0  IO-APIC    1-edge      i8042
   8:     0     0     0   0  IO-APIC    8-edge      rtc0
   9:     0   601     0   0  IO-APIC    9-fasteoi   acpi
  14:     1     0     0   0  IO-APIC   14-fasteoi   INT34C5:00
  20:     0     0     0 516  IO-APIC   20-fasteoi   idma64.6, ttyS0
  28:     0   395     0   0  IO-APIC   28-fasteoi   idma64.0, i2c_design
  29:     0     0  1654   0  IO-APIC   29-fasteoi   idma64.1, i2c_design
  30:     0     0     0   0  IO-APIC   30-fasteoi   idma64.2, i2c_design
  31:     0     0     0   0  IO-APIC   31-fasteoi   idma64.3, i2c_design
  32:     0     0     0   0  IO-APIC   32-fasteoi   idma64.4, i2c_design
  33:     0     0 14469   0  IO-APIC   33-fasteoi   idma64.5, i2c_design
  35:     0 18494     0   0  IO-APIC   35-edge      cr50_spi
  36: 95705     0     0   0  IO-APIC   36-fasteoi   idma64.7, pxa2xx-spi
  37:     0     0  1978   0  IO-APIC   37-fasteoi   idma64.8, pxa2xx-spi
  51:  1865     0     0   0  IO-APIC   51-fasteoi   ELAN9008:00
  59:     0     0   422   0  IO-APIC   59-fasteoi   ELAN0000:00
 116:     0     0     0  23  IO-APIC  116-fasteoi   chromeos-ec
abbreviated _PRT dump:
Method (_PRT, 0, NotSerialized)  // _PRT: PCI Routing Table
  If (PICM)
    Package () {0x0002FFFF, 0x00, 0x00, 0x10},
    Package () {0x0004FFFF, 0x00, 0x00, 0x11},
    Package () {0x0005FFFF, 0x00, 0x00, 0x12},
    Package () {0x0006FFFF, 0x00, 0x00, 0x13},
    Package () {0x0007FFFF, 0x00, 0x00, 0x14},
    Package () {0x0007FFFF, 0x01, 0x00, 0x15},
    Package () {0x0007FFFF, 0x02, 0x00, 0x16},
    Package () {0x0007FFFF, 0x03, 0x00, 0x17},
    Package () {0x000DFFFF, 0x00, 0x00, 0x10},
    Package () {0x000DFFFF, 0x01, 0x00, 0x11},
    Package () {0x000DFFFF, 0x02, 0x00, 0x12},
    Package () {0x0010FFFF, 0x00, 0x00, 0x13},
    Package () {0x0010FFFF, 0x01, 0x00, 0x14},
    Package () {0x0011FFFF, 0x00, 0x00, 0x18},
    Package () {0x0012FFFF, 0x00, 0x00, 0x19},
    Package () {0x0012FFFF, 0x01, 0x00, 0x1A},
    Package () {0x0013FFFF, 0x00, 0x00, 0x1B},
    Package () {0x0014FFFF, 0x00, 0x00, 0x15},
    Package () {0x0015FFFF, 0x00, 0x00, 0x1C},
    Package () {0x0015FFFF, 0x01, 0x00, 0x1D},
    Package () {0x0015FFFF, 0x02, 0x00, 0x1E},
    Package () {0x0015FFFF, 0x03, 0x00, 0x1F},
    Package () {0x0016FFFF, 0x00, 0x00, 0x16},
    Package () {0x0016FFFF, 0x01, 0x00, 0x17},
    Package () {0x0016FFFF, 0x02, 0x00, 0x10},
    Package () {0x0016FFFF, 0x03, 0x00, 0x11},
    Package () {0x0017FFFF, 0x00, 0x00, 0x12},
    Package () {0x0019FFFF, 0x00, 0x00, 0x20},
    Package () {0x0019FFFF, 0x01, 0x00, 0x21},
    Package () {0x0019FFFF, 0x02, 0x00, 0x22},
    Package () {0x001CFFFF, 0x00, 0x00, 0x10},
    Package () {0x001CFFFF, 0x01, 0x00, 0x11},
    Package () {0x001CFFFF, 0x02, 0x00, 0x12},
    Package () {0x001CFFFF, 0x03, 0x00, 0x13},
    Package () {0x001DFFFF, 0x00, 0x00, 0x10},
    Package () {0x001DFFFF, 0x01, 0x00, 0x11},
    Package () {0x001DFFFF, 0x02, 0x00, 0x12},
    Package () {0x001DFFFF, 0x03, 0x00, 0x13},
    Package () {0x001EFFFF, 0x00, 0x00, 0x14},
    Package () {0x001EFFFF, 0x01, 0x00, 0x15},
    Package () {0x001EFFFF, 0x02, 0x00, 0x24},
    Package () {0x001EFFFF, 0x03, 0x00, 0x25},
    Package () {0x001FFFFF, 0x01, 0x00, 0x17},
    Package () {0x001FFFFF, 0x02, 0x00, 0x14},
    Package () {0x001FFFFF, 0x03, 0x00, 0x15},
    Package () {0x001FFFFF, 0x00, 0x00, 0x16},
  Else
    Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0004FFFF, 0x00, 0x00, 0x0A},
    Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0006FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x02, 0x00, 0x0B},
    Package () {0x0007FFFF, 0x03, 0x00, 0x0B},
    Package () {0x000DFFFF, 0x00, 0x00, 0x0B},
    Package () {0x000DFFFF, 0x01, 0x00, 0x0A},
    Package () {0x000DFFFF, 0x02, 0x00, 0x0B},
    Package () {0x0010FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0010FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0014FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
    Package () {0x0016FFFF, 0x03, 0x00, 0x0A},
    Package () {0x0017FFFF, 0x00, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
    Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
    Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001EFFFF, 0x00, 0x00, 0x0B},
    Package () {0x001EFFFF, 0x01, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
    Package () {0x001FFFFF, 0x00, 0x00, 0x0B},

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49409
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 21:54:17 +00:00
Angel Pons
f585c6eeea soc/intel: Drop casts around soc_read_pmc_base()
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then
casted to a pointer type for use with `read32()` and/or `write32()`. But
since commit b324df6a54 (arch/x86: Provide
readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()`
functions live in `arch/mmio.h`. These functions use the `uintptr_t type
for the address parameter instead of a pointer type, and using them with
the `soc_read_pmc_base()` function allows dropping the casts to pointer.

Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-28 04:16:48 +00:00
Subrata Banik
c3a5c0558d soc/intel/tigerlake: Use devfn_disable() function for XDCI
Use devfn_disable() for disabling a PCI device rather than
using `dev->enabled = 0`.

Also, use is_devfn_enabled() to get the device current state prior
updating the FSP-S UPD for XDCI.

TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI
is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`.

Change-Id: I0e400ded7ba268a5f289b0ac568598e0dad1899a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55722
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23 08:25:37 +00:00
Werner Zeh
2b45ba089b soc/intel/{alderlake,tigerlake}: Fix typo in pmc.h
"corredsponding" --> "corresponding"

Change-Id: I0b0e5d461de29583c269896911167f8a44d84c2a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55555
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17 15:59:29 +00:00
Subrata Banik
49a2109324 soc/intel/tigerlake: Make use of is_devfn_enabled() function
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.

TEST=Able to build and boot without any regression seen on TGLRVP.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ic9d91b711bab83de1911e0b7ea876f2ad018c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55330
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16 03:49:05 +00:00
Wisley Chen
1852303682 util: Add DDR4 generic SPD for MT40A512M16TB-062E:R
Add SPD support for DDR4 memory part

BUG=b:190020997
TEST=none

Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14 05:27:39 +00:00
Andy Pont
d2f52ff053 soc/intel/tigerlake: Move MAX_CPUS to Kconfig
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS
value within src/soc/intel/*/Kconfig.

Move the definition there for Tiger Lake and remove from the mainboard
Kconfig files.

Signed-off-by: Andy Pont <andy.pont@sdcsystems.com>
Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-10 05:37:18 +00:00
Felix Singer
3e3c4560e1 soc/intel/tigerlake: Hook up FSP repository
Select `HAVE_INTEL_FSP_REPO` so that the FSP binary from the FSP
repository is used by default. Also, use the FSP headers from the FSP
repository and adjust some UPD names so that coreboot is able to use
them.

Also added new config FSP_TYPE_CLIENT/IOT. Respective mainboard Kconfigs
to select right FSP_TYPE when using FSP repository.

BUG=b:175957775
BRANCH=none

Change-Id: I5e694b91be7734dd98665051a6a3d9eccab7dac7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-06-10 05:34:52 +00:00
Kyösti Mälkki
41a2c73b06 cpu/x86: Default to PARALLEL_MP selected
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-07 21:02:54 +00:00
Furquan Shaikh
b9b6f4d013 soc/intel: Drop unused lpss functions
This change drops the following unused lpss functions and related
code:
* soc_lpss_controllers_list
* is_dev_lpss

These functions were added to determine if a controller is LPSS for
performing IRQ configuration. But, these never got used and hence are
being dropped.

Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07 11:35:08 +00:00
John Zhao
ac2cb42621 soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3
TBT PowerResource _ON/_OFF methods are currently invoked by _PS0 and
_PS3 respectively. It is defined for ACPI driver to call _ON and _OFF
methods. This change drops the _PS0 and _PS3 call for _ON/_OFF and
returns TBT PowerResource declaration in the _PR0 and _PR3, then ACPI
driver will call the TBT PowerResource _ON and _OFF methods.

BUG=b:188891878
TEST=Traced both of TBT _ON and _OFF methods invocation and execution
at run time. Verified TBT's power_state to be D3Cold.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I398b3f58ec89f98673cbbe633149d31188ec3351
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-27 14:40:09 +00:00
John Zhao
d8bb05ade0 soc/intel/tigerlake: Add validity for TBT firmware authentication
After Thunderbolt firmware is downloaded to IMR, its authentication
validity needs to be checked. This change adds the TBT firmware IMR
status register offset and its authentication valid bit for
valid_tbt_auth function usage.

BUG=b:188695995
TEST=Built Voxel coreboot image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia25827f18a10bf4d2dcabfe81565ac326851af3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54709
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26 15:43:01 +00:00
Arthur Heymans
6419cd3335 cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y
This removes the need to include this code separately on each
platform.

Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-18 16:54:21 +00:00
Nick Vaccaro
4b3e06edf2 soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design.

BUG=b:184660529
TEST="emerge-volteer coreboot" compiles without error.

Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-14 23:00:01 +00:00
Patrick Georgi
40b8f01697 src: Match array format in function declarations and definitions
gcc 11.1 complains when we're passing a type* into a function that was
declared to get a type[], even if the ABI has identical parameter
passing for both.

To prepare for newer compilers, adapt to this added constraint.

Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-13 18:34:38 +00:00
Kane Chen
3aee3ad46d soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT
On tgl, we noticed system hang if a shutdown is triggered before fsps.
The dut is unable to shutdown properly due to tcss is stuck before
tcss_init in fsps.

This change enable power button smi on jsl, tgl, adl after fsps.
it can also prevent a shutdown failure due to lack of fsps init on
certain ip.

BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
     cause the system hang during shutdown.

Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07 06:05:37 +00:00
Kane Chen
7b7b33e3a6 soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster
If a power button SMI is triggered between where it is currently
enabled and before FSP-S exits, when the SMI handler disables
bus mastering for all devices, it inadvertently also disables
the PMC's I/O decoding, so the register write to actually go into
S5 does not succeed, and the system hangs.

This can be solved by skipping the PMC when disabling bus
mastering in the SMI handler, for which a callback,
smihandler_soc_disable_busmaster is provided.

BUG=b:186194102, b:186815114
TEST=Power on the system and pressing power button repeatedly doesn't
     cause the system hang during shutdown.

Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07 06:05:18 +00:00
Tim Wawrzynczak
59a621abc7 soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.

BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:59 +00:00
Tim Wawrzynczak
6dc72022a5 soc/intel/tigkerlake: Add IOM PCR PID
Required for accessing IOM REGBAR space.

Change-Id: Ic1c9beee69d184388f3e850744b3aeebe38eafbb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:49 +00:00
Tim Wawrzynczak
a137201edd soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities
Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06 04:12:41 +00:00
Tim Wawrzynczak
8d3cc1bcc2 soc/intel/tigerlake: Add known GPIO virtual wire information
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at
least some of their groups; add the known information into the community
definitions.

Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06 04:12:13 +00:00
Tim Wawrzynczak
b1623f23c0 soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros
The usage of `pci_devfn_t` here is misleading, as these intentionally
store the `PCH_DEVFN_*` macros so they can be used across `smm` and
`ramstage` without requiring the device model. Update to `unsigned int`
instead, as `pci_devfn_t` implies the data is an MMCONF-compatible PCI
devfn offset.

Change-Id: Ic8880de984e6eceda4cbe141e118f3a5fdd672a2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52808
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 16:28:53 +00:00
Tim Wawrzynczak
93982c3a6e device: Switch pci_dev_is_wake_source to take pci_devfn_t
With the recent switch to SMM module loader v2, the size of the SMM for
module google/volteer increased to above 64K in size, and thus failed to
install the permanent SMM handler. Turns out, the devicetree is all
pulled into the SMM build because of elog, which calls
`pci_dev_is_wake_source`, and is the only user of `struct device` in
SMM. Changing this function to take a pci_devfn_t instead allows the
linker to remove almost the entire devicetree from SMM (only usage left
is when disabling HECI via SMM).

BUG=b:186661594
TEST=Verify loaded program size of `smm.elf` for google/volteer is
almost ~50% smaller.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-03 16:28:42 +00:00
John Zhao
ae3f524a1f soc/intel/tigerlake: Use device ID from pci_devs header file
This change applies device ID from the SoC pci_devs.h directly.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0c3bd60c62664337429e6817d2cf54cf2e8d500b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26 08:27:34 +00:00
Angel Pons
0c0d49229d soc/intel: Replace open-coded buffer length calculation
Use `sizeof(value)` instead of manually calculating the buffer size.

Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 14:21:44 +00:00
Angel Pons
73a22edcc8 soc/intel: Fix typo in comment
rotine ---> routine

Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 14:21:26 +00:00
Rizwan Qureshi
a979460614 soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21 09:19:58 +00:00
John Zhao
3062083d42 soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=b:185631878
TEST=Built image and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-21 09:16:08 +00:00
Tim Wawrzynczak
7f7c3882a6 dptf: Move platform-specific information to struct dptf_platform_info
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.

Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13 08:22:49 +00:00
Shaunak Saha
82d5123e1c intel/tigerlake: Add Acoustic features
On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate

We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.

BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06 23:28:17 +00:00
Tim Wawrzynczak
e2852579b8 soc/intel/tigerlake: Fix REG_BASE_SIZE
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space
in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2
indicates REGBAR is 16MiB in size, therefore update the constant to
reflect this.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:04:44 +00:00
Tim Wawrzynczak
eb6ebc025e soc/intel/tigerlake: Move TCSS code to intel/common/block
The Type-C subsystem ("TCSS") IP block is similar between TGL and
ADL. For pre-boot purposes, the limited amount of functionality required
appears to be common between the two, therefore move the functionality
to intel/common/block and rename from `early_tcss to `tcss` along the way.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:23 +00:00
Subrata Banik
2ccc0a4d9f soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.

An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.

Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.

TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)

With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)

Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:23:12 +00:00
Tim Wawrzynczak
e433042a8e soc/intel/tigerlake: Add #include guards to soc/early_tcss.h
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8a630655731b3ee30ef8377296878cce7b8c2201
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 15:24:00 +00:00
Nick Vaccaro
96094b31e9 util: Add DDR4 generic SPD for H4AAG165WB-BCWE
Add SPD support for DDR4 memory part H4AAG165WB-BCWE.

BUG=b:181732562
TEST=none

Change-Id: I923fcbd08875a2a581fba4b1db00a4d1c1bb11cf
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51666
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:26:40 +00:00
Derek Huang
8056187e4e soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable
PmcUsb2PhySusPgEnable is enabled by default. Expose devicetree
parameter to disable

Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ibd54a10c57d39bb8762b705ef0d6ff4cd47f0d89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19 11:22:07 +00:00
Cliff Huang
172d2d140d soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI device
There is no PCI host interface for this version of CNVi BT.
CNVi BT on Tigerlake is an USB device.

Change-Id: Ib71a827c36dfac55c3e5ce586b00a26fc6264464
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:27:15 +00:00
Cliff Huang
b34be4d4bb soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry
FSP has added the Cnvi BT Core enabling in addition to the existing
CnviMode. This change adds the flag at the soc config side (i.e.
soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host
interface for BT. Therefore, BT core should not use the pci port status to turn
on/off.

TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make
        sure BT is turned on.

Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:24:14 +00:00
Michael Niewöhner
405f229689 soc/intel/*: drop UART pad configuration from common code
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.

Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.

Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
2021-03-12 08:48:03 +00:00
Brandon Breitenstein
d8774f6899 soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
TCSS muxes being left uninitialized during boot is causing some USB3
devices to downgrade to USB2 speed. To properly configure the Type C ports
the muxes should be set to disconnected state during boot so that the port
mapping of USB2/3 devices is properly setup prior to Kernel initializing
devices.

BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple
times to verify that devices were no longer downgrading to USB2 speed.

Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 17:02:20 +00:00
Brandon Breitenstein
29144554fb soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and soc
The original implementation of early tcss resulted in calling to mainboard
then back to soc then back to mainboard to properly configure the muxes.
This patch addresses that issue and instead just gets all the mux
information from mainboard and does all config in the soc code.

BUG=none
BRANCH=firmware-volteer-13672.B
TEST=Verified functionality is not effected and early TCSS still functions

Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 03:53:24 +00:00
Furquan Shaikh
338d668b6f soc/intel/tigerlake: Fix NULL being passed for response buffer
`pmc_send_ipc_cmd()` expects the caller to pass in a pointer to a valid
request and response buffer. However, early_tcss driver was passing in
a NULL pointer for response buffer which would result in invalid
access by `pmc_send_ipc_cmd()`.

Currently, the response buffer is not used in `update_tcss_mux()`. So,
this change drops the passing of `rbuf` parameter to `send_pmc*`
helpers and instead uses a local `rsp` variable in the respective
functions. All the PMC functions used in early_tcss driver return some
kind of response. These should be checked to return appropriate
response code back to the caller. However, this needs to be done as a
separate change.

Change-Id: I215af85feed60b6beee17f28e3d65daa9ad4ae69
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05 03:53:16 +00:00
Angel Pons
a4cd9117da soc/intel: Factor out common smmrelocate.c
There are seven identical copies of the same file. One is enough.

Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:06:09 +00:00
Francois Toguo
4280b43473 soc/intel/tigerlake: Re-use existing define in CrashLog implementation
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS.
This fix re-uses an already existing variable in crashLog.

BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:02:16 +00:00
Angel Pons
98521c51f4 soc/intel: Retype CnviBtAudioOffload devicetree option
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.

Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.

Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:02:03 +00:00
Angel Pons
5d98dabb4e soc/intel: Drop bootblock_cpu_init() function
Just call `fast_spi_cache_bios_region()` directly instead.

Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:43:04 +00:00
Angel Pons
53496e69ec soc/intel: Drop romstage_pch_init() function
It only calls `smbus_common_init()`, so just call that directly.

Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:41:17 +00:00
Angel Pons
e178df27dd soc/intel: Factor out common smbus.h
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:39:27 +00:00
Angel Pons
8a269deee6 soc/intel: Factor out common gpe.h
The definitions are identical across seven platforms. Unify them.

Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:38:40 +00:00
Angel Pons
98f672a5ea soc/intel: Factor out identical acpigen GPIO helpers
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:37:56 +00:00
Angel Pons
09f06056eb soc/intel: Include gfx.asl from northbridge
The iGPU is on the northbridge or system agent, not the southbridge.

Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-01 08:32:47 +00:00
Angel Pons
b6d7a12d0f soc/intel/*/smmrelocate.c: Sync includes
Since Elkhart Lake and Alder Lake use alphabetical ordering, apply that
to the other platforms. Now there are only two versions of smmrelocate.c
across seven different platforms. They will be unified in follow-ups.

Change-Id: I5425323a6d4eecaa97916b6f2683dff57392157c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50935
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:40:47 +00:00
Angel Pons
11aeebec32 soc/intel/*/smmrelocate.c: Uniformize cosmetics
Use the same log message everywhere for consistency.

Change-Id: I9d2230bc92313269470839486f6644f16e837d7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50934
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:35:32 +00:00
Angel Pons
f5d090d19a soc/intel/*/pmutil.c: Align cosmetics across platforms
Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24 11:34:42 +00:00
Aamir Bohra
4742f53770 soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore
Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.

Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-24 11:28:45 +00:00
John Zhao
2c7842407a soc/intel/tigerlake: Remove polling for Link Active Status at resume
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.

BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-23 22:14:04 +00:00
Nick Vaccaro
202b1899dc soc/intel/tigerlake: Enable end of post support in FSP
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.

BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
  ./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".

Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22 23:20:32 +00:00
Francois Toguo
15cbc3b599 soc/intel/tigerlake: Add CrashLog implementation for intel TGL
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.

BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-22 07:22:50 +00:00
Kyösti Mälkki
fce36e448d vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMIC
Always allocate RAMOOPS from CBMEM and drop the related
static variable CHROMEOS_RAMOOPS_RAM_START.

Change-Id: Icfcf2991cb78cc6e9becba14cac77a04d8ada56a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50608
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16 09:39:04 +00:00
Kyösti Mälkki
4de1a31cb0 ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.

Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-16 09:28:42 +00:00
Kyösti Mälkki
c4b3903361 soc/intel: Drop aliases on MMCONF_BASE_ADDRESS
Change-Id: I5ba60c1d8c314d37b4ef71c4613e6e0629da8149
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-16 08:07:52 +00:00
Elyes HAOUAS
7cb4cb64ba soc/intel: Remove unused <console/console.h>
Change-Id: I630b7b0b1d564bcd99358caaaef4afd78c22866c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50528
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-15 10:50:09 +00:00
Elyes HAOUAS
45ce5d8973 src: Remove unused <arch/cpu.h>
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:25:23 +00:00
Shreesh Chhabbi
fbad99f347 soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 07:23:09 +00:00
Kyösti Mälkki
cc93c6e474 soc/amd,intel: Drop s3_resume parameter on FSP-S functions
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.

Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-09 07:53:23 +00:00
Kyösti Mälkki
62044c3e57 soc/intel: Drop CID1 from GNVS
The only reference to CID1 is in common/acpi/wifi.asl and
only two braswell boards include it. Everywhere else
the value in GNVS was unused.

Change-Id: I09ea756fb3743e33d1e221f0a0df3a6fdc3fc3ba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-08 04:57:04 +00:00
Aamir Bohra
30cca6ca2a drivers/intel/fsp2_0: Add support for MP services2 PPI
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.

This implementation also selects the respective MP services PPI version
supported for SoCs

BUG=b:169196864

Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-02-06 09:06:10 +00:00
Furquan Shaikh
5f262be24c intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
This change renames config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPI
in preparation to allow V1 and V2 versions of MP services PPI.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I04acf1bc3a3739b31d6e9d01b6aa97542378754f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50275
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:05:57 +00:00
Furquan Shaikh
1a5f25ea7f intel: Drop FSP_PEIM_TO_PEIM_INTERFACE
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.

FSP_PEIM_TO_PEIM_INTERFACE is used for:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
* Adding ppi to subdirs-y
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y

and is selected by SoCs that want to enable MP PPI services.

Instead of using the indirect path of selecting MP PPI services, this
change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The
above uses are handled as follows:

* Auto-selecting FSP_USES_MP_SERVICES_PPI
  --> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI.
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
  --> The guard isn't really required. The Kconfig options in this
  file don't present user prompts and don't really need to be guarded.
* Adding ppi to subdirs-y
  --> Makefile under ppi/ already has conditional inclusion of files
  and does not require a top-level conditional.
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
  --> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.

TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom

Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-06 09:05:42 +00:00
John Zhao
21e2b5a0ce soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.

BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04 09:53:15 +00:00
Derek Huang
ed6bda2818 soc/intel/tgl: Add configurable value for ConfigTdpLevel
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level

Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-02-03 20:11:06 +00:00
Elyes HAOUAS
0322bc5ed8 src: Remove unused <cbmem.h>
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-03 08:56:35 +00:00
Michael Niewöhner
33c0aac3b6 soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK
Before enabling IO decode ranges, current code checks if the DMI SRLOCK
is set to prevent inconsistencies between LPC PCI cfg registers and LPC
DMI registers, when the latter are locked.

DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H,
PCH-S and others with discrete PCH packages. So this check is at least
incomplete.

Further, the lock gets applied by FSP and gets reset on a warm reset.
Thus, there is no case where the lock would be already set at the
places where the DMI registers get written currently.

Drop the checks for the reasons mentioned above.

Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31 19:27:55 +00:00
Angel Pons
9849488da1 soc/intel: Replace SA_PCIEX_LENGTH Kconfig options
Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols.

Change-Id: I88dcc0d5845198f668c6604c45fd869617168231
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30 23:14:08 +00:00
Angel Pons
7d638784a2 device/Kconfig: Declare MMCONF symbols' type once
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.

Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29 17:46:55 +00:00
Kyösti Mälkki
e76ce871c8 arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits
With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.

Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:55:31 +00:00
Marc Jones
08de06ad6d soc/intel: Move c-state resource define
De-duplicate the MWAIT_RES define. Move it to intel/common/block.

Change-Id: I43903e4f02a549f53101e79f6febd42f2e54f98f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49802
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-26 10:34:52 +00:00
Michael Niewöhner
d2c57f2a0c soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring
Drop the old, redundant code for mirroring LPC registers to DMI and make
use of the new common code.

Select the new Kconfig option for LPC DMI mirroring by the option
SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with
SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig
directly.

APL, even though it's younger than SPT, does not need mirroring.

Test: Set LGMR address by calling `lpc_open_mmio_window` and check that
      both the PCI cfg and DMI LGMR register get written correctly.

Tested successfully on clevo/cml-u.

Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-25 09:06:10 +00:00