Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: I791273e5dd633cd1d6218b322106e2f62a393259
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Invoke PCIe root port devicetree update to swap the enabled root port
devices with the disabled devices.
BUG=b:162046161
TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is
swapped with the PCIe device 1c.0 corresponding to Root port 1.
Change-Id: I7d422014a2f5cafc41296ce0a2c116c82aefb0d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43835
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!
BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling VT-d on pre-QS silicon may have issues like rendering the
Thunderbolt driver useless. This change will ensure that VT-d is
disabled for pre-QS silicon and enabled for QS.
BUG=b:152242800,161215918,158519322
TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for
QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled
and no DMAR table exists, IOMMU will not be enabled.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following changes are done in this patch:
1. Get the CSE partition info containing version of CSE RW using
GET_BOOT_PARTITION_INFO HECI command
2. Get the me_rw.version from the currently selected RW slot.
3. If the versions from the above 2 locations don't match start the update
- If CSE's current boot partition is not RO, then
* Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
HECI command.
* Send global reset command to reset the system.
- Enable HMRFPO (Host ME Region Flash Protection Override) operation
mode using HMRFPO_ENABLE HECI command
- Erase and Copy the CBFS CSE RW to CSE RW partition
- Set the CSE's next boot partition to RW using
SET_BOOT_PARTITION HECI command
- Trigger global reset
- The system should boot with the updated CSE RW partition.
TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995
Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
Currently, audio is not working on Boten, caused by the coreboot
HDA driver not being run as the Jasper Lake PCI ID is missing.
So, add the Jasper Lake ID.
BUG=b:160651126
BRANCH=NONE
TEST=Connect speaker to audio jack, and verify sound is played.
Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: Ib62c332d8d87201b3e6903251d824e1c3e06cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43441
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot Waddledoo successfully.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Iaa0a41f3b5972251d6cd9359bbb46d392196b2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell, and avoids
unlikely but potential bugs regarding missing braces in macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I08ccbc70744a17d589450e321a3ed77d9a56492f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43196
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no reason to return the result of a void function.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I677dec1622768874a51effd6d73f0b2329f27aed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43193
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell, and
prevents possible bugs when using these macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I18e9a750901f1bf8d3b61f4b64bbed907bc1fa15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43192
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates Tiger Lake SA DID and report platform. According to
doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below
definitions of SA ID for TGL-UP4 skus:
TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h
TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h
Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register)
does not affect the pad in native function mode,
PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure
the pad. This macro has not been used, so deleting it will not affect
anything.
Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42913
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IO Standby State can use various settings independently of
PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this
parameter:
- PAD_CFG_GPI_IOSSTATE_TRIG_OWN()
- PAD_CFG_GPI_TRIG_IOS_OWN()
Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42912
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates existing macros for the GPI:
- PAD_CFG_GPI_IOSSTATE_IOSTERM()
- PAD_CFG_GPI_IOSSTATE()
to allow the user to set the RX Level/Edge Configuration (trig) and
the Host Software Ownership (own) fields in addition to IO Standby State
(iosstate) and IO Standby Termination (iosterm) in the pad configuration
using these macros.
Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things.
It is a fairly large structure, so the pointer to the data instead of
the structure itself, is included in the HOB. Use pointer to
SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body.
Adjust the structure definition to match with CPX-SP ww28 release.
Display more fields to ensure the structure definition is correct.
TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob
to make sure they are correct:
0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID
================== MEMORY MAP HOB DATA ==================
hob: 0x777f7000, structure size: 0x6c88
lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0
memSize: 0x600, memFreq: 0xb76
NumChPerMC: 3
SystemMemoryMapElement Entries: 2, entry size: 16
memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1
memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1
BiosFisVersion: 0x0
MmiohBase: 0x80000
0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
...
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SkipCpuReplacementCheck config to control the FSPM UPD used
for skipping the CPU replacementment check to avoid the forced
MRC training for the platforms with soldered down SOC.
BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddleddo.
Cq-Depend: chrome-internal:3142530
Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on jasperlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on cannonlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards.
Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This file does not contain useful information and is not used to build
the image. The common GPIO driver from soc/intel/common uses layout in
lewisburg_pch_gpio_defs.h [1,2] file, which is correct for all chipsets
from the Lewisburg family: C621, C621A, C622, C624, C625, C626, C627,
C627A, C628, C629, C629A [3]
[1] src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
[2] https://review.coreboot.org/c/coreboot/+/39425
[3] Intel document #547817
Change-Id: I1f3ac4afff9e628890df8cec075fd3e42a590172
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43535
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the ACPI specification, version 6.3:
Accesses to the PM1 status registers are done through byte or word
accesses.
The same is said about the PM1 Enable registers. Therefore, reporting
dword-sized access is wrong and means nothing anyway. Since some other
platforms use word-sized access, use word everywhere for consistency.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both `acpi_fill_fadt` and `soc_fill_fadt` set many FADT fields. Since
the latter runs later, the values programmed in it overwrite any other
values. Drop unused assignments and consolidate everything in a single
function. Use `acpi_fill_fadt` as it is mandatory (no weak definition).
Change-Id: Ia8248f20dae2b93426f309605bb2076592b08df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43386
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):
If the PM1b_EVT_BLK is not supported, its pointer contains a value of
zero in the FADT.
If the PM1b_CNT_BLK is not supported, its pointer contains a value of
zero in the FADT.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:
If a generic register block is not supported then its respective
block pointer and block length values in the FADT table contain zeros.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add configs for USB 3.1 Gen2 EV settings so that people can set the
EV settings per board in device tree.
BUG=b:150515720
BRANCH=none
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to puff and checked the log.
All usb configs were set correctly.
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: Id4860665619095139c329565d433d9eb495cac02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39448
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the common soc code automatically selects
POWER_STATE_DEFAULT_ON_AFTER_FAILURE which making other mainboard
options unselectable.
However, there're some cases that power state should change to different
states after reapplying power.
Make POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y but do not select it
in soc code so that we can disable it and select other options in the
mainboard code.
Tested on OCP Delta Lake.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa853d81ee9477d2440ceaa67b2bd6b863ee52c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.
* PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
(DITO), Default is 625ms.
BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I2fd2ec5a3029dc1bd1fa65dc3d1af5505f1f1dad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to
make the code in gpio_defs.h cleaner.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.
Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41034
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code
cleaner and reduce the length of the macro.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.
Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41033
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner
and reduce the length of the macro, which is often used.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 & T10-TNI carrierboard
does not change.
Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41032
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current the common soc code automatically selects PCIEXP_CLK_PM and
PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA
graphics card attached on mainboards that do not have a CLKREQ# signal.
This is commonly used on server and workstations boards where the
additional power savings of L1 substate are not required.
Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not
select it anymore by the soc code, thus we can disable it in the
mainboard code.
Tested on CFL with Windows 10.
Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type
HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure.
Remove the erroneous code related to resource structure.
Remove unnecessary function prototypes from header files, and define them
as static in hob_display.c.
Since we have the HOB pointer, there is not need to search HOB by GUID.
Remove unnecessary calling of fsp_find_extension_hob_by_guid().
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.
Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.
The CPX-SP soc code is updated accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
On ChromeOS systems with a serial-enabled BIOS and vboot writing a new
firmware image to the Chrome EC, it was possible for the TCO watchdog
timer to trip 2 times before tco_configure() was called in romstage.
This caused an extra reboot of the system (at a rather inopportune time)
and because the EC didn't perform a full reset, the system boots into
recovery mode.
This patch moves the call to tco_configure() for Tiger Lake from
romstage to bootblock, in order to make sure the TCO watchdog timer is
halted before vboot_sync_ec() runs in romstage. It should be harmless to
configure the TCO device earlier in the boot flow.
BUG=b:160272400
TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds Type-C Intel Input Output Manager(IOM) device with HID
INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600.
Intel Input Output Manager(IOM) kernel driver reads relevant
information such as Type-C port status (whether a device is connected
to a Type-C port or not) and the activity type on the Type-C ports
(such as USB, Display Port, Thunderbolt) using this memory resource.
BUG=b:156016218
TEST=Able to detect USB, TBT and USB4 on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds Type-C IO Manageability engine base address and size.
Tigerlake EDS(#575681) section 3.4.3 describes host bridge
REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a
port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is
determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000.
IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=🅱️156016218
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new IGD device ID for new Tigerlake SKU support.
BUG=b:160394260
Branch=None
TEST=build, boot and check IGD device is reported.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ia314148abc900685d85aede3add480614fa8e99c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner
This reduces the differences between Bay Trail and Braswell.
The resulting binary changes, but it shouldn't matter.
Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This can result in accesses outside array bounds. Copy what Braswell
does, which is slightly safer.
Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops.
Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.
Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change disables Thunderbolt PCIe root ports bus master before
handing over to payload in order to mitigate the threat from the
unauthorized external DMA. In this state, the PCIe root ports would
be considered as trusted to not forward any DMA transactions to
downstream endpoint devices.
BUG=b:141609884
TEST=Verified PCIe resource has been allocated properly and USB behind
Thunderbolt dock is enumerated successfully.
Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For both Tiger Lake and Jasper Lake, add the DEVFN for Image Processing
Unit (IPU) to soc_acpi_name, which is set to return "IPU0".
Change-Id: Ib11be5be7fbaec688d8788945a3bcab3f8d834a1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42878
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a minimal PCI driver for Intel's IPU, this allows devices to be
added underneath it in the devicetree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I531b293634a5d40112dc6af7b33fedb5e13f35e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42812
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028
TEST=build.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.
Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.
Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it.
Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot
BUG=None
BRANCH=None
TEST=FSP is able to push debug logs on UART with this setting
Cq-Depend: TBD
Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB.
Build hob display into romstage, in addition to ramstage.
Memory map HOB data is a big structure. Update the soc_display_memmap_hob()
to assist trouble shooting of FSP interface.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP Tioga Pass and Delta Lake.
Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A UPD HybridStorageMode allows a platform to dynamically configure the
PCIe strap configuration required if an Optane device is connected.
The strap configuration is done by HECI commands between FSP and CSE to
override the default PCIe strap value, and the updated strap value is
stored in SPI RW data to be used on the next boot.
CSE Lite supports the strap override when running on CSE RW partition,
while CSE RO partition does not support it because CSE RO is not allowed
to access SPI RW data. The strap override failure on CSE RO causes FSP
not initializing PCH Clkreq and PCIe port mapping and this results NVMe
and Optane initialization failure.
By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is
done by the default PCIe configuration and Optane is detected as a
single NVMe storage device on CSE RO boot in recovery mode. Both NVMe
and Optane devices detection as well as OS installation to these storage
devices are verified on CSE RO boot in recovery mode.
BUG=b:158643194
TEST=boot and verified with tglrvp and volteer in recovery mode
Cq-Depend: chrome-internal:3100721
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Time Window Tau bits are only supported by Comet Lake/Cannon Lake
onwards, so skip setting those bits for earlier SoCs.
Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This is a W/A to avoid a communication issue with CSE Lite over Heci
interface. This will help to avoid boot failures with CSE Lite until
the permanent fix is available.
BUG=b:159884143
TEST=build and boot volteer with serial and non-serial image
Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the FSP UPD
Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42803
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Many previous versions of this function would return early if tcc_offset
is 0. This adds that logic back in.
Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Use some defines as well for clarity.
Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42898
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds Platform-Wide _OSC capabilities for native USB4
support. There is Engineering Change Request (ECR) with _OSC addition
for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18
as native USB4 support. The OS sets this bit to indicate support for
an OSPM-native USB4 Connection Manager which handles USB4 connection
events and link management. The OS use the _OSC mechanism and the bit
defined in this ECR to obtain configuration and connection management
capabilities of USB4 connections. This change also fixs the byte index
for the DWord-addressable field CDW3 from the capabilities buffer.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
`commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
This adds the USB Wake Enable Setup (UWES) ASL blocks
required to inform the OS about plug wake events bits
being set in the PORTSCN register configured by devicetree.
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This enables Thermal Control Circuit (TCC) activation feature to set
tcc_offset value to new value in devicetree.
BUG=None
BRANCH=None
TEST=Built for dedede platform and verified the MSR value
Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This enables Thermal Control Circuit (TCC) activation feature to set
tcc_offset to new value in devicetree.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I36b0d6aad4be8a9cbb145dcd66d65235d3f6ac35
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.
TEST=boot and verified with volteer
Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coverity detects dereferencing pointers that might be "NULL" when
calling acpigen_write_scope and acpigen_write_device. Add sanity
check for both of scope and name to prevent NULL pointer dereference.
Found-by: Coverity CID 1429981
TEST=Built and boot up to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iea3801585e8c294fb889a8137b534bb932696025
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42836
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pmc_set_acpi_mode() should run after Chrome EC dealt with all host event
bits, like SMI mask (otherwise the FAFT firmware_FWScreenCloseLid test
will fail).
BUG=b:153249055
TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage
Change the GBB flag to 0x140 then check SMI mask during depthcharge
phase, make sure it's 0x0000000000000001.
Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com>
Change-Id: Icfff5cc5550f23938343e4d26ef76093bb9cf7c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The previous Intel CPX-SP FSP release was ww20 release.
The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end
flow of using memory training data to generate FSP_NV_STORAGE HOB and
using memory training data passed from bootloader to skip memory
training, works now. This saves 8 minutes of boot time (with FSP verbose
logging enabled on DeltaLake server).
This release also adds UPD parameters to support IIO bifuration.
The ww24 release has following updates:
a. Removed a number of unnecessary UPD parameters, such as mmiolSize,
mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate.
b. Added UPD parameters to support PCIe ports configuration.
c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit
fields, in addition to PCIe resource memory base/limit fields.
With ww24 release, the issue with PCIe link training persists. On YV3
config A, the onboard NIC card has x4 connection to port 2D. This
NIC device is not recognized by FSP.
Corresponding soc/intel/xeon_sp/cpx change is made:
* There are changes in PLATFORM_DATA structure, so hob_display.c
is updated.
* There are changes in UPD parameters, so romstage.c is updated.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP DeltaLake with change
https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add PchPmPwrCycDur to chip options to control the UPD FSPS PchPmPwrCycDur
from devicetree. The UPD determines the minimum time a platform will stay
in reset during host partition reset with power cycle or global reset.
This patch also ensures configured PchPmPwrCycDur value doesn't violate
the PCH EDS specification.
TEST=Verified on Hatch and Puff boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e836c78fab34e34d57b04428a1498b7dc7174b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Not all FSPs based on FSP 2.1 supports the feature of external PPI
interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE.
Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is
selected.
Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake).
Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Support display of CPX-SP specific HOBs (when CONFIG_DISPLAY_HOBS
is selected, and UPD parameters (when CONFIG_DISPLAY_UPD_DATA is selected).
Such display is used for FSP debugging purpose. It adds small
amount of boot time.
Some UPD display log excerpts:
UPD values for SiliconInit:
0x04: BifurcationPcie0
0x03: BifurcationPcie1
Some HOB display log excerpts:
=== FSP HOBs ===
0x758df000: hob_list_ptr
0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF
0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41348
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
`commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: Ie63e4f1fcdea130f8faed5c0d34a6a96759946b6
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42716
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dmesg shows unresolved symbol CDW1 with AE_NOT_FOUND error after
booting to kernel. Fix the error by properly creating the buffer field
CDW1 to cover all errors scenarios.
BUG=b:140645231
TEST=Verified no AE_NOT_FOUND error related to \_SB.OSC.CDW1.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ibfe677f87736ce1930e06b9cd649791977116012
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42693
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the ACPI specification, version 6.3:
OSPM accesses GPE registers through byte
accesses (regardless of their length).
So, reporting dword-sized access is wrong and means nothing anyway.
Tested on Asus P8Z77-V LX2, Windows 10 still boots.
Change-Id: I965131a28f1a385d065c95f286549665c3f9693e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Except for whitespace and varying casts the codes were
the same when implemented.
Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.
Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide CmdMirror option in chip.h so that it can control CmdMirror FSP
UPD via dev tree.
BUG=b:156435028
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Idae9fa439f077f8f3fb16fe74c2f263c008cd5f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42276
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename function from xeon_sp_get_cpu_count()
to xeon_sp_get_socket_count().
This function returns CPU socket count, by getting it from the field
named as numCpus in FSP HOB.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ic96bdf4ab042ac15d43f9b636185627c63fbf8a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42439
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4)
are available for TGL-U. They are dependent upon the SKU of the CPU
that the mainboard is running on. Volteer is updated here to use these
new limits.
To accomplish this, the SoC chip config's power_limits_config member
was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE
macros. Just before power limits are applied, the correct set of them
is chosen from the array based on System Agent PCI ID. Therefore, a
TGL board should have two sets of power limits available in the
devicetree.
BUG=b:152639350
TEST=On a Volteer SKU4 (4-core), verified the following console output:
CPU PL1 = 15 Watts
CPU PL2 = 60 Watts
CPU PL4 = 105 Watts
Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Each IIO stack has a personality. Only when personality of a stack is
TYPE_UBOX_IIO, the stack has PCIe devices.
For example, for CPX-SP, the stack 3 has personality of TYPE_UBOX, it
does not have PCIe devices.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2f6bfdac4d1110dd95f1b3a72e2e51f70c79212b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42333
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add processor power limits control support to configure values for
jasperlake soc based platforms.
BRANCH=None
BUG=None
TEST=Built for dedede system
Change-Id: Ib5502b225c1158c1f0729ce799ed0b8101f0233f
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Program PCU (Power Control Unit) during chip_final(). This
is needed to allow ACPI power control related feature to work
in target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I1f5b18d66b351acecdc7b3f515a552c36f08eb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This change updates platform.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for volteer.
Change-Id: I248f5e9a1e3ba4f6426167f0406073252cc6513a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42506
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Old (!PARALLEL_MP) cpu bringup uses this as the first
control to do SMM relocation.
Change-Id: I4241120b00fac77f0491d37f05ba17763db1254e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Broadwell does not have any `TESGMB`, but it has a `TSEGMB`.
Change-Id: Id25030aa86f2312e261eceb8b78c3878e9e0ee04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change adds support for SW CM. Add Operating System Capabilities
(_OSC) method to enable USB/DisplayPort/Inter-domain USB4 Internet
Protocol tunneling and enable PCIe tunneling as well. Remove Connect
Topology(CNTP) command because kernel driver directly works with SW CM
Thunderbolt firmware. Update _DSD method for USB4 support across XHCI
and PCIe root ports.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I859c5075882e40d7be30d4ba88cc825886712b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
