Commit Graph

8055 Commits

Author SHA1 Message Date
Paul Menzel 209238755a device/device_util.c: Fix wording in comment of `new_resource()`
Change-Id: Ieb0d5de37870a359f3a7ea1543640e26f86c1684
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5952
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 20:37:50 +02:00
Dave Frodin ac1b875b55 amd/southbridge/lpc: SPI BAR has fixed size/location
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.

Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 20:06:21 +02:00
Vladimir Serbinenko 61f902d4a7 ibexpeak: Set number of USB ports.
Change-Id: Ife3febcc88967386dfae624cd237562a34a68471
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5956
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 19:43:46 +02:00
Vladimir Serbinenko 49c3045c2d ibexpeak: Remove some dead code.
Change-Id: I68ae49d20a2524f03c4503f2b3be93f07b9cb6e3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5955
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 19:43:36 +02:00
Mike Loptien c93a75a5ab AMD/CIMx: Add functions for AMD PCI IRQ routing
The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01.  This table is responsible for physically
routing IRQs to the PIC and IOAPIC.  The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.

The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately.  This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts.  It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table.  It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE.  Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.

For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2.  This corresponds to PIN B.  On the
Persimmon mainboard, I want the USB device to use IRQ 11.  I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11.  This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read.  It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.

Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.

Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.

Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-11 17:07:50 +02:00
Mike Loptien ce740c474c PIC i8259: Move #defines and functions to i8259.h
The PIC i8259.c file has a lot of #defines and function
definitions in it.  I am moving these to the i8259.h file
and also adding a few functions to update the PIC IRQ mask
register.  The PIC default configuration has all of its
interrupts masked off except for IRQ2.  IRQ2 is where
the Slave PIC is cascaded from the Master PIC.

Change-Id: I78d505358c29fadbc184137a09120863ea1d5c13
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5950
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-11 17:07:38 +02:00
Kyösti Mälkki f5a2d2607f lippert/toucan-af: Fix comment on HAVE_ACPI_RESUME
S3 resume is expected to work now, however the 3s delay and flash wear
is still there.

Change-Id: I7edbce7bcf9c2160099fd5e371562b1ec63d45d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5971
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-11 15:52:45 +02:00
Kyösti Mälkki 1b6aef754e lippert/frontrunner-af: Fix comment on HAVE_ACPI_RESUME
S3 resume now works, however the 3s delay and flash wear is still there.

Change-Id: I9d2eda5454baf7704807cf67f3aca94a67de3406
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-06-11 15:52:35 +02:00
Dave Frodin 8ef20cf922 amd/hudson: Add the IOAPIC space to the fixed resources table
Without this change the IOAPIC memory window would collide
with PCI config space. This was tested on the hp/abm board.

Change-Id: I5dd53463961f75bab80a41dc7beff8d0434b24ae
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5946
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 15:05:48 +02:00
Dave Frodin bccd408169 amd/family16kb: Move and resize the MMIO region
The Kabini MMIO region was assigned a 256MB region at
0xA0000000. That location is below TOP_MEM and is getting
carved out of useable system memory which is not being
reclaimed above 4GB. This changes its size to 64MB and
moves it to 0xF8000000.

This was tested on the hp/abm and asrock/imb-a180 boards.

Change-Id: Ib226bc954311a3a2a15f182ab4618f4924e95a5b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5945
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-11 15:05:01 +02:00
Dave Frodin 0240f9492b nuvoton/nct5104d: Update the #defined LDNs
Change-Id: I4e4bc09a8f8fabe68519a29dc421af82c76c9873
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5944
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-09 23:33:22 +02:00
Felix Held da09d02c57 superio/nuvoton: factor out generic romstage components
The romstage of Nuvoton Super I/O chips (but not Nuvoton BMC chips)
is identical, so the early_serial.c file can be moved under
nuvoton/common.
The Nuvoton BMC chip WPCM450 is however left untouched.

Change-Id: I4663176c1003b24a49a9fe5f9ebd27a1963b5565
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/5909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-06 23:05:42 +02:00
Kyösti Mälkki ef9343cac1 AGESA: Use common heap allocator
Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:31:31 +02:00
Kyösti Mälkki 6025efa347 AGESA: Use common GetBiosCallout()
Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5688
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:30:52 +02:00
Kyösti Mälkki 83cc3b0ed5 AGESA fam15tn fam16kb: Use shared default callouts
Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5687
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:30:38 +02:00
Kyösti Mälkki cb989f2c3c AGESA fam15tn fam16kb: Use common handler for GNB_GFX_GET_VBIOS_IMAGE
Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5686
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:30:24 +02:00
Kyösti Mälkki bc84450082 Drop unused change_i2c_mux()
Change-Id: I3ac39441746d739ac19e831bb67c76405c24ba27
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-06 07:30:23 +02:00
Edward O'Callaghan f5bde44df2 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
1. Remove #include .c in romstage.
2. Make romstage component symbols linker-time.
3. Provide header guards and prototypes in superio romstage support.
4. Correct function type-signatures to be static/non-static where
appropriate, avoid 'pretend optimisations' by unnecessarily inlining
functions.
5. Separate out UART enable from various other PNP hard coding

Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5916
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-06 01:46:19 +02:00
Edward O'Callaghan 4ba8ba4654 build: Drop libgcc runtime wrapper in Clang builds
This GCC specific workaround of wrapping of libgcc runtime symbols with
gcc.c is not nessary with libcompiler-rt linkage.

Change-Id: I50a2bc99d97f68a2ad2b51a92ea0e7086bab35fe
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5812
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-06 01:45:20 +02:00
Edward O'Callaghan fdceb48b36 superio/smsc/smscsuperio: Make romstage linkable with header
Rewrite smsc/smscsuperio romstage component to be more consistent and
provide header there-by removing #include's of early_serial.c's in
mainboard's.

Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5915
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:37:57 +02:00
Edward O'Callaghan 8f45761a67 superio/ite/it8661f: Make early_serial into romstage sym
Following similar reasoning as commit:
d304331 superio/fintek/f81865f: Avoid .c includes

Avoid any mistaken future inclusion of early_serial.c in mainboard.c
code by providing symbols in romstage.

Change-Id: I9e763a7ad9de090e35acdcf4d6a280d8227c6015
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5508
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:37:03 +02:00
Edward O'Callaghan 6fb379a1db mainboard: Remove #include early_serial.c from w83977tf boards
These non-ROMCC boards #include the model specific w83977tf Super I/O
romstage component. The generic winbond_early_serial() function serves
well here to further tighten integration into the new Super I/O
framework and drop dependence on #include'ing .c files, leaving only
ROMCC boards.

Change-Id: Ib63c0f29f994c54e6112702506f288535799706c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5898
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:36:33 +02:00
Edward O'Callaghan aef5594f74 superio/ite/it8772f: Depreciate early wdt functions
We have better written generic implementations of these functions
introduced in commit:

 a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers

Change-Id: Ic93d78fce18c68d1d1bf3b537e8985a2532a8fcf
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5901
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:35:50 +02:00
Edward O'Callaghan 1b3acb13e4 superio/ite/it8772f: Move towards removing #include .c
Move samsung/stumpy board towards generic romstage component and away
from poorly written hard-coded model specific Super I/O component. This
is an incremental step towards getting obj-level abstraction between
board and Super I/O.

Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5899
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:35:38 +02:00
Paul Menzel d235da108b northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR`
Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5923
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:34:50 +02:00
Paul Menzel 50684638be northbridge/intel/i945/i945.h: Move define `BSM` to section D2F0
The Base of Stolen Memory (BSM) register belongs to device 2,
function 0.

Change-Id: I2381f87ffaccb2f8034c160fc30c1d92f8b19402
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5922
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:32:50 +02:00
Vladimir Serbinenko 12fcb86bba sandybridge: Pass chip info to i915lightup.
Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5284
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-02 21:47:39 +02:00
Kyösti Mälkki fd2501b3f1 i945: Fix TSEG size allocation for get_top_of_ram()
Seems boards with i945 had TSEG disabled so this had gone unnoticed.

Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I6a00ea9121847ce2fede22538e1b53a870d761f1
Reviewed-on: http://review.coreboot.org/5892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-02 10:51:30 +02:00
Kyösti Mälkki 15935ebe24 i945: Fix resource bases for UMA and TSEG
TSEG appears in memory below graphics UMA region. Seems boards
with i945 had TSEG disabled, so the incorrect order did not make
a difference.

Change-Id: Ie293aab17b60b5f06a871a773cd42577c7dc7c7b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5891
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-02 10:50:49 +02:00
Edward O'Callaghan 9c65978f38 mainboard/ibase/mb899: Trivial, Non-local header treated as local
Change-Id: I5cb496d0d582d3dc5c0c0635f632561f8a3dd853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5897
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-01 13:35:24 +02:00
Edward O'Callaghan a34a1da44d northbridge/intel/i945/i945.h: Trivial, fixup header guards
Change-Id: Iff15ab436e5b7b4e189c7341e7c508faaef07a3a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5896
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-01 13:34:47 +02:00
Vladimir Serbinenko ee62164bb2 lenovo/x201: Fix order of SPI init.
The lock bit for UVSVC/LVSVC was set before both registers were programmed.

Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5167
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 11:11:26 +02:00
Vladimir Serbinenko 25b55f3d1c lenovo/t60: Implement intel VGA callbacks.
Without it option ROM run results in just a black screen.

Change-Id: Id203f55ca0f02c290a3f40ac1ec7c5f23c5580bf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5344
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 02:16:25 +02:00
Vladimir Serbinenko 63acd22dc5 lenovo: Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.

Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.

Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4650
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 01:58:47 +02:00
Vladimir Serbinenko 4c81a9e142 i915_reg: Declare LVDS register values.
Change-Id: If8b3578c4fa31bf9f09c0053a5cac7ebc993b634
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5319
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 01:57:12 +02:00
Vladimir Serbinenko 8ecdc9e877 acpigen: Add acpigen_emit_eisaid.
Change-Id: Ib92142a133445018cd152dabe299792ba5f36548
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5240
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 01:24:53 +02:00
Edward O'Callaghan 32da8d900e superio/nsc/pc87309: Avoid .c includes in mainboard
Make superio romstage component link-time symbols.

Change-Id: Icde27465a05946498ff7b8f1aaa7a9e8ba074272
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5880
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 21:18:05 +02:00
Edward O'Callaghan beb0f2631f superio/winbond/w83627hf: Avoid .c includes in mainboards
Move towards the removal of the superio model specific xxx_serial_enable
implementation. Make remaining superio romstage parts link-time symbols
and fix corresponding mainboards to match.

The following mainboards remain unconverted as they are ROMCC:
 - mainboard/supermicro/x6dai_g
 - mainboard/supermicro/x6dhe_g
 - mainboard/supermicro/x6dhr_ig
 - mainboard/supermicro/x6dhr_ig2
and so block the final removal of w83627hf_serial_enable().

Special cases:
 - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
Provide local superio pnp_ programming entry/exit functions as to avoid
making superio implementation global symbols. Although this is not the
proper/final solution, it does mitigate possible symbol collisions and
allow for continued superio refactorisation.

Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5601
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 21:17:37 +02:00
Edward O'Callaghan 9068788a8f superio/winbond/w83627ehg: Depreciate romstage component
Part 1/2: These are actually not necessary if Super I/O support is
properly utilized.

Change-Id: I39b621e582f8d0762276d29492c91dce500f0665
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5870
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 21:16:39 +02:00
Kyösti Mälkki 3c3e34d69f i945: Use defines for DEVEN
Change-Id: I32461449354155510c0e14e9d0ce396068ea50d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5890
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-31 14:33:43 +02:00
Paul Menzel 66f10b1a19 northbridge/intel/i945/northbridge.c: Use define `TOLUD` instead of hardcoded value
Change-Id: I4739c5544aade105399347d239ba64f5115db397
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5869
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 13:11:02 +02:00
Paul Menzel 355ce38dc2 northbridge/intel/i945: Add define for register `BSM` and use it
Add a define for the register Base of Stolen Memory (BSM) and use it.

Change-Id: I5b1df4e088d88344fac8cd8d218e76b08a885f58
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5884
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 11:12:32 +02:00
Martin Roth ae6e0c6beb cpu/intel/fsp_model_206ax: change realpath to readlink
realpath and readlink can be used to do the same thing - in this case
we're turning path1/path2/../path3/path4 into path1/path3/path4 so
that the makefile's wildcard routine can evaluate it.

Debian derivatives don't seem to include realpath. (and even when it's
installed, it's not the gnu coreutils version.)

Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5793
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2014-05-30 23:52:17 +02:00
Martin Roth d75800c7f2 intel/bayleybay: Add Intel's Bayley Bay mainboard
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board

The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.

This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.

Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts

Board support page will be updated on acceptance.

Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-30 17:34:22 +02:00
Mike Loptien 0f5cf5e45b PCI IRQs: Swizzle PCI IRQs for PCI bridges
The PCI Specification states that devices that implement
a bridge and a secondary bus must swizzle (rotate) the
interrupt pins according to the table below:
	Child Dev #     Child PIN       Parent PIN
	0,4,8,12...     A/B/C/D         A/B/C/D
	1,5,9,13...     A/B/C/D         B/C/D/A
	2,6,10,14..     A/B/C/D         C/D/A/B
	3,7,11,15..     A/B/C/D         D/A/B/C

Which is also described by this equation:
	PIN_parent = (Pin_child + Dev_child) % 4

When a device is found and its bus number is greater than 0,
it is on a bridge and needs to be swizzled.  Following the
string of parents up to the root bus and swizzling as we go
gives us the desired swizzling result.  When BIOS_SPEW is
defined, it will print out each step of the swizzling process.

Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5734
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-05-29 23:24:28 +02:00
Martin Roth 433659ad1e fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip
While similar to the Bay Trail-M/D code based on the MRC, there are
many differences as well:
- Obviously, uses the FSP instead of the MRC binaries.
- FSP does additional hardware setup, so coreboot doesn't need to.
- Different microcode & microcode loading method
- Uses the cache_as_ram.inc from the FSP Driver
- Various other changes in support of the FSP
Additional changes that don't have to to with the FSP vs MRC:
- Updated IRQ Routing
- Different FADT implementation.
This was validated with FSP:
BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd
SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5
MD5: 9360cd915f0d3e4116bbc782233d7b91

Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5791
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-29 23:10:36 +02:00
Martin Roth 2a9b2ed3ff drivers/intel/fsp: update enable_mrc_cache with fast boot
When going from a configuration with fast boot disabled to one with
it enabled, ENABLE_MRC_CACHE was not being enabled properly.  This
forces it on with ENABLE_FSP_FAST_BOOT.

Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-29 23:09:26 +02:00
Martin Roth 7312c54dc6 add rtc_init() to romstage
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory.  Because of this, we need to initialize
the RTC in romstage instead of ramstage.

Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5735
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-29 23:09:12 +02:00
Edward O'Callaghan 2c55b70d1a superio/winbond/w83627thg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5724
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:53:33 +02:00
Edward O'Callaghan 92da206532 superio/winbond/w83627uhg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.

Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5725
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:53:30 +02:00
Edward O'Callaghan b918623f2e superio/ite/it8712f: Depreciate model specific early_serial.c
We now have common ite_*_*() functions for romstage and hence no longer
require the model specific portion of this superio support.

Change-Id: I30400abf27008a88072673075bba445f100d9ad3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5838
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:51:49 +02:00
Edward O'Callaghan 9bea0c1d14 superio/ite/it8712f: Drop model specific sio func for generic ver
Drop it8712f_kill_watchdog() in favor of common ite_kill_watchdog()
introduced in commit rev:

a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers

Change-Id: I9fc4d3ee7992618b5b14e35166e848d6e1cffa8b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5837
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:46:29 +02:00
Paul Menzel 18600aa1ef payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4
SeaBIOS 1.7.4 was released in December 2013 [1] and, besides other
things, supports writing debug messages to CBMEM console.

The new SeaBIOS Kconfig option `DEBUG_COREBOOT` has to be added to the
SeaBIOS configuration file `.config` as otherwise the SeaBIOS build
from within coreboot (`PAYLOAD_SEABIOS`) is interrupted as it is
detected as a new option.

This option was already added and enabled in commit 7c1a49bc [1]

	SeaBIOS: have coreboot pass the choice to run optionroms in parallel

so SeaBIOS messages are now written to the CBMEM console.

Successfully tested on the Asus M2V-MX SE.

[1] http://seabios.org/Releases
[2] http://review.coreboot.org/5443

Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5093
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-28 22:41:59 +02:00
Edward O'Callaghan 76d8fd6095 mainboard/*: Convert to generic ITE superio romstage component
Convert mainboard's that use model specific romstage functions of
it8712f to the generic framework by following the reasoning of:

a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers

Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5737
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-28 20:08:21 +02:00
Kyösti Mälkki f2f7f03aff console: Add console for GDB
Connection of UARTs to GDB stub got lost in the console transition
process, bring it back. In theory, GDB stub should work also over
usbdebug, but that solution is not really tested at all yet.

Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5343
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 10:52:16 +02:00
Kyösti Mälkki c009601f29 AGESA fam12 fam14 fam15: Declare local callouts static
Change-Id: I2ff70cafdd808a235ed4f0663e182d306f493c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:29:43 +02:00
Kyösti Mälkki f646f6d582 amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT
Removed function only read ACPI MMIO base address from a couple of
registers in IO space.

Change-Id: I25a31b7ac1706b9eebc5db0b9604039928328b0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:29:18 +02:00
Kyösti Mälkki 6b4b1513a5 AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP
Change-Id: I9f27e1e814a80864d8ca315fe816a083c55708c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5682
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:38 +02:00
Kyösti Mälkki 838e211013 AGESA fam12 fam15: Unify agesawrapper_amdlaterunaptask
Pass parameter Func like fam14, fam15tn and fam16kb.

Change-Id: I262bf88e431f7035e668ac8f3fb29ac0690b3e52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5681
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:23 +02:00
Kyösti Mälkki 5e19fa4c51 AGESA fam12 fam14 fam15: Common handler for AGESA_DO_RESET
This is x86 "standard" 0xcf9 reset mechanism.

Change-Id: Ieb48290b21a7cb1425881fdd65c794e96da0248f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5680
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:09 +02:00
Kyösti Mälkki f1bb19abee AGESA fam14: Comment lack of PCI-e slot resets
These boards return with AGESA_UNSUPPORTED, while other boards return
AGESA_SUCCESS here when there is no hardware for external reset signalling.

Change-Id: I5aed211b1812888af55a691cfbfa8d7b5aff91bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5679
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:27:51 +02:00
Kyösti Mälkki c459f9658b AGESA: Add common callouts
Most of the callouts are not specific to board or even family.
Start new file with default callouts doing nothing and returning
either AGESA_SUCCESS or AGESA_UNSUPPORTED.

Also add callout for returning empty IdsIdData. This feature is
not used and could be easily overriden at board-level at later time.

Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:27:31 +02:00
Vladimir Serbinenko 20ea04034d acpigen: Add acpigen_write_irq.
Change-Id: Iba52dc2d52b7ac9a65d1d17b43e7204f5ede373e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5241
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 15:59:46 +02:00
Vladimir Serbinenko a31a838cdb lenovo: Add lenovo_mainboard_partnumber.
Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5246
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 15:59:19 +02:00
Kyösti Mälkki dfdf001392 ChromeOS: Rename chromeos.c in vendorcode
Rename the file to vboot_handoff.c and compile it conditionally
with VBOOT_VERIFY_FIRMWARE.

Change-Id: I8b6fd91063b54cb8f5927c6483a398b75e1d262a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5645
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-25 08:10:49 +02:00
Edward O'Callaghan 604559c193 northbridge/intel/i82810/raminit.c: Unused func spd_read_byte()
Spotted by Clang

Change-Id: Ib119f46fbbbd09a660bd6c4647b96a55d2c532a7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5846
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 07:54:11 +02:00
Edward O'Callaghan 08280cb99b northbridge/intel/e7505/raminit.c: Silence warn of unused func
Spotted by Clang.

Change-Id: Iec34a23d0cf193ca6a4af0407b0763bf77ea03b3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5845
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 07:53:56 +02:00
Edward O'Callaghan 636cd61346 northbridge/intel/i3100/raminit.c: Uninitialized variable
Spotted by Clang

Change-Id: If524a5cd984602a332c4ca28a8167a3597206b94
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5844
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 07:53:51 +02:00
Edward O'Callaghan 2f237c1859 nb/intel/i945/raminit.c: duplicate 'const' declaration specifier
Spotted by Clang

Change-Id: I7e91f3edfa773560131e267a7776d8bf1ff7e295
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5843
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 07:53:28 +02:00
Edward O'Callaghan a916b39e74 southbridge/amd/agesa/hudson: Unused func smbus_delay()
Spotted by Clang

Change-Id: Ic5b04f6f334bc9b1b014a7ada44e9656f7992063
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5847
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 06:06:56 +02:00
Edward O'Callaghan 33d664d9a1 southbridge/amd/cimx/sb900: Unused func smbus_delay()
Spotted by Clang

Change-Id: I14c099625db6f38fd0630b8864cf2a702b81d353
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5832
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 06:06:06 +02:00
Kyösti Mälkki 71714838a6 Drop PCI_BDF macro declaration
Not used and did not have 12 bits reserved to address full PCIe
configuration space per every function.

Change-Id: Ib04a1eb2487735375b4ee738d48a5bebe41ba3c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5835
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-25 04:52:57 +02:00
Edward O'Callaghan 8102a9afb8 mainboard/google/slippy: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I219ae74d60fd7211de2edee96e74bbe13130bb94
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5849
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 04:37:08 +02:00
Edward O'Callaghan 6224c31860 mainboard/google/bolt: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I31841e7bf578c77d08d452779936fcf5b3026d4f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5848
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 04:36:48 +02:00
Edward O'Callaghan 511b383805 superio/ite/it8721f: Trivial drop redundant headers
Change-Id: Ib086cd567c926dd659f67900195f93262ceb50c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5839
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-24 22:48:35 +02:00
Edward O'Callaghan 8f9132fab1 mainboard/amd: Incorrect usage of logical vs. bitwise and
Spotted by Clang

Change-Id: I26201c7f5e421c38d3965d8e7e62c4a8e670e449
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5833
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-24 21:02:14 +02:00
Edward O'Callaghan 6cec824a28 mainboard/google/link: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Id967f6057759cf0603c84514d32b067c3658306f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5831
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-23 22:24:11 +02:00
Edward O'Callaghan 0f2355a090 mainboard/google/falco: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I4e5f2d7e8e6b76703fccce38fc7e3165d763e97f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5830
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-23 22:23:53 +02:00
Edward O'Callaghan 9492b9dab4 superio/winbond/w83697hf: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5727
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-23 20:14:41 +02:00
Edward O'Callaghan 1704637719 mainboard/asus/k8v-x: Remove dubious SIO PNP programming in romstage
Remove bogus attempt to double program the Super I/O. Remove also a
questionable function that enters Super I/O LDN config space, does no
actual LDN programming, rather multi-function register programming and
then never leaves the config space. Further, we don't export pnp_
symbols from the early_serial.c component into the global namespace.

Change-Id: I7d6b97b174249ae16fe881728da5ca3dd069b696
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5800
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-23 20:13:38 +02:00
Rudolf Marek 80b627eb4d Asus F2A85-M: Move to ther proper SIO
The F2A85-M has IT8603E which is a strip down version of IT8728F.
Change configuration from provisional IT8712F to the IT8728F.
While at it also enable only needed LPC bridge decodes.
As the side effect, this change also implements setup of environmental
controller, thus it87 driver can detect the temperatures/fans.

Change-Id: I22067b13ea27ee37e959a246718d9559c2a3215d
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4499
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 20:09:36 +02:00
Rudolf Marek 290bed7258 Implement proper IT8728F PNP ops
The Asus F2A85-M has IT8306E which is a stripped down version
of this SIO. Implement the PNP operations of the SIO.

Change-Id: Ibc4f3fafc3ffb1cd799948e63be01e6924b45d6c
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4498
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 20:07:37 +02:00
Rudolf Marek a7d14a170e ite/common: Introduce common watchdog and 3.3V VSB helpers
Introduce the watchog and 3.3 VSB helper functions.
The IT8712F can be migrated to use those too. To be used
with IT8728F.

Change-Id: If21e99b6069c7222f0bc8eb7c7121fe119b8dfe1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/5728
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 20:06:34 +02:00
Rudolf Marek 4405b06521 superio/ite/it8728f/it8728f_hwm.c: Small fixes
Use proper include header in it8728f_hwm.c, fix format error.
The base of HWM block starts at offset +5.

Change-Id: I6855225b38bbcf5687d506bea9482c951d314684
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/5729
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-23 19:44:52 +02:00
Edward O'Callaghan b27d3602e0 mainboard/samsung/stumpy: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I6c5cc46385581d6b69d20f6bc9b016b799765d9e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:42:03 +02:00
Edward O'Callaghan ea4ae2f02b mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Idda1a49277c156670014fac27b9f1c378f8df0cd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:42:00 +02:00
Edward O'Callaghan c686c95c98 mainboard/intel/baskingridge Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I61fe91e467c29f144323af9c4612420f322098b4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:41:59 +02:00
Edward O'Callaghan 6aa6509cae mainboard/intel/wtm2: Fix usage of GNU field designator extension
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I46fad8d236c620ee5dbeb24f4517f20f00db839f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:41:57 +02:00
Edward O'Callaghan 6f49f69ed0 mainboard/kontron/ktqm77: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: If948960abbd927aa6d2b471a42a2321a04d992f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:41:56 +02:00
Martin Roth a0427cb844 vendorcode/intel/fsp/rangeley: remove extra file
This is an extra file that is included in the Intel GSP release.
It's got a coreboot header on it, isn't used, and looks very
platform specific.
I'm not sure where it belongs, but it doesn't belong in vendorcode.

I've sent the contacts at Intel an email letting them know that this
file should probably be removed from their FSP release and is getting
removed here.

Change-Id: I5ac6649235846ce5716bb180af29a5e422f4cce3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-23 19:32:08 +02:00
Patrick Georgi e9e99e976e drivers/pc80/Kconfig: Revert PS/2 initialization defaults
Remove the inconsistent behaviour based on unrelated
configuration: PS/2 init is now always enabled.
This can change once we find a better approach.

Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5634
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
2014-05-23 19:28:22 +02:00
Edward O'Callaghan 8084e5b6da mainboard/google/peppy Fix usage of GNU field designator extension
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Idd7305cb34be77894ca4b6062bc0a2dc61126347
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 15:38:35 +02:00
Edward O'Callaghan f5037bd570 mainboard/google/parrot Fix usage of GNU field designator extension
Following the reasoning in:

8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I5be77fe6670601e103260077fae07a5b9fd41f1d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5821
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 15:38:34 +02:00
Edward O'Callaghan 68a56caf7e northbridge/amd/amdmct: Incorrect usage of logical over bitwise and
Small mix up of logical/bitwise logical and operation. Spotted by Clang.

Change-Id: I2c2256b9b2f2b6ca627914118c745f579555acc9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5820
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23 01:49:48 +02:00
Edward O'Callaghan ba363d3f18 northbridge/amd/amdmct: Superfluous parenthesis in if-statements
Remove superfluous parenthesis found in some if-statements, spotted by
Clang.

Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5817
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23 01:45:33 +02:00
Edward O'Callaghan de6c3c846a southbridge/amd/cimx/sb700: Unused func smbus_delay()
Spotted by Clang.

Change-Id: Ie4bed914ab694f4e96155140b8b54b6eb96d70d7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5819
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22 22:55:16 +02:00
Edward O'Callaghan 3a5ea48c0c vendorcode/amd/agesa/f*: Fix typo in header guards
_CPU_L3_FEATIRES_H -> _CPU_L3_FEATURES_H

Spotted by Clang

Change-Id: I1eabebffc7fd5e4f37b28dabcd28984bed64acd8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5818
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22 22:54:48 +02:00
Edward O'Callaghan 72ae4a3091 northbridge/amd/amdmct/mct: Initialize variables at the eol
Spotted by Clang

Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5816
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22 22:49:48 +02:00
Edward O'Callaghan f67395ee5b southbridge/amd/sb700/smbus.c: Unused func smbus_delay()
Spotted by Clang

Change-Id: I0f04c380b5ada28fb900710facc293edd65ac177
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5815
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22 22:49:17 +02:00
Martin Roth 351aff85ee device/pci_ids.h: defines for new Intel LPC devices
Add defines for the Cave Creek and Rangeley LPC devices.  These
chipsets will be added shortly.  This file is outside of any of
the directories that will be touched by those additions, so it's
getting changed in its own commit.

Change-Id: Ia829282b2ad67eef09689858500bc7f93a1cd05b
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5810
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-22 05:22:25 +02:00
Martin Roth efac717f3c x86/include/arch/acpi.h: remove incorrect semicolon
The semicolon really shouldn't be in the include...

Change-Id: I90a0f516857365fddd21311cd703132af8d51007
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5808
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-22 05:20:32 +02:00
Martin Roth 16d953a460 device_romstage: Add a way to move to the next device
When trying to loop through all the devices in romstage, there was
no function to just go from one to the next.

This allows an easy way to go all the way down the chain of devices.

Change-Id: Id205b24610d75de060b0d48fa283a2ab92d1df0a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5732
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-21 22:38:33 +02:00
Edward O'Callaghan db0e0e2c54 amd/agesa/*/gcc-intrin.h: Invaild inline asm
The 'm' (a memory reference) constraint makes little sense here since we
are talking about a fs relative read, rather 'ir' (immediate or
register) constraint is more sensible.

N.B. The 'p' constraint allows anything which fits the form of an address
calculation where the 'ir' constraint is just a register /xor/
immediate. Hence would produce better code here however, unfortunately,
clang does not currently support it properly.

The %b and %w constraints are also redundant and only hide errors.

The functions writefsword() and writefsdword() should use ir instead of
iq. iq is unnecessarily restrictive (it is only required for writing
bytes).

The cld in stosb is redundant (and the constraints are unnecessarily
complicated). Note that The ABI guarantees that the direction flag is
cleared. i.e. eax, ecx, edx are caller-saved, returned value in eax,
eax+edx, st0, yaddayadda, direction flag cleared. In fact bad things can
happen if you set it in some asm and do not clear it until the end of
the asm.

Line wrap these extraneously long lines found with these particular functions.

Many thanks to Christoph Mallon <christoph.mallon@gmx.de> from #llvm for
helping me with this.

Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21 21:40:53 +02:00
Edward O'Callaghan 3312ed7e7a amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct
The semantics of this loop relies on an integer overflow in Index >=0
that implies a return value of (UINT8)-1 which around wraps to 0xFF, or
VOLT_UNSUPPORTED.

Change-Id: I44d68973d0a80093350b2a8a4d3b46bfbb57917a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5801
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21 21:35:16 +02:00
Edward O'Callaghan 2c9e370646 mainboard/ibase/mb899: Sanitize headers
These are not local headers.

Change-Id: Ie0b0a682565a08dbfa089986dc7860fdb0846949
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5796
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-21 02:29:28 +02:00
Edward O'Callaghan 0deb355d0e vendorcode/amd/agesa: unsigned enum is strictly positive
The typedef'ed BIT_FIELD_NAME enum is type unsigned. The parameter
'FieldName' is decleared with type BIT_FIELD_NAME and thus the redudant
comparison of unsigned enum expression >= 0 is always true.

BIT_FIELD_NAME is declared in vendorcode/amd/agesa/f14/Proc/Mem/mm.h

Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5757
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21 02:17:20 +02:00
Edward O'Callaghan 8a661ed788 amd/cimx/sb?00/SATA.c: Integer overflow in loop condition
The conditional comparison in the for-loop construct with the constant
300000 has an index incrementor of type 'UINT16' (aka 'unsigned short')
which is always true.

Change-Id: I932c168742163be4038728fb40833231a447fa78
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5799
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-21 01:58:56 +02:00
David Hendricks 03b00e9675 baytrail: Fix some minor errors in FSP
- Duplicate declaration of GetFspReservedMemoryFromGuid
- Corrupt line that was only compiled for a southbridge that no
  board in coreboot currently uses.

(thanks for Mike Hibbett <mhibbett@ircona.com> for pointing this out)

Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/5798
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-21 01:21:30 +02:00
Edward O'Callaghan 61113de923 mainboard/ibase/mb899: Indent devicetree.cb
Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5778
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-20 13:47:38 +02:00
Edward O'Callaghan fb8df3240f drivers: Drop GbE stub drivers
These NIC stub drivers were to initialize the Gigabit Ethernet adapters
just enough to keep coreboot from trying to execute an option ROM.
However this is no longer required as non-VGA option roms are not ran;
See:

b32816e Remove PCI_ROM_RUN option

Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5777
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-20 13:46:35 +02:00
Edward O'Callaghan 8dd407a878 vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp
The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum
sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk.
However, MinDeltaSclk incorrectly self-assigns.

Change-Id: Id01c792057681516bba411adec268769a3549aa8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5752
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-05-19 22:39:23 +02:00
Edward O'Callaghan b2d68976c8 amd/agesa: Implicit assigment between enum without cast
Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19 22:39:01 +02:00
Edward O'Callaghan e1845b38c7 amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.h
Change-Id: I1d801b9d8387e267feeb95563e55910b30ebbc34
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5790
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-19 22:38:34 +02:00
Kyösti Mälkki 5cf8824923 via/vx900: Remove GFXUMA and use of related global variables
Remove global variables uma_memory_base and uma_memory_size
from builds with via/vx900 northbridge, as these variables can be kept
within the chipset.

Change-Id: I9f8aea4836d81e704eae6a0f2cefc7fd4586b8b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5721
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 17:20:44 +02:00
Kyösti Mälkki f7bfc34942 intel: Remove GFXUMA and related global variables
Remove use of global variables uma_memory_base and uma_memory_size
from builds with Intel northbridges, as these variables can be kept
within the chipset or even as stack locals.

Intel platforms have no functional implemenation for option GFXUMA.
If we did implement some choice between external and integrated graphics,
it needs to be named in less obscure fashion.

Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 17:20:13 +02:00
Kyösti Mälkki 5f09807229 Add guard for UMA globals
We no longer need these globally. Guard them so we get to declare
static replacements at few locations until complete removal.

Change-Id: Ie33e2a680fc9bbb7e28c8fbe17e5181e626736a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5718
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 17:19:46 +02:00
Patrick Georgi 5930774f57 build: use CFLAGS_* in more places where they're needed
After moving out -m32 from CC_*, 64bit compilers need
CFLAGS_* in more places to handle everything in 32bit
as appropriate.

Change-Id: I692a46836fc0ba29a3a9eb47b123e3712691b45d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5789
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 15:21:52 +02:00
Patrick Georgi 9f5af6a65a vendorcode/amd: kill some intermediate variables in build system
They don't exactly add clarity, but increase the risk
they're used at some obscure place.

Change-Id: Ic74f72dae3f9b7eb2343cb5c51bc44c888e1276c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5787
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 15:20:33 +02:00
Patrick Georgi e3927436c6 build: move include paths where they belong
They're _not_ part of the compiler binary, so they have
no place in $(CC_*)

Change-Id: I1e1c3c0be6f75629450a824ea834e1614d48ed9b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5785
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 15:20:28 +02:00
Patrick Georgi 2313c8bb65 agesa: drop non-existing search paths
With the upcoming CC/CFLAGS/CPPFLAGS split,
romcc gets more CPPFLAGS, and it's picky about
directories actually existing.

Change-Id: Ib9c525296e5be0c8ace935ab8096bc98206cbcc1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5784
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 15:20:18 +02:00
Patrick Georgi 6f7e4b21db fix printk types
Some size_ts were considered long int and some compilers
are picky about that.

Change-Id: I671daa18eb3bfa2a7defc120e77bbb1ef72bd417
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5788
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 15:19:01 +02:00
Kyösti Mälkki a6b6172ae3 Add aliases for Chromebooks in board_info
This defines new board_info entry 'Vendor name' to be displayed in place of, or
in addition to, the CONFIG_VENDOR string 'Google'.

Also flag these as flashrom accessible SPI without socket. Instructions to
disable flash write-protection can be found at Chromium developer documentation.

Change-Id: I69791a091417a80d01e0ba2c6462417730a07be0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 14:57:54 +02:00
Kyösti Mälkki ee96c2ccbb LiPPERT: Add aliases for board_status wiki
While at it, fix frontrunner-af board URL.

Change-Id: I3b631830d679abc20f8a72411f2402689d9f9aac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-05-19 14:57:14 +02:00
Edward O'Callaghan c86762657d device/oprom/yabel/vbe.c: Avoid unused func warn
Change-Id: Idd74893c1fc3d0818d00c1f727c9fdc27168af0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5782
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-18 18:05:43 +02:00
Edward O'Callaghan 9c8532b350 drivers/spi/sst.c: Remove unused func to_sst_spi_flash()
Trips up clang builds with a warn treated as error.

Change-Id: I9c0e2930ba8a60c7ad6063e9826b1b8638185505
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5779
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-18 18:05:42 +02:00
Damien Zammit 40788c6a4e lenovo/t60: Enable dock serial port when undocked and redocked
When the system is started with dock, the serial port works.
As soon as the laptop is undocked and redocked, the serial port
no longer works.  See below superiotool dump snippet:

Upon bootup: SIO @ 0x2e
LDN 0x03 (COM1)
idx 30 60 61 70 71 74 75 f0
val 01 03 f8 04 03 04 04 02

Redocked:    SIO @ 0x2e
LDN 0x03 (COM1)
idx 30 60 61 70 71 74 75 f0
val 00 03 f8 04 03 04 04 02

Since the function dock_connect is executed every time the
dock is reconnected, starting without a dock and then attaching
it to a dock is now also fixed.

Change-Id: Ibd97589a8c743673a55e382a5db2ba62656c595e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5761
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:27:11 +02:00
Patrick Georgi fadbe5f657 build: make scan-build work again
This drops the scan-build related Kconfig options
since it's now possible to simply run

    scan-build [-o outdir] make

and get coreboot built with its report.

There's also no inner make process anymore, and the way
things work should be clearer now.

Also adapt abuild to this new reality.

Change-Id: I03e03334761ec83f718b3235ebf811834cd2e3e3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5774
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:15:14 +02:00
Patrick Georgi b145b8301f build: break compiler flags out of $(CC)
Having more than the executable in $(CC) only leads to
trouble in a number of situations.

Change-Id: I7642ca4068b3a3bd5798219d74de9e0eb85bb4e5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5769
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:52 +02:00
Patrick Georgi 4ebd3d9195 build: kill one indirection
No need to first define X86_32 and then replace every
single use of it with its lower cased equivalent.
Just start out with the lower case versions in the first
place.

Change-Id: I1e771ef443db1b8d34018d19a64a9ee489cd8133
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5767
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:41 +02:00
Patrick Georgi 58f73a69cd build: separate CPPFLAGS from CFLAGS
There are a couple of places where CPPFLAGS are
pasted into CFLAGS, eliminate them.

Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5765
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:29 +02:00
Patrick Georgi 98f49d2823 build: CPPFLAGS is more common than INCLUDES
Rename INCLUDES to CPPFLAGS since the latter is more
commonly used for preprocessor options.

Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5764
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:24 +02:00
Patrick Georgi 1ec065bffa drivers/pc80/Kconfig: simplify PS/2 selection rules
There's no need to state the dependency twice.

Change-Id: Ia241d441211c6f476d0a6ed7589b038f7a220265
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5633
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-05-15 10:08:38 +02:00
Duncan Laurie 9fd7c0f18e baytrail: Add SOC thermal settings
Apply the SOC thermal settings from DPTF reference code for
SdpProfile=4 and adjust graphics PUNIT setting to match.

BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=boot on rambi and check for valid GPU power values from DPTF

Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5052
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-15 05:09:27 +02:00
Duncan Laurie c6313db34f baytrail: Enable PCIe common clock and ASPM
Enable the config options to have the device enumeration layer configure
common clock and ASPM for endpoints.

BUG=chrome-os-partner:23629
BRANCH=baytrail
TEST=build and boot on rambi, check PCIe for ASPM and common clock:

lspci -vv -s 0:1c.0 | grep LnkCtl:
 LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

lspci -vv -s 1:00.0 | grep LnkCtl:
 LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+

Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:07:07 +02:00
Aaron Durbin 3549462a95 baytrail: enable graphics turbo
Though the limited documentation indicates the default is
0 for the gfx_turbo_disable bit, in practice that isn't
true. Knock down the gfs_turbo_disable bit to enable
graphics turbo mode.

BUG=chrome-os-partner:25044
BRANCH=baytrail
TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG.
     Noted that bit 7 was set to 0.

Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5050
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:06:53 +02:00
Duncan Laurie 469b5205c3 rambi: Add ACPI devices and interrupts for codec and ALS
The Codec and ALS both have interrupt sources that can be configured.
The ALS kernel driver currently does not try to use it but the codec
driver does for things like jack detect.

ACPI Devices are added, but as with other ACPI devices the HID may
need to be updated once more official strings are decided.

BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual: build and boot on rambi and check for functional lightsensor

Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182366
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5049
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:06:38 +02:00
Aaron Durbin 59d1d87c86 baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
On baytrail, it appears that the turbo disable setting is
actually building-block scoped. One can see this on quad
core parts where if enable_turbo() is called only on the
BSP then only cpus 0 and 1 have turbo enabled. Fix this
by calling enable_turbo() on all non-bsp cpus.

BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and booted rambi. All cpus have bit 38 set to 0
     in msr 0x1a0.

Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182406
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5048
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:06:17 +02:00
Duncan Laurie 3f94a74de2 baytrail: Add ACPI Device for XHCI
This will allow USB devices to wake the system (if 5V is not turned off)
and the controller to enter D3 at runtime. (if autosuspend is enabled)

BUG=chrome-os-partner:23629
BRANCH=baytrail
TEST=build and boot on baytrail

1) with modified EC to leave 5V on in S3 ensure that waking from suspend
with USB keyboard works.
2) with laptop-mode-tools usb autosuepend config updated see that device
enters D3 at runtime when no external devices attached.

Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182536
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:44 +02:00
Duncan Laurie 5a45c9529a rambi: Add ACPI table support for I2C devices
In order to support probing I2C devices when the controller is
in ACPI mode the mainboard needs to decalre them in the proper
scope with the address/interrupt information.  The touchpad devices
are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can
be distinguished in userland scripts based on ID.  There is also
a special "ISTP" node that indicates whether the devices is a
touchpad (=1) or touchscreen (=0) in case this is useful to drivers.

These names may not be final but they are a starting point and can
be easily changed.

Atmel devices also have a bootloader mode which needs to be
declared as a separate device.  Unfortunately it does not work as
expected to have multiple I2cSerialBus() resources declared in a
single device and have it select properly, even with the use of
StartDependentFn(), so bootloader devices are declared separately.

The original devices are left in \_SB scope and are only enabled
if the I2C controllers are in PCI mode.  The new devices are only
enabled if the I2C controllers are in ACPI mode.

BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual

1) Ensure there is no change in functionality by default and that
the devices are still probed by chromeos_laptop in the kernel.
2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to
add _HID entries for devices in appropriate drivers.  Ensure that
the devices are probed successfully.  Further changes are needed
to the chromeos-touch-firmware scripts to load config and update
firmware based on the new ACPI _HID entries.
3) Put touchpad in bootloader mode (by flashing bad firmware) and
ensure that it is detected at address 0x25 and the firmware is
able to be updated.

Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5045
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:31 +02:00
Aaron Durbin b013fff5a3 baytrail: nvm: use proper types for checking erase
The current byte value was being converted to an int
when checking against literal 0xff. As the type of
the current pointer was char (signed) it was sign
extending the value leading to 0xffffffff != 0xff.
Fix this by using an unsigned type and using a
constant type for expected erase value.

BUG=chrome-os-partner:24916
BRANCH=baytrail
TEST=Booted after chromeos-firmwareupdate. Noted that MRC
     cache doesn't think the erased region isn't erased.

Change-Id: If95425fe26da050acb25f52bea060e288ad3633c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182154
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5044
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:21 +02:00
Aaron Durbin 931e590745 baytrail: mrc_cache: check region erased before erasing
On a firmware update the MRC cache is destroyed. On the
subsequent boot the MRC region was attempted to be erased
even if it was already erased. This led to spi part taking
longer than it should have for an unnecessary erase
operation. Therefore, check that the region is erased
before issuing the erease command.

BUG=chrome-os-partner:24916
BRANCH=baytrail
TEST=Booted after chromeos-firmeareupdate. Noted no
     error messages in this path.

Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182153
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5043
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:09 +02:00
Aaron Durbin 58d6e18f0c rambi: disable SERIRQ native functionality
Nothing can actually use this as the EC cannot speak
using baytrail's SERIRQ protocol. Also, the voltage
bridge is going away so nothing will be hooked up to it.
Therefore disable this it.

BUG=chrome-os-partner:24693
BRANCH=rambi
TEST=Built and booted.

Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182082
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5042
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:00 +02:00
Edward O'Callaghan f24318dfb6 southbridge/amd/cimx/sb800: Unused func smbus_delay()
Change-Id: Icc12aafc1462c08bca77a1798d4fae86b8250708
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5748
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-05-14 21:48:27 +02:00
Edward O'Callaghan f6ba9f6a65 mainboard/lenovo/t520: too many arguments to pc_keyboard_init
Fix build regression introduced in:
a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support

Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5738
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-14 13:10:43 +02:00
Kyösti Mälkki a6130fc8f9 intel: Drop obsolete comments on MTRR usage
Problem with UMA region allocation was fixed when MTRRs changed to use
memrange implementation.

Change-Id: I420dac30de2836a91596d81f88bb45b46f248532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-05-14 07:30:20 +02:00
Zaolin a823f9b545 mainboard/lenovo: Add Lenovo Thinkpad T520 support
Short list of known issues for this patchset:

* Suspend/Resume - does not work
* Combi pci card for SD/MMC card reader with IEEE1394 - not found
* Shutdown - sometimes does not work as expected
* At least mysterious harddrive i/o

Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/5672
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-13 22:00:10 +02:00
Zaolin 3d68b1a62a cpu/intel: Add CPU socket rPGA988B
Used by the Lenovo ThinkPad T520

Change-Id: I1009616cc4c18ebd0e3be7ceb50398617b49e3a3
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/5671
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-13 21:58:16 +02:00
Aaron Durbin 580b1ad618 baytrail: add C0 microcode update
Include C0 microcode drop.

BUG=None
BRANCH=rambi,squawks
TEST=Built. Booted B3 part.

Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182080
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5041
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:02:40 +02:00
Aaron Durbin 107b71c3a3 baytrail: reboot with EC in S0 with no MRC cache and EC in RW
This improves boot time in 2 ways for a firmware upgrade:

1. Normally MRC would detect the S0 state without an MRC cache
   even though it's told to the S5 path. When it observes this
   state a cold reset occurs. The cold reset stays in S5 for
   at least 4 seconds which is time observed by the end user.

2. As the EC was running RW code before the reset after firmware
   upgrade it will still be running the older RW code. Vboot will
   then reboot the EC and the whole system to put the EC into RO
   mode so it can handle the RW update.

The issues are mitigated by detecting the system is in S0 with
no MRC cache and the EC isn't in RO mode. Therefore we can do the
reboot without waiting the 4 secs and the EC is running RO so
the 2nd reboot is not necessary.

BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
     EC reboot before MRC execution.

Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182061
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5040
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:02:09 +02:00
Aaron Durbin 9f1a7cffab chromeec: add function to reboot on unexpected image
It's helpful to have a generic function that will tell
the EC to reboot if the EC isn't running a specified
image. Add that and implement google_chromeec_early_init()
to utilize the new function still maintaing its semantics
of if recvoery mode is enabled the EC should be running its
RO image. There is a slight change in that no communication
is done with the EC if not in recovery mode.

BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Built and boot with recovery request. Noted EC reboot.

Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182060
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5039
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:01:52 +02:00
Duncan Laurie b376ea632f baytrail: dptf: Add disable trip point methods
Added a method in each temp sensor to disable the aux trip points
and then a wrapper function to call this method for each enabled
temperature sensor.

The event handler function is changed to not use a switch statement
so it does not need to be serialized.  This was causing issues
with nested locking between the global lock and the EC PATM mutex.

Some unused code in temp sensors that was added earlier is removed
and instead a critical threshold is specified in _CRT.

The top level DPTF device _OSC method is expanded to check for the
passive policy UUID and initialize thermal devices.  This is done
for both enable and disable steps to ensure that the EC thermal
thresholds are reset in both cases.

Additionally the priority based _TRT is specified with TRTR=1.

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, load esif_lf kernel drivers and start
esif_uf application.  Observe that temperature thresholds are set
properly when running 'appstart Dptf' and that they are disabled
after running 'appstop Dptf'

Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182024
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5037
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:01:38 +02:00
Duncan Laurie dec0148100 rambi: dptf: Set critical thresholds
Set critical temperature thresdholds to 70C.  This will cause DPTF
framework to shut down the system so it may need to be higher or
lower but will need some testing.

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, start DPTF framework and observe it
using specified critical thresholds.

Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182025
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5038
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:01:28 +02:00
Duncan Laurie 8be6759f79 chrome ec: Fix temperature calcualtion in PATx methods
The PATx methods will be passed a temperature in deci-kelvin,
so it needs to be converted back to kelvin before being sent
to the EC.

The PAT disable method is changed to take the temperature ID
as an argument so individual sensors can be disabled.

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, load esif_lf kernel drivers and
esif_uf userspace application.  Start and stop DPTF and see
that temperature thresholds are set to sane values.

Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182023
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5036
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:00:11 +02:00
Aaron Durbin b3ce658608 chrome ec: call DPTF thermal threshold event handler
When an EC thermal event occurs call the DPTF thermal threshold
event handler to handle notifications.

Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5726
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 20:59:38 +02:00
Duncan Laurie a36d60af1a baytrail: Updates for DPTF ACPI framework
- Remove some unused functions from CPU participant that were
confusing the userland component since the CPU does not have
an ACPI managed sensor.

- Guard the charger participant with an ifdef so it can be
left out if not supported.

- Use the EC methods for setting auxiliary trip points and for
handling the event when those trip points are crossed.

- Add _NTT _DTI _SCP methods for thermal sensors.  I'm not
clear if these are required or not but they seem to be expected
by the other DPTF framework components.

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi and load ESIF framework

Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5028
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 20:59:27 +02:00
Duncan Laurie 93e244433a chrome ec: Update header and add functions to support DPTF
The EC now supports two auxiliary programmable trip points for
thermal monitoring.  These are expected to be used by DPTF and
need to be exported.

In order to support these the header was updated from the latest
chrome ec source.

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 20:59:11 +02:00
Duncan Laurie 063b2c4df7 rambi: Update the DPTF configuration
- Add passive thresholds for thermal participants
- Disable the charger participant and remove from _TRT

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi and start ESIF framework

Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181663
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5029
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 20:59:02 +02:00
Aaron Durbin 766482d320 baytrail: don't SMI on tco timer firing
The SMI on TCO timer timeout policy was copied from other
chipsets. However, it's not very advantageous to have
the TCO timer timeout trigger an SMI unless the firmware
was the one responsible for setting up the timer.

BUG=chromium:321832
BRANCH=rambi,squawks
TEST=Manually enabled TCO timer. TCO fires and logged in
     eventlog.

Change-Id: I420b14d6aa778335a925784a64160fa885cba20f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181985
Reviewed-on: http://review.coreboot.org/5035
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:11:40 +02:00
Aaron Durbin 19edc3a2e5 baytrail: clear the pmc wake status registers
The PMC in baytrail maintains an additional set
wake status in memory-mapped registers. If these
bits aren't cleared the device won't be able to
go to S5 or S3 without being immediately woken up.
Therefore clear these registers.

BUG=chrome-os-partner:24913
BRANCH=rambi,squawks
TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work
     correctly.

Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181984
Reviewed-on: http://review.coreboot.org/5034
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:11:25 +02:00
Aaron Durbin 8f31ecf28b baytrail: log reset, power, and wake events in elog
When CONFIG_ELOG is selected the reset, power, and wake
events are logged in the eventlog.

BUG=chrome-os-partner:24907
BRANCH=rambi,squawks
TEST=Various resets and wake sources. Interrogated eventlog
     to ensure results are expected.

Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181983
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5033
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:11:13 +02:00
Aaron Durbin 00bf3dbf35 baytrail: snapshot power state in romstage
The memory reference code doesn't maintain some of
the registers which contain valuable information in order
to log correct reset and wake events in the eventlog. Therefore
snapshot the registers which matter in this area so that
they can be consumed by ramstage.

BUG=chrome-os-partner:24907
BRANCH=rambi,squawks
TEST=Did various resets/wakes with logging patch which
     consumes this structure. Eventlog can pick up reset
     events and power failures.

Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181982
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5032
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:11:04 +02:00
Aaron Durbin 1ea9bde5af baytrail: add cpuid for C0
The C0 part uses a new cpuid.

BUG=None
BRANCH=squawks,rambi
TEST=None.

Change-Id: Iddf1bc4d6f7bbec3ca92bff8edf613e00a4b4286
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181980
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5031
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:10:50 +02:00
Shawn Nematbakhsh b697eab938 rambi: Move KBD_IRQ pin for Rambi 2.0 board
KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original
SERIRQ function.

Note that this change breaks Rambi 1.5 keyboard functionality.

BUG=chrome-os-partner:24424
TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB
interrupt toggling removed from EC code.
BRANCH=Rambi, Glimmer, Clapper

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b
Reviewed-on: https://chromium-review.googlesource.com/181757
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:10:41 +02:00
Edward O'Callaghan e1fe688c9b src/*: Remove the last remnants of struct keyboard
Change-Id: I7d0e8d2119a470428cfc01c0738b8988ab75ba2d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5624
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 12:14:34 +02:00
Edward O'Callaghan f6f1ad6376 superio/*: Remove redundant chip.h header
Change-Id: If7141112ea67071ee05c52f455c3b2496aa7e17e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5622
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 12:14:00 +02:00
Edward O'Callaghan 0403c863e1 superio/*: Deal with some chip.h special cases
While backing out the empty pc80 keyboard struct we encountered some
special cases where chip.h is used for other purposes. Deal with these
cases.

Change-Id: Ib11a46cfd14d050d5daa213623b9d8a401c06410
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5621
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 10:31:55 +02:00
Edward O'Callaghan def00be41d src/drivers/pc80: Remove empty struct keyboard
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.

Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-13 10:03:51 +02:00
Edward O'Callaghan e61dd0f7a2 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.

Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 10:03:38 +02:00
Kyösti Mälkki 216a619a74 Rambi: Enable 32k SUSCLK signal
The SoC needs to provide a 32k clock signal SUSCLK for
some modems to work properly, so this enables the signal.

BUG=chrome-os-partner:24425
TEST=Manual, check SUSCLK pin with a scope.

Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c
Reviewed-on: https://chromium-review.googlesource.com/180101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5722
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:38:42 +02:00
Shawn Nematbakhsh 6a70258c69 rambi: Make eMMC CLK pull-down and change pull strengths to 20K
eMMC CLK was incorrectly configured as PULL_UP, but should have been
PULL_DOWN. 2K pulls somehow masked this problem.

BUG=chrome-os-partner:24353
TEST=Verify eMMC is bootable on Rambi on boards that previously failed
with an all-20K, all-PU eMMC pin configuration.
BRANCH=None

Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5026
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:11:37 +02:00
Aaron Durbin 003931975f baytrail: align with intel recommendations
The BISOC.EXIT_SELF_REFRESH_LATENCY field should
not be updated from the default.

BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. S3 resumed.

Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180730
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5025
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:11:10 +02:00
Aaron Durbin 68530cdb7c rambi: specify reference code index in vboot area
Rambi's reference code will live at slot 3 in the
verified firmware section.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. Verified correct area where
     reference code was loaded from.

Change-Id: I8bee46600429ac8f732fe334852f69aff1324150
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180027
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5024
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:10:55 +02:00
Aaron Durbin 7f17759e82 baytrail: add way to load reference code from vboot area
When employing vboot firmware verification the reference
code loading should load from the verified firmware
section. Add this ability.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted rambi. Noted firmware being loaded
     from rw verified area. Also noted S3 resume loading
     from cached area.

Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180026
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5023
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12 22:10:33 +02:00
Duncan Laurie 2e65796481 baytrail: Expose IOSF as ACPI object
The kernel iosf driver uses HID INT33BD to probe and
be provided the 12 bytes in PCI for access.

BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, load iosf_mbi driver and
verify that it gets address 0xe00000d0

Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180098
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5021
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:10:18 +02:00
Duncan Laurie 73c0a05bc7 rambi: Disable HSUART2 and SPI interfaces
Not used currently on rambi board.  Disable in case it
saves power.

BUG=chrome-os-partner:23862
BRANCH=none
TEST=build and boot on rambi

Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180084
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5020
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:09:49 +02:00
Duncan Laurie 7e647f596c rambi: Enable SCC devices in ACPI mode
With the ACPI GNVS exported and depthcharge changed to
initialize eMMC in ACPI mode we can now put the SCC
devices into ACPI mode.

BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot on rambi, test eMMC and SD card

Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5018
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:08:30 +02:00
Duncan Laurie c29d6b8ab2 baytrail: Put devices in ACPI mode after setup
Make sure reg_script is executed before the device is put into
ACPI mode.

BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi from eMMC in ACPI mode

Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5017
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:08:22 +02:00
Duncan Laurie d82caded48 baytrail: Add header include wrapper and offset define
Since this file will get added to payloads it is useful if it
exports what offset in NVS it lives.

BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot rambi with emmc in ACPI mode

Change-Id: I52860980c91dfe2525628e142b34ca192e69b258
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5014
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:08:15 +02:00
Edward O'Callaghan 2e4dea663c superio/ite/it8718f: Remove hard coding from romstage
Make use of the ITE common Super I/O framework and there-by removing any
hard coding of Super I/O base address.

Change-Id: I14af89d2727d7c6bac0f9840043c430726297429
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5717
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12 17:43:46 +02:00
Edward O'Callaghan f29200240e superio/ite/*: Factor out generic romstage component
Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5585
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11 17:52:08 +02:00
Edward O'Callaghan 946bee1c34 superio/ite/it8728f: RAMstage PNP configuration component
Provide devicetree.cb RAMstage configuration of this superio component.

Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5668
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11 17:20:31 +02:00
Patrick Georgi 31dbb536fa SeaBIOS: Fix cpp use
No need to pass CPP down to SeaBIOS, it's not
architecture specific and they define their own
variable.

Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5715
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-11 08:51:54 +02:00
Furquan Shaikh a3b06c99d0 Arch-level Kconfig menu cleanup
Remove arch-level Kconfig menu option as it shows all available architectures in
make menuconfig. Instead pull the bootblock options for choice and update image
to top-level Kconfig since it is already present for both x86 and arm.

Change-Id: Iab9c4539f05cd54a7f751565fefcaf7b6f0edc86
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5673
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-10 14:32:26 +02:00
Kyösti Mälkki 5c3f384f06 Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT
Lines with 'select SERIAL_CPU_INIT' where redundant with the
default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
possibility, invert the default and rename option.

This squelches Kconfig warnings about unmet dependencies.

Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5700
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-10 11:27:25 +02:00
Edward O'Callaghan a7e2cc507b mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cb
Turn on WDT support in the devicetree. Turn off CIR support.
Dispense with old commentary.

Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5698
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:34:34 +02:00
Edward O'Callaghan c848098b2f superio/fintek/f71869ad: Fix incorrect LDN's
Turns out there are a few minor differences of the LDN's in the AD rev.
of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the
now incorrect io mask. Add missing CIR LDN functionality and touch up
src inline doc.

Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5696
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:34:21 +02:00
Aaron Durbin 63fcb4a1f8 baytrail: cache reference code for S3 resume
In order to use the same reference code on S3 resume
that was booted the program needs to be cached. Piggy
back on the ramstage cache to save the loaded reference
code program.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed. Noted locations of reference
     code caching and load addresses in console.

Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179777
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5013
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:59 +02:00
Aaron Durbin ce727e18f0 baytrail: allow ramstage_cache_location() usage in ramstage
To prepare for caching reference code for S3 resume the
ramstage cache needs to be accesible in ramstage as well.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.

Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5012
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:52 +02:00
Aaron Durbin be2512973d ramstage_cache: allow ramstage usage add valid helper
Allow ramstage cache to be used from ramstage proper. Also
add a helper function for checking validity of ramstage
cache structure.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.

Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179775
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5011
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:45 +02:00
Aaron Durbin 7d34c6070b baytrail: note S3 resume status earlier
Certain code paths want to know if S3 resume is
happening. However, the current baytrail code doesn't
note S3 resume early enough. Therefore, mark S3
resume just after pattr setup.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.

Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179774
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5010
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:37 +02:00
Aaron Durbin 616f394d36 baytrail: utilize reg_script_run_on_dev()
The inclusion of reg_script_run_on_dev() allows
for removing some of the chained reg_scripts just
to set up the device context. Use the new reg_script
function in those cases.

BUG=None
BRANCH=None
TEST=Built and booted. Didn't see any bizarre dmesg or coreboot
     console output.

Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438
Signed-off-by: Aaron Durbin <adurbin@chromium.og>
Reviewed-on: https://chromium-review.googlesource.com/179541
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5009
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:29 +02:00
Aaron Durbin cffe795dc1 baytrail: initialize perf/power registers
According to the reference code all these registers
need to be set to their best known values.

BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. Suspend and wake. No idea about
     observable impact yet.

Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179749
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5008
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:07 +02:00
Aaron Durbin bc5b557a81 baytrail: add more iosf access functions
There's a slew of ports required to initialize baytrail's
perf and power values. Therefore, add the necessary
functionality in the iosf module as well as the reg_script
library.

BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted.

Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179748
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5007
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:00 +02:00
Aaron Durbin 5cc3b401d8 baytrail: remove verbosity in iosf
The iosf access functions already use some common code,
however there is a duplication for setting up the proper
control register for port and opcode. Introduce macros
to remove this verbosity.

BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted. Suspend and wake.

Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179747
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5006
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:30:53 +02:00
Aaron Durbin d86f0b743f reg_script: add reg_script_run_on_dev()
The reg_script library has proven to be useful. It's
also shown that many scripts operate on devices. However,
certain code paths run the same script on multiple,
but different, devices. In order to make that easier
introduce reg_script_run_on_dev() which takes a device
as a parameter. That way, chained reg_scripts are not
scrictly needed to run the same script on multiple devices.

BUG=None
BRANCH=None
TEST=Built.

Change-Id: I273499af4d303ebd7dc19e9b635ca23cf9bb2225
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179540
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5005
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:30:43 +02:00
Duncan Laurie 430bf0d8a9 baytrail: Add support for LPSS and SCC devices in ACPI mode
This adds the option to put LPSS and SCC devices into ACPI mode
by saving their BAR0 and BAR1 base addresses in a new device
NVS structure that is placed at offset 0x1000 within the global
NVS table.

The Chrome NVS strcture is padded out to 0xf00 bytes so there
is a clean offset to work with as it will need to be used by
depthcharge to know what addresses devices live at.

A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and
the EMMC 4.5 IRQ is changed to 44.

New ACPI code is provided to instantiate the LPSS and SCC devices
with the magic HID values from Intel so the kernel drivers can
locate and use them.

The default is still for devices to be in PCI mode so this does
not have any real effect without it being enabled in the mainboard
devicetree.

Note: this needs the updated IASL compiler which is in the CQ now
because it uses the FixedDMA() ACPI operator.

BUG=chrome-os-partner:23505,chrome-os-partner:24380
CQ-DEPEND=CL:179459,CL:179364
BRANCH=none
TEST=manual tests on rambi device:

1) build and boot with devices still in PCI mode and ensure that
nothing is changed

2) enable lpss_acpi_mode and see I2C devices detected by the kernel
in ACPI mode.  Note that by itself this breaks trackpad probing so
that will need to be implemented before it is enabled.

3) enable scc_acpi_mode and see EMMC and SDCard devices detected by
the kernel in ACPI mode.  Note that this breaks depthcharge use of
the EMMC because it is not longer discoverable as a PCI device.

Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179481
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5004
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:30:36 +02:00
Martin Roth 2dd3f877cc cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.

These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda

Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:36:12 +02:00
Martin Roth a6427161c2 Intel FSP: add a shared set of functions for the FSP
- Move the non chipset-specific fsp pieces out of the chipset into a
shared area.  This is used by northbridge / southbrige / SOC code.  It
pulls in pieces from Kconfig, Makefile and FSP specific code.
- Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP"

Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5635
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:35:56 +02:00
Edward O'Callaghan f18abab200 superio/serverengines/pilot: Avoid .c includes
Following the same reasoning as commit
d3043313a9 superio/fintek/f81865f: Avoid
.c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09 08:26:14 +02:00
Kyösti Mälkki 618de689c3 Squelch some warnings from Kconfig
Overriding global config entries in mainboard directory Kconfig
files often raise unnecessary warnings. Squelch some of those.

Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5699
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09 08:24:40 +02:00
Duncan Laurie 4acd3c05d6 rambi: Enable DPTF
This enables the DPTF framework, but it doesn't do much
without some sort of kernel+user components to drive it.

BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF

Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5003
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09 05:43:01 +02:00
Duncan Laurie ad8d913f42 baytrail: Basic DPTF framework
This is not complete yet but it compiles and doesn't cause
any issues by itself.  It is tied into the EC pretty closely
so that is part of the same commit.

Once we have more of the EC support done it will need some
more work to make use of those new interfaces properly.

BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF

Change-Id: I4b27e38baae18627a275488d77944208950b98bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179459
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5002
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09 05:42:52 +02:00
Duncan Laurie 4cc4b04d8a rambi: Set panel power timings
These are the values that are seen with VBIOS and
may need tweaked for derivative panels.

BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up

Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5001
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:42:47 +02:00
Duncan Laurie b40e444aee baytrail: Enable panel and set timings
These need to be set before the kernel will work without
running the VBIOS option rom.

Also necessary is setting the PP_CONTROL register with
the EDP_FORCE_VDD bit.

BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up

Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5000
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:42:40 +02:00
Aaron Durbin 7b35706cf3 rambi: change SD card pulls to 20K
Now that the SD card controller is limited to the SD card
2.0 spec it's possible to use 20K pulls for the pads.

BUG=chrome-os-partner:24423
BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without
     any errors.

Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179423
Reviewed-on: http://review.coreboot.org/4999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:42:33 +02:00
Aaron Durbin 40b7455f93 rambi: limit SD card controller to 2.0 spec
The rambi board can only meet the SD card 2.0 specification.
Therefore, the controller capabilities need to be overridden
to match.

BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows
     high speed as maximum timing as well as 3.3V signal voltage.

Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179415
Reviewed-on: http://review.coreboot.org/4998
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09 05:41:59 +02:00
Aaron Durbin 8b120a87c3 baytrail: allow SD card controller capabilities overrides
The SD card controller can have the capabilities it supports
to be overridden. Add two optional fields to the chip structure
to allow the mainboard to override the SD card controller
capabilities.

BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. Noted capabilities override console output.

Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4997
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:41:48 +02:00
Aaron Durbin 16cc9c9599 baytrail: fix nvs offsets
The VDAT data was off by 2 bytes when reading it from the
kernel. The reason is that the header did not line up
correctly with actual ACPI code.

BUG=chrome-os-partner:24440
BRANCH=None
TEST=crossystem devsw_cur now returns either 0 or 1 depending
     on state.

Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a
Signed-off-by: Aaron durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179372
Reviewed-on: http://review.coreboot.org/4996
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:41:40 +02:00
Aaron Durbin 7538937d6e rambi: export SPI write-protect GPIO correctly
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).

BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
     chromeos_acpi directory.

Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
Reviewed-on: http://review.coreboot.org/4995
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:41:29 +02:00
Aaron Durbin f4fe3c303c baytrail: lpe audio device needs memory for its firmware
The LPE audio device needs 1MiB of memory for its firmware.
It also has a requirement that the memory needs to be on a
512MiB boundary. Just take 1MiB @ 512MiB for the LPE device.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and analyzed console logs for resources. Also interrogated
     registres within the kernel.

Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b
Reviewed-on: https://chromium-review.googlesource.com/179192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4994
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:41:20 +02:00
Kyösti Mälkki 5c4b8483d2 ChromeOS boards: Always build code for bootmode straps
Leave it under BOOTMODE_STRAPS to control whether these have
any functional meaning on the build.

Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 16:26:58 +02:00
Kyösti Mälkki ab7280970a ChromeOS boards: Fix includes
Change-Id: Ib8448f3d36a23538cd9fea897f09da3ec4ad007a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 16:25:57 +02:00
Kyösti Mälkki 1645589ce7 Declare get_write_protect_state() without ChromeOS
Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:30 +02:00
Kyösti Mälkki e3ddee0437 Rename from save_chromeos_gpios() to init_bootmode_straps()
This feature is no longer specific to ChromeOS builds.

Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:16 +02:00
Kyösti Mälkki ff402e3aeb ChromeOS boards: Use explicit include of chromeos.c
Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:05 +02:00
Edward O'Callaghan 63f28c00aa superio/fintek/f71869ad: Make hwm devicetree configurable
Provision the configuration of the Fintek F71869AD Hardware Monitor's
configuration by way of devicetree.cb. Make use of this in the
jetway/nf81-t56n-lf board to properly control fan's.

Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5580
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08 12:10:55 +02:00
Edward O'Callaghan dd2e8c35fb superio/fintek/f71869ad: Configure multi-func reg in devicetree
Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.

Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.

Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5576
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 12:10:37 +02:00
Edward O'Callaghan 708be1a453 mainboard/jetway/nf81-t56n-lf: Improve diags in romstage
romstage reports a completely unintelligible printf of "error level:",
fix this and document meaning of the return values in source.

Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5465
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 12:10:29 +02:00
Shawn Nematbakhsh 9928197c26 rambi: Make ec_in_rw a legacy GPIO
ec_in_rw needs to be read by depthcharge, which only supports legacy
GPIOs.

BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge
detects the proper ec_in_ro state.
BRANCH=None

Change-Id: I25802b445c795eb85580c22d880efee8eeb21318
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4993
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-05-08 07:07:28 +02:00
Shawn Nematbakhsh 27351b93c0 baytrail: gpio: Make GPIO inputs MMIO by default
The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the
default input GPIO type MMIO.

BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat
/sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic
jack status.
BRANCH=None

Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179169
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4992
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:07:17 +02:00
Shawn Nematbakhsh 70cc9084a5 rambi: Change eMMC pin PUs to 2K
Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up
on certain boards.

BUG=chrome-os-partner:24353
TEST=Manual. Burn FW on board that previously failed to boot eMMC,
verify chromeos can now install + boot from eMMC.
BRANCH=none

Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4991
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:07:07 +02:00
Aaron Durbin fad3703ce8 rambi: configure SD card signals
Rambi 1.5 boards use the native SD card controller on baytrail.
Therefore, enable those signals. The CLK, D*, and CMD pins use
2K pulls as these were shown to not exhibit any errors when
doing reads or writes to a DDR50 sd card.

Note that if a servo is connected on needs to enable the
sd_vref_sel rail to pp1800 as this causes issues with card
detect if it is not set to pp1800.

BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Tested sd card read and write works in kernel.
     Also noted that write protect detection works as well.

Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178961
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4990
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:06:59 +02:00
Aaron Durbin 4334c87634 baytrail: enable lpe resources assigned to device
The enable_resources callback was accidentally populated
with NULL. Make that callback be the generic
pci_dev_enable_resources.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted.

Change-Id: I670b51bd9aff6764e9b549287a737b662572cdc7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178960
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4989
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:06:48 +02:00
Duncan Laurie b50566ef63 baytrail: Fix _CRS to build with new IASL
The new IASL is complaining about the PCI memory region not
having consistent base/end/length values because they are
placeholder that are fixed up in the method before returning.

Put in some more valid placeholder values to make it happy.

BUG=chromium:311294
BRANCH=none
TEST=build and boot with IASL 20130117 on rambi

Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4988
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:06:07 +02:00
Aaron Durbin ac9a905cf1 rambi: configure the LPE audio codec clock
Rambi has the LPE audio codec connected to PMC_PLT_CLK[0].
Configure it for 25MHz.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Noted message in console output.

Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178781
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4987
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08 07:06:00 +02:00
Aaron Durbin 8cbf47f12c baytrail: add lpe codec clock configuration
Add device tree option to determine if the LPE
audio codec has a platform clock signal connected
to it from the SoC. If a frequency is selected the
platform clock number is used to enable the
clock.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted rambi with 25MHz option. Probed pin
     to audio codec. Noted 25MHz clock.

Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178780
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4986
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:05:50 +02:00
Duncan Laurie bb0d1ea247 baytrail: Add ACPI code to describe GPIO controller
There are 3 banks of GPIOs that need to be described
with specific _UID and memory/interrupt values.

BUG=chrome-os-partner:24314
BRANCH=none
TEST=build and boot on rambi, check for probed driver:

gpiochip_find_base: found new base at 154
gpiochip_add: registered GPIOs 154 to 255 on device: INT33FC:00
gpiochip_find_base: found new base at 126
gpiochip_add: registered GPIOs 126 to 153 on device: INT33FC:01
gpiochip_find_base: found new base at 82
gpiochip_add: registered GPIOs 82 to 125 on device: INT33FC:02

  fed0c000-fed0cfff : INT33FC:00
    fed0c000-fed0cfff : INT33FC:00
  fed0d000-fed0dfff : INT33FC:01
    fed0d000-fed0dfff : INT33FC:01
  fed0e000-fed0efff : INT33FC:02
    fed0e000-fed0efff : INT33FC:02

Change-Id: I9619e2af4e1ccdf3d7b2e4ae280aadf22e278aeb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178601
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4985
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:05:42 +02:00
Duncan Laurie 22f1dcdfc4 baytrail: Update to microcode 31E and fix C-state table
With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.

BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now

Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4984
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:05:29 +02:00
Patrick Georgi 5b33dc1ec9 baytrail: minor style
use IS_ENABLED() over #if brackets

Change-Id: I101f99971c0f7b5311ef19cc9832713ab0696935
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5692
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-07 22:08:35 +02:00
Patrick Georgi 802a8ece3f rambi: Remove outdated comment
Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5691
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-07 22:08:19 +02:00
Aaron Durbin 100b14d12b rambi: handle single channel configs
Some 1.5 boards have a single channel ram configuration.
Accomodate such configs.

BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built and booted ChromeOS.

Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178340
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: http://review.coreboot.org/4983
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:08:04 +02:00
Shawn Nematbakhsh 13d9341660 baytrail: romstage: Add config option to enable RMT
Add config option to enable RMT in the MRC.

BUG=chrome-os-partner:21807
TEST=Manual. Build w/ "USE=rmt", verify RMT print seen on FW console.
Build w/o USE flag, verify no RMT print.
BRANCH=None.
CQ-DEPEND=CL:*148655

Change-Id: Ibd3da87317a3359e797d9b43bc437e7227a85048
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4982
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:07:03 +02:00
Aaron Durbin ae31f7dcc4 baytrail: pcie: Root port initialization
Add PCIe driver to initialize root ports.

BUG=chrome-os-partner:24111
TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to
detect networks.
BRANCH=None.

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>

Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12
Reviewed-on: https://chromium-review.googlesource.com/177652
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4981
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:54 +02:00
Shawn Nematbakhsh 5f5cd72a55 baytrail: gpio: Fix NCORE gpio-to-pad LUT
NCORE pad addresses were wildly wrong due to documentation bugs.

BUG=chrome-os-partner:24179
TEST=Manual on Rambi. Verify display isn't always on. Verify brightness
control now works in Chrome OS.
BRANCH=None.

Change-Id: I464436a58baa4957329c11231c5a866dafd97ce8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177597
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4980
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:45 +02:00
Aaron Durbin 21565cac1b rambi: use SERIRQ pad as keyboard irq in gpio mode
The level shifting between 3.3V and 1.8V for the SERIRQ
signal is not working. Instead use the SERIRQ pad as
a gpio which is used as a direct IRQ signal for the
keyboard interupt.

BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi. Keyboard works with associated EC change.
CQ-DEPEND=CL:177189

Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177223
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4979
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:34 +02:00
Aaron Durbin baa1e38217 rambi: make ramids non-legacy gpio inputs
The romstage code for rambi uses the mmio way of reading
inputs. However, this is a problem is the GPIOs are set up
as legacy mode. Subsequent warm resets mean the ram_id is
read incorrectly. Ensure the ram_id is read consistently
by keeping the GPIOs for ram_id in mmio mode.

BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted. And rebooted. Now seeing consistent ram_id
     values on warm resets.

Change-Id: Ieff98c000be80998854f325754f1e819975d2be5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177230
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:10 +02:00
Aaron Durbin 6f9947a3ec baytrail: enable caching and prefetching in spi controller
The default mode of the SPI controller has prefetching disabled.
That obviously has a performance impact. Enable both caching
and prefetching to make booting faster. This has a significant
impact on streaming data out of SPI.

BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted rambi. Payload loading step went from ~285ms
     to ~54ms.

Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177220
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:03 +02:00
Aaron Durbin bd4ea8cd4d baytrail: fix direct irq pad configuration
When a pad is configured for direct IRQ it needs to be in
non-legacy. Additionally, the signal is passed directly to
the APIC by setting the LEVEL and TPE bits in the pad config
register. The APIC can then be configured for level, edge,
and rising/falling.

BUG=chrome-os-partner:24037
BUG=chrome-os-partner:22863
BRANCH=None
TEST=Built and booted with this config. Trackpad is firing interrupts
     more than it should, but it appears to be a trackpad firmware
     and/or configuration issue.

Change-Id: I00042b2ddba67d6bf23f0e7468d0719196e6f865
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176793
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4975
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:05:55 +02:00
Aaron Durbin ebf7ec5dab baytrail: ensure init_chromeos() is called in romstage
The TPM needs to have the TPM_Startup command sent to it
on all boot paths. The call init_chromeos() in romstage_common()
fulfills this requirement.

BUG=chrome-os-partner:24057
BRANCH=None
TEST=Built and booted. Was able to suspend to ram multiple times
     in a row.

Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176803
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-07 22:05:48 +02:00
Aaron Durbin ee3ec728d8 rambi: distribute IRQs away from PIRQA on pci devices
Some of the drivers in the kernel were not so happy about
having shared IRQs. Also, sharing IRQs means more code
needs to be run in interrupt context to determine if the IRQ
was meant for a particular device. Fix this.

No more 'mmc1: got irq while runtime suspended' messages.

BUG=chrome-os-partner:24056
BRANCH=None
TEST=Built and booted. Looked at /proc/interrupts and noted no
     more sharing between pci devices.

Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176792
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4973
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:05:40 +02:00
Edward O'Callaghan bf9f243857 superio/common/conf_mode: Provide another common pnp entry/exit
ITE Super I/O's make use of this method to enter and exit in and out of
their PNP configuration. Provide functions for use in ram stage
component.

Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5666
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-07 21:36:48 +02:00
Aaron Durbin 99d8818af3 baytrail: don't allow PCIE wake ups
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.

BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
     cause wakeups.

Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4972
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:58 +02:00
Shawn Nematbakhsh 281abfb2db baytrail: gpio: Make pad input/output state mutually exclusive
Previously pads were being configured as both input and output
simultaneously due to the config bits being active low. Create new
defines that only enable either input or output, and use them in our
GPIO configs.

BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Verify system boots and peripherals still
function.
BRANCH=None.

Change-Id: If386682a3d810864b7b9f5d2aecdb2e6cfceea86
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4971
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:49 +02:00
Aaron Durbin afaaa3a618 rambi: fixup settings so trackpad can be found in kernel
The kernel chromeos_laptop driver nomenclature expects the
board name to not be in all caps. Fix this as well as the i2c
address for the trackpad.

BUG=chrome-os-partner:24307
BRANCH=None
TEST=Built and booted. trackpad device is found. IRQs still not
     working yet.

Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176680
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4970
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:19 +02:00
Aaron Durbin dc866cff31 baytrail: first pass at lpss device initialization
This commit does the common parts for all LPSS devices
that are enabled: enable snoop in IOSF and enable power
management. Additionally, the i2c devices are taken out of
reset.

BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted with modified kernel-next. I2C bus devices
     show up and I see 0x10 on one of the buses.

Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176424
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4969
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:10 +02:00
Aaron Durbin 64b902b57a reg_script: add iosf lpss port access
Add the LPSS IOSF port access to reg_script. This is
going to be used by baytrail.

BUG=chrome-os-partner:23790
BRANCH=None
TEST=Buit.

Change-Id: I0367acdb584f2de0bb871b136042b57fe6b7ec90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176423
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4968
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:01 +02:00
Aaron Durbin 1592169495 baytrail: initialize eMMC device
The eMMC device is initialized as version 4.5 with HS200 speeds.

BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted rambi to login screen off of eMMC device.

Change-Id: I686c6136005fcb2587b939ddea293f4398df9868
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176536
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4967
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:04:32 +02:00
Aaron Durbin c626b74c1d baytrail: initialize common SSC functionality
The SSC (storage control cluster) houses the SD, SDIO, and eMMC
interfaces. The scc cofniguration function, baytrail_init_scc(),
is ran in the pre device stage to initialize the SCC. The eMMC
is expected to be configured for version 4.5.

BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted with some other eMMC changes into login screen off
     of eMMC device.

Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176535
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4966
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:04:23 +02:00
Aaron Durbin e8f97d4f55 reg_script: add iosf paths for score, ccu, and ssc
Handle SCORE, CCU, and SSC IOSF accesses.

BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built.

Change-Id: I6e678eb79bd1451f156bdd14cf46d3378dc527c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176534
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4965
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:04:09 +02:00
Aaron Durbin d7f0f3de10 baytrail: add score and ssc iosf access functions
The SCORE allows controlling the pad configuration while
the SSC handles the configuration for the storage control
cluster.

BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built.

Change-Id: Ifd9f67a4e88d5bb99faec6ceeb3e263001a87c41
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176533
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:04:03 +02:00
Shawn Nematbakhsh 9547f8d799 rambi: Add DIRQs for trackpad and touchscreen
Also add the relevant info about these pins to the ASL tables + add
SMBIOS type 41 data for these parts.

BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.

Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8
Reviewed-on: https://chromium-review.googlesource.com/176299
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:03:54 +02:00
Furquan Shaikh 99ac98f7e1 Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.

These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.

In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.

Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.

We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.

Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-06 20:23:31 +02:00
Shawn Nematbakhsh fb494d68ff baytrail: gpio: Add support for direct / dedicated IRQs
Add support for DirectIRQ / dedicated IRQs. This consists of up to 16
IRQs for both SCORE and SSUS banks.

BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.

Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c
Reviewed-on: https://chromium-review.googlesource.com/176165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4962
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:40:04 +02:00
Aaron Durbin 7e9634ffc0 rambi: disable HDA device
For some reason HDA can now be disabled. It's unclear what changes
in the baytrail code allowed this to happen, sadly.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Noted hda is not in lspci.

Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176394
Reviewed-on: http://review.coreboot.org/4961
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:55 +02:00
Aaron Durbin 59cd6216dd rambi: enable SCI and SMI gpios
Rambi has 3 pins that need to be configured for SCI and SMI:

1. GPIO_CORE[0] - runtime SCI pin
2. GPIO_SUS[7] - SMI for firmware lid events
3. GPIO_SUS[0] - wake pin for S3 wakes from EC.

Configure these pins now that the rest of the infrastructure
is in place. The one thing that is yet to work is runtime SCI
for lid events once booted.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=built and booted. lid close at rec screen works. And wake
     from S3 with a keyboard press works.

Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176393
Reviewed-on: http://review.coreboot.org/4960
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:49 +02:00
Aaron Durbin 3fbf671194 rambi: mainboard EC - SCI and SMI fixes
As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
     'lidclose' on EC console while at recovery screen. Machine properly
     shutdown.

Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
Reviewed-on: http://review.coreboot.org/4959
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:38 +02:00
Aaron Durbin 9f83e873f4 baytrail: add GPIO SMI support
GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI
regier. No bits in the SMI_STS register are set. Therefore, the
ALT_GPIO_SMI register needs to be read and cleared on every SMI.
Additionally, the mainboard_gpi_smi() handler needs to be called as
well on every SMI because of this property.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted to recovery screen. Typed 'lidclose' on EC
     console. SMI occurred which caused the board to be shutdown.

Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4958
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:29 +02:00
Aaron Durbin 59a4cd5578 baytrail: add support for routing gpio pins to smi/sci
In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.

The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
     and toggling PCH_WAKE_L on the EC console.

Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4957
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:22 +02:00
Aaron Durbin 997d25219b baytrail: fix fadt structure for gpe0 block
The gpe0 block's size was being misreported. Correct
the gpe0 size and use make the FADT fields be more
robust instead instead of hand calculating fields that
are the based on the same size.

This change correctly enables GPE events in the kernel.
Confirmed this by using iotools read the gpe_cnt register.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Confirmed EC's GPE event is enabled (but
     still not working).

Change-Id: I415710f7fec2e95cecee3bf679ee673dacc27480
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176271
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4956
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:16 +02:00
Duncan Laurie ea7d4e0901 baytrail: Add microcode/punit release 31a
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi

Change-Id: I89c25142245cd268f755210784fd9d0c60dc5661
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176305
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4955
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:10 +02:00
Duncan Laurie 8923be58b8 baytrail: Add ACPI CPU entries
- C-state table based on static config
MWAIT values are from ref code for non-S0ix config
C6 substate 8 is ignored by the kernel as it violates the CPUID
but it is left in as the other substate may not work.
- P-state table generated with proper ratio and VID values
relies on having the package power msr set to magic value
as the power-on default is wrong
- T-state table uses static table

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175742
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4954
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:04 +02:00
Duncan Laurie 6aa9f1f0eb baytrail: Add BCLK and IACORE to pattrs
The bus clock speed is needed when building ACPI P-state tables
so extract that function and have the value be saved in pattrs.

The various IACORE values are also needed, but rather than have
the ACPI code to the bit manipulation have the pattrs store an
array of the possible values for it to use directly.

BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi

Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:38:58 +02:00
Duncan Laurie 05a3393a2c baytrail: Enable Turbo/Burst and set some magic MSRs
As far as I can tell turbo enabling behaves like
it did on haswell so use the standard code.

There are also some magic values to set in some magic
MSRs related to turbo and package power so they report
correctly.

The L2 cache shrink is enabled and a threshold is set
that makes both dual and quad core happy.

C1E is disabled to match the reference code.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4952
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:20:07 +02:00
Duncan Laurie fd461e396b regscript: Add support for MSR type
This required changing value/mask types to uint64_t.

Another option would be to use id field to select low or high
32 bits of the MSR and set them independently.

BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi

Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176304
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4951
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:19:57 +02:00
Aaron Durbin 9e68fe68ff rambi: include the EC devices normally on superio
The superio.asl file allows for the mainboard to hang
devices off of the LPC bus in ACPI. Include the keyboard
controller, EC memory map, and host interface's resources.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted resource reservations in dmesg.

Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176134
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4950
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:19:19 +02:00
Aaron Durbin ab7ed054be baytrail: include mainboard's superio.asl
The mainboard needs an opportunity to hang devices off of
the LPC device. Therefore, provide this opportunity for the
mainboard.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Buit and booted with keyboard. Keys work.

Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176133
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4949
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:19:08 +02:00
Aaron Durbin 84da959c69 rambi: update EC support
Fix the SMI and SCI gpios for Rambi. Also, add in the
EC callbacks for the SMI handler. Note that the handler
for GPI SMIs has not been tested yet as baytrail chipset
code  doesn't yet support setting up those configurations
yet.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts
     for the EC's SCI GPI. Also was able to see Chrome EC messages
     with CONFIG_DEBUG_SMI and powering down at the dev screen.

Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4948
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:18:54 +02:00
Aaron Durbin fa91e02a15 baytrail: add more irq defintions
The IRQs used for devices that are in acpi mode are added as well
as the IRQ defitions for the dedicated GPIO IRQ routing.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built.

Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176120
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:18:38 +02:00
Aaron Durbin 1af366322e baytrail: configure acpi SCI irq
Baytrail has a configurable SCI irq. Add support for
properly configuring SCI irq. Note that it is currently
fixed to IRQ9, but the code supports setting it to the
other supported values. The current mainboards using
baytrail defer the madt IRQ override information to the
chipset.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted 'SCI is IRQ9' message.

Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176075
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4946
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:40 +02:00
Aaron Durbin 952d85e5f2 rambi: mirror bayleybay's eMMC gpio setup
These changes to the eMMC pads allows the kernel to see the
eMMC device. One is able to install onto the eMMC device, and
the kernel is loaded and booted from eMMC device. Note, that
it may not fully boot because of other issues such as
not-completely working ACPI support.

BUG=chrome-os-partner:22580
BRANCH=None
TEST=booted off of usb drive. can see eMMC device.

Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4945
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:27 +02:00
Duncan Laurie 8de0ca435e rambi: Fix eDP panel functionality
For some mysterious reason GPIO_S0_NC22 is making the eDP panel
go entirely white when it is configured with internal pullup.
Since these (supposedly XDP related) pins are unknown functionality
lets set them to GPIO_DEFAULT instead of GPIO_NC.

Additionally the VBIOS is being changed to issue int15 callback
to determine the boot graphics device.  If we list both LFP and EFP
then the dev/rec screens will show on the panel when HDMI is not
attached and otherwise will display on HDMI.

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi, see firmware/kernel screens on the panel
when HDMI is not attached, and firmware screens on the panel and
kernel screens on both when HDMI is attached.

Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175952
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4944
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:17 +02:00
Aaron Durbin 6e3289372c baytrail: add support for S3 resume
Previously the only path through memory init and coreboot was
hardcoding S5. Therefore all S3 paths would not be taken. Allow
for S3 resume to work by enabling the proper control paths in
romstage.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=While in kernel 'echo mem > /sys/power/state'. Board went
     into S3. Power button press resumed back into kernel.

Change-Id: I3cbae73223f0d71c74eb3d6b7c25d1b32318ab3e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175940
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4943
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:05 +02:00
Trevor Mosey 2237324e77 lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
linux/drivers/platform/x86/thinkpad_acpi.c looks for an EC
version string before loading, this code copies the vendor BIOS by
exposing this string. This was originally part of x60's mainboard.c 

Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845
Signed-off-by: Trevor Mosey <uberushaximus@gmail.com>
Reviewed-on: http://review.coreboot.org/5638
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 14:17:44 +02:00
Paul Menzel 69634c316e northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in comment
Change-Id: I0daf5d1d446de1f09b695f177b0491301613e278
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5667
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 13:55:39 +02:00
Aaron Durbin 303525b446 baytrail: fix up FADT
The FADT for baytrail had incorrect offsets leading to
the kernel spewing a huge mess of ACPI errors. Fix these offsets
to be initialized in the chipset code.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted into kernel on rambi. Login screen comes up.

Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175663
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4941
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 23:38:56 +02:00
Aaron Durbin 3bde3d74c5 baytrail: interrupt routing support
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.

There are still a lot of ACPI errors in the kernel with this
change, though.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 23:38:38 +02:00
Aaron Durbin 014baea1ce haswell: move to mp_init library
The mp_init library was based off of haswell code, but baytrail
was the first chipset to take advantage of it. Move haswell over
to using it so that the code duplication can be removed.

Change-Id: Id6e9464df028aa6ec138051f925817c85b4c13e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5413
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-05-05 23:38:22 +02:00
Paul Menzel 60ec2ff2f0 lib/hexdump: Use `size_t` for length parameter of `hexdump32()`
In the signature of the function `hexdump32()` it does not make sense to
represent a length, assumed to be positive, as a signed integer.
With this change, it is no longer necessary to cast a pointer to
unsigned long when passing it to `hexdump32()`.

The same change for the function `hexdump()` was done in commit
3dd0e72d [1].

	lib/hexdump: Take const void * and size_t as arguments

[1] http://review.coreboot.org/4575

Change-Id: Id97f5daff95f94e862ee8b5be896a6629b125a13
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5646
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:59:05 +02:00
Paul Menzel f0a59914d8 lib/hexdump.c: Indent with tabs instead of spaces and remove empty lines
The coding style requires to use tabs for indentation and not spaces.
Use GNU indent 2.2.11 with the switch `-linux` to indent the file,
which also removes the empty lines at the end of the file.

Change-Id: I874f178e50d7558d3299026aec2771ad45f88d8e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4576
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:58:57 +02:00
Kyösti Mälkki 08df7326e6 AGESA: Fix BiosCallouts table formatting
Already done for fam15tn and fam16kb.

Change-Id: I3da36bfe6fd1805867eee5aa1f017c4fda084349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5660
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:57 +02:00
Kyösti Mälkki 088fd67a38 AGESA: Implement EmptyHeap()
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear
the fields individually.

Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5659
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:50 +02:00
Kyösti Mälkki 8ef30253e3 AGESA fam14: Use common callouts
Backported from fam15tn and fam16kb.

This also implements GetHeapBase() to satisfy some requirements
of HAVE_ACPI_RESUME for the following boards:
  amd/inagua
  amd/south_station
  amd/union_station
  asrock/e350m1

Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5658
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:45 +02:00
Kyösti Mälkki 5601922130 AGESA fam14: Add fam14_callouts header
Backported from fam15tn and fam16kb.

Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5657
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:35 +02:00
Kyösti Mälkki 6711dce552 jetway/nf81-t56n-lf: Revert change on function prototypes
These function prototypes to remain identical across all
AGESA families.

Change-Id: If2a0a08fa7122e6becded37d032d3c40bde2d149
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5656
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:48 +02:00
Kyösti Mälkki f15e53a730 AGESA fam15: Add GetHeapBase()
While fam15 boards do not select HAVE_ACPI_RESUME, backport this
from fam14.

Implementation of this function is common across different families.

Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5655
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:43 +02:00
Kyösti Mälkki 4f998a07b5 AGESA fam12: Add GetHeapBase()
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this
from fam14.

Implementation of this function is common across different families.

Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5654
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:38 +02:00
Kyösti Mälkki e3aef13933 AGESA fam15tn: Use common GetHeapBase()
Implementation of this function is common for all boards in family,
and also across different families.

Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:33 +02:00
Kyösti Mälkki 5caa9d9d81 AGESA fam16kb: Use common GetHeapBase()
Implementation of this function is common for all boards in family,
and also across different families.

Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:26 +02:00
Kyösti Mälkki 575cf9df66 AGESA fam15: Use common callouts
Backport from fam15tn and fam16kb.

Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:19 +02:00
Kyösti Mälkki 05531a5f44 AGESA fam15: Add fam15_callouts header
Backported from fam15tn and fam16kb.

Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5650
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:10 +02:00
Kyösti Mälkki 5c96525b6a AGESA fam12: Move dimmSpd
Implemented under northbridge/ on other families.

Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:05 +02:00
Kyösti Mälkki 328ce9a8b4 AGESA fam12: Add fam12_callouts
Although amd/torpedo is only fam12 board at the moment,
backported this from fam15tn and fam16kb.

Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5648
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:51:44 +02:00
Edward O'Callaghan 028dc1e151 AMD F14h boards: Sanitise headers in agesawrapper.c
Change-Id: Ic9c5e8abb3da020a642635ee74c9242091923619
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5628
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05 08:51:39 +02:00
Edward O'Callaghan 8864e1c149 AMD F14h boards: Use std memset/memcpy func over AGESA
In amd/{persimmon,inagua} and derived boards avoid using AGESA
reimplementation of memcpy as following the reasoning in:
e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA

Change-Id: I943b46103c3bf1c5fd88b25e9f9595b9adfcafeb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5625
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05 08:51:34 +02:00
Trevor Mosey 8e5435a74b lenovo/t60: Move mainboard_enable() code into a mainboard_init()
mainboard_enable() is now modelled after google/parrot where the
enable function only sets dev->ops->init for the root device to
point to a mainboard_init() function, which in turn is called in a
later pass over the device tree to do the actual initialization.

Change-Id: I89a5192bd45ca8321b2b1ac49b073122e0f6ee2b
Signed-off-by: Trevor Mosey <uberushaximus@gmail.com>
Reviewed-on: http://review.coreboot.org/5637
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:46:16 +02:00
Kyösti Mälkki ae16d3dfbd AMD: Drop redundant test for CONFIG_RAMTOP
Same test is already done in x86/mtrr.h.

Change-Id: Ib0785d047567374294b9ee7afc4f4244f9ced926
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5620
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03 09:51:21 +02:00
Patrick Georgi f771e569d7 Drop useless mainboard-romstage defines
Some src/mainboard/*/*/romstage.c files use defines which later
modify the behaviour of included .c files.
Since it's a pain to work out what is affected by these, drop
values that are only defined in the board but never used, or
defined to identical values as in spd.h (and use that one instead).

Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5639
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 09:44:34 +02:00
Furquan Shaikh 88ca81a6d4 Move redundant Makefile rules from arch to top level.
Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others
from arch level Makefile.inc to top level Makefile.inc.
Also, organize Makefile.inc at arch level into per-stage rules and variables.

Change-Id: I7dc5b2d31c959b55bb92d9c7811427c4dada1db5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5571
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 00:26:40 +02:00
Furquan Shaikh fd33781fbf Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.

Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 00:25:20 +02:00
Paul Menzel 2d9725e763 drivers/pc80/Kconfig: Do not init PS/2 keyboard if GRUB 2 is chosen as payload
If the user selects GRUB 2 as the payload in Kconfig, coreboot does
not need to initialize the PS/2 keyboard as GRUB 2 is going to do it.

Change-Id: Ia5d902e7c0fa34eaff26a31507751815bf2d2581
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 15:05:07 +02:00
Paul Menzel 4fdc680efc drivers/pc80/Kconfig: Do not init PS/2 keyboard if SeaBIOS is chosen as payload
As the Kconfig description of `DRIVERS_PS2_KEYBOARD` says, SeaBIOS is
able to initialize the PS/2 keyboard itself, so it is not necessary to
let coreboot do it.

SeaBIOS is also able to do it faster as discussed in a thread on the
coreboot mailing list from October 2010 [1]. In that thread it was
also proposed to not let coreboot initialize the PS/2 coreboot when
SeaBIOS is used as a payload.

[1] http://www.coreboot.org/pipermail/coreboot/2010-October/thread.html#61310
    subject: [coreboot] coreboot+seabios timings

Change-Id: I1248cec3e2ca5b9311e46df8aabf67e14ffd4ea6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 15:04:58 +02:00
Paul Menzel 7ac7627546 drivers/pc80/Kconfig: Mention that GRUB 2 is able to init PS/2 keyboard
Change-Id: I0783ee123e0e1ecd5603bc6a40b53d3b0c23bf6d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 15:03:57 +02:00
Kyösti Mälkki e93776579d qemu-armv7: Kconfig cleanup
RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7.

Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5627
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:22:45 +02:00
Edward O'Callaghan b53b50b8c1 asrock/e350m1: Sanitize #includes
Following similar reasons as:
5ff4b08 jetway/nf81-t56n-lf: Sanitize #includes

Change-Id: Ie88b884bc2d4481bc2583d5be1f4d1376547f3c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5614
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2014-05-02 12:08:14 +02:00
Edward O'Callaghan dbadb0a827 jetway/nf81-t56n-lf: Set OEM to Jetway in DSDT and mptables
Jetway builds this hardware, so let us be sure to set the truth in the
DSDT Definition block and MPTables.

Change-Id: I2dfb89152aa3b895ec6975293c5a5998ab6b52bd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5630
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:07:26 +02:00
Edward O'Callaghan 0bb0affede arch/x86/boot: Indent mpspec.c and make a loop more legible
Fix some space->tab style and a for-for loop embedded to be more
understandable/readable.

Change-Id: I740c544e8c9330e6efbbd66a5c1e6a4a33d1a75e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5631
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:05:39 +02:00
Paul Menzel e72645a852 asrock/e350m1/devicetree.cb: Correctly indent device line
Fix up commit dfa8a32f [1].

	src/mainboard/asrock/e350m1: Properly indent devicetree.cb

[1] http://review.coreboot.org/5612

Change-Id: I59b3ec2f00d69951aa8a96c4a9c3de5b219acbfb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5619
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:04:36 +02:00
Edward O'Callaghan bbe3e44310 mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cb
Following the reasoning in,
dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb

Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5629
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:03:06 +02:00
Edward O'Callaghan f12a2473c0 superio/winbond/w83627thg: Remove w83627thg_enable_serial symbol
Remove model specific implementation, w83627thg_enable_serial, from
romstage component of sio support.

Change-Id: I8ef1de5ccccae5f4dba69dbdb939e7070d3cecfc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5604
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-02 09:44:58 +02:00
Edward O'Callaghan 0dd0669c59 mainboard/*: Use generic winbond romstage in place of w83627thg
Use the generic implementation of winbond in place of the model specific
w83627thg_enable_serial() as so that it maybe removed later.

Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5603
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-02 09:44:44 +02:00
Kyösti Mälkki 04f5c4eca7 Build without ChromeOS
Change-Id: I1da636573eed62ce693b984917084643787c094b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3978
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:40:39 +02:00
Kyösti Mälkki 6578475d93 ChromeOS: Use common fill_lb_gpio()
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:40:11 +02:00
Kyösti Mälkki 9ab1c106c3 device: Conditionally bypass oprom execution
Builds with CHROMEOS can bypass VGA oprom when boot is not in
developer or recovery modes. Have the same functionality available
without CHROMEOS but with BOOTMODE_STRAPS.

Change-Id: I97644364305dc05aad78a744599476ccc58db163
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5595
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01 15:39:52 +02:00
Kyösti Mälkki ab56b3b11c ChromeOS: Remove oprom_is_loaded
A global flag oprom_is_loaded was used to indicate to
U-boot that VGA option ROM was loaded and run, or that
native VGA init was completed on GMA device.

Implement this feature without dependency to CHROMEOS option
and replace use of global variable oprom_is_loaded with call
to gfx_get_init_done().

Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:26 +02:00
Kyösti Mälkki 926a8d1262 google/stout: Fix build without ChromeOS
Currently we have no developer or recovery mode switches when
building without ChromeOS.

Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:05 +02:00
Kyösti Mälkki 5687fc9d21 Declare recovery and developer modes outside ChromeOS
Move the implementation for recovery and developer modes from
vendorcode/google/chromes to lib/.

Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-01 15:38:41 +02:00
Kyösti Mälkki 580e5642a8 device: provide option to always load PCI option roms
Certain kernel drivers require the presence of option rom
contents because the board's static configuration information
is located within the blob. Therefore, allow a chipset/board to
instruct the pci device handling code to always load but not
necessarily run the option rom.

BUG=chrome-os-partner:25885
BRANCH=baytrail
TEST=Both enabling and not enabling this option shows expected behavior.

Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188720
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5594
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-05-01 15:38:11 +02:00
Kyösti Mälkki d540377390 console: Fix UART selection prompt
Without this change, removal of default UART_FOR_CONSOLE entries
under mainboard/ Kconfig will remove this option entirely from
created .config file.

Change-Id: I11422ddb8c51abca177f999936c995ae0c91c459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5626
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-04-30 23:47:28 +02:00
Duncan Laurie 93966e8592 baytrail: Add default _OSC method
This is needed to let the kernel know it can control everything
and not to disable features.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175629
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4939
Tested-by: build bot (Jenkins)
2014-04-30 23:12:03 +02:00
Duncan Laurie 053bd0753b baytrail: Add root bus resource regions
Populate the PCI mmio region from NVS TOLM variable.
Other regions are fixed.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175628
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4938
Tested-by: build bot (Jenkins)
2014-04-30 23:11:56 +02:00
Duncan Laurie 03ff2a242e baytrail: Add MCFG table to ACPI
This adds the PCI configuration region table to baytrail.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4937
Tested-by: build bot (Jenkins)
2014-04-30 23:11:46 +02:00
Duncan Laurie abab05cb3c baytrail: Clean up NVS region
There is a lot of NVS allocated to things that are not really
used.  Most of these are removed and some are moved around.
Thermals are expected to be handled with DPTF so I've removed
that bit of code but have not yet cleaned up the thermal zone.

I left in the SIO BARs since I think we will need those still
even though they may need work still.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4936
Tested-by: build bot (Jenkins)
2014-04-30 23:11:34 +02:00
Duncan Laurie 1f52f51f4e baytrail: Add function to read top of low memory
The top of low memory is also the start of the region where
PCIe resources are allocated.  This needs to be passed in
ACPI but is only readable from IOSF.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4935
Tested-by: build bot (Jenkins)
2014-04-30 23:11:21 +02:00
Duncan Laurie 7fbe20bd2c baytrail: Add reserved MMIO regions to ACPI
Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.

Add a region for the "abort page" documented in the EDS.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4934
Tested-by: build bot (Jenkins)
2014-04-30 23:11:11 +02:00
Duncan Laurie a90a59f5a3 baytrail: Fix XHCI problems and re-enable
- a few clock gating bits were set improperly and were preventing
the system from transitioning out of S0 state.
- the XHCC registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control.  This was causing memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver

Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4933
Tested-by: build bot (Jenkins)
2014-04-30 23:08:35 +02:00
Edward O'Callaghan 8199809079 mainboard/: Avoid including early_serial.c from w83627hf
Following the reasoning of:
dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c

Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5597
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30 19:06:47 +02:00
Kyösti Mälkki f385ba42e3 console: Move UART port defaults to mainboard
Correct selection of UART depends of board layout, not the CPU
internals, so default setting should originate from mainboard.

Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5618
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:43 +02:00
Kyösti Mälkki 48713a1bf7 console: Drop EARLY_CONSOLE option
We have means to easily disable a specific console in romstage if
necessary, so this global option makes little sense.

The option was initially introduced as a work-around for build issues
around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.

Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5607
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:20 +02:00
Kyösti Mälkki 28837c6b01 allwinner/a10: Hide SoC specific UART functions
If platform has a component coreboot has to communicate with using
one of the UARTs, that device would not be part of the SoC and
must not use functions specific to a10 UART.

Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5469
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:37 +02:00
Kyösti Mälkki 70342a7f51 uart: Support multiple ports
The port for console remains to be a compile time constant.
The Kconfig option is changed to select an UART port with index
to avoid putting map of UART base addresses in Kconfigs.

With this change it is possible to have other than debug console
on different UART port.

Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5342
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:05 +02:00
Paul Menzel 68eff4fb1c lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in comment
$ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g'

Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5325
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:23:52 +02:00
Edward O'Callaghan dfa8a32f1f src/mainboard/asrock/e350m1: Properly indent devicetree.cb
Trivial: clean up spaces to tabs to properly indent devicetree.cb

Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29 20:54:03 +02:00
Edward O'Callaghan 178a60b4b3 mainboard/kontron/986lcd-m: Remove a duplicate header
Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5602
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29 20:18:52 +02:00
Kyösti Mälkki bb6c2162d1 AGESA SPI: Fix Kconfig options
Option AMD_SB_SPI_LEN leaked to non-AMD configs.
Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME.

Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29 17:31:40 +02:00
Kyösti Mälkki 88e518f4bc SPI: Use common dependency in Kconfig
Change-Id: I11118a4fe1e05017349feae004f98a17bb02386b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-29 17:31:03 +02:00
Edward O'Callaghan 9e308b9955 superio/winbond/w83627ehg: Convert romstage to generic component
Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5589
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 20:14:58 +02:00
Edward O'Callaghan 959adc3fcf mainboard/tyan/s8226: Remove redundant sio header
Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 19:40:23 +02:00
Edward O'Callaghan ffe460d77a superio/winbond/w83627dhg: Convert romstage to generic component
Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 19:22:14 +02:00
Edward O'Callaghan dbbc136c83 mainboard/asrock/e350m1: Avoid including early_serial.c
Use generic winbond romstage serial init symbols instead of model
specific implementation. We do this on a case by case basis as some
boards are ROMCC and so need to #include .c files. This is a step to
migrate non-romcc boards to a more generic superio framework.

Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5591
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 18:59:39 +02:00
Edward O'Callaghan 5a032c628b superio/winbond/*: Provide common romstage component
Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I3e889c0305c012e7556a5dd348e7f1e1ba629a9d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5587
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 18:58:51 +02:00
Kyösti Mälkki 2458f42b27 AMD: Add common header file for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-28 18:36:35 +02:00
Edward O'Callaghan cf7b498908 superio/fintek/*: Factor out generic romstage component
The romstage of Fintek Super I/O's is identical, leading to replication
of essentially the same code prone to bitrot. Herein we consolidate the
early pre-ram UART initialisation code into fintek/common, rather we
leave the exceptions to be implemented under model/.

More precisely we provide a well documented version of early_serial.c
under fintek/common and select by way of Kconfig as a generic romstage
component to Super I/O support. We leave future Super I/O's the option
to implement `non-standard` initialisation code should such a (unlikely)
need araise. A primary advantage is that new support for romstage serial
is now trival to add. We also provide some Kconfig documentation while
here.

Change-Id: I3c62561558a62ece944a167ba302fb7076bba001
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5575
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 18:22:11 +02:00
Kyösti Mälkki 4566d2e7cd uart8250io: Fix build with DEBUG_SMI
Change-Id: I5110af348d22c0abc940f0922854fdd7e0c7e2e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-26 15:09:07 +02:00
Patrick Georgi f33782fb86 lippert/hurricane-lx: Kconfig cleanup
A Kconfig option defined instead of selected that really comes from
somewhere else.

Change-Id: I8730d12ed053520b794655e943c93583c441f3f1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5542
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 14:13:58 +02:00
Edward O'Callaghan 6d51f6b2e8 superio/fintek/*: Fix header style
Remove some redundant includes. Fix repetitiveness in include guards and
strip some misplaced tabs for whitespaces.

Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5572
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:48:36 +02:00
Furquan Shaikh 20f25dd5c8 Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:27:09 +02:00
Furquan Shaikh 817149643c Get rid of HAVE_INIT_TIMER config option
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use a stub for init_timer in
places where we do not have any init_timer defined. Thus, remove the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include a stub_timer if required.

Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 13:25:28 +02:00
Edward O'Callaghan ea2900bd6c superio/ite/it8673f: Remove poor implementation
Following the reasoning of:
HASH superio/ite/it8705f: Remove poor implementation

Change-Id: Ic0722116b84acf4f3c3ef4b18b961a56f0f50718
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5568
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:10:54 +02:00
Edward O'Callaghan 45b7b5af76 superio/ite/it8705f: Remove poor implementation
This super io support is poorly implemented and would not work for all
boards since it hardcodes values. Since there are no users of it, remove
for now pending a fresh reimplementation from scratch.

Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5566
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:08:53 +02:00
Edward O'Callaghan 5c41ee69ef superio/ite/it8716f: Rewrite from hardcoded base addr
Following the same reasoning as:
HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr
Removing hard coded magics and expose sio pnp api in romstage.

Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5565
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:06:15 +02:00