Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The device function is missing in the PCI device table in the PPR, but
is present in the hardware. Verified on a Mandolin board with PCO APU.
The corresponding ticket for the PPR is DESPCSOC-6667.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.
TOM2 isn't used by any ASL, so we could remove it later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This adds the SMM finalization to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 64d0ad347b. In the
current revision 3.001 of the PPR #56569 the register exists and the bit
definitions match.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that all ACPI names are moved to the corresponding PCI devices, the
functionality in the chip code isn't needed any more.
TEST=No warnings or errors on coreboot console or in the Linux ACPI
parser.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d39b6d4bd53cd0ca189fb6f55ca26dab68793fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function isn't used outside of the same compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.
Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This was replaced by APM_CNT defined in src/include/cpu/x86/smm.h, so
remove the now unused definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibd25dcdb57de14fe42352f01067cedca53712d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I also removed the unnecessary #include in soc.asl.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The exact same mechanism is used on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.
Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is another common ACPI setting.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between stoney, picasso, and cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between all the chipsets.
It's also required by common/block/lpc/lpc.c.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The same functionality will eventually be needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.
Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The corresponding bit is marked as reserved in the PPR. Also there's no
BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also
fix the style of the comment.
Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.
Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
southbridge.c was renamed and split into early_fch.c and fch.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Triggering SMI is not part of the semantics of global_smi_enable(), so
move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3
check we don't get PSP warnings/errors during resume, so we can drop the
workaround introduced in commit 5dbe45e0f5
in this patch.
Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 75f6ab35ff.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The same functionality is needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
No PCI or PNP functions are used in here.
TEST=Timeless build results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need the same functionality for cezanne.
TEST=Boot ezknil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The `_MASK` macros should be using the corresponding `_SHIFT` macros.
Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674
Found-by: Coverity CID 1445928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso has 32 configurable GPEs, not only 28.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 3f2467032e changed this in the APCI
code itself, but the change in the ACPI byte code generation in
pcie_gpp.c was missed and this patch fixes that.
TEST=Fixes the regression on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60de29581296101947336f70343d6206af97e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This define was copied over from Stoneyridge, but isn't present on
Picasso and newer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The function to get the PSP mailbox address is the same on Picasso and
Cezanne, so move it to the common PSP generation 2 code. The function is
only used in the same compilation unit, but it can't be marked as static
due to the function prototype in amdblocks/psp.h that is still needed
for Stoneyridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieea91ef76523d303f948d29ef48e3b2e56293f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If MSR_PSP_ADDR is uninitialized, it's all zeros and not all ones.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecd3039f63f9d0cb75fe3cb37aee92ba65bbbb50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and
Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
acpi_is_wakeup_s3() is defined in acpi/acpi.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53916cd15bb28484eb06be4d43f26152de159391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50125
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also move the fch_* functions in the header file in the order they get
called.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6c6ad744b26f8488015c38a84d7e21c7d7687a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50093
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.
Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow to override the RFMUX setting if the board does not use PD chip.
BUG=b:177389383
BRANCH=none
TEST=Build; Check the USB_PD port been override.
Change-Id: Idd559b67668846805005a6e00f5a84655310f348
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.
More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a common place where acpigen generates these,
so the declarations for the OperationRegions should be
centralized too.
Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI0 MMIO window was defined between TOM and 4 GiB. This was
overlapping with the FCH MMIO devices. The first MMIO device after TOM
is the FCH IOAPIC.
This wasn't causing a problem for linux other than the fact that
/proc/iomem showed all the MMIO devices under the PCI root bridge.
On Windows this was causing all the MMIO devices to have conflicting
resource errors.
BUG=b:175146875
BRANCH=zork
TEST=Boot linux and verify peripherals all work. Boot windows and
verify the i2c controllers show up. The GPIO controller still has a
problem related to power.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zork platform was not booting with MCACHE enabled since psp_verstage
had following issues with MCACHE.
Fix all the issues and re-enable MCACHE for Zork.
* psp_verstage should call vboot_run_logic, not verstage_main.
vboot_run_logic calls after_verstage which handles RW MCACHE build.
* It should avoid low-level apis for cbfs access.
cbfs_map will build RO MCACHE if it's the first stage, while other
low-level apis won't.
* It should call update_boot_region before save_buffers
MCACHE should be transferred to x86 so we should build it before
calling save_buffers
BUG=b:177323348
BRANCH=none
TEST=boot Ezkinil
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is not the correct way to specify the FixedDMA devices. I'm
removing for now since it adds confusion.
BUG=none
BRANCH=zork
TEST=Boot zork to linux and make sure UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The default case is only needed to make the compiler happy.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The empty string causes an undetectable build error.
Filter out the board which doesn't define this variable.
A great odds that the reason is the board doesn't set a
valid ROM size.
Change-Id: Iade1961460285acdec245c553c7b84014c30c267
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.
Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.
For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().
Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This matches the _HID used in the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
This does change the fixed clock used by linux from 133 MHz to 150 MHz.
BUG=none
BRANCH=zork
TEST=boot linux and verify touch screen and touchpad still function
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Change the hardcoded location of microcode patches to using
FIRMWARE_LOCATION.
Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.
BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a _HID/_CID are not unique, we need to add a _UID field to
differentiate the objects.
BUG=b:175146875
BRANCH=zork
TEST=Boot linux, dump ACPI table and verify UIDs are unique
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icd2ccede2b6c2e332157e2eeca89fba14a46b360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Create uniform logging for the (unlikely) case of a CBMEM
entry disappearing.
Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To implement some common helpers for CBMEM_ID_POWER_STATE
allocation use the same struct name as soc/intel.
Change-Id: I5d2c06a2a7b4602374562197c99b0ad7bcf50afb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is no reason to duplicate the table.
BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ief714266cdb1b4f89afd0d9e50238200b87687ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
I think it makes the code a bit cleaner.
BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Each bridge can only have one device.
BUG=b:170595019
BRANCH=zork
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e476221dfcabc841cc1ed4bc4b1175c0652dcfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The dummy AOAC parent device was nice because it grouped all the AOAC
devices. Unfortunately windows doesn't like this dummy device and causes
"Not Found" errors. This change moves the AOAC devices to the actual
devices that use them.
BUG=b:175146875
TEST=Boot linux and make sure power resources are enabled/disabled.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idd4a94baa4358ee4f15c461a5bb54ca925023a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug, so there is no need to specify a MMIO address for the early EHCI
BAR configuration.
Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug.
Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.
Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add code to collect all required information and generate ACPI CRAT
table entries. Publish tables generated from cb, rather than use the
tables created by FSP binary.
BUG=b:155307433
TEST=Boot trembyle and compare coreboot generated tables with tables
that FSP published previously.
BRANCH=Zork
Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This struct isn't used anywhere else, so there's no need to name it.
Change-Id: I22eda07f14096d2b7400e6ab715641ffd68fbc08
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49444
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are no longer really useful. We can also enable Power Resource
ACPI debug in the kernel if we want these messages.
BUG=none
BRANCH=zork
TEST=emerge-zork and verify debug messages are no longer posted
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I936e816266825f1c59377c2e079ffe1a5188838c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This will result in less code duplication when the common AMD SoC UART
support gets used for more AMD SoCs.
Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts commit 6f8f9c969b
by moving CONSOLE_UART_BASE_ADDRESS back to the SoC-specific code, since
the number and base addresses of UARTs turned out to be rather SoC-
specific. The help text for the AMD_SOC_CONSOLE_UART option also
contained those base addresses, so remove that as well.
Change-Id: I01211ec62421c56f22ed611313d6245a05bdea67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.
In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.
The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.
TEST=SoC UART console still works on Mandolin.
Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is causing boot errors on zork:
coreboot-v1.9308_26_0.0.22-18590-g4598a7bed945 Wed Dec 16 17:32:25 UTC 2020 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area FW_MAIN_B found @ 312000 (3137280 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f2bbdd9c87c4efdfb0042e90a20b489fa0efced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used as a guard to not raise SMI with
APM_CNT_GNVS_UPDATE. The handler has been removed
now completely.
Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI interrupt line registers are used as a last resort if routing
can't be fetched from either ACPI or the MPTable. This change correctly
sets the registers. It overrides the pirq_data set by the mainboards
since the routing is fixed in AGESA.
BUG=b:170595019
TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic`
Verified all PCI peripherals are still functional.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The original routing table did not handle all 8 INTx interrupts.
Additionally it also didn't take the swizzling into account.
Now that we know how AGESA programs the routing table we can correctly
generate it.
We still route the PCI interrupts through the FCH IOAPIC. A follow up
will have the GNB IOAPIC handle the PCI interrupts.
There is still work to be done to fix the legacy PCI_IRQ register for
each PCI device. We can then remove the mainboard_pirq_data from each
mainboard.
BUG=b:170595019
TEST=Used ezkinil
Boot kernel with `pci=nomsi amd_iommu=off noapic` and
`pci=nomsi amd_iommu=off` then verified system
was usable and verified /proc/interrupts looked correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The set_resources field in the root_complex_operations struct shouldn't
be NULL, but a pointer to noop_set_resources instead. This fixes the
error "PCI: 00:00.0 missing set_resources".
Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move CPUID definitions out of msr.h into new cpuid.h header.
BUG=b:155307433
BRANCH=Zork
Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally.
We may have another device need this clock e.g. superio chip.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
GEVENT_MASK should cover all GEVENT pins, but was missing
SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8.
Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Base address symbols for ACPIMMIO banks that would not get
assigned at runtime must not resolve at linker-stage either.
The build of PSP-verstage should pass without the preprocessor
macros that have x86-centric view of memory space.
Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.
Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new helper function to support reading a register from the data
fabric.
BUG=b:155307433
TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and
confirm read values match expected values.
BRANCH=Zork
Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
