Commit Graph

6489 Commits

Author SHA1 Message Date
Gabe Black ea9c98d454 exynos5420: Replace the 5250 GPIO code with code that should work on 5420.
Change-Id: Iac6615240e94c74037afc801169c32d3ebc4ac03
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:54 +02:00
Stefan Reinauer 919c804425 ARMv7: Clean up console code
- Guard console_init() with CONFIG_EARLY_CONSOLE in bootblock
 - Don't initialize console twice in the bootblock
 - remove printk in memory init that would mess up the UART
 - unconditionally run console_init() in romstage, as it is
   also unconditionally run in the bootblock.

Change-Id: I8f0d60877433162367074d0e55e01f935fd81f8e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3647
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:42 +02:00
Gabe Black d3163abd43 pit: Add a "pit" mainboard which is mostly a copy of "snow".
This change adds a pit mainboard which is mostly a copy of snow, except that
mentions of the 5250 were replaced with the 5420, and mentions of snow were
replaced with pit.

Change-Id: I8eb0ce379eb2fa353bb88d5656a0c5e2290afbf0
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:21 +02:00
Gabe Black b2d811aa9e pit: Fix some settings for the exynos5420 CPU.
Some of the settings which were defaulted to or automatically selected for the
exynos5420 which were inherited from the exynos5250 were not correct for this
SOC.

Change-Id: I11ffd8a6b80628405ac493fe2139f79c05d15d7e
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3645
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:09:07 +02:00
Gabe Black 607c0b6d63 pit: Create an exynos5420 directory which is nearly a copy of exynos5250.
This change creates an exynos5420 directory with code that will eventually
implement support for the exynos5420 cpu from Samsung. Currently it's a copy
of the exynos5250 directory with the name changed. There are going to be some
problems where headers in src/cpu/samsung/exynos-common include headers in the
exynos5250 directory directly.

Change-Id: Ia8d7244310d32499238bbc171c0c668ec48178e1
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3644
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:53 +02:00
Stefan Reinauer dc006c1db4 ARMv7: De-uboot-ify Exynos5250 GPIO code
The Exynos GPIO code has three different APIs that, unfortunately,
were widely used throughout the code base. This patch is cleaning
up the mess.

Change-Id: I09ccc7819fb892dbace9693c786dacc62f3f8eac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3643
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:29 +02:00
Stefan Reinauer 08dc357146 ARMv7: De-uboot-ify Exynos5250 code
When starting the Exynos5250 port, a lot of unneeded u-boot code
was imported. This is an attempt to get rid of a lot of unneeded
code before the port is used as a basis for further ARM ports.

There is a lot more that can be done, including cleaning up the
5250's Kconfig file.

Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3642
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 20:08:15 +02:00
Stefan Reinauer f73de9b975 Update 3rdparty hash for latest ARM BL1 binaries
Change-Id: Ice28114e5f53f510d305cd85d095044e2f4bd7b2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3740
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-07-10 03:02:05 +02:00
Christoph Grenz 2cccacff90 w83627hf/acpi: Fix endianess error in floppy drive enumeration code
The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.

Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3602
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-10 02:54:01 +02:00
Stefan Reinauer b98dec032f samsung/exynos5250: unify code
It turns out that the exynos5-common code previously imported from
u-boot is not common code at all but very specific to the 5250 and
not compatible with the 5450. Hence, unify the directories exynos5250
and exynos5-common. We will try to factor out common code while
progressing with the 5450 port.

Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3641
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:41:23 +02:00
Stefan Reinauer 043eb0e35f Wield battle axe at ARM port
This patch unfortunately incorporates a number of changes,
all of which are making future ARM ports easier.

 - drop cruft that came in with u-boot
 - move serial console from mainboard Kconfig to Exynos Kconfig
 - factor out non-board specific wakeup code
 - move generic bootblock code from mainboard to Exynos
 - actually call arch_cpu_init()
 - remove dead code
 - fix up copyright messages
 - remove snow_ prefix from a lot of code to reduce the noise
   when creating a new mainboard based on that code.

Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3640
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:41:09 +02:00
Stefan Reinauer 6adef0847e Rename hardwaremain() to main()
... and drop the wrapper on ARMv7

Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3639
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:40:30 +02:00
Stefan Reinauer 2ae6d6f6de ARMv7: normalize ramstage code flow
In ram stage, all code flow should be tied to the resource allocator.
Stuff that has to happen before everything else goes into the mainboard
enable function in mainboard.c. This patch empties the main() wrapper
around hardwaremain.c, allowing to get rid of this special case in the
ARM port.

Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:40:17 +02:00
Ronald G. Minnich 78c3e33550 FUI: reorganize include files
We've got enough of a handle on this to realize some things:
drm_dp_helper.h is by design device and architecture independent
i915.h is common to most intel graphics chipsets going back several years
i915_reg.h is as well

Move these files to src/include/device, and adjust the .c files accordingly.

Change-Id: I07512b3695fea0b22949074b467986420783d62a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:39:42 +02:00
Ronald G. Minnich b2893a0169 Provide support for setting up the framebuffer from EDID
Add three functions to edid.c:

void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
takes an edid and uintptr_t, and fills in a static lb_framebuffer struct
as well as setting the static vbe_valid to 1 unless some problem
is found in the edid. The intent here is that this could be called from
the native graphics setup code on both ARM and x86.

int vbe_mode_info_valid(void)
returns value of the static vbe_valid.

void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
copies the static edid_fb to lb_framebuffer.

There is now a common vbe.h in src/include, removed the two special ones.

In general, graphics in coreboot is a mess, but graphics is always a
mess.  We don't have a clean way to try two different ways to turn on
a device and use the one that works. One battle at a time. Overall,
things are much better.

The best part: this code would also work for ARM, which also uses EDID.

Change-Id: Id23eb61498b331d44ab064b8fb4cb10f07cff7f3
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3636
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:39:28 +02:00
Gabe Black 3fb30eeb14 ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.
The default for this variable should be n, it should only depend on
EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when
needed. This prevents it from being turned on when the EC bus is SPI.

Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3737
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 02:38:55 +02:00
Kyösti Mälkki 54d6abd276 Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.

Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 01:24:42 +02:00
Kyösti Mälkki 872c922296 Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.

The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.

Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10 00:57:09 +02:00
Denis 'GNUtoo' Carikli 20b6d91fd3 southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG
Without that fix, and with CONFIG_SMM_TSEG, we have:
  src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep':
  src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration]
  cc1: all warnings being treated as errors
  make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1

The fix is modelled after src/cpu/x86/smm/smihandler.c which
  ifdefs smi_release_lock().

Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3281
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:54:03 +02:00
Denis 'GNUtoo' Carikli 1b32a51e51 i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.c
Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3304
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:53:17 +02:00
Denis 'GNUtoo' Carikli b694f10c00 southbridge: i82801gx: smihandler.c: Correct outl->outw mistake.
This mistake was spoted by comparison with the
  src/southbridge/intel/bd82x6x/smihandler.c file.

Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3303
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:52:20 +02:00
Nico Huber d1fb5641b6 sandybridge: Add option to lock SPI regions on resume
Add an option to mark all SPI regions write protected on each S3 resume.
We were used to lock the SPI interface in the payload which isn't run on
the resume path. So we have to do it here.

For the write protection to be effective, all write opcodes in the
opmenu have to be marked correctly (as write operations) and the whole
SPI interface has to be locked. Both is already done.

Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3594
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 00:48:33 +02:00
Ronald G. Minnich 4f78b18749 fox_wtm2: First step support for coreboot-based graphics startup
This code is the initial version of FUI for haswell and wtm2.

The code is simplified from before in many ways. I've gotten rid of
the opcode table, because it obscured meaning and I don't think it is
needed any more. Register sets, mainly used for reset, are just lines
of code -- not many of them. There are a bunch of not-yet-documented
registers here; the VBIOS seemed to think they were necessary and
testing shows they seem to be right.

As a bit of added paranoia, we always include the VBIOS code as our
emergency recovery path. You have to run it now anyways, so this is no
regression from our current situation; and, if all goes well, in a
week (or so), you'll never have to run it again, but like the Force
and nose hair, it will be with you always.

The code can return in three ways. The first, best way is success:
panel is up and the VBIOS need not run. The second mode is that we
tried to light up the panel but could not, for some reason, but will
return with the panel partly up. In this case, it's ok not to power
cycle the panel. The third, worst case, which will NEVER happen, ha
ha, is that we have to turn the panel off and wait the required 600ms
for it to cycle. Life sucks sometimes. This failure mode is in the
'hang on we're going to fix it' category now that we have ramstage in
RW.

The Big Goal here is to create something other coreboot ports can use
as well. The guys doing the x60 report that the link FUI works,
without too many mods, on that chipset, so it seems Intel is keeping
things from changing too much over time.

Also, again, please note: this and the next 3 versions will ALWAYS fail.
The goal is to verify the correctness of the recovery path.

The bizarre tab-space formatting in drm_dp_helper.h is from the original,
as in i915_reg.h

Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09 22:16:37 +02:00
Ronald G. Minnich 2a66d6b804 FOX_WTM2: First pass at FUI.
This lights up the display. We don't get graphics but we are missing the gttsetup
at this point, so that is no shock. The real shock is that anything works at all.

Change-Id: I03fc470334e96878aeb8465044b3cc9c90378735
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-09 22:16:09 +02:00
Andrew Wu 49f620221a Fix Vortex86EX devicetree.cb indentation.
Change-Id: If357b55b91618ee2438e6c6b2efb7018c56d26d0
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3628
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-08 17:35:49 +02:00
Peter Stuge d0b04003d0 Revert "Radio and dock support in EC on X60 and X201"
This reverts commit 7d1ebbff5a

Change-Id: I4a9d0cd31a3df3d1e092193953f334697ca65167
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3616
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-08 06:18:50 +02:00
Gabe Black 8cfa33eb7c am335x: Implement support for the UART.
This patch was started by Dave Hendricks and implements the procedure for
setting up the UART as described in the manual. Some unused code was removed.

Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3490
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-07-06 00:46:18 +02:00
Andrew Wu 8522f9940a Add support for DMP Vortex86EX PCI mainboard.
Change-Id: I8d42f765519e356d8f0cc6ed339d9b74f0a3e4d7
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3610
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-05 21:39:14 +02:00
Nico Huber f66dd6966a w83627hf/acpi: Fix offset of logical device activation
The PnP's logical device activation normally resides at 0x30. This might
have been overlooked as 0x29 looks very close to 0x30 in human eyes.

Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-04 11:28:11 +02:00
Christoph Grenz 0bd5dff58c w83627hf/acpi: Fix type error in floppy drive enumeration code
The enumeration method tried to evaluate an one-byte OperationRegion
instead of a field in this OperationRegion, which resulted in an
AE_TYPE error at runtime.
Indexing the OperationRegion with a single field fixes this error.

Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3603
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 05:15:41 +02:00
Kyösti Mälkki 9e974232e4 intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 03:10:22 +02:00
Kyösti Mälkki 575e6817e6 Move select MMCONF_SUPPORT under northbridge (fix)
I missed the board with gm45 when I moved MMCONF_SUPPORT lines.

Also, the intel/i3100 does not have MMCONF_SUPPORT implemented
even though it was previously selected for intel/eagleheights board.

Change-Id: I9c7f6b0a150b4d54288a1e015277b9d98467fca4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3598
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-04 03:06:53 +02:00
Kyösti Mälkki 032c23db08 intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with i945 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3584
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:39 +02:00
Kyösti Mälkki fbdb085549 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards
with SandyBridge and IvyBridge. To enable MMIO style access,
add explicit PCI IO config write in the bootblock.

Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3576
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-04 00:53:06 +02:00
Kyösti Mälkki 15c4ab7adf Move select MMCONF_SUPPORT under northbridge
Move/remove MMCONF_SUPPORT reference under mainboard Kconfig, as
that feature originates from northbridge and cannot be disabled
for a single mainboard.

Change-Id: I6d6861079876ddddaff90b10f18edb6936e93bd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3589
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 19:34:11 +02:00
Andrew Wu 00bf647bf6 Add support for DMP Vortex86EX PCI southbridge.
Change-Id: Iad11cb1b22e9d1e2953b12221541b1478cad9665
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 18:31:22 +02:00
Nico Huber dd94fa93b4 winbond/w83627dhg: Fix logical device power down in ACPI
The W83627DHG has some power managements bits to power down individual
logical devices. These are called `* Power Down`. Counterintuitively and
in contrast to `Immediate Power Down` (bit to power down the whole chip),
these bits are set when the respective logical device is powered.

Unfortunately, our ACPI code set them wrong which led to disabled
devices after a S3 suspend/resume. Adding an option how to set the PM
bits and setting them to zero for the W83627DHG, corrects it.

Tested with kontron/ktqm77.

Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3590
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-03 17:58:20 +02:00
Nico Huber 1c81128dcd pnp: Add some default functions to enter/exit config state
Implement some common default functions to enter and exit the
configuration state. Also provide default pnp_mode_ops for common
enter()/exit() function pairs.

The following cocci ensures their use:
    @ mode_match @
    identifier enter, exit, ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = enter,
             .exit_conf_mode   = exit,
     };

    @ enter_match_8787 @
    identifier mode_match.enter, dev;
    @@
     enter(...)
     {
             outb(0x87, dev->path.pnp.port);
             outb(0x87, dev->path.pnp.port);
     }

    @ depends on enter_match_8787 @
    identifier mode_match.enter, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .enter_conf_mode  = enter,
    +        .enter_conf_mode  = pnp_enter_conf_mode_8787,
     };

    @ enter_match_55 @
    identifier mode_match.enter, dev;
    @@
     enter(...)
     {
             outb(0x55, dev->path.pnp.port);
     }

    @ depends on enter_match_55 @
    identifier mode_match.enter, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .enter_conf_mode  = enter,
    +        .enter_conf_mode  = pnp_enter_conf_mode_55,
     };

    @ depends on enter_match_8787 || enter_match_55 @
    identifier mode_match.enter;
    @@
    -enter(...) {...}

    @ exit_match_aa @
    identifier mode_match.exit, dev;
    @@
     exit(...)
     {
             outb(0xaa, dev->path.pnp.port);
     }

    @ depends on exit_match_aa @
    identifier mode_match.exit, mode_match.ops;
    @@
     struct pnp_mode_ops ops = {
    -        .exit_conf_mode   = exit,
    +        .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @ depends on exit_match_aa @
    identifier mode_match.exit;
    @@
    -exit(...) {...}

    @ depends on enter_match_8787 || enter_match_55 || exit_match_aa @
    @@
     #include <device/pnp.h>
    +#include <superio/conf_mode.h>

    @ mode_match_55_aa @
    identifier ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = pnp_enter_conf_mode_55,
             .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @@
    identifier mode_match_55_aa.ops;
    @@
    -struct pnp_mode_ops ops = {...};

    @@
    identifier mode_match_55_aa.ops, devops;
    @@
     struct device_operations devops = {
    -        .ops_pnp_mode     = &ops,
    +        .ops_pnp_mode     = &pnp_conf_mode_55_aa,
     };

    @ mode_match_8787_aa @
    identifier ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = pnp_enter_conf_mode_8787,
             .exit_conf_mode   = pnp_exit_conf_mode_aa,
     };

    @@
    identifier mode_match_8787_aa.ops;
    @@
    -struct pnp_mode_ops ops = {...};

    @@
    identifier mode_match_8787_aa.ops, devops;
    @@
     struct device_operations devops = {
    -        .ops_pnp_mode     = &ops,
    +        .ops_pnp_mode     = &pnp_conf_mode_8787_aa,
     };

Change-Id: I1480336b54523cc95210d99cf31c1a0b3a14b464
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-03 16:13:11 +02:00
Paul Menzel abe6847cd2 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
Use the same indentation, comment placement and spelling of words.
Run `indent -linux …`.

Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3220
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-02 21:07:44 +02:00
Dave Frodin 59158b2fb0 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900
The MAX_PIRQ_LINKS is defined in src/Kconfig with a default value
of 4. The src/northbridge/via/vx900/Kconfig also defines
MAX_PIRQ_LINKS with a default of 8 and it ends up giving us
a value of 8 for non-VIA platforms.

Change-Id: Iee1938d38a93ab7c35c8cb6fe9656a92cf3fa21e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3586
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-02 16:24:04 +02:00
Christoph Grenz dda4095101 w83627hf: Add comments about parallel port modes in superio.asl
Add comments in PAR0._PRS explaining which dependent resource
descriptor puts the parallel port into EPP or SPP mode.

Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3495
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-07-01 23:22:41 +02:00
Gabe Black 595ab4f955 beaglebone: Enable the clocks and pins for the configured UART.
Set up the pinmux to enable the pins and the clocks for whichever UART is
currently configured.

Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3573
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01 21:31:46 +02:00
Gabe Black 94f631cdc9 am335x: Fix the address of the pinmux registers.
The pinmux register data structure describes a subset of the control module
registers, but the address which pointed to the base of the pinmux registers
was actually being set to the beginning of all the control module registers,
not just those having to do with the pinmux. With this address fixed, the UART
now works on the beaglebone black.

Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3574
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-01 18:31:28 +02:00
Kyösti Mälkki caaf0bf483 usbdebug: Support i82801dx/ex southbridge
Tested on i82801dx system with board aopen/dxplplusu.

Change-Id: I522455ac79c87b9b6fc9cd8c4dc0da3563dfbfad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3381
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-01 17:11:32 +02:00
Kyösti Mälkki 54c586c7e7 usbdebug: Unify Intel southbridge builds
EHCI controller enable is identical on the affected chipsets.

Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-01 17:11:14 +02:00
Kyösti Mälkki fb387dfb92 usbdebug: Drop duplicates of EHCI BAR relocation code
All the additional work that needs to be done in EHCI BAR relocation
is independent of the hardware platform and was functionally identical
in all the copies removed.

When USBDEBUG is not selected, PCI EHCI controllers use standard
pci_dev_read_resources() call.

With USBDEBUG selected, PCI EHCI controller's device_operations
.read_resources is replaced with pci_ehci_read_resources() call,
which in turn will replace the device_operations .set_resources call.
The replacement for .set_resources reconfigures usbdebug driver side,
and calls the original .set_resources to configure hardware side.

Change-Id: I8e136a5da4efedf60b6dd7068c0488153efaaf8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3412
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-01 17:10:55 +02:00
Siyuan Wang 0d8d482f63 AMD S3 resume: Add framwork to write bigger data
This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1]

Some AMD south bridge can write bigger data when saving S3 info.
In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size.
AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig'
and then can be overridden in the Kconfig for specific
southbridges that support larger size.

I have tested on AMD Parmer and Thatcher. We will release a new board
whose south bridge can transfer more than 4 bytes each time.

[1] http://review.coreboot.org/#/c/2306/

Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3413
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-29 18:57:42 +02:00
Denis 'GNUtoo' Carikli bc2c9efd56 ELOG: Fix warning to fix the compilation.
Without that fix we have:
  src/drivers/elog/elog.c: In function 'elog_is_header_valid':
  src/drivers/elog/elog.c:213:3: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format]

Change-Id: I71b80a94c03a04eedb688ae107d92c05a878315e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3551
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-28 11:04:44 +02:00
Stefan Reinauer c0b1a48cda Drop WARNINGS_ARE_ERRORS exceptions
Thanks to Bruce's great work, we can finally drop this workaround.

Change-Id: Ie92d1e53ef867fa34aa2489ccfb682d73195b213
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3569
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-28 02:49:05 +02:00
Bruce Griffith 160243d73e Supermicro H8SCM/H8QGI: Increase size of bus variable to meet API
Users of mptable_write_buses() pass two pass-by-reference
parameters reflecting a maximum bus number and a search bus
number.  These bus numbers are expected to be held in "int"
variables and are updated by the function.  Both of the
Supermicro boards define the search bus number as a
byte value in mptable.c.

For now, change the two Supermicro boards to use "int"
to hold the search bus index.

Change-Id: Ie71850719c1fa3cda0ac9c8773bb80650de95c70
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3546
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:49:46 +02:00
Bruce Griffith e8dca508d3 AMD Dinar: Eliminate warnings (initializers/prototypes/unused var)
Fix a bunch of compiler-generated warning messages.  These fixes are 
mainly braces for grouping initializers.  These changes are not
intended to change any code functionality.  There are two changes where
function prototypes are added, and two cases where unused variables are 
eliminated. 

Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3545
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:49:00 +02:00
Bruce Griffith 21d6fd9d78 AMD SB700 boards: Set Azalia configuration flags
The existing code for setting Azalia configuration assumes that
the configuration bits are contiguous within a single byte and
can be set using a byte copy addressed into the lowest 2-bit
subfield.

The fix in Family 14 defines a union that can be addressed as a
byte to overlay the bit fields.  Since the offset of the four
subfields is not necessarily fixed, change the code to initialize
each of the four subfields individually.

Change-Id: I1dff20bb8bd3e1bcd8b4e6b0537e20779d2a3521
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:40:03 +02:00
Bruce Griffith f9ba7bb4f9 supermicro/h8scm: Add a type cast for printk to correct a warning message
Copy a type cast from the other cases of the same switch statement
to eliminate compiler warning messages.

Change-Id: I8d0a88892f6a5f8e43227ab5f830041894b07f6a
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3543
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:39:07 +02:00
Bruce Griffith 93b57c55a9 Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf()
On Dinar, H8SCM, and H8QGI, add <cpu/amd/amdfam15.h> as an
include to pick up the prototype definition of get_bus_conf().

Change-Id: Ie4887670ac52aa194745881362df19cd1d75773e
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3542
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:38:18 +02:00
Bruce Griffith 01677b6625 amd/cimx/sb700/late.c: Add type cast to (UINT8)
This change inserts a type cast to eliminate a compiler warning.

Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3541
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:37:51 +02:00
Bruce Griffith 53abac1767 amd/cimx/rd890/amd.h: Eliminate redefinition of NULL
This change replaces a redefinition of NULL with the standard
definition from <stddef.h> to eliminate a compiler redefinition
warning.

Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3540
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:36:29 +02:00
Bruce Griffith 58fff9d44f amd/agesa/family15/northbridge.c: Delete unused variable
This change eliminates an unused variable that causes a build warning.

Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3526
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:35:59 +02:00
Stefan Reinauer 1cc3416f5f Add support to enable/disable builtin GbE (again)
This requires a new system agent binary (v6 / v11 on haswell).
Note that the existing system agent binaries are long time obsolete
and won't work with current coreboot, so this update is overdue.

Change-Id: I48d8649576ca84d2b85ab082ce06f3462e189059
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3568
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-28 01:35:39 +02:00
Bruce Griffith e44a89f6fd amd/agesa/f15/Lib/amdlib.c: Add missing breaks to switch statement
Static analysis often flags case statements that do not include
a terminating "break;" statement. Eclipse's CODAN is an example
of this.  This changelist modifies amdlib.c to terminate
case statements with "break;".

Change-Id: I3d43acaf64e2e2d9717421cb547fec35e582cf8b
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3539
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:35:20 +02:00
Bruce Griffith af881b898a amd/agesa/f15/Proc/CPU: Add length modifier to eliminate compiler warnings
This change adds length modifiers to constant values to eliminate
compiler warning messages.

Change-Id: I032cb37cec788e2b5f79f5bbf9efc19a7892dc14
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3538
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:33:04 +02:00
Bruce Griffith 940ccaa510 vendorcode/amd/agesa/f15: Eliminate compiler warnings
This change is mostly type casts to eliminate compile time
warnings. These specific changes are mostly cherry-picked from
AMD Family 14 code and, as such, contain artifacts copied over
from F14. For example, there are a number of UINT64 casts that
are commented out rather than removed.  This is to maintain
consistency between AGESA versions.  Ultimately, this is in
preparation for turning on warnings as errors for AMD Family 15
server parts.

Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3525
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:32:20 +02:00
Kyösti Mälkki 714212a421 Revert "Add support to enable/disable builtin GbE"
This reverts commit d358a506c4

http://review.coreboot.org/#/c/3514/ comments:
The pei_data version changed to 6, so new binaries are needed.

However, demand for new binary blob is not referenced with this commit nor is git submodules hash updated. Also the new binary blob almost doubles its size and no longer fits in the allocation sandybridge defines.

Change-Id: I84eb70517d5b9278c611fdfa587a71f6ca0f657f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3553
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-27 00:27:14 +02:00
Nico Huber 99b024db88 bd82x6x: Fix early USB BAR programming (finally?)
The xHCI controller's MMIO space has a length of 64KiB not 4KiB.
Therefore, setting the xHCI BAR to 0xe8001000 worked the same like
setting it to 0xe8000000, as bit12 is reserved and ignored. This again
interfered with the MMIO space of the first EHCI controller and broke
S3 resume on Ivy Bridge.

AFAIK, the MRC ignores the setting of the xHCI BAR, anyway. So just drop
these lines.

Change-Id: I8af9c2ba34133f15636a9056fc8880b3b6ab95e0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3521
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-25 18:50:55 +02:00
Patrick Georgi c000352d5c ktqm77: redesign cmos.layout slightly
BIOS write protects 8 bytes of CMOS, which nvramtool can't cope with.
This makes initial installation harder, so just mark those as reserved
to work around the issue.

Change-Id: I210861dff8572e226a0f250556a3b811671ea8f2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3531
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-25 16:22:45 +02:00
Andrew Wu 8b9d4f3296 Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code.
6021 is Vortex86DX northbridge PCI device ID, not for Vortex86EX.

Change-Id: I9bea799c9033adbcfacc8ad47052280a32f9ee59
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3529
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-25 16:16:42 +02:00
Nico Huber 99fd30e486 sandybridge: Make inclusion of me.bin optional
Current build configuration always wants to include an Intel Management
Engine firmware (me.bin) on Sandy Bridge systems. However, we can have
a working coreboot without it, as long as the factory delivered ME
firmware is kept untouched in the flash ROM. So let the user decide if
a ME firmware will be included in the build.

Change-Id: I9a1cc29d4940ba22355eb9e653606e436f07e04c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3522
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-25 09:49:02 +02:00
Kyösti Mälkki 59fb82aab1 intel/sch: Use MMCONF_BASE_ADDRESS
For iwave/iWRainbowG6 using intel/sch, MMCONF_BASE_ADDRESS was unused
and different from hardware setting. Change that to match hardware
programming.

Change-Id: I3324b7ea0e6f092206d4b6b791476d538e826657
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-25 08:03:52 +02:00
Nico Huber efe1feda19 kontron/ktqm77: New board
Change-Id: Ife1c0a8597c2de04773899cdd87af6b6c630906a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3392
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 17:50:01 +02:00
Nico Huber a15cd66b9e sandybridge: Make build possible without descriptor.bin
On newer Intel systems, the flash ROM is shared between the host
processor (BIOS), it's Management Engine (ME) and an integrated ethernet
controller (GbE). The layout of the flash ROM (and other information) is
kept in the so called Intel Firmware Descriptor (IFD). If we only want
to build coreboot to update the BIOS section, all we need is the flash
layout.

This patch adds the option to specify the flash layout in the
mainboard's Kconfig, and thus, to build without the real IFD. However,
with such a build, one has to make sure that the IFD section on the
flash ROM won't be written over (nor any other section that hasn't been
included by coreboot). A patch to write selected sections of a flash ROM
with IFD has been sent to the flashrom mailing list [1].

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

Change-Id: Ia23e439a00a197fb54852263f8e206f16c3e8851
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3524
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 17:42:48 +02:00
Kyösti Mälkki 6aeb4a269c AMD: Drop empty root_complex
There are no files to build left under AMD nortbridge/x/root_complex
directories. For some cases, even the Kconfig file was no longer sourced.
Remove all such references and empty files.

For devicetree.cb treat component paths with "/root_complex" in them valid
even when the directory does not exists. This is because AMD boards us this
dummy chip component as the root node in their devicetree.cb.

The generated devicetree file static.c remains unchanged.

Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-24 17:22:44 +02:00
Rudolf Marek ef561a5582 Asus F2A85-M: Add IRQs for IOMMU
The IOMMU needs IRQs assigned. So add those.

Change-Id: Ic9f02e28aac593cddf7d222a8abb780a10572d32
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3318
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 05:39:15 +02:00
Rudolf Marek 5ce0506618 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
The IOMMU AGESA needs a reserved scratch space and it wants
to allocate the stuff for runtime. So provide a simple
allocator for 4 KB CBMEM page.

Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3315
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 00:53:52 +02:00
Rudolf Marek 88ebbeb7e2 AMD Fam15tn: Add IOMMU BAR allocation to northbridge
For IOMMU we need to allocate a 512 KB BAR in a non-standard
location. Use the standard allocator for that and limit the BAR
to 32-bits to be compatible with older systems.

Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3314
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 00:52:50 +02:00
Kyösti Mälkki 81d3d7d001 lynxpoint: Fix early EHCI BAR programming
LynxPoint LP has only EHCI controller #1.
Change EHCI #2 to different BAR from EHCI #1.

Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.

Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3472
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-23 23:36:58 +02:00
Paul Menzel a390d77966 AMD boards: routing.asl: Uniformly start `Package()` with capital letter
In commit  Rudolf Marek discovered, that it is not uniformly written. As
»ASL names are not case-sensitive and will be converted to upper case.« [2]
this change does not have any functional change.

The following command was used to create this patch.

    $ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),'

[1] http://review.coreboot.org/#/c/3318/
[2] http://www.acpi.info/spec40a.htm
    (18.2.1 ASL Names)

Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3516
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-23 19:51:49 +02:00
Kyösti Mälkki eac00d2dbb intel/sandybridge: Locate CBMEM TOC early in ramstage
This patch allows the use of migrated CAR_GLOBAL variables from
the very beginning of ramstage. Without the patch, CAR_GLOBALS were
not available until northbridge set_resources().

Change-Id: Ifd4ab2ed52e07dcbe8c77e2e460dc483323e93c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3513
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-22 20:48:08 +02:00
Aaron Durbin 7f5897a1c5 Do CAR variable migration only once
Non-S3 resume paths of sandy/ivybridge call cbmem_initialize()
more than once. Doing car_migrate_variables() more than twice caused
at least loss of some lines in CBMEM console.

Change-Id: Idd14aba9384984aa3a7d38937a4b3572aa5dc088
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3512
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-22 20:47:21 +02:00
Andrew Wu 0651072597 Add support for DMP Vortex86EX PCI northbridge.
Change-Id: I60675a357f9db430ebb59b17be6d8c92a9cadf43
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3511
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-22 17:33:27 +02:00
Denis 'GNUtoo' Carikli 378d04640d qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM.
This commit was tested on qemu with and without CONFIG_DYNAMIC_CBMEM
  by running cmbmem -c once booted. The qemu command that was used was:
    qemu-system-i386 -bios ./build/coreboot.rom  -serial stdio -hda ../virt/parabola.img

Note that using CONFIG_RELOCATABLE_RAMSTAGE make it fails like that:
  Loading image.
  CBFS: Decompressing stage fallback/coreboot_ram @ 0x3ffbefc0 (184400 bytes)
  Loading module at 3ffbf000 with entry 3ffbf000. filesize: 0x18db8 memsize: 0x2c050
  Processing 1703 relocs with adjust value of 0x3ffbe000
  FATAL: Essential component is missing.
However without CONFIG_RELOCATABLE_RAMSTAGE set it boots fine.

Change-Id: I633a8c3832eee4e8bed244940fdc370b98dd26f0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3504
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-06-22 17:31:03 +02:00
Stefan Reinauer d358a506c4 Add support to enable/disable builtin GbE
In case we are going to use this in future designs.

BUG=none
TEST=none
BRANCH=none

Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/55844
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3515
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-21 19:36:55 +02:00
Denis 'GNUtoo' Carikli 8a0a8488fe Dynamic cbmem: don't compile src/lib/cbmem.c when dynamic cbmem is selected.
src/lib/cbmem.c is for the static cbmem.

Thanks to adurbin for the Makefile.inc pointer and code on #coreboot IRC channel on freenode:
  <adurbin> no. if you have CONFIG_DYNAMIC_CBMEM then cbmem.c shouldn't be compiled
  [...]
  <adurbin> +ifeq ($(CONFIG_EARLY_CBMEM_INIT),y)
  <adurbin> +ifneq ($(CONFIG_DYNAMIC_CBMEM),y) romstage-$(CONFIG_EARLY_CBMEM_INIT) += cbmem.c
  <adurbin> +endif
  <adurbin> +endif

Without that fix we have:
  src/lib/cbmem.c:58:43: error: no previous prototype for 'get_cbmem_toc' [-Werror=missing-prototypes]
  src/lib/cbmem.c:76:6: error: no previous prototype for 'cbmem_init' [-Werror=missing-prototypes]
  src/lib/cbmem.c:107:5: error: no previous prototype for 'cbmem_reinit' [-Werror=missing-prototypes]

This commit was tested on qemu-i440fx with the following commit:
  qemu-i440fx: Make it compile with CONFIG_DYNAMIC_CBMEM
  ( http://review.coreboot.org/#/c/3504/ ).

Change-Id: I98636aad4bb4b954f3ed3957df67c77f3615964a
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3503
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-06-21 19:29:52 +02:00
Kyösti Mälkki e761b71e52 bd82x6x: Fix early EHCI BAR programming
Change EHCI #2 to different BAR from EHCI #1.

Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.

Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3471
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-21 15:51:22 +02:00
David Hendricks cca685936a fix bootstate typo (bs_dev_eanble -> bs_dev_enable)
Change-Id: I2e3fd58404c48e863a3a1b255337fb397086651b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3506
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-20 23:45:01 +02:00
Andrew Wu 52e665bdd2 Add initial support for DMP Vortex86EX CPU.
Change-Id: I74de250c69a57109362be1b2f00c0b4aa24a64e8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3473
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-20 19:14:44 +02:00
Patrick Georgi 483ff82539 sandybridge: Store MRC cache in CBFS
Location is hard-coded right now, which isn't optimal.
It must be chip erase block aligned, which might fail on some flash chips
(it's 64k aligned which should work for most cases).

Change-Id: I6fe0607948c5fab04b9ed565a93e00b96bf44986
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-20 12:43:01 +02:00
Nico Huber 44c392f8c2 lenovo/t60: Collect timestamps in romstage
Collect early timestamps in T60's romstage like some newer boards do.
This should also work on X60s (and other ICH7 based systems with
EARLY_CBMEM_INIT).

Change-Id: I3b2872dd7423f3379ff3b68ad999523ec35fc08e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 17:59:50 +02:00
Nico Huber 9359f2de00 intel/i82801gx: Store initial timestamp
Upgrade the ICH7 bootblock to store an initial timestamp like we do it
since Sandy Brigde. I've checked the datasheets for the used scratchpad
registers and grepped for their usage. I'm pretty sure that they aren't
used on any ICH7 based board (for anything before the usual S3-resume
indication).

Change-Id: I28a9b90d3e6f6401a8114ecd240554a5dddc0eb5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 17:58:55 +02:00
Gerd Hoffmann 414b947851 qemu: complete bochs dispi interface vga driver.
Ditch unused fb*.h files.
Rename init.c (name is _way_ to generic) to bochs.c.
Add proper bochs dispi interface detection and mode setup.
Hook up coreboot framebuffer table initialization.

Change-Id: I7154b1593902e7d42606b64819217872eee10683
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3500
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 02:00:08 +02:00
Gerd Hoffmann 0ea3664bc3 edid: fix warning
src/lib/edid.c:1177: error: ‘y’ may be used uninitialized in this function

Warning is bogus, but seems my gcc (4.4.7 as shipped by RHEL-6)
isn't clever enougth to figure this on its own.  So help a bit
by explicitly initializing the variable.

Change-Id: Ia9f966c9c0a6bd92a9f41f1a4a3c8e49f258be37
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3501
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-19 01:58:29 +02:00
Nico Huber cacc58a874 winbond/w83627dhg: Correct resource setting for SPI (LDN6)
The SPI logical device on the W83627DHG uses the second i/o port
register pair but not the first one. So we have to also set `io1`
(the second io_info struct) and not `io0` in the pnp_info structure.

Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to
hang in pnp_enable_devices() until commit aeead274 which added a
check for an unset mask.

Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3391
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-18 19:15:12 +02:00
Gerd Hoffmann df8d27357f qemu/q35: uncomment cache-as-ram Kconfig entries
Change-Id: I8371764e3f2d16a3a776beb1c064f461b20a4262
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3496
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-18 17:44:38 +02:00
Gabe Black 5acc76cd3e am335x: Add pinmux support based on the functions in U-Boot
I was unable to find documentation that said what mode numbers correspond
to what functionality, so I translated over what U-Boot does.

Change-Id: I34fab0f024fa2322d6bb66106aed75224e67354d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3489
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 22:05:35 +02:00
Kyösti Mälkki 56892fc475 AMD southbridges: Move HAVE_HARD_RESET
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c
file already placed under southbridge/.

All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally
identical reset.c file under mainboard/. Move those files under
respective southbridge/.

Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3486
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 21:50:46 +02:00
Kyösti Mälkki d715105d30 AMD: Use same sourcecode for reset in romstage as ramstage
Confusingly, romstage compiled in different copy of soft_reset()
than ramstage. Use source in reset.c for both.

Change-Id: I2e4b6d1b89c859c7cf5d9e9c8f7748b43d369775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3487
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 21:49:33 +02:00
Kyösti Mälkki 397ca6176c AMD boards: Clean use of Kconfig options
The chip component is unconditionally selected for the mainboard
so these uses are superfluous.

Change-Id: I84b053ab47f7b1f68e88d968cf305e24bc95f4da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3485
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 21:48:31 +02:00
Dave Frodin 0fd6a65243 Add support for XHCI (USB 3.0)
CONFIG_HUDSON_XHCI_ENABLE will control the XHCI flags in the
amd/parmer and asus/f2a85-m mainboards.  The XHCI ports on
amd/thatcher are not wired to USB jacks so always disable the flags.
This was tested on amd/parmer using a USB 3.0 thumbdrive.

Change-Id: I596b040fec30882d8d4dee34ab9f866dc1f8896b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3465
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:45:39 +02:00
Dave Frodin 1fa1904e53 AMD Hudson: Add config option to enable XHCI
To have USB 3.0 support the XHCI controller needs to be enabled
and the xhci.bin firmware needs to be added to CBFS.

Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3464
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:45:06 +02:00
Nico Huber 0b2ee93910 pnp: Remove now plain wrappers for default PnP functions
After removing the enter()/exit() functions for configuration mode,
most wrappers for our standard PnP functions just call the underlying
default implementation.

Remove those with a little cocci:
    @ op_match @
    identifier op;
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    type device_t;
    identifier dev;
    @@
     static void op(device_t dev) { pnp_op(dev); }

    @@
    identifier op_match.op;
    @@
    -op(...) {...}

    /* Three rules to match the alignment, hmmp... */
    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .set_resources    = op,
    +        .set_resources    = pnp_op,
     };

    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .enable_resources = op,
    +        .enable_resources = pnp_op,
     };

    @@
    identifier op_match.op, op_match.pnp_op;
    identifier ops;
    @@
     struct device_operations ops = {
    -        .enable           = op,
    +        .enable           = pnp_op,
     };

Change-Id: Idc0e52c7e3600a01f3b6a4e17763557b271b481e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3483
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:42:21 +02:00
Nico Huber 13dc976a52 pnp: Register implementations of enter/exit config state
Find all the (ramstage) implementations of enter()/exit() functions
for the configuration state, register and call them through the new
struct pnp_mode_ops. As our standard PnP functions are aware of the
pnp_mode_ops, it's not necessary to call enter()/exit() around them
anymore.

Patch generated with the cocci below. It's not perfect. The movement
of the enter()/exit() calls is somehow fragile. So I checked the
remaining calls for sense, and changed some empty lines. Also a
duplicate insertion of pnp_conf_mode_ops had to be removed.
    /* Try to find enter and exit functions by their outb() structure and
       their usage around calls to our standard pnp functions: */
    @ enter_match @
    identifier enter;
    identifier dev;
    type device_t;
    @@
     void enter(device_t dev)
     {
             <...
             outb(..., dev->path.pnp.port);
             ...>
     }

    @ exit_match @
    identifier exit;
    identifier dev;
    type device_t;
    @@
     void exit(device_t dev)
     {
             <...
             outb(..., dev->path.pnp.port);
             ...>
     }

    @ pnp_match @
    identifier op;
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    identifier enter_match.enter, exit_match.exit;
    type device_t;
    identifier dev;
    @@
     void op(device_t dev)
     {
             ...
             enter(dev);
             ...
             pnp_op(dev);
             ...
             exit(dev);
             ...
     }

    /* Now add enter/exit to a pnp_mode_ops structure: */
    @ depends on pnp_match @
    identifier enter_match.enter;
    identifier exit_match.exit;
    identifier ops;
    @@
    +static const struct pnp_mode_ops pnp_conf_mode_ops = {
    +        .enter_conf_mode  = enter,
    +        .exit_conf_mode   = exit,
    +};
    +
     struct device_operations ops = {
             ...,
    +        .ops_pnp_mode     = &pnp_conf_mode_ops,
     };

    /* Match against the new structure as we change the code and the above
       matches might not work anymore: */
    @ mode_match @
    identifier enter, exit, ops;
    @@
     struct pnp_mode_ops ops = {
             .enter_conf_mode  = enter,
             .exit_conf_mode   = exit,
     };

    /* Replace enter()/enter() calls with new standard calls (e.g.
       pnp_enter_conf_mode()): */
    @@
    identifier mode_match.enter;
    expression e;
    @@
    -enter(e)
    +pnp_enter_conf_mode(e)

    @@
    identifier mode_match.exit;
    expression e;
    @@
    -exit(e)
    +pnp_exit_conf_mode(e)

    /* If there are calls to standard PnP functions, (re)move the
       enter()/exit() calls around them: */
    @@
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    expression e;
    @@
    -pnp_enter_conf_mode(e);
     pnp_op(e);
    +pnp_enter_conf_mode(e);
     ...
     pnp_exit_conf_mode(e);

    @@
    identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
    expression e;
    @@
     pnp_enter_conf_mode(e);
     ...
    +pnp_exit_conf_mode(e);
     pnp_op(e);
    -pnp_exit_conf_mode(e);

    @@
    expression e;
    @@
    -pnp_enter_conf_mode(e);
    -pnp_exit_conf_mode(e);

Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3482
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:42:06 +02:00
Nico Huber dd4715b6a5 pnp: Implement common handling for PnP config modes
Many super i/o chips only answer to PnP requests if they are in a
configuration state (sometimes also called ext func mode). To cope with
that, the code of many chips implements its own version of our default
PnP functions like pnp_set_resource(), pnp_enable_resource() etc.

To avoid this code duplication, this patch extends our PnP device
interface with optional functions to enter and exit configuration mode.

Change-Id: I9b7662a0db70ede93276764fa15020f251eb46bd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3481
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:39:40 +02:00
Nico Huber f898f7ba4d pnp: Provide alternative pnp_enable() implementation
The current default implementation of pnp_enable() only disables devices
- if set so in the devicetree - but does not enable them. Enablement takes
place in pnp_enable_resources(). Yet, many PnP chips implement their own
version of pnp_enable() which also enables devices if set in the devicetree.

It's arguable, if enabling those devices makes sense, before they get
resources assigned. Maybe we can't write the resource registers if not,
who knows? The least we can do is providing a common implementation for
this behavior, and get rid of some code duplication.

Used the following cocci:
    @@
    expression e;
    @@
    +pnp_alt_enable(e);
    -pnp_set_logical_device(e);
    (
    -pnp_set_enable(e, !!e->enabled);
    |
    -(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0);
    |
    -if (e->enabled) { pnp_set_enable(e, 1); }
    -else { pnp_set_enable(e, 0); }
    )

Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3480
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-17 21:38:37 +02:00
Patrick Georgi 3cc151ede0 Make intel blob locations configurable
They were hard-coded to be copied from 3rdparty/ which isn't always
the right choice.

Since the defaults stay the same, this should be compatible.

Change-Id: If2173bef86ad1fcf2335e13472ea8ca41eb41f3d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3453
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-17 19:16:52 +02:00
Nico Huber 9cb0941cb2 pnp: Unify some alignment to ease autogenerating patches
Most PnP drivers align the initialization of their `device_operations`
with spaces. Unify this, so next autogenerated patches always match the
alignment.

Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3479
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 18:11:35 +02:00
Gerd Hoffmann 7fd1beeaf7 qemu: i440fx whitespace fixup
Change-Id: I0d499027ffb175638cba0a9830d6ec2041a139db
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3488
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 17:04:43 +02:00
Gerd Hoffmann ee941b38d6 qemu: add q35 support
Add support for the new q35 chipset emulation
added in qemu 1.4.

Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3430
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 17:04:17 +02:00
Gerd Hoffmann 9839a385bb qemu: add support for memory above 4G
Change-Id: Ic83f55d01b29b43028e3b363749d64b927db5489
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3492
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 17:00:10 +02:00
Gerd Hoffmann 44b11f2fe4 qemu: move ram ressource reservation from "set" to "read" stage
So the pci allocation code knows where memory is and doesn't
try map pci devices there.  We also don't have to check for
overlaps between pci hole and memory then.

Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3491
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-17 16:59:14 +02:00
Christopher Kilgour 156ff13049 cpu/amd/geode_lx/cache_as_ram.inc: Use $ for constant value instead of memory reference
An uninitialized RAM value was used to select an MSR because a $ was forgotten
in front of `CPU_DM_CONFIG0`. It should be the constant value 0x1800, corresponding
to CPU_DM_CONFIG0 MSR defined in `src/include/cpu/amd/lxdef.h`.

Change-Id: Id53ca98b06cc4a9b55916fd8db23904f98008d45
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Reviewed-on: http://review.coreboot.org/3478
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-06-17 08:26:59 +02:00
Kyösti Mälkki 04372975bd AMD sb800 agesa/hudson: Use PCI defines
The original lines had contradicting comment and code.
This change follows the code and sets MASTER bit too.

Change-Id: Id2886bfc107612530f0e9747e5d49a9740fb8532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3466
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-14 18:54:57 +02:00
Gerd Hoffmann 00cc7f4355 qemu: move i440fx bits
Prepare tree for adding q35 support:
Move emulation/qemu-x86 to emulation/qemu-i440fx.
Rename some stuff to include 'i440fx'.

Change-Id: Ib8c58175c5734cfcda1b22404ef52c09d38f0462
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3429
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-14 18:19:26 +02:00
Kyösti Mälkki e49679d5a1 usbdebug: Drop temporary disables of log output
With this patch, output on usbdebug also includes the section of
MTRR setups for every CPU. This makes usbdebug output almost identical
with that of serial port and CBMEM console.

Tested with model_206ax. Also tested previously on model_f2x which does
not have these disable/enable calls in model_f2x_init() without detected issues.

Change-Id: Idfd0e93439907b17255633658195d698feab3895
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3423
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-06-14 18:18:56 +02:00
Kyösti Mälkki f55a54257a lynxpoint: Fix PCI IDs for EHCI
IDs were leftovers from bd82x6x.

Change-Id: I4ab6062929d346d7f000ce8c0b8c97490bb2b154
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3463
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-06-14 16:04:19 +02:00
Dave Frodin ea90963666 AMD Hudson: Add support for the SD controller
This patch provides the correct SD controller timings for
the Family16 device. It also will remove the SD controller
from PCI space when device 0:14.7 is set to off in devicetree.
This was tested on a AMD Parmer board and a AMD G-series SOC
reference board. The settings were found in the AMD
Hudson2 RRG and family16 BKGD.

Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3348
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 22:57:21 +02:00
Siyuan Wang 6c4f3ce490 AMD S3 resume: use a function to replace duplicated code
In function OemAgesaSaveMtrr of 'src/cpu/amd/agesa/s3_resume.c',
there are many code like this:
  msr_data = rdmsr(0x258);
  flash->write(flash, nvram_pos, 4, &msr_data.lo);
  nvram_pos += 4;
  flash->write(flash, nvram_pos, 4, &msr_data.hi);
  nvram_pos += 4;
Add a function write_mtrr to do this.

Change-Id: Id6464e637db1758b07ac2d79d3be1375a8d49651
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3410
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 01:17:22 +02:00
Siyuan Wang d2ae6ae789 AMD Thatcher: fix issue 'S3 fails to suspend after wake up from USB keyboard'
This issue can be reproduced in Linux by the following steps:
1) use pm-suspend to suspend.
2) use USB keyboard to wake up.
3) use pm-suspend to suspend. FAIL To SUSPEND.

The cause of this issue is:
USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
but this bit is not clear after wake up. So OS thinks there is a
wake up signal and wake up immediately.

In this patch, I add AcpiGpe0Blk using MMIO access and write 1
on bit 11. Write 1 to clear as spec says.
I have tested on Thatcher

The same change was done for AMD Parmer in commit »AMD Parmer:
fix issue 'S3 fails to suspend after wake up from USB keyboard'
(03901124) [1].

[1] http://review.coreboot.org/#/c/3347/
    (Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1)

Change-Id: Iaef39237497ef896d0f186e8f5522222c0ce6cb7
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3374
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 01:15:35 +02:00
Kyösti Mälkki 59d0d159f4 AMD: Kconfig cleanup
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-13 01:08:12 +02:00
Vladimir Serbinenko 22dcdd914c Add support for Intel Nehalem CPU
Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3395
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 00:32:01 +02:00
Stefan Reinauer 3a09179f46 Revert "Add support for Intel Ibex Peak (Mobile 5) southbridge"
This reverts commit 0210119b4b

Change-Id: I5be3f2a54394c592650a0dcd671e4a72ae796cb2
Reviewed-on: http://review.coreboot.org/3443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-13 00:27:07 +02:00
Stefan Reinauer 0210119b4b Add support for Intel Ibex Peak (Mobile 5) southbridge
Change-Id: If56f2cacc5f1b2ef9c7b6aea508d458a43dd1309
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3397
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:31:04 +02:00
Vladimir Serbinenko 26419285bf Avoid tripping overheat alarm on X201 before ME boots
Until ME boots (which takes seconds on X201) the reported temperature
is 128 °C which triggers Linux overheat alarm which shuts down.
Pretend temperature is 40°C until ME boots.

Change-Id: Ia49fa03c6eb27f539a23711f2c8ebfde72b1dc18
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3404
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:29:51 +02:00
Vladimir Serbinenko fe50d0bcfe Make acpi/ec.c usable in romstage
On X201 to enable EHCI debug you need to go through EC if USB power is
disabled so we need to inclue ec.c.

Change-Id: I8f8b7de639ecaebceaa53cd338136befaeec8214
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3405
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:29:07 +02:00
Vladimir Serbinenko 7d1ebbff5a Radio and dock support in EC on X60 and X201
Enable UMTS on Lenovo X60 and X201.
Enable radios if no options are available.
Enable dock on Lenovo X201.

Based on my X201 branch.

Change-Id: I6e8d3bbd6a6b1a8e59473dd5cc8125a1583d75df
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/3377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:28:25 +02:00
David Hendricks 942e69dea1 am335x: Add struct `am335x_uart` for uart registers
Add a struct for referencing UART registers. The layout is quite
strange on this chip, as the entire register space can take on three
different meanings depending on the line control settings (in the LCR
register) And to make things more confusing, some offsets reference
different registers depending on if a read or a write operation is
used.

Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3319
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:25:11 +02:00
Kyösti Mälkki b7d7cfbb30 usbdebug: Quirk for board aopen/dxplplusu
This ancient board with Intel e7505 invalidates cache while it does HW
scrubbing for ECC in romstage. This breaks usbdebug console and prevents
system from booting.

If both EARLY_CONSOLE and USBDEBUG are selected, skip ECC scrubbing under
these rare conditions to boot system.

Change-Id: I6cb43bf69af54119f4a582dcaf498dd941d4c62d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3385
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-12 05:22:46 +02:00
Kyösti Mälkki 5272a5feb7 usbdebug: Drop printk within console_init()
In case with EARLY_CONSOLE, this printk is called before any other
console is configured to transmit data. This outputs garbage on
CONSOLE_SERIAL as baudrate is not yet programmed.

For case without EARLY_CONSOLE, the order in which different console
drivers initialize is obscure. Might sometimes work properly.

Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3384
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12 05:20:54 +02:00
Kyösti Mälkki 1b7fd08ca1 usbdebug: Improve solving EHCI debug port problems
Add comment how one can debug the usbdebug hardware init.
Do not send printk's to usbdebug console when one is debugging
the usbdebug console initialisation itself.

Change-Id: I21a285cb31cf64e853bc626f8b6a617bc5a8be19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3382
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12 05:20:04 +02:00
Kyösti Mälkki 8351243e4a Fix i82801a/b/c/d IOAPIC
Setting IRQ delivery to FSB got lost in the rebase process
for commit e6143531.

I captured following error on dmesg and this patch fixes it for
i82801dx.

..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
..MP-BIOS bug: 8254 timer not connected to IO-APIC
...trying to set up timer (IRQ0) through the 8259A ...
..... (found apic 0 pin 2) ...
....... failed.
...trying to set up timer as Virtual Wire IRQ...
..... works.

Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3371
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-12 05:19:39 +02:00
Konstantin Aladyshev 07c3fc089c intel/*/smi.c: Output correct GPIO in ALT_GP_SMI_STS register dump
Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to
GPIO0.

Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/3436
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-12 01:54:19 +02:00
Paul Menzel 550f726d40 intel/bd82x6x/Makefile.inc: Revert duplicate addition of `usb_debug.c`
Currently in Intel BD82x6x southbridge’s `Makefile.inc` the
file `usb_debug.c` is added twice to the build.

This was introduced in

    commit 4063ede3fb
    Author: Ronald G. Minnich <rminnich@google.com>
    Date:   Mon Feb 4 20:31:51 2013 -0800

        bd82x6x: Fix compiling with USB debug port support

        Reviewed-on: http://review.coreboot.org/2784

but was unneeded because it had been already added in
the following commit.

    commit 4141993536
    Author: Sven Schnelle <svens@stackframe.org>
    Date:   Sat Jul 28 08:52:44 2012 +0200

        bd82x6x: Fix CONFIG_USBDEBUG

        Reviewed-on: http://review.coreboot.org/1376

Therefore basically revert that hunk.

There is no policy on how to order these additions, so leave
it to a possible separate commit, unifying this.

Kyösti Mälkki suspects that these additions were meant for
the Intel Lynx Point [1].

[1] http://review.coreboot.org/#/c/3424/

Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11 20:06:46 +02:00
Konstantin Aladyshev 62f8083dfd Fix cycle error in intel southbridges to display GPI status
Fix obvious mistake in cycle that displays GPI status
I hope i found all duplicates of it.

Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/3435
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11 20:04:03 +02:00
Gabe Black 6e5c86ff7d am335x: Revert how the header load size is calculated to an earlier method.
The current method will treat hex values as 0 and would calculate the wrong
size. This change switches back to an earlier method which used shell syntax
to add the offset and size.

Change-Id: I9fb2d9b323f113cc56a5ad2e38b47d2d22084f08
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3432
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-11 05:20:47 +02:00
Nico Huber 73b7632ad4 winbond/w83627dhg: Add ACPI support
This is loosely based on Christoph Grenz' ACPI code for the W83627HF
and makes use of the PnP super i/o ACPI framework.

Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3288
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11 00:14:00 +02:00
Nico Huber ae7c96889f Start ACPI framework for PnP (super i/o) devices
I'm trying to make writing ACPI code for super i/o devices more
comfortable.

pnp.asl hosts some general cpp macros.

The other four files are to be included in dsdt trees. They are
controlled by cpp macros which should be defined/undefined before
inclusion.

Work was inspired by Christoph Grenz' ACPI code for the W83627HF.

Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3286
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-11 00:13:31 +02:00
Gabe Black 1ef5ff2770 am335x: Make the iROM load only the bootblock and ROM stage.
The bootblock and ROM stages are the only ones that are really required to be
loaded in the quite limited on chip RAM during startup. Rather than load the
whole image which requires everything to be small, load just the bootblock and
the ROM stage, allowing the rest of the image to be arbitrarily large. Loading
a minimal amount of stuff should also improve boot performance a little bit.

Change-Id: I2fede63b8d3d8f0d880e4a692ae423021f8232b6
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3421
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-11 00:03:10 +02:00
Gabe Black 437a1e67a3 beaglebone: Expand "ROM" size to 4MB.
Now that the ROM size is decoupled from the size of the on chip RAM,
it's size is now only constrained by the size of the medium it's loaded
from and the memory it's being loaded into, probably GBs in both cases.
Making it 4MB is a reasonable compromise between giving the payload lots
of breathing room and wasting space on the source medium which won't be
used.

Change-Id: I80932e0d4ce2dad02c3879345382e7d6ba44503a
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3422
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 23:13:48 +02:00
Gabe Black 7cb57a1c30 beaglebone: Force on every other user LED to show that coreboot is running.
Until we get serial working, this is a good way to show that coreboot is
running. It can be removed once we have better methods.

Change-Id: I62d25e52aa88a97aba4c959538d680b67a0bbbb2
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3329
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 23:13:02 +02:00
Alexandru Gagniuc 560433b493 VX900: Use MIN/MAX from stdlib.h instead of redefining them
Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3431
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-10 23:11:48 +02:00
Alexandru Gagniuc 37a8a8bd9e Add support for VIA EPIA-M850 board
EPIA-M850 can now boot linux. For a list of issues, see:
http://www.coreboot.org/VIA_EPIA-M850

That's all folks.

Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1228
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 23:00:53 +02:00
Alexandru Gagniuc 23211b0200 VIA VX900: Add minimal ramstage needed to boot linux
This is the minimal code needed to get past ramstage, load SeaBIOS, jump
to GRUB2, and boot linux (or load memtest). See individual source files for
the status of each individual component.

Change-Id: Ib7d5d7593c945f18af2c2fc5e0ae689ba66131a2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3419
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:58:21 +02:00
Alexandru Gagniuc 7d31e7c138 VX900: Add DDR3 initialization
The VX900 can be connected to either DDR2 or DDR3. On my board, it is
DDR3, hence why there is no and will be no DDR2 code from my side.

This is the raminit for DDR3 dimms for the VX900. I like the term
"raminit" better than "memory training". This is a device, not a dog.

What works and what doesn't is documented in the code. It does not
make sense to hide that information in a commit message.

Change-Id: Ib2ebc10e6d4d22d0a937fe9e895c17ce79153c88
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3417
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:56:06 +02:00
Alexandru Gagniuc 5239ba2f8f ramtest.c: Add silent ram_check
In some cases, we want a ram_check that does not die and does not
clobber the terminal with useless output that slows us down a lot.
Usage examples include Checking if the RAM is up at the start of
raminit, or checking if each rank is accessible as it is being
initialized.

As with all other ram_checks, this is more of a "Is my DRAM properly
configured?" test, which is exactly what we want for something to use
during memory initialization.

Change-Id: I95d8d9a2ce1e29c74ef97b90aba0773f88ae832c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3416
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:30:39 +02:00
Alexandru Gagniuc 88a302346f VX900: Add support for early romstage
Add support for VX900 early initialization up until, but not including
raminit. Add the basic infrastructure, add a romstrap table, and
functionality to configure the CPU bus and SMBus.

This code is necessary and sufficient to prepare us for raminit.

Change-Id: Icc9c41e4927b589f17416836f87a6a5843b24aa7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3372
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 22:30:04 +02:00
Alexandru Gagniuc ee2bc27dc5 early_smbus: Add early SMBus implementation for VIA chipsets
Add a common implementation of SMBus functionality for early chipsets. Note
however, that existing via chipsets are not ported to this code. Porting
will require hardware testing to make sure everything is fine.

This code is used in the VIA VX900 branch.

Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/144
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 19:07:26 +02:00
Gabe Black ddbfc645c2 am335x: Build an omap style header and an image with it at the front.
Loading on an OMAP SOC requires that the first sector of the image have a
configuration header, and, when not an execute in place image, an additional
header which describes how big the image is and where it should be loaded.
This change adds some infrastructure to statically build that header using C
code, and to paste the header onto the front of coreboot.rom in a new top
level target file called MLO.

The configuration header we're using is as inert as possible, in line with
what U-Boot is doing. I think it could be used to give additional
configuration parameters to the built-in ROM on the SOC, but we don't need to
do that, and there didn't seem to be any actual documentation how to do that.
Because the header is built from C and is defined per CPU, it would be
possible to include extra settings in other CPUs if desired.

Adding a new top level build target is a bit disruptive, but should be
contained to the am335x directory and not interfere with other mainboards.

Change-Id: I06d346a4050c20963b3c7c6e8a152070bf2d145a
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3332
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-10 17:53:50 +02:00
Gabe Black b7d81e05bb ARM: Put the ROM stage into the image before other bits.
On ARM, there's frequently some firmware built into the SOC which runs
first and which loads other firmware like Coreboot from some other
media. To prevent the bootblock from having to know how to find and load
the ROM stage from what may be a complicated source (sd card,
netbooting, etc.), we can put the ROM stage immediately after the
bootblock and ensure that they're both loaded at the same time.

This change adjusts the Makefile.inc for ARM so that the ROM stage is put
into the image before any other files so that we know it comes first.
This changes the behavior of the CONFIG_UPDATE_IMAGE config option used
by abuild, although it's not entirely clear whether that's still used.

Change-Id: I832386243788156db5f5abbc9760a4e2026cf2cd
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3420
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-06-10 17:52:15 +02:00
Christian Gmeiner 1990ab9f15 OT200: bring LEDs into a defined state
Keep in mind that we can _NOT_ read back the current state
of the LEDS as some crazy FPGA designer wanted it that way.

Change-Id: I5cd1ac598072318b3234d1ec35a79271655b46ac
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3271
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-06-10 08:45:50 +02:00
Siyuan Wang 641f00ce64 fam15 vendorcode: Change license to BSD from AMD software license
fam15 vendorcode (src/vendorcode/amd/agesa/f15tn) was licensed under the
AMD software license agreement. Change this license to 3-clause BSD.

Change-Id: I7cab09bb58ef7cd24602628e2278672d577214a2
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3414
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-09 17:37:16 +02:00
Kyösti Mälkki ecbc0c5cb9 usbdebug: Fix use without EARLY_CONSOLE
If EARLY_CONSOLE is not selected, the PCI function for EHCI
host controller must be configured in ramstage instead.

Change-Id: I20f7569f79484c744bc413450bfa139052f3580f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-07 09:50:12 +02:00
Denis 'GNUtoo' Carikli 4062f179a7 Lenovo X60: Add int15 handler
Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL,
  The VGA option rom doesn't init the right display:
  it initializes the external display, where we have
  a black scren(with backlight on).

This commit is based on the code of mainboard.c in
  src/mainboard/roda/rk886ex.

Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3265
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-06-07 02:49:31 +02:00
Denis 'GNUtoo' Carikli 7ed739445b i945: Add Display defines for int15h handler.
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3306
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-07 02:49:06 +02:00
Gerd Hoffmann 8130b1ec1b qemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpi
First copy over from SeaBIOS git repo, then adapt for coreboot:

Disable cpu/pci hotplug bits.  Disable dynamic pci window.
Both depend on stuff in the SSDT tables created by SeaBIOS.

Bits are left in, but deactivated via #if 0, so it's easier
to see the differences when diffing the coreboot tables with
the SeaBIOS tables.

Adapt dsdt DefinitionBlock.

Enable acpi table generation in acpi_tables.c.

With this patch linux boots successfully with ACPI enabled.
It's not bug-free though.  Missing cpu detection leads to
funky messages like this one:

  weird, boot CPU (#0) not listed by the BIOS.

and SMP most likely wouldn't work either.

Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3342
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-06-06 21:31:51 +02:00
Nico Huber 7bb02512d9 ec/acpi: Add ACPI methods for generic EC access
Port most of the functions found in ec/acpi/ec.c to ACPI Source Language
(ASL). These functions are used to control embedded controllers with the
standard ACPI interface (mostly through i/o ports 0x62 / 0x66).

The following methods are implemented and tested against the power
managements channels of a ITE IT8516E embedded controller:
 * WAIT_EC_SC           Wait for a bit in the EC_SC register
 * SEND_EC_COMMAND      Send one command byte to the EC_SC register
 * SEND_EC_DATA         Send one data byte to the EC_DATA register
 * RECV_EC_DATA         Read one byte of data from the EC_DATA register
 * EC_READ              Read one byte from ec memory (through cmd 0x80)
 * EC_WRITE             Write one byte to ec memory (through cmd 0x81)

To use the provided methods, one should include `ec/acpi/ec.asl` in the
EC device code. Prior doing so, two macros should be defined to identify
the used i/o ports:
 * EC_SC_IO     I/o address of the EC_SC register
 * EC_DATA_IO   I/o address of the EC_DATA register

Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3285
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-06-06 21:19:28 +02:00
Bruce Griffith e1cddc1278 AMD Trinity: Remove unnecessary lookup table copy
The DDI connector table and the PCIe Port List lookup table are
copied onto HEAP.  This copy is not needed since these are lookup
tables used to define the platform configuration.

Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:59:59 +02:00
Bruce Griffith 283ba78415 AGESA: Add "const" modifier to function parameters
Add CONST modifiers to read-only pass-by-reference function
parameters in AGESA.  This allows the use of "const" modifiers
on the declaration of lookup tables that are pass-by-reference.
These will be used to identify tables that are copied onto the
HEAP but don't need to be.

Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:59:43 +02:00
Gerd Hoffmann aa588e0273 qemu: wind up new cpu chip
Add boot cpu to the device tree.  Figure the number of CPUs installed
(using the qemu firmware config interface) and add cpu devices for them,
so they show up in all generated BIOS tables correctly.  This gets SMP
going.

Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:52:48 +02:00
Gerd Hoffmann cbf30736b6 qemu: add x86 cpu
This patch adds a qemu x86 cpu chip.  It has no initialization function
as this isn't needed on virtual hardware.  A virtual machine can have
pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu
-cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu
which is (almost) identical to the one on the host machine.  So I've
added X86_VENDOR_ANY as wildcard match for the cpu_table.

Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:52:30 +02:00
Nico Huber a53266bee0 ec/kontron/it8516e: Add it8516e EC driver
This driver communicates with the IT8516e on the Kontron KTQM77.
Since we don't know if the firmware and protocol are standard for
the chip or customized to the board, call it kontron/it8516e.

Change-Id: I7382172c6d865d60106c929124444821a07a5184
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:39:52 +02:00
Nico Huber ea6d6e8c1f intel/bd82x6x: Add option to include ethernet firmware
Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:38:41 +02:00
Patrick Georgi 4af2bb5724 intel/bd82x6x: fix building usb debug on SNB/IVB
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3389
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:34:27 +02:00
Alexandru Gagniuc 5c4645b0ee (Trivial) early_smbus: fix printsmbus macro
When I've first written this macro in 2011, the correct define for
verbose SMBus message was CONFIG_DEBUG_SMBUS_SETUP. This has since
been changed to CONFIG_DEBUG_SMBUS. I didn't catch that, and this made
the printsmbus macro always evaluate to an empty statement.

Use the proper CONFIG_DEBUG_SMBUS define. This makes printsmbus
functional again.

Change-Id: Iaf03354b179cc4a061e0b65f5b746af10f5d2b88
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3379
Tested-by: build bot (Jenkins)
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-06-06 08:52:57 +02:00
Gerd Hoffmann 3979eda571 qemu: add power management function to device tree
Needed to make 'register "gpo" = ...' work.
While being at it add comments saying which device is which.

Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3346
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:26:20 +02:00
Gerd Hoffmann 4321d60acb console: log qemu debugcon detection result
Change-Id: Ie0507475f33d029d6e8ce59f138e0e7da5156d4f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:25:34 +02:00
Gerd Hoffmann 22f01e611b console: add qemu debugcon detection
The qemu debugcon port returns 0xe9 on reads in case the device is
present.  Use that for detection and write console output to the
port only in case the device is actually present.

Change-Id: I41aabcf11845d24004e4f795dfd799822fd14646
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:24:08 +02:00
Gerd Hoffmann d7c6e444ac console: add qemu prefix to debugcon
Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:22:46 +02:00
Gerd Hoffmann 2b9620343b qemu: Initial support for the qemu firmware config interface.
qemu has a special device to pass configuration information
from qemu to the firmware.  This patch adds initial support
the interface, namely some infrastructure, detection code and
a function to query the number of CPUs.

Change-Id: I43ff5f4fbf12334a91422aa38f514a82a1d5219e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-05 17:46:14 +02:00
Paul Menzel 019f0fc2c7 Revert "Asus F2A85-M: Activate IOMMU support"
This reverts commit eed28f97b3.

For whatever reason, the dependencies were lost in Gerrit and the
commit [1] was submitted without its dependencies. As a result
buidling the ASUS F2A85-M fails now [2] and therefore commits
based on this commit fail to pass the buid tests by Jenkins.

    […]
    Created CBFS image (capacity = 8387656 bytes)
        LINK       cbfs/fallback/romstage_null.debug
        CC         cbfs/fallback/coreboot_ram.debug
    coreboot-builds/asus_f2a85-m/generated/coreboot_ram.o:(.data+0x16b9c): undefined reference to `GnbIommuScratchMemoryRangeInterface'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/coreboot_ram.debug] Error 1
    make: *** Waiting for unfinished jobs....
    coreboot-builds/asus_f2a85-m/mainboard/asus/f2a85-m/buildOpts.romstage.o:(.data+0x3d8): undefined reference to `GnbIommuScratchMemoryRangeInterface'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1
    […]

Therefore revert the commit to get the tree working again and
submit this patch with its dependencies again.

[1] http://review.coreboot.org/#/c/3317/
[2] http://qa.coreboot.org/job/coreboot-gerrit/6618/testReport/junit/(root)/board/i386_asus_f2a85_m/

Change-Id: I911755884da09eb0a0651b8db07ee2a32e6eaaaa
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3373
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05 12:50:23 +02:00
Gerd Hoffmann 082d2a0ab7 qemu: fix IRQ routing setup
Do the setup for all PCI slots, not only the third.

Also remove the bogus message, as slot 3 may carry
any device, not only NICs.

This makes IRQ setup simliar to SeaBIOS.

SeaBIOS assignments (with patch for logging added,
and a bunch of pci devices for testing purposes):

    PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10
    PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10
    PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11
    PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11

Coreboot assignments without this patch:

    Assigning IRQ 11 to 0:3.0

Coreboot assignments with this patch:

    Assigning IRQ 10 to 0:1.3
    Assigning IRQ 11 to 0:3.0
    Assigning IRQ 11 to 0:4.0
    Assigning IRQ 10 to 0:5.0
    Assigning IRQ 10 to 0:6.0
    Assigning IRQ 10 to 0:1d.0
    Assigning IRQ 10 to 0:1d.1
    Assigning IRQ 11 to 0:1d.2
    Assigning IRQ 11 to 0:1d.7

Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05 12:49:00 +02:00
Denis 'GNUtoo' Carikli fd39ddd635 Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS
X86EMU_DEBUG_TIMING is needed for producing i915tool
  compatible output. So add its dependencies to the
  i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS,
  which depends on HAVE_MONOTONIC_TIMER which
  LAPIC_MONOTONIC_TIMER provides/selects.

Note that UDELAY_LAPIC is already selected by the Intel CPU.

Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3356
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 01:07:14 +02:00
Rudolf Marek eed28f97b3 Asus F2A85-M: Activate IOMMU support
Activate the IOMMU support for the Asus F2A85-M.

Add the device to `devicetree.cb`.

    $ pci -s 0.2
    […]
    00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit

    $ dmesg
    […]
    [    0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02  AMD   AMDIOMMU 00000001 AMD  00000000)
    [    0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02    AMD     ALIB 00000001 MSFT 04000000)
    [    0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD    POWERNOW 00000001 AMD  00000001)
    [    0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE   COREBOOT 0000002A CORE 0000002A)
    […]
    [    0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS
    […]
    [    0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000
    [    0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600
    [    0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000
    […]
    [    0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
    [    0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT]
    [    0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT]
    [    0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT]
    [    0.598073]  pci0000:00: >Requesting ACPI _OSC control (0x1d)
    [    0.603808]  pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d
    [    0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM
    [    0.620508] Freeing initrd memory: 14876k freed
    […]
    [    0.882674] pci 0000:00:01.0: >Boot video device
    [    0.882876] PCI: CLS 64 bytes, default 64
    [    0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features:  PreF PPR GT IA
    [    0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X
    [    0.917457] AMD-Vi: Lazy IO/TLB flushing enabled
    [    0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
    [    0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff]
    [    0.938535] LVT offset 0 assigned for vector 0x400
    [    0.943338] perf: AMD IBS detected (0x000000ff)
    [    0.948037] audit: initializing netlink socket (disabled)
    [    0.953432] type=2000 audit(1369659616.800:1): initialized
    [    0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages
    […]
    [    7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used)
    [    7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
    […]
    [    7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X
    [    7.885525] radeon 0000:00:01.0: >radeon: using MSI.
    […]
    [    8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010]
    [    8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010]
    [    8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010]
    [    8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010]
    [    8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010]
    [    8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010]
    [    8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010]
    [    8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010]
    [    8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010]
    [    8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010]
    [    8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010]
    [    8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010]
    [    8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010]
    [    8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010]
    [    8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010]
    [    8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010]
    [    8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010]
    [    8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010]
    [    8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010]
    [    8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010]
    [    8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010]
    [    8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010]
    [    8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010]
    [    8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010]
    [    8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010]
    [    8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010]
    [    8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010]
    [    8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010]
    [    8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010]
    [    8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010]
    [    8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010]
    […]
    [    8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010]
    [    8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010]
    [    8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010]
    [    8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010]
    [    8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010]
    [    8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010]
    [    8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010]
    [    8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010]
    [    8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010]
    [    8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010]
    [    8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010]
    [    8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010]
    [    8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010]
    [    8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010]
    [    8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010]
    [    8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010]
    [    8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010]
    [    8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010]
    [    8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010]
    [    8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010]
    [    8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010]
    [    8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010]
    [    8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010]
    [    8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010]
    [    8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010]
    [    8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010]
    [    8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010]
    [    8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010]
    [    8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010]
    [    8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010]
    [    8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010]
    [    8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010]
    [    8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010]
    [    8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
    [    8.963165] radeon 0000:00:01.0: >WB enabled
    […]

It is not known, what the implications of the `IO_PAGE_FAULT` are.

Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 23:49:20 +02:00
Denis 'GNUtoo' Carikli 4cdc5d6fc6 Yabel : Add tracing option needed by i915tool.
This patch was made by listenning to what Ron Minnich told
  me to do on #coreboot IRC channel on Freenode with my
  adaptations on top.

i915tool is at https://code.google.com/p/i915tool/ ,
  the one in coreboot is outdated.

Change-Id: I13cd684f4c290114836fbd7babd461153e8d6124
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 22:57:26 +02:00
Ronald G. Minnich a296ce75e3 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer
since it was defined in sandybridge. It is really
more of an x86 thing however, and we now have
three systems that can use it.

I considered making this more general, since it technically
can apply to PTE-based systems like ARM, and maybe we should.
But the 'WRCOMB' moniker is usually closely tied to the x86.

Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3349
Tested-by: build bot (Jenkins)
2013-06-04 22:36:03 +02:00
Denis 'GNUtoo' Carikli 873965e2a7 Lenovo X60: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
     # ./nvramtool -a
     boot_option = Fallback
     last_boot = Fallback
     baud_rate = 115200
     debug_level = Spew
     hyper_threading = Enable
     nmi = Enable
     boot_devices = ''
     boot_default = 0x40
     cmos_defaults_loaded = Yes
     lpt = Enable
     volume = 0xff
     tft_brightness = 0xbf
     first_battery = Primary
     bluetooth = Enable

The code for handling the invalid CMOS space in mainboard.c
  is now useless and so it was removed.

Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3335
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04 21:35:56 +02:00
Denis 'GNUtoo' Carikli 649f18f834 Asus M4A785T-M: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Enable
    baud_rate = 115200
    hw_scrubber = Enable
    interleave_chip_selects = Enable
    max_mem_clock = 400Mhz
    multi_core = Enable
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0xc
    slow_cpu = off
    nmi = Enable
    iommu = Enable
    nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04 21:34:52 +02:00
Denis 'GNUtoo' Carikli 03c66202de PC Engines ALIX.1C: Add CMOS defaults.
After Booting the BIOS, flashing coreboot
  and booting coreboot with that patch we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Disable
    baud_rate = 115200
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0x7f
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3323
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04 21:31:57 +02:00
Alexandru Gagniuc fcf2a17a86 pci_ids.h: Add PCI IDs for VIA VX900 chipset
Change-Id: I4a75326fef0a10a6290cdd4b1b93d9af8e3ab23d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3268
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-04 21:21:05 +02:00
Alexandru Gagniuc 359501a7b7 coreboot: Add generic early SMBus API
Early SMBUS code with similar functionality is duplicated for all
southbridges. Add a generic SMBus API (function declarations) designed to
unify the early SMBus structure.

This patch only adds the API. It does not implement any hardware-specific
bits.

Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/143
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 18:39:06 +02:00
Alexandru Gagniuc 78706fd61f DDR3: Add utilities for creating MRS commands
MRS commands are used to tell the DRAM chip what timing and what
termination and drive strength to use, along with other parameters.
The MRS commands are defined by the DDR3 specification [1]. This
makes MRS commands hardware-independent.

MRS command creation is duplicated in various shapes and forms in any
chipset that does DDR3. This is an effort to create a generic MRS API
that can be used with any chipset.

This is used in the VX900 branch.

[1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf

Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 18:37:53 +02:00
Alexandru Gagniuc 775551c69e VIA Nano: Add microcode updates files
While we had support for updating microcode on the VIA Nano CPUs for a
while now, we never included the actual microcode. Unlike, Intel and
AMD CPUs, VIA microcode is not available for download, and was
extracted from the vendor BIOS. It was not included in coreboot since
we never had explicit permission to do so. I have just received
confirmation from VIA that we can distribute the microcode.

Change-Id: I4c15b090cd2713cfe5dc6b50db777ff89dbc0f19
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3357
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-06-04 18:02:11 +02:00
Christian Gmeiner 7bc3575458 AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:48 +02:00
Christian Gmeiner c4e07bb503 AMD Northbridge LX: convert spd_read_byte() to non-static version
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:35 +02:00
Christian Gmeiner 4eb5aa2894 AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"
Move the include before static inline int spd_read_byte().

Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:03 +02:00
Christian Gmeiner e2dc80ceac AMD Northbridge LX: rename get_systop() to get_top_of_ram()
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3367
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:45 +02:00
Christian Gmeiner 84ae76caf8 AMD Northbridge LX: include northbridge.h in raminit.c
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3365
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:15 +02:00
Christian Gmeiner 194ec4d4d5 AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:56 +02:00
Christian Gmeiner 6f9f785d9b AMD Northbridge LX: add some missing includes
This commit fixes problems if we build raminit.c
for romstage.

Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3363
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:27 +02:00
Christian Gmeiner eb6322f4b0 AMD Northbridge LX: make sdram_* function prototypes non-static
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c"
line we need to do some prepartion steps. This commit is one of them.

Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3362
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:53:57 +02:00
Siyuan Wang 29840e234c AMD Fam 15tn: Use all memory on systems with more than 4 GB
Take a Parmer board with 4G memory as an example.

Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
Parmer uses 512M as video memory when it has 4G.
3327540+512*1024 = 3851828(kB), so some memory is lost.

When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
0x00000001. But in e820 table or coreboot table, the last item is

    6: 0000000100000000 - 0000000118000000 = 1 RAM

This is not correct, it should be

    6: 0000000100000000 - 000000011f000000 = 1 RAM

This patch changes the memory layout when TOM2 is set.

Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:48:47 +02:00
Alexandru Gagniuc f97ff3f72c dram: Add utilities for decoding DDR3 SPDs
Add convenience utilities for decoding DDR3 SPDs and printing the
information to the console. These have proven invaluable when writing the
VX900 memory initialization.

These are used in the VX900 branch

Information printed has the following format:

> SPD Data for DIMM 51
>   Revision: 10
>   Type    : b
>   Key     : 2
>   Banks   : 8
>   Capacity: 1 Gb
>   Supported voltages: 1.5V
>   SDRAM width       : 8
>   Bus extension     : 0 bits
>   Bus width         : 64
>   Optional features : DLL-Off_mode RZQ/7 RZQ/6
>   Thermal features  : ASR ext_temp_range
>   Thermal sensor    : no
>   Standard SDRAM    : no
>   Row    addr bits  : 13
>   Column addr bits  : 10
>   Number of ranks   : 1
>   DIMM Capacity     : 1024 MB
>   CAS latencies     : 6 7 8 9
>   tCKmin            :   1.500 ns
>   tAAmin            :  13.125 ns
>   tWRmin            :  15.000 ns
>   tRCDmin           :  13.125 ns
>   tRRDmin           :   6.000 ns
>   tRPmin            :  13.125 ns
>   tRASmin           :  36.000 ns
>   tRCmin            :  49.125 ns
>   tRFCmin           : 110.000 ns
>   tWTRmin           :   7.500 ns
>   tRTPmin           :   7.500 ns
>   tFAWmin           :  30.000 ns

Change-Id: I30725a75caf74ac637db0a143344562bd9910466
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3267
Tested-by: build bot (Jenkins)
2013-06-03 22:35:37 +02:00
Alexandru Gagniuc 32610462d1 spd.h: Add all known SPD_MEMORY_TYPE definitions.
This file was missing some definitions, so add them. Also turn the defines
into an enum. The reason for doing this is that functions can now
explicitly take an spd_memory_type as a parameter:

> int do_something_with_dram(enum spd_memory_type type, ...)

Which is a lot more explicit and readable than:

> int do_something_with_dram(u8 type, ...)

These are used in the VX900 branch.

Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3266
Tested-by: build bot (Jenkins)
2013-06-03 22:35:21 +02:00
Paul Menzel 8048e740a3 include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines
Probably due to different (character) widths for a tab, sometimes only
one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For
the “correct” alignment, that means where a tab is eight characters,
two tabs are necessary. Change it accordingly.

Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3263
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03 18:03:42 +02:00
Rudolf Marek 1b22827cf0 Asus F2A85-M: Fix the _CRS PCI0 bus info
On Asus F2A85-M, the Linux kernel complains that the _CRS method does
not specify the number of PCI busses.

    [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS

Just put there 256. This should be part of re-factoring of the whole
ACPI stuff.

The same change was already done for the AMD Brazos (SB800) boards,
based on commit »Persimmon DSDT: Add secondary bus range to PCI0«
(4733c647) [1].

[1] http://review.coreboot.org/2592

Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3320
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-03 17:50:24 +02:00
Christian Gmeiner 01c095ff4c AMD Geode CS5536: downgrade BIOS_ERR
There is no need to use everywhere BIOS_ERR.

Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3307
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03 17:47:06 +02:00
Gerd Hoffmann 038aa29dc2 console: add support for QEMU's debugcon
Add support for sending debug output to an I/O port.

It can be used together with QEMU's isa-debugcon driver to log the
coreboot output to a file.  The port is configurable and defaults
to 0x402 which has established as the de facto standard. For example,
SeaBIOS+OVMF [1] use that one too.

[1] http://www.linux-kvm.org/page/OVMF
    Open Virtual Machine Firmware
Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3331
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03 17:32:31 +02:00
Aaron Durbin 66da043e48 haswell: allow for disabled hyperthreading
There were assumptions being made in the haswell
MP and SMM code which assumed the APIC id space
was 1:1 w.r.t. cpu number. When hyperthreading is
disabled the APIC ids of the logical processors
are all even. That means the APIC id space is sparse.
Handle this situation.

Change-Id: Ibe79ab156c0a171208a77db8a252aa5b73205d6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3353
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03 17:30:48 +02:00
Aaron Durbin 27435d3bcd haswell: fix overflow handling TOUUD
It's possible that the TOUUD can be set to less than
4GiB. When that is the case the size_k variable is
an extremely large value. Instead ensure TOUUD is greater
than 4GiB before adding said resources.

Change-Id: I456633d6210824e60665281538300fd15656b86d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3352
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03 17:30:09 +02:00
Paul Menzel 373a20c335 Intel Lynx Point: LPC: Unify I/O APIC setup
Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a41
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.

As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3182
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03 08:22:59 +02:00
Paul Menzel 9c50e6a4a0 Intel BD82x6x: LPC: Unify I/O APIC setup
Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a41
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.

As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3183
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03 08:21:54 +02:00
Paul Menzel 42409e8732 northbridge/amd/amdmct: Use `static const` instead of `const static`
From ISO C99 standard: »The placement of a storage-class specifier
other than at the beginning of the declaration specifiers in a
declaration is an obsolescent feature.«

Found at <http://www.approxion.com/?p=41>.

The following command was used to make the change.

    $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/'

As asked by Bruce Griffith, the changes in `src/vendorcode` were
reverted as that is what AMD prefers.

The same change was done already for AMD Persimmon in the following
commit.

    commit 824e192809
    Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Date:   Wed Feb 20 21:24:20 2013 +0100

        Persimmon: platform_cfg.h: Declare codec arrays as `static const`

        Reviewed-on: http://review.coreboot.org/2474

Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3197
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03 08:20:54 +02:00
Gabe Black 3aa58162e1 am335x: Clean up/fix some settings in the am335x Kconfig.
Some settings in the am335x Kconfig weren't actually used for anything, some
where place holders, and some where left over from another CPU. The memory
addresses are in the internal RAM in the SOC as described in the reference
manual. The stack is put where the internal ROM had its stack, and the
bootblock is put at the bottom of that region as the manual suggests. The
ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the
bootblock currently takes up.

Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3327
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-06-03 03:10:17 +02:00
Denis 'GNUtoo' Carikli 29a4355973 Provide sane Kconfig default for cmos.default.
Without that fix we have with CONFIG_USE_OPTION_TABLE:

    OPTION     cmos_layout.bin
  build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin
  make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'.  Stop.
  rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c

That log was captured with make V=1 but the error also appear with make.

Tested on the PC Engines ALIX.1C with the following commit (Change-Id: Ia87b090) [1]:

  PC Engines ALIX.1C: Add CMOS defaults.

[1] http://review.coreboot.org/#/c/3323/

Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3223
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-06-02 23:07:22 +02:00
Denis 'GNUtoo' Carikli 8977b6ac5c Lenovo ThinkPad X60: cleanup Native VGA init.
Change-Id: Iaefa23a6257fd0295357465eb03ccadbef0f70da
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3272
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31 18:57:42 +02:00
Steven Sherk 474eeedbc8 AMD Trinity boards: Add reserved memory area for SPI base address in ACPI
- SPI controller base address gets overwritten by SD controller under Linux.

    - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't
      get automatically reserved. Solution is to add it as a reserved memory area in
      ACPI.

    - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this
      platform was made as part of: http://review.coreboot.org/#/c/3167/3

    - Once approved a follow-on patch for other southbridges using a non-standard BAR for
      the spi controller.

Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3270
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31 18:17:49 +02:00
Siyuan Wang 0390112407 AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'
This issue can be reproduced in Linux by the following steps:
1) use pm-suspend to suspend.
2) use USB keyboard to wake up.
3) use pm-suspend to suspend. FAIL To SUSPEND.

The cause of this issue is:
USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
but this bit is not clear after wake up. So OS thinks there is a
wake up signal and wake up immediately.

In this patch, I add AcpiGpe0Blk using MMIO access and write 1
on bit 11. I have tested on Parmer.

Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3347
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31 17:50:53 +02:00
Paul Menzel d189229b45 AMD Llano, Brazos boards: Use `sizeof(var)` to get its size
Change `sizeof(type) * n`, where n is the number of array
elements, to `sizeof(variable)` to directly get the size of the
variable (struct, array). Determining the size by counting array
elements is error prone and unnecessary.

Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe
config« [1] contains the same change and is ported over. In
the commit message Rudolf makes the following comment.

»Not sure why the copy is needed instead of direct reference.
Maybe it has something to do with CAR?«

Testing on the ASRock E350M1, no regressions were noticed.

[1] http://review.coreboot.org/#/c/3194/

Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3248
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-30 18:10:45 +02:00
Rudolf Marek d3ed411123 AMD Trinity boards: Use `sizeof(var)` to get its size
Change `sizeof(type) * n`, where n is the number of array
elements, to `sizeof(variable)` to directly get the size of the
variable (struct, array). Determining the size by counting array
elements is error prone and unnecessary.

Not sure why the copy is needed instead of direct reference.
Maybe it has something to do with CAR?

These changes are based on Rudolf’s original patch »ASUS F2A85-M:
Correct and clean up PCIe config« [1], where it was just done for
the ASUS board.

[1] http://review.coreboot.org/#/c/3194/

Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3247
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-30 18:04:52 +02:00
Gerd Hoffmann 1a71f4c21f qemu: remove vga hook
Extra care for the qemu vga should not be needed any more.
Since release 0.12 qemu loads the vgabios into the PCI ROM
bar, so everything works exactly like it does on real hardware.

Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29 18:19:23 +02:00
Christian Gmeiner c4fd2973ab cpu/amd/geode_lx/Kconfig: Select TSC_MONOTONIC_TIMER
The following is an excerpt from serial log of the Bachmann OT200.

$ grep usec coreboot_log
clocks_per_usec: 500
Root Device init 48034 usecs
CPU_CLUSTER: 0 init 133251 usecs
PCI: 00:01.0 init 33376 usecs
PCI: 00:01.1 init 9930 usecs
PCI: 00:01.2 init 9929 usecs
PCI: 00:04.0 init 9929 usecs
PCI: 00:0f.0 init 185788 usecs
PCI: 00:0f.2 init 21473 usecs
PCI: 00:0f.3 init 9930 usecs
PCI: 00:0f.4 init 9930 usecs
PCI: 00:0f.5 init 9930 usecs
PCI: 00:0f.6 init 9930 usecs
PCI: 00:0f.7 init 9929 usecs

Change-Id: I4d0805c4cf8fcb25ec107615787fc6da0c945a30
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3308
Tested-by: build bot (Jenkins)
2013-05-29 09:22:42 +02:00
Gabe Black 3c7e939c3e beaglebone: initial Kconfig and Makefiles
Initial structure of Beaglebone port

Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26 18:19:36 +02:00
Paul Menzel ac6ea04b62 Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console
Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console
support by copying GNUtoo’s commit for the Lenovo ThinkPad X60.

    commit 4560ca5003
    Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Date:   Fri Apr 26 12:21:41 2013 +0200

        Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.

        Reviewed-on: http://review.coreboot.org/3142

Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3187
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-26 18:01:22 +02:00
Gabe Black c6d1da0b18 snow: Add a name to the serial console UART choice block.
This allows other boards to have the same choice block without confusing
kconfig.

Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3293
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-26 15:19:04 +02:00
Ronald G. Minnich 5750fddcba Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
multiply_to_tsc was being copied everywhere, which is bad
practice. Put it in the tsc.h include file where it belongs.
Delete the copies of it.

Per secunet, no copyright notice is needed.

This might be a good time to get a copyright notice into tsc.h
anyway.

Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3242
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-25 14:22:06 +02:00
Paul Menzel 60c54cc017 cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER
Thanks to Aaron Durbin coreboot provides monotonic timers. Select
the LAPIC monotonic timer for the AMD AGESA CPUs.

The following is an excerpt from serial log of the ASRock E350M1.

    $ grep usec seriallog-20130502_100902.log
    01.016: Root Device init 1578 usecs
    01.029: CPU_CLUSTER: 0 init 112415 usecs
    01.029: PCI: 00:00.0 init 3240 usecs
    01.088: PCI: 00:01.0 init 104572 usecs
    01.088: PCI: 00:01.1 init 1663 usecs
    01.088: PCI: 00:11.0 init 1662 usecs
    01.088: PCI: 00:14.0 init 1662 usecs
    01.088: PCI: 00:14.3 init 8665 usecs
    01.088: PCI: 00:14.4 init 1665 usecs
    01.088: PCI: 00:18.0 init 1662 usecs
    01.088: PCI: 00:18.1 init 1663 usecs
    01.088: PCI: 00:18.2 init 1663 usecs
    01.088: PCI: 00:18.3 init 1663 usecs
    01.088: PCI: 00:18.4 init 1663 usecs
    01.088: PCI: 00:18.5 init 1665 usecs
    01.088: PCI: 00:18.6 init 1664 usecs
    01.088: PCI: 00:18.7 init 1663 usecs
    01.088: PNP: 002e.2 init 1576 usecs
    01.088: PNP: 002e.5 init 1577 usecs
    01.088: PNP: 002e.a init 1590 usecs
    01.088: PNP: 002e.b init 30144 usecs
    01.088: PCI: 03:00.0 init 1663 usecs

So the graphics device needs around 100 ms for being initialized.

The full serial log is in the Gerrit comments.

Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3172
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-05-24 08:11:57 +02:00
Paul Menzel 4e01cfb6d5 cpu/intel/haswell/Kconfig: Intend help text with two spaces
Commit »haswell: 24MHz monotonic time implementation« (c46cc6f1) [1]
added the Kconfig variable `MONOTONIC_TIMER_MSR` with a help text,
but only used one space instead of the suggested two spaces for
indentation. So add one space.

»Lines under a "config" definition are indented with one tab, while
help text is indented an additional two spaces.« [2]

[1] http://review.coreboot.org/3153
[2] https://www.kernel.org/doc/Documentation/CodingStyle
    (Chapter 10: Kconfig configuration files)

Change-Id: I39cf356bfd54c66a2f1b837c6667dcc915e41f29
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3262
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-24 07:57:33 +02:00
Paul Menzel 87b9bf5bad include/timer.h: Fix typo in in*iti*alize in comment
Correct a typo in a comment introduced in commit »coreboot:
introduce monotonic timer API« (a421791d) [1].

[1] http://review.coreboot.org/3152

Change-Id: Ia0abc5304547d419478db1ae37b5525406fa19cc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-23 20:17:37 +02:00
Paul Menzel 51837f9dac Intel Sandy Bridge: udelay.c: Change comparison from <= to <
Currently code in `udelay.c` differs between the Intel northbridges
GM45, 945 on the one hand and Sandy Bridge on the other hand.

The reason for this is that a wrong comparison > was used.

The following commit

    commit 784ffb3db6
    Author: Sven Schnelle <svens@stackframe.org>
    Date:   Tue Jan 10 12:16:38 2012 +0100

        i945: fix tsc udelay()

        Reviewed-on: http://review.coreboot.org/530

fixed the sign from > to <, whereas Stefan Reinauer changed it from
> to <= before adding the Sandy Bridge port in the following commit.

    commit 00636b0dae
    Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Date:   Wed Apr 4 00:08:51 2012 +0200

        Add support for Intel Sandybridge CPU (northbridge part)

        Reviewed-on: http://review.coreboot.org/854

As there are no technical reasons for this difference, unify this
between the chipsets. See the discussion of the other patch set in
Gerrit [1].

[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c

Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3259
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-23 10:44:36 +02:00
Paul Menzel 1e24f4b37f Kconfig: Remove duplicate entry for `USE_OPTION_TABLE`
The following commit

    commit eb50c7d922
    Author: Edwin Beasant <edwin_beasant@virtensys.com>
    Date:   Tue Jul 6 21:05:04 2010 +0000

    Re-integrate "USE_OPTION_TABLE" code.

added a duplicate entry `config USE_OPTION_TABLE`. Remove it again.

Change-Id: I3ff64c360bad531439e74fa1b25a06c4a447a33f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3165
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-23 10:42:41 +02:00
Nico Huber 393619b9a6 intel/gm45: Add more debug output to read/write training
Add debug output for the timing values of the edges found during
read and write training.

Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:

[...]
Lower bound for byte lane 0 on channel 0: 0.0
Upper bound for byte lane 0 on channel 0: 8.4
Final timings for byte lane 0 on channel 0: 4.2
Lower bound for byte lane 1 on channel 0: 0.0
Upper bound for byte lane 1 on channel 0: 10.2
Final timings for byte lane 1 on channel 0: 5.1
Lower bound for byte lane 2 on channel 0: 0.0
Upper bound for byte lane 2 on channel 0: 7.5
Final timings for byte lane 2 on channel 0: 3.6
Lower bound for byte lane 3 on channel 0: 0.0
Upper bound for byte lane 3 on channel 0: 11.4
Final timings for byte lane 3 on channel 0: 5.6
Lower bound for byte lane 4 on channel 0: 0.0
Upper bound for byte lane 4 on channel 0: 9.4
Final timings for byte lane 4 on channel 0: 4.6
Lower bound for byte lane 5 on channel 0: 0.0
Upper bound for byte lane 5 on channel 0: 11.2
Final timings for byte lane 5 on channel 0: 5.5
Lower bound for byte lane 6 on channel 0: 0.0
Upper bound for byte lane 6 on channel 0: 8.4
Final timings for byte lane 6 on channel 0: 4.2
Lower bound for byte lane 7 on channel 0: 0.0
Upper bound for byte lane 7 on channel 0: 10.4
Final timings for byte lane 7 on channel 0: 5.2
Lower bound for group 0 on channel 0: 1.7.5
Upper bound for group 0 on channel 0: 2.2.2
Final timings for group 0 on channel 0: 1.10.7
Lower bound for group 1 on channel 0: 1.6.1
Upper bound for group 1 on channel 0: 2.0.2
Final timings for group 1 on channel 0: 1.9.1
Lower bound for group 2 on channel 0: 2.0.7
Upper bound for group 2 on channel 0: 2.8.1
Final timings for group 2 on channel 0: 2.4.4
Lower bound for group 3 on channel 0: 2.4.7
Upper bound for group 3 on channel 0: 3.0.0
Final timings for group 3 on channel 0: 2.8.3
[...]

Final timings are always the average of the two bounds. The last dots
separate eights (not decimals) and the middles are elenvenths or twelfths
depending on the clock speed (twelfths in this case).

Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:07:22 +02:00
Nico Huber 12276acfd7 intel/gm45: Handle overflows during DDR3 write training
We halted the machine on any overflow during the write training.
However, overflows during the search for a good to bad edge are
non-fatal, and should be ignored.

Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3256
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:05:34 +02:00
Nico Huber 08bee23f7e intel/gm45: Refactor DDR3 write training
Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3255
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:04:11 +02:00
Nico Huber 35e45c0780 intel/gm45: Handle overflows during DDR3 read training
We halted the machine on any overflow during the read training. However,
overflows during the search for a good to bad edge are non-fatal, and
should be ignored.

Change-Id: I77085840ade25bce955480689c84603334113d1f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3254
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:02:24 +02:00
Nico Huber 26a6435123 intel/gm45: Refactor DDR3 read training
Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3253
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 18:00:56 +02:00
Nico Huber 0da92863a7 intel/gm45: Fix interpretation of VT-d disable bit
When configuring the GTT size for the integrated graphics, the state
of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
_disabled_.

In the log of a VT-d enabled roda/rk9 we have now:

[...]
VT-d enabled
[...]
IGD decoded, subtracting 32M UMA and 4M GTT
[...]

Without this patch, only 2M GTT were reported.

Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-22 17:59:10 +02:00
Nico Huber 0f43af2ebb intel/i5000: Remove unused copy of udelay.c
It's a copy from i945 and looks like not beeing included in a
build at all.

If you should ever want to use that file for the Intel 5000,
please copy it from another chipset like the Intel 945 as it
is going to be improved.

Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a
Reported-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-21 17:46:02 +02:00
Paul Menzel 883b03f323 AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build
Apparently the files `smbus.{h,c}`, where never used and therefore
build beforehand. Needing one function in them for the ASUS F2A85-M
the build fails as some headers are missing. Including the headers
`stdint.h` and `io.h` fixes the following errors.

    […]
        CC         southbridge/amd/agesa/hudson/smbus.romstage.o
    In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0:
    src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8'
    src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8'
    src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay':
    src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration]
    src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration]
    […]

Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and
should be fixed. Even better, as these function do not differ
between most boards, the file should be moved out from the
specific southbridge directories.

[1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/

Change-Id: I285101fa06a365da44fa27b688c536e614d57f50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3202
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-05-20 18:34:18 +02:00
Paul Menzel b2cddd4c12 ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
Currently the code in the if statement

    if (!byte)
    	do_smbus_write_byte(0xb20, 0x15, 0x3, byte);

only gets executed if `byte == 0x0`, that means only in the
default case where RAM voltage is 1.5 Volts. But the RAM voltage
should be changed when configured for the non-default case.

So negate the predicate to alter the RAM voltage for the
non-default cases.

To prevent the build error

    OBJCOPY    cbfs/fallback/coreboot_ram.elf
    coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main':
    /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1

add `southbridge/amd/agesa/hudson/smbus.c` providing the function
`do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can
actually be used after the needed header files are included in a
previous commit.

Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6
Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3200
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-20 18:33:23 +02:00
Stefan Reinauer b0fb2234be Drop llshell
This feature has not been used and was never fully integrated.
In the progress of cleaning up coreboot, let's drop it.

Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3251
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-20 08:42:28 +02:00
Bruce Griffith d433acb816 AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
The following commit

    commit 05f3b117dd
    Author: Paul Menzel <paulepanter@users.sourceforge.net>
    Date:   Tue May 14 09:28:26 2013 +0200

        AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer

        Reviewed-on: http://review.coreboot.org/3246

changed one calculation for the size of the array PortList[] to
reflect only four elements, but neglected three additional calculations
of the size of the same table.

Correct that by setting the size for four array elements in all four
calculations.

[1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c

Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939
Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3250
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-17 18:50:23 +02:00
Paul Menzel 05f3b117dd AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
The following commit

    commit d0790694b0
    Author: Kerry Sheh <shekairui@gmail.com>
    Date:   Thu Jan 19 13:18:37 2012 +0800

        Inagua: Inagua GNB ddi lanes and pcie lanes config update

        Reviewed-on: http://review.coreboot.org/544

assigns lanes 4 and 5 to PCI device number 4, but does not
adapt the rest of the code.

After the commit above, the array `PortList []` only has four
elements, but the buffer size `AllocHeapParams.RequestedBufferSize`
is set to a size as it still has five elements.

Correct that by setting the size for four array elements.

[1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c

Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199
Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3246
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-16 06:06:50 +02:00
Aaron Durbin 5b54d353aa haswell: enable cache-as-ram migration
The haswell code allows for vboot ramstage verification.
However, that code path relies on accessing global cache-as-ram
variables after cache-as-ram is torn down. In order to avoid
that situation enable cache-as-ram migration.

cbmemc_reinit() no longer needs to be called from romstage
because it is invoked automatically by the cache-as-ram
migration infrastructure.

Change-Id: I08998dca579c167699030e1e24ea0af8802c0758
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:30:25 +02:00
Aaron Durbin 2ad6bd23a7 cbmem console: use cache-as-ram API and cleanup
Allow for automatic cache-as-ram migration for the cbmem
console. The code was refactored in the thought of making
it easier to read. The #ifdefs still exist, but they are no
longer sprinkled throughout the code. The cbmem_console_p
variable now exists globally in both romstage and ramstage.
However, the cbmem_console_p is referenced using the
cache-as-ram API. When cbmem is initialized the console
is automatically copied over by calling cbmemc_reinit()
through a callback.

Change-Id: I9f4a64e33c58b8b7318db27942e37c13804e6f2c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:30:17 +02:00
Aaron Durbin 677e1558c3 chromeos: use cache-as-ram migration API for vbnv
It's possible that the vbnv global variables may be accessed
in romstage after cache-as-ram is torn down. Therefore use
the cache-as-ram migration API. Wrappers were written to
wrap the API to keep the existing code as close as possible.

Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:30:09 +02:00
Aaron Durbin cb997d3710 pc80/tpm: allow for cache-as-ram migration
As the TPM driver can be accessed in romstage after
cache-as-ram is torn down use the cache-as-ram migration
API to dynamically determine the global variable address.

Change-Id: I149d7c130bc3677ed52282095670c07a76c34439
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:29:59 +02:00
Aaron Durbin 716738a6b8 x86: add cache-as-ram migration option
There are some boards that do a significant amount of
work after cache-as-ram is torn down but before ramstage
is loaded. For example, using vboot to verify the ramstage
is one such operation. However, there are pieces of code
that are executed that reference global variables that
are linked in the cache-as-ram region. If those variables
are referenced after cache-as-ram is torn down then the
values observed will most likely be incorrect.

Therefore provide a Kconfig option to select cache-as-ram
migration to memory using cbmem. This option is named
CAR_MIGRATION. When enabled, the address of cache-as-ram
variables may be obtained dynamically. Additionally,
when cache-as-ram migration occurs the cache-as-ram
data region for global variables is copied into cbmem.
There are also automatic callbacks for other modules
to perform their own migration, if necessary.

Change-Id: I2e77219647c2bd2b1aa845b262be3b2543f1fcb7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3232
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-16 01:29:50 +02:00
Ronald G. Minnich 4bd7b0cbad EXYNOS5250/SNOW: fix the build script. Add a script to get the bl1.
build-snow got broken when the snow makefile improved. So fix it.

While we're at it, create a script like the update-microcode
scripts that gets the bl1. I thought about making this a common
script but the various names and paths always evolve, leaving
me thinking it's not worth it. This script is just a
piece of the snow build script.

Change-Id: I65c0f8697a978c62fe12533c4f0152d14dbaefda
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3238
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-14 22:03:07 +02:00
Paul Menzel 3a1457137e AMD Fam15tn boards: BiosCallOuts.c: Declare codec arrays as `static`
These arrays are declared as `static` for AMD SB800 based boards,
so do the same for this generation.

Rudolf Marek just changed `const CODEC_TBL_LIST` to `static const`
in [1]. Adapt all Fam15tn based boards (AMD Parmer, AMD Thatcher,
ASUS F2A85-M) to keep the differences between them small.

[1] http://review.coreboot.org/#/c/3170/3/src/mainboard/asus/f2a85-m/BiosCallOuts.c

Change-Id: I353b38bd8bc77ba500a4b7fe9250e9aa3071c530
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3198
Tested-by: build bot (Jenkins)
2013-05-14 15:58:34 +02:00
Rudolf Marek cd1cef4438 AMD Fam15tn boards: Document lane ID mapping from BKDG
To make it easier to fill in the values, place the table
from the BIOS and Kernel Developer’s Guide (BKDG) [1]
as a comment.

[1] http://www.coreboot.org/Datasheets#AMD_Fam15

Change-Id: I218f76e9fa2dc88d47af51ea6c062e315afb0000
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3221
Tested-by: build bot (Jenkins)
2013-05-14 15:53:14 +02:00
Aaron Durbin 38c326d041 x86: add thread support
Thread support is added for the x86 architecture. Both
the local apic and the tsc udelay() functions have a
call to thread_yield_microseconds() so as to provide an
opportunity to run pending threads.

Change-Id: Ie39b9eb565eb189676c06645bdf2a8720fe0636a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3207
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-14 05:24:18 +02:00
Aaron Durbin 4409a5eef6 coreboot: add thread cooperative multitasking
The cooperative multitasking support allows the boot state machine
to be ran cooperatively with other threads of work. The main thread
still continues to run the boot state machine
(src/lib/hardwaremain.c).  All callbacks from the state machine are
still ran synchronously from within the main thread's context.
Without any other code added the only change to the boot sequence
when cooperative multitasking is enabled is the queueing of an idlle
thread. The idle thread is responsible for ensuring progress is made
by calling timer callbacks.

The main thread can yield to any other threads in the system. That
means that anyone that spins up a thread must ensure no shared
resources are used from 2 or more execution contexts. The support
is originally intentioned to allow for long work itesm with busy
loops to occur in parallel during a boot.

Note that the intention on when to yield a thread will be on
calls to udelay().

Change-Id: Ia4d67a38665b12ce2643474843a93babd8a40c77
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3206
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-14 05:18:47 +02:00
Paul Menzel 8c8af592ca AMD Brazos/Trinity boards: PlatformGnbPcie.c: Reserve correct amount of memory
In `PlatformGnbPcie.c` AGESA functions are used to reserve memory
space to save the PCIe configuration to. This is the

With the following definitions in `AGESA.h`

    $ more src/vendorcode/amd/agesa/f14/AGESA.h
    […]
    /// PCIe port descriptor
    typedef struct {
      IN       UINT32               Flags;                    /**< Descriptor flags
                                                               * @li @b Bit31 - last descriptor in complex
                                                               */
      IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
      IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
    } PCIe_PORT_DESCRIPTOR;

    /// DDI descriptor
    typedef struct {
      IN       UINT32               Flags;                    /**< Descriptor flags
                                                               * @li @b Bit31 - last descriptor in complex
                                                               */
      IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
      IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
    } PCIe_DDI_DESCRIPTOR;

    /// PCIe Complex descriptor
    typedef struct {
      IN       UINT32               Flags;                    /**< Descriptor flags
                                                               * @li @b Bit31 - last descriptor in topology
                                                               */
      IN       UINT32               SocketId;                 ///< Socket Id
      IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
      IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
      IN       VOID                 *Reserved;                ///< Reserved for future use
    } PCIe_COMPLEX_DESCRIPTOR;
    […]

memory has to be reserved for the `PCIe_COMPLEX_DESCRIPTOR` and,
as two struct members are pointers to arrays with elements of type
`PCIe_PORT_DESCRIPTOR` and `PCIe_DDI_DESCRIPTOR`, space for these
times the number of array elements have to be reserved:
a + b * 5 + c * 2.

      sizeof(PCIe_COMPLEX_DESCRIPTOR)
    + sizeof(PCIe_PORT_DESCRIPTOR) * 5
    + sizeof(PCIe_DDI_DESCRIPTOR) * 2;

But for whatever reason parentheses were put in there making this
calculation incorrect and reserving too much memory.

    (a + b * 5 + c) * 2

So, remove the parentheses to reserve the exact amount of memory
needed.

The ASRock E350M1 still boots with these changes. No changes were
observed as expected.

Rudolf Marek made this change as part of his patch »ASUS F2A85-M:
Correct and clean up PCIe config« [1]. Factor this hunk out as it
affects all AMD Brazos and Trinity based boards.

[1] http://review.coreboot.org/#/c/3194/

Change-Id: I32e8c8a3dfc5e87eb119eb17719d612e57e0817a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3239
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-14 04:49:03 +02:00
Peter Stuge c49ae3c655 Revert "PC Engines ALIX.1C: Add CMOS defaults."
Revert commit f90071faee [1] as
it was merged without its dependencies and therefore the source
tree currently does not build [2][3].

        OPTION     option_table.h
        GEN        build.h
        SCONFIG    mainboard/pcengines/alix1c/devicetree.cb
        CC         arch/x86/lib/cbfs_and_run.romstage.o
        CC         arch/x86/lib/memcpy.romstage.o
        CC         arch/x86/lib/memset.romstage.o
        CC         arch/x86/lib/rom_media.romstage.o
        CC         arch/x86/lib/romstage_console.romstage.o
        CC         console/die.romstage.o
        CC         console/post.romstage.o
        CC         console/vtxprintf.romstage.o
        CC         device/device_romstage.romstage.o
        CC         lib/cbfs.romstage.o
        CC         lib/compute_ip_checksum.romstage.o
        CC         lib/gcc.romstage.o
        CC         lib/lzma.romstage.o
        CC         lib/memchr.romstage.o
        CC         lib/memcmp.romstage.o
        CC         lib/memmove.romstage.o
        CC         lib/ramtest.romstage.o
        CC         lib/uart8250.romstage.o
        CC         southbridge/amd/cs5536/smbus.romstage.o
        ROMCC      generated/bootblock.inc
        GEN        generated/bootblock.ld
    make: *** No rule to make target `nvramtool', needed by `coreboot-builds/pcengines_alix1c/coreboot.pre1'.  Stop.
    make: *** Waiting for unfinished jobs....
        OPTION     cmos_layout.bin

[1] http://review.coreboot.org/#/c/3229/
[2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
[3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_pcengines_alix1c/

Change-Id: I4764d90c39ccdb4dc7e7a9aef7525c306614e1a8
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-12 20:42:20 +02:00
Peter Stuge 08d0baa77a Revert "Asus M4A785T-M: Add CMOS defaults."
Revert commit b8b3e8bff3 [1] as
it was merged without its dependencies and therefore the source
tree currently does not build [2][3].

        OPTION     option_table.h
        SCONFIG    mainboard/asus/m4a785t-m/devicetree.cb
    make: *** No rule to make target `nvramtool', needed by `coreboot-builds/asus_m4a785t-m/coreboot.pre1'.  Stop.
    make: *** Waiting for unfinished jobs....
        OPTION     cmos_layout.bin

[1] http://review.coreboot.org/3224
[2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
[3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_asus_m4a785t_m/

Change-Id: I8bf33b62b56627f0eea9440ff5e5136e4122ef01
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3244
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-12 20:41:39 +02:00
Duncan Laurie d289852741 Remove the wtm1 mainboard
This was an early bring-up reference board for ULT but it is no
longer being worked on and was never complete enough to be useful
and I no longer have a board so it is already stale and untested.

All ULT bring-up work has moved to the wtm2 mainboard instead.

Change-Id: If64d61bf7a3fc8c9e16096ffc28fa4128aa99477
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3231
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-11 20:21:05 +02:00
Denis 'GNUtoo' Carikli f90071faee PC Engines ALIX.1C: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Disable
    baud_rate = 115200
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0x7f
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Iba2701d4611cd2c2e5a2d76d41ffc23ed65574e8
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3229
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-11 05:20:22 +02:00
Martin Roth 33cde9a0ba Make early x86 POST codes written to IO port optional
This continues the work done in patch 6b908d08ab
http://review.coreboot.org/#/c/1685/
and makes the early x86 post codes follow the same options.

Change-Id: Idf0c17b27b3516e79a9a53048bc203245f7c18ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3237
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-11 05:19:31 +02:00
Duncan Laurie c1ef740d88 haswell: Fix VGA option rom INT15 handler
The format of this function changed but was not updated in
all mainboards.  This fixes BaskingRidge and WTM2.

The int15 handler no longer takes a regs structure as an
argument and instead uses global variables.  The yabel interface
is now similar enough that we can drop the duplicate handler.

Change-Id: Ia717ae14f99cee6d83ccdb1e26b9d7defe1638c4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3230
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-11 00:15:30 +02:00
Ronald G. Minnich 711a6fde0d Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary
This option has never had much if any use. It solved a problem over 10
years ago that resulted from an argument over the value or lack thereof
of including all the debug strings in a coreboot image. The answer is
in: it's a good idea to maintain the capability to print all messages,
for many reasons.

This option is  also misleading people, as in a recent discussion, to
believe that log messges are controlled at build time in a way they are
not. For the record, from this day forward, we can print messages at all
log levels and the default log level is set at boot time, as directed by
DEFAULT_CONSOLE_LOGLEVEL. You can set the default to 0 at build time and
if you are having trouble override it in CMOS and get more messages.

Besides, a quick glance shows it's always set to max (9 in this case) in
the very few cases (1) in which it is set.

Change-Id: I60c4cdaf4dcd318b841a6d6c70546417c5626f21
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3188
Tested-by: build bot (Jenkins)
2013-05-10 17:33:49 +02:00
Stefan Reinauer c5e036a043 Get rid of a number of __GNUC__ checks
In the process of streamlining coreboot code and getting
rid of unneeded ifdefs, drop a number of unneeded checks
for the GNU C compiler. This also cleans up x86emu/types.h
significantly by dropping all the duplicate types in there.

Change-Id: I0bf289e149ed02e5170751c101adc335b849a410
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3226
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 17:31:31 +02:00
Denis 'GNUtoo' Carikli b8b3e8bff3 Asus M4A785T-M: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Enable
    baud_rate = 115200
    hw_scrubber = Enable
    interleave_chip_selects = Enable
    max_mem_clock = 400Mhz
    multi_core = Enable
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0xc
    slow_cpu = off
    nmi = Enable
    iommu = Enable
    nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Ifa09c7a468e3e0713b426763266ae633e67d8397
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3224
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 17:27:05 +02:00
Siyuan Wang e04dc7529f AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h
The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE,
GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used.

Change-Id: I5c7b7d45880367dba452ebcd4f01fbd0c15aac22
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3087
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-10 09:57:03 +02:00
Paul Menzel bed88d65b2 northbridge/intel/i5000/udelay.c: Remove unused header `console.h`
Nothing from the header `console.h` is needed in `udelay.c`, so do
not include it.

This header was included since commit
»Add Intel i5000 Memory Controller Hub« (17670866) [1].

[1] http://review.coreboot.org/491

Change-Id: Ie136a1b862b55c9471f9293ed616ce27a1d01a50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3218
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 00:36:22 +02:00
Stefan Reinauer 3f5f6d8368 Drop prototype guarding for romcc
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .

[1] http://review.coreboot.org/2424

Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-10 00:06:46 +02:00
Paul Menzel d654f42e27 AMD: Reduce stack size from 64 KB to the default of 4 KB
Apply the following commit to all AMD boards.

    commit 935850e082
    Author: Stefan Reinauer <reinauer@chromium.org>
    Date:   Mon May 6 16:16:03 2013 -0700

        asrock/e350m1: reduce default stack size

        The stack used on the ASRock E350M1 is significantly less than
        what we currently set (64k per core). In fact, we use about half
        of the default stack size (4k) on core 0 and even less on non
        BSP cores [1]:

        $ grep stack coreboot_without_patch_but_monotonic_timer.log
        CPU1: stack_base 002a0000, stack_end 002afff8
        CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes
        CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes

        […]

        Reviewed-on: http://review.coreboot.org/3209

Please note that AGESA seems to define bigger stack sizes. But
these seem to be too much too.

    $ git grep STACK_SIZE src/vendorcode/amd
    […]
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define BSP_STACK_SIZE            16384
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE0_STACK_SIZE          16384
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:#define CORE1_STACK_SIZE          4096
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  BSP_STACK_SIZE,
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  CORE0_STACK_SIZE,
    src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c:  CORE1_STACK_SIZE,
    […]

The following command was used to create the patch.

    $ git grep -l STACK_SIZE src/mainboard/ | xargs sed -i '/STACK_SIZE/,+3d'

Change-Id: I36b95b7a6f190b64d0639fc036ce2fb0253f3fa1
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3217
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-09 20:19:24 +02:00
Stefan Reinauer 3949e37834 Drop CONFIG_AP_CODE_IN_CAR
This option has not been enabled on any board and was considered
obsolete last time it was touched. If we need the functionality,
let's fix this in a generic way instead of a K8 specific way.
This was mostly a speedup hack back in the day.

Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3211
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 19:14:21 +02:00
Stefan Reinauer 648d16679c copy_and_run: drop boot_complete parameter
Since this parameter is not used anymore, drop it from
all calls to copy_and_run()

Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-08 18:24:23 +02:00
Stefan Reinauer 2a3c10677f hardwaremain: drop boot_complete parameter
it has been unused since 9 years or so, hence drop it.

Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3212
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 18:23:33 +02:00
Aaron Durbin 758076cceb x86: use asmlinkage macro for smm_handler_t
The smm_handler_t type was added before the introduction
of the asmlinkage macro. Now that asmlinkage is available
use it.

Change-Id: I85ec72cf958bf4b77513a85faf6d300c781af603
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3215
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-05-08 16:17:27 +02:00
Dave Frodin 37f8c3af0e cbfs_core.c: make cfbs searches even less verbose
The cbfs core code would print out the name of the file it is
searching for and when it is found would print out the name
again. This contributes to a lot of unnecessary messages in a
functioning payload’s output. Change this message to a DEBUG one
so that it will only be printed when CONFIG_DEBUG_CBFS is enabled.

Change-Id: Ib238ff174bedba8eaaad8d1d452721fcac339b1a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3208
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-08 05:02:13 +02:00
Paul Menzel ea23a6b23f src/cpu/amd/agesa/Kconfig: Use tabs instead of spaces for alignment
Some entries still used spaces while others used tabulators[1]. Convert
spaces to tabs to uniformly use tabs.

---------------------- 8< -------------- 8< -----------------------------
For all of the Kconfig* configuration files throughout the source tree,
the indentation is somewhat different.  Lines under a "config" definition
are indented with one tab, while help text is indented an additional two
spaces. [2]
---------------------- 8< -------------- 8< -----------------------------

[1] http://en.wikipedia.org/wiki/File:HollerithMachine.CHM.jpg
[2] http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/CodingStyle?id=HEAD

Change-Id: Iee80ad4a90e95b925afbb0c6adc563fa3a6503cf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3173
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 02:12:30 +02:00
Aaron Durbin 703aa978aa x86: harden tsc udelay() function
Since the TSC udelay() function can be used in SMM that means the
TSC can count up to whatever value. The current loop was not handling
TSC rollover properly. In most cases this should not matter as the TSC
typically starts ticking at value 0, and it would take a very long time
to roll it over. However, it is my understanding that this behavior is
not guaranteed. Theoretically the TSC could start or be be written to
with a large value that would cause the rollover.

Change-Id: I2f11a5bc4f27d5543e74f8224811fa91e4a55484
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3171
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-07 22:53:08 +02:00
Paul Menzel ddddf15ca3 Intel 82801Gx: LPC: Unify I/O APIC setup
Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a41
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too.

As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3181
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-07 22:40:50 +02:00
Paul Menzel 1b3e176468 x86 I/O APIC: Dump I/O APIC regs in `ioapic.c`
Some southbridges have code in their `lpc.c` files to dump the
I/O APIC registers.

    printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
    for (i=0; i<3; i++) {
            *ioapic_index = i;
            printk(BIOS_SPEW, "  reg 0x%04x:", i);
            reg32 = *ioapic_data;
            printk(BIOS_SPEW, " 0x%08x\n", reg32);
    }

Add similar code to `src/arch/x86/lib/ioapic.c` so all boards using
the function `set_ioapic_id()` get the debug feature and the other
boards can be more easily adapted in follow-up patches.

Change-Id: Ic59c4c2213ed97bdf3798b3dc6e7cecc30e135d8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3184
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-05-07 22:40:31 +02:00
Paul Menzel ac75bc682b x86 I/O APIC: Make functions `io_apic_{read,write}()` public
Some LPC initialiation can save some lines of code when being able
to use the functions `io_apic_read()` and `io_apic_write()`.

As these two functions are now public, remove them from the generic
driver as otherwise we get a build errors like the following.

    […]
    Building roda/rk9; i386: ok, using i386-elf-gcc
    Using payload /srv/jenkins/payloads/seabios/bios.bin.elf
      Creating config file... (blobs, ccache) ok;  Compiling image on 4 cpus in parallel .. FAILED after 12s!
    Log excerpt:
    coreboot-builds/roda_rk9/arch/x86/lib/ramstage.o: In function `io_apic_write':
    /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/arch/x86/lib/ioapic.c:32: multiple definition of `io_apic_write'
    coreboot-builds/roda_rk9/drivers/generic/ioapic/ramstage.o:/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/drivers/generic/ioapic/ioapic.c:22: first defined here
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/roda_rk9/generated/coreboot_ram.o] Error 1
    make: *** Waiting for unfinished jobs....
    […]

Change-Id: Id600007573ff011576967339cc66e6c883a2ed5a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3180
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-07 22:40:10 +02:00
Aaron Durbin 15c671efb5 boot state: remove drain timers option
Internally there were states that had an attribute to
indicate that the timers needed to be drained. Now that
there is a way to block state transitions rely on this
ability instead of draining timers. The timers will
drain themselves when a state is blocked.

Change-Id: I59be9a71b2fd5a17310854d2f91c2a8957aafc28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3205
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-07 20:08:03 +02:00
Aaron Durbin 0748d30554 boot state: add ability to block state transitions
In order to properly sequence the boot state machine it's
important that outside code can block the transition from
one state to the next. When timers are not involved there's
no reason for any of the existing code to block a state
transition. However, if there is a timer callback that needs to
complete by a certain point in the boot sequence it is necessary
to place a block for the given state.

To that end, 4 new functions are added to provide the API for
blocking a state.
1. boot_state_block(boot_state_t state, boot_state_sequence_t seq);
2. boot_state_unblock(boot_state_t state, boot_state_sequence_t seq);
3. boot_state_current_block(void);
4. boot_state_current_unblock(void);

Change-Id: Ieb37050ff652fd85a6b1e0e2f81a1a2807bab8e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3204
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-07 20:07:42 +02:00
Aaron Durbin 39ecc65158 haswell: use asmlinkage for assembly-called funcs
When the haswell MP/SMM code was developed it was using a coreboot
repository that did not contain the asmlinkage macro. Now that the
asmlinkage macro exists use it.

BUG=None
BRANCH=None
TEST=Built and booted.

Change-Id: I662f1b16d1777263b96a427334fff8f98a407755
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3203
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-07 19:39:24 +02:00
David Hendricks d39c650e06 exynos5: select HAVE_MONOTONIC_TIMER
We have the monotonic timer implemented on exynos now, and this
also enables helpful bootstage prints with timing info.

Change-Id: I3baa4c9d70d4b4d059abd5e05eddcabd5258dbfd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3210
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-07 18:35:55 +02:00
Aaron Durbin 8e73b5d952 x86: add TSC_CONSTANT_RATE option
Some boards use the local apic for udelay(), but they also provide
their own implementation of udelay() for SMM. The reason for using
the local apic for udelay() in ramstage is to not have to pay the
penalty of calibrating the TSC frequency. Therefore provide a
TSC_CONSTANT_RATE option to indicate that TSC calibration is not
needed. Instead rely on the presence of a tsc_freq_mhz() function
provided by the cpu/board.  Additionally, assume that if
TSC_CONSTANT_RATE is selected the udelay() function in SMM will
be the tsc.

Change-Id: I1629c2fbe3431772b4e80495160584fb6f599e9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3168
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07 18:35:04 +02:00
Aaron Durbin 7cb1ba9a61 haswell: use tsc for udelay()
Instead of using the local apic timer for udelay() use the tsc.
That way SMM, romstage, and ramstage all use the same delay
functionality.

Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3169
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07 18:32:41 +02:00
Stefan Reinauer 935850e082 asrock/e350m1: reduce default stack size
The stack used on the ASRock E350M1 is significantly less than
what we currently set (64k per core). In fact, we use about half
of the default stack size (4k) on core 0 and even less on non
BSP cores [1]:

    $ grep stack coreboot_without_patch_but_monotonic_timer.log
    CPU1: stack_base 002a0000, stack_end 002afff8
    CPU1: stack: 002a0000 - 002b0000, lowest used address 002afda8, stack used: 600 bytes
    CPU0: stack: 002b0000 - 002c0000, lowest used address 002bf75c, stack used: 2212 bytes

Removing the Kconfig variable STACK_SIZE to use the default results
in the following numbers of stack usage.

    $ grep stack coreboot_with_patch.log
    CPU1: stack_base 00287000, stack_end 00287ff8
    CPU1: stack: 00287000 - 00288000, lowest used address 00287da8, stack used: 600 bytes
    CPU0: stack: 00288000 - 00289000, lowest used address 0028875c, stack used: 2212 bytes

[1] http://review.coreboot.org/#/c/3154/
    (comment May 2 10:21 AM)

Change-Id: Ibdb2102c86094fce3787e3b5a162ca8423de205c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3209
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-07 18:30:43 +02:00
David Hendricks 998d0c6d50 exynos5250/snow: deprecate time.h
This re-introduces 2fde966 (http://review.coreboot.org/#/c/3177/)
which was reverted due to unsatisfied dependencies.

time.h We Hardly Knew Ye.

This deprecates time.h which is currently only used by Exynos5250 and
Snow. The original idea was to try and unify some of the various timer
interfaces and has been supplanted by the monotonic timer API.

timer_us() is now obsolete. timer_start() is now mct_start() and
is exposed in exynos5250/clk.h.

Change-Id: I8e60105629d9da68ed622e89209b3ef6c8e2445b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3201
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-06 05:32:07 +02:00
David Hendricks 040f25b73a timer.h: add mono_time_diff_microseconds()
The current way to get a simple mono_time difference is:
1. Declare a rela_time struct
2. Assign it the value of mono_time_diff(t1, t2)
3. Get microseconds from it using rela_time_in_microseconds().

This patch adds a simpler method. Now one only needs to call
mono_time_diff_microseconds(t1, t2) to obtain the same value which
is produced from the above three steps.

Change-Id: Ibfc9cd211e48e8e60a0a7703bff09cee3250e88b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3190
Tested-by: build bot (Jenkins)
2013-05-05 23:57:03 +02:00
David Hendricks 0bb875be5e exynos5/5250: Update timer call sites to use monotonic timer API
This goes thru various call sites where we used timer_us() and updates
them to use the new monotonic timer API.

udelay() changed substantially and now gracefully handles wraparound.

Change-Id: Ie2cc86a4125cf0de12837fd7d337a11aed25715c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3176
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-05-05 00:18:48 +02:00
Paul Menzel c2f177737b Lenovo ThinkPad X60: Clean up `romstage.c`
1. Move comment for console init to correct place.
2. Start output with capital letter and add full stop at the end.
3. Add missing »)« at the end of description of GPIO 10.
4. Use tabulators instead of spaces.
5. Indent the code automatically using GNU indent [1] with the `-sc`
   switch adding stars in front of comment blocks as the good indent
   manual documents.

       $ indent -linux -sc src/mainboard/lenovo/x60/romstage.c

   Leave the numbers left aligned as it is more beneficial to be
   able to run indent without adapting the result afterward.

[1] http://www.coreboot.org/Development_Guidelines#Coding_Style

Change-Id: I2fa018ec28ff19d23d68754b565c13a7d7a57355
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3185
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-04 22:20:04 +02:00
David Hendricks ab98cfe110 Revert "exynos5250/snow: deprecate time.h"
This reverts commit 2fde9668b4

Somehow this got merged before its dependencies. 3190 must be merged first, followed by 3176. However 3190 will fail while this patch is in. So the situation can't correct itself.

Reverting this until the other two go in.

Change-Id: I176f37c12711849c96f1889eacad38c00a8142c4
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3195
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-05-04 20:36:36 +02:00
Rudolf Marek cc76d7e011 Asus F2A85-M Enable the SD controller for F2A85-M
If the SD controller is "off" hudson.c won't disable that because,
there is no code for this yet.

The PCI device is still visible and PCI BAR will be allocated
by Linux. Unfortunately it may happen that the particular address
is used by non-standard BAR for SPI controller.

Change-Id: Ied7c581727541e2c81b0b1c2b70fd32de0014730
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3167
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04 00:26:36 +02:00
Martin Roth dfb0686f84 AMD F15: Fix warning in Proc/CPU/Feature
Fix Warning:
cpuFeatureLeveling.c:265, GNU Compiler 4 (gcc), Priority: Normal
cast to pointer from integer of different size [-Wint-to-pointer-cast]
with an intermediate cast to (intptr_t)

Change-Id: I3bfd2ea1e797632316675338789dabef8f73ba64
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04 00:25:19 +02:00
Martin Roth 8187f3d32c AMD F15: Fix warnings in Proc/Common
This fixes 3 warnings in the Proc/Common directory:

AmdS3Save.c:250, GNU Compiler 4 (gcc), Priority: Normal
AmdS3LateRestore.c:123, GNU Compiler 4 (gcc), Priority: Normal
cast from pointer to integer of different size [-Wpointer-to-int-cast]
Fixed with a second cast to (intptr_t)

AmdInitReset.c:153, GNU Compiler 4 (gcc), Priority: Normal
statement with no effect [-Wunused-value]
Fixed by commenting the line out as it is in the other families code.

Change-Id: Ib35ec466671712af01568b7c2a18ee138fe883c0
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3125
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-04 00:25:08 +02:00
David Hendricks 2fde9668b4 exynos5250/snow: deprecate time.h
time.h We Hardly Knew Ye.

This deprecates time.h which is currently only used by Exynos5250 and
Snow. The original idea was to try and unify some of the various timer
interfaces and has been supplanted by the monotonic timer API.

timer_us() is now obsolete. timer_start() is now mct_start() and
is exposed in exynos5250/clk.h.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I14ebf75649d101491252c9aafea12f73ccf446b5
Reviewed-on: http://review.coreboot.org/3177
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-03 17:27:28 +02:00
Paul Menzel fe9f0f4734 cpu/amd/agesa/family15tn/Kconfig: Remove unneeded `UDELAY_LAPIC`
Commit

    commit 825c78b5da
    Author: David Hubbard <david.c.hubbard+coreboot@gmail.com>
    Date:   Thu May 2 18:06:03 2013 -0600

        mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPIC

        Reviewed-on: http://review.coreboot.org/3178

adds `UDELAY_LAPIC` to `cpu/amd/agesa/family15tn/Kconfig`. This is
not needed, because since commit

    commit e135ac5a7e
    Author: Patrick Georgi <patrick.georgi@secunet.com>
    Date:   Tue Nov 20 11:53:47 2012 +0100

        Remove AMD special case for LAPIC based udelay()

        Reviewed-on: http://review.coreboot.org/1618

`select UDELAY_LAPIC` is present in `src/cpu/amd/agesa/Kconfig` which
applies also to AMD Family 15tn.

Therefore remove `select UDELAY_LAPIC` again from
`cpu/amd/agesa/family15tn/Kconfig`.

Change-Id: I98b783a97c4a1e45ecb29b776cb3d3877bad9c0f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3179
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2013-05-03 12:52:11 +02:00
David Hendricks 5ec69ed884 exynos5250: monotonic timer implementation (using MCT)
This implements the new monotonic timer API using the global
multi-core timer (MCT).

Change-Id: Id56249ff5d3e0f85808f5754954c83c0bc75f1c1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3175
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-05-03 06:28:54 +02:00
Paul Menzel 008616247d AMD SATA: Correct »them implement« to »then implement« in comments
The following command was used to correct all occurences of this typo.

    $ git grep -l "them implem" | xargs sed -i 's/them implem/then implem/'

Change-Id: Iebd4635867d67861aaf4d4d64ca8a67e87833f38
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03 06:27:05 +02:00
Paul Menzel ac22227370 Intel Lynx Point: Use 2 << 24 to clarify that I/O APIC ID is 2
Commit »haswell: Add initial support for Haswell platforms« (76c3700f)
[1] used `1 << 25` to set the I/O APIC ID of 2. Instead using
`2 << 24`, which is the same value, makes it clear, that the
I/O APIC ID is 2.

Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
is 2« (8c937c7e) [2] is used as a template.

[1] http://review.coreboot.org/2616
[2] http://review.coreboot.org/3100

Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3123
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-03 06:26:28 +02:00
Paul Menzel e62b8e9a8f Kconfig: Capitalize CBMEM in description of `EARLY_CBMEM_INIT`
Capitalizing CBMEM seems to be the official spelling as can be seen
in the descriptions around the `EARLY_CBMEM_INIT` Kconfig option.

Change-Id: I046a678c3b04ef7e681de46aa137cedc405d546f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-05-03 06:26:19 +02:00
Aaron Durbin e690eda978 cbfs: make searching for a file less verbose
The cbfs core code would print out all unmatched file
names when searching for a file. This contributes to a lot
of unnecessary messages in the boot log. Change this
message to a DEBUG one so that it will only be printed when
CONFIG_DEBUG_CBFS is enabled.

Change-Id: I1e46a4b21d80e5d2f9b511a163def7f5d4e0fb99
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3131
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2013-05-03 06:25:03 +02:00
David Hubbard 825c78b5da mainboard/{asus/f2a85-m,amd/thatcher}: move UDELAY_LAPIC
Stefan Reinauer suggested 'select UDELAY_LAPIC' did not belong in
f2a85-m/Kconfig. It got there via copy-paste from thatcher/Kconfig
so this commit removes the 'select UDELAY_LAPIC' from both and puts
it in cpu/amd/agesa/family15tn/Kconfig

Since f2a85-m is the only Thatcher board coreboot supports right
now, this should not break any other boards.

Change-Id: I811b579c31f8d259a237d3a6724ad3b17f3a6c3e
Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-on: http://review.coreboot.org/3178
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2013-05-03 06:23:41 +02:00
David Hendricks 3f39cd2920 armv7: invalidate TLB entries as they are added/modified
The old approach was to invalidate the entire TLB every time we set up
a table entry. This worked because we didn't turn the MMU on until
after we had set everything up. This patch uses the TLBIMVAA wrapper
to invalidate each entry as it's added/modified.

Change-Id: I27654a543a2015574d910e15d48b3d3845fdb6d1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3166
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-01 23:57:16 +02:00
Bruce Griffith 5c2025c40f AMD Hudson A55E: Remove GEC firmware blob kconfig prompt
The "gigabit ethernet controller" (GEC) block was added to AMD
Hudson A55E to integrate ethernet capabilities into an AMD
southbridge.

The GEC is designed to work with B50610 and B50610M gigabit PHY
chips from Broadcom.  These parts may not be generally available
in small quantities for embedded development.

The GEC block requires an opaque firmware blob to function.  The
GEC blob is controlled by AMD and Broadcom and is not available
from coreboot.org.

This change removes GEC support from AMD Parmer and AMD Thatcher
mainboards since these boards do not have the Broadcom PHY.

AMD has requested that the GEC be hidden for Hudson FCH since
the PHY parts are not generally available.  This Kconfig option
can make it appear that this is a viable and supported way to
add Ethernet to an embedded board.  It is possible to use the
Hudson GEC block with other PHYs, but this requires development
of a custom GEC blob and a custom Ethernet driver.  A custom GEC
blob has been developed for a Micrel PHY, but there is no
accompanying driver.

Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-05-01 23:49:06 +02:00
Aaron Durbin 052942923b device tree: track init times
With the introduction of a monotonic timer it is possible to
track the individual times of each device's init() call. Add this
ability behind a HAVE_MONOTONIC_TIMER option.

Example log messages:
Root Device init 5 usecs
CPU_CLUSTER: 0 init 66004 usecs
PCI: 00:00.0 init 1020 usecs
PCI: 00:02.0 init 456941 usecs
PCI: 00:13.0 init 3 usecs
PCI: 00:14.0 init 3 usecs
PCI: 00:15.0 init 92 usecs
PCI: 00:15.1 init 37 usecs
PCI: 00:15.2 init 36 usecs
PCI: 00:15.3 init 35 usecs
PCI: 00:15.4 init 35 usecs
PCI: 00:15.5 init 36 usecs
PCI: 00:15.6 init 35 usecs
PCI: 00:16.0 init 3666 usecs
PCI: 00:17.0 init 63 usecs
PCI: 00:1b.0 init 3 usecs
PCI: 00:1c.0 init 89 usecs
PCI: 00:1c.1 init 15 usecs
PCI: 00:1c.2 init 15 usecs
PCI: 00:1c.3 init 15 usecs
PCI: 00:1c.4 init 15 usecs
PCI: 00:1c.5 init 16 usecs
PCI: 00:1d.0 init 4 usecs
PCI: 00:1f.0 init 495 usecs
PCI: 00:1f.2 init 29 usecs
PCI: 00:1f.3 init 4 usecs
PCI: 00:1f.6 init 4 usecs

Change-Id: Ibe499848432c7ab20166ab10d6dfb07db03eab01
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3162
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-01 21:36:16 +02:00
Ronald G. Minnich c0466d46b7 ARMV7: add a function to disable MMU entries
It is useful to be able to lock out certain address ranges,
NULL being the most important example.

void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)

will allow us to lock out selected virtual addresses on MiB boundaries.
As in other ARM mmu functions, the addresses and quantities are in units
of MiB.

Change-Id: If516ce955ee2d12c5a409f25acbb5a4b424f699b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3160
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-05-01 20:12:48 +02:00
Hung-Te Lin 043b823a73 Google/Snow: Revise bootblock initialization.
It's fine to always start timer even in suspend/resume mode, so we can
move the timer_start() back to the very beginning of boot procedure.
That provides more precise boot time information.

With that timer change, the wake up state test procedure can be simplified.

Verified by building and booting firmware image on Google/Snow successfully,
and then suspend-resume without problem (suspend_stress_test).

Change-Id: I0d739650dbff4eb3a75acbbf1e4356f2569b487d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3151
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 18:26:50 +02:00
David Hendricks c99ae5d9a9 armv7: add wrapper for tlbimvaa
This adds an inline wrapper for the TLBIMVAA instruction (invalidate
unified TLB by MVA, all address space identifiers).

Change-Id: Ibcd289ecedaba8586ade26e36c177ff1fcaf91d3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3161
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-01 08:17:01 +02:00
Hung-Te Lin 0004c0deec Google/Snow: Remove duplicated SPI1 initialization in bootblock.
The firmware media source (SPI1) is already initialized by Exynos iROM.
There is no need to do it again.

Verified by building and booting Google/Snow successfully.

Change-Id: I89390506aa825397c0d7e52ad7503f1cb808f7db
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3147
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:43:31 +02:00
Aaron Durbin 8fc41e1b84 boot state: run timers on state entry
When TIMER_QUEUE is configured on call the timer callbacks on
entry into a state but before its entry callbacks. In addition
provide a barrier to the following states so that timers are drained
before proceeding. This allows for blocking state traversal for key
components of boot.
	BS_OS_RESUME
	BS_WRITE_TABLES
	BS_PAYLOAD_LOAD
	BS_PAYLOAD_BOOT

Future functionality consists of evaluating the timer callbacks within
the device tree. One example is dev_initialize() as that seems state
seems to take 90% of the boot time. The timer callbacks could then be
ran in a more granular manner.

Change-Id: Idb549ea17c5ec38eb57b4f6f366a1c2183f4a6dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3159
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:19:52 +02:00
Aaron Durbin 340ca91f18 coreboot: add timer queue implementation
A timer queue provides the mechanism for calling functions
in the future by way of a callback. It utilizes the MONOTONIC_TIMER
to track time through the boot. The implementation is a min-heap
for keeping track of the next-to-expire callback.

Change-Id: Ia56bab8444cd6177b051752342f53b53d5f6afc1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:19:12 +02:00
Aaron Durbin 6b0fb0dc3c boot state: track times for each state
When the MONOTONIC_TIMER is available track the entry, run, and exit
times for each state. It should be noted that the times for states that
vector to OS or a payload do not have their times reported.

Change-Id: I6af23fe011609e0b1e019f35ee40f1fbebd59c9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3156
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:16:52 +02:00
Aaron Durbin e850164bac tsc: provide monotonic timer
Implement the timer_monotonic_get() using the TSC.

Change-Id: I5118da6fb9bccc75d2ce012317612e0ab20a2cac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3155
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:15:55 +02:00
Aaron Durbin fd8291c9d4 lapic: monotonic time implementation
Implement the timer_monotonic_get() functionality based off of
the local apic timer.

Change-Id: I1aa1ff64d15a3056d6abd1372be13da682c5ee2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3154
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:15:17 +02:00
Aaron Durbin c46cc6f149 haswell: 24MHz monotonic time implementation
Haswell ULT devices have a 24MHz package-level counter. Use
this counter to provide a timer_monotonic_get() implementation.

Change-Id: Ic79843fcbfbbb6462ee5ebd12b39502307750dbb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3153
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:14:36 +02:00
Aaron Durbin a421791db8 coreboot: introduce monotonic timer API
The notion of a monotonic timer is introduced. Along with it
are helper functions and other types for comparing times. This
is just the framework where it is the responsibility of the
chipset/board to provide the implementation of timer_monotonic_get().

The reason structs are used instead of native types is to allow
for future changes to the data structure without chaning all the
call sites.

Change-Id: Ie56b9ab9dedb0da69dea86ef87ca744004eb1ae3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3152
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:13:43 +02:00
Aaron Durbin 001de1aeb0 boot state: rebalance payload load vs actual boot
The notion of loading a payload in the current boot state
machine isn't actually loading the payload. The reason is
that cbfs is just walked to find the payload. The actual
loading and booting were occuring in selfboot(). Change this
balance so that loading occurs in one function and actual
booting happens in another. This allows for ample opportunity
to delay work until just before booting.

Change-Id: Ic91ed6050fc5d8bb90c8c33a44eea3b1ec84e32d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3139
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:13:16 +02:00
Aaron Durbin bebf66909a x86: use boot state callbacks to disable rom cache
On x86 systems there is a concept of cachings the ROM. However,
the typical policy is that the boot cpu is the only one with
it enabled. In order to ensure the MTRRs are the same across cores
the rom cache needs to be disabled prior to OS resume or boot handoff.
Therefore, utilize the boot state callbacks to schedule the disabling
of the ROM cache at the ramstage exit points.

Change-Id: I4da5886d9f1cf4c6af2f09bb909f0d0f0faa4e62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3138
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:12:17 +02:00
Aaron Durbin 243aa44b74 boot: remove cbmem_post_handling()
The cbmem_post_handling() function was implemented by 2
chipsets in order to save memory configuration in flash. Convert
both of these chipsets to use the boot state machine callbacks
to perform the saving of the memory configuration.

Change-Id: I697e5c946281b85a71d8533437802d7913135af3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:11:22 +02:00
Aaron Durbin 40131cfa46 cbmem: use boot state machine
There were previously 2 functions, init_cbmem_pre_device() and
init_cbmem_post_device(), where the 2 cbmem implementations
implemented one or the other. These 2 functions are no longer
needed to be called in the boot flow once the boot state callbacks
are utilized.

Change-Id: Ida71f1187bdcc640ae600705ddb3517e1410a80d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3136
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:10:03 +02:00
Aaron Durbin 4dd87fb2d8 coverage: use boot state callbacks
Utilize the static boot state callback scheduling to initialize
and tear down the coverage infrastructure at the appropriate points.
The coverage initialization is performed at BS_PRE_DEVICE which is the
earliest point a callback can be called. The tear down occurs at the
2 exit points of ramstage: OS resume and payload boot.

Change-Id: Ie5ee51268e1f473f98fa517710a266e38dc01b6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3135
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:08:44 +02:00
Aaron Durbin 0a6c20a2a3 acpi: split resume check and actual resume code
It's helpful to provide a distinct state that affirmatively
describes that OS resume will occur. The previous code included
the check and the actual resuming in one function. Because of this
grouping one had to annotate the innards of the ACPI resume
path to perform specific actions before OS resume. By providing
a distinct state in the boot state machine the necessary actions
can be scheduled accordingly without modifying the ACPI code.

Change-Id: I8b00aacaf820cbfbb21cb851c422a143371878bd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3134
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:07:33 +02:00
Aaron Durbin a4feddf897 boot state: schedule static callbacks
Many of the boot state callbacks can be scheduled at compile time.
Therefore, provide a way for a compilation unit to inform the
boot state machine when its callbacks should be called. Each C
module can export the callbacks and their scheduling requirements
without changing the shared boot flow code.

Change-Id: Ibc4cea4bd5ad45b2149c2d4aa91cbea652ed93ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:06:12 +02:00
Aaron Durbin 7e35efa83c ramstage: introduce boot state machine
The boot flow currently has a fixed ordering. The ordering
is dictated by the device tree and on x86 the PCI device ordering
for when actions are performed. Many of the new machines and
configurations have dependencies that do not follow the device
ordering.

In order to be more flexible the concept of a boot state machine
is introduced. At the boundaries (entry and exit) of each state there
is opportunity to run callbacks. This ability allows one to schedule
actions to be performed without adding board-specific code to
the shared boot flow.

Change-Id: I757f406c97445f6d9b69c003bb9610b16b132aa6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3132
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 07:04:47 +02:00
Aaron Durbin e1be5ae2f4 rmodule: put all code/data bits in one section
While debugging a crash it was discovered that ld was inserting
address space for sections that were empty depending on section
address boundaries. This led to the assumption breaking down that
on-disk payload (code/data bits) was contiguous with the address
space. When that assumption breaks down relocation updates change
the wrong memory. Fix this by making the rmodule.ld linker script
put all code/data bits into a payload section.

Change-Id: Ib5df7941bbd64662090136e49d15a570a1c3e041
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-05-01 03:25:51 +02:00
Aaron Durbin ac4b00e230 string: Add STRINGIFY macro
STRINGIFY makes a string from a token. It is generally useful.
Even though STRINGIFY is not defined to be in the C library it's
placed in string.h because it does make a string.

Change-Id: I368e14792a90d1fdce2a3d4d7a48b5d400623160
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3144
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-01 03:25:04 +02:00
Hung-Te Lin 032dd14514 Google/Snow: Remove unnecessary serial console init code.
The "console_init" does initialize UART driver (which will setup peripheral and
pinmux) and print starting message. Duplicated initialization can be removed.

Also, console_init (from console.c) is always linked to bootblock (and will do
nothing if CONFIG_EARLY_CONSOLE is not defined) so it's safe to remove #ifdef.

Verified by building and booting on Google/Snow, with and without
CONFIG_EARLY_CONSOLE.

Change-Id: I0c6b4d4eb1a4e81af0f65bcb032978dfb945c63d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3150
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-30 19:22:05 +02:00
Denis 'GNUtoo' Carikli 4560ca5003 Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.
Enable `EARLY_CBMEM_INIT` for CBMEM console support by looking how
other boards do this.

This commit is tested by enabling the CBMEM console (`CONSOLE_CBMEM` in
Kconfig) and then in GRUB 2 (as a payload) with the cbmemc command from
the cbmemc module and in userspace with ./cbmem -c. Both worked.

Change-Id: I34618a55ded7292a411bc232eb76267eec17d91e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3142
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-04-30 17:47:41 +02:00
Hung-Te Lin bf92b19b2a Google/Snow: Temporary fix for resume failure.
The DDR3 memory initialization (with "mem_reset" set on normal boot) will cause
resume to be unstable, especially when X is running. System may show X screen
for few seconds, then crash randomly and unable to recover - although text
console may still work for a while.  Probably caused by corrupted memory pages.

'mem_reset' (which refers to RESET# in DDR3 spec) should be enabled according
to DDR3 spec. But it seems that on Exynos 5, memory can be initialized without
setting mem_reset for both normal boot and resume - at least no known failure
cases are found yet.  So this can be a temporary workaround.

Verified by booting a Google/Snow device with X Window and ChromeOS, entering
browser session with fancy web pages, closing LID to suspend for 5 seconds, then
re-opening to resume.  Suspend/resume worked as expected.

Also tried the "suspend_stress_test" with X running and finished 100 iterations
of suspend/resume test without failure.

Change-Id: I7185b362ce8b545fe77b35a552245736c89d465e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3148
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-30 05:49:42 +02:00
Hung-Te Lin 3f73eec4d3 Google/Snow: Enable suspend/resume.
Add the suspend/resume feature into bootblock and romstage.

Note, resuming with X and touchpad driver may be still unstable.

Verified by building and booting successfully on Google/Snow, and then executing
the "suspend_stress_test" in text mode ("stop ui; suspend_stress_test") in
Chromium OS, passed at least 20 iterations.

Change-Id: I65681c42eeef2736e55bb906595f42a5b1dfdf11
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3102
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-29 15:34:10 +02:00
Hung-Te Lin 31039e315c google/snow: Revise romstage initialization code.
Move board setup procedure to snow_setup_* functions, and Snow board-specific
(wakeup) code to snow_* for better function names and comments.

Verified by successfully building and booting on Google/Snow.

Change-Id: I2942d75064135093eeb1c1da188a005fd255111d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3130
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-26 20:00:45 +02:00
Paul Menzel 526a46ed7e Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used
`1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which
is the same value, makes it clear, that the I/O APIC ID is 2.

Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
is 2« (8c937c7e) [2] is used as a template.

[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0
[2] http://review.coreboot.org/3100

Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3122
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-26 18:37:00 +02:00
David Hendricks dfad17de02 exynos5250: uncomment $(INTERMEDIATE)
This makes the intermediate rule visible so BL1 gets automatically
placed in the final image.

Change-Id: Iffb0268e5bbcbe135f2d39863ed64fa302409a22
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3141
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-04-26 08:50:11 +02:00
David Hendricks 64a69e8e4d armv7: invoke intermediate build rules
This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on
armv7. It is modeled after the $(obj)/coreboot.rom rule for x86.

Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2095
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-04-26 03:00:34 +02:00
Hung-Te Lin bd7f5f6492 google/snow: Add "wakeup" module for suspend/resume.
The "wakeup" procedure will be shared by bootblock and romstage for different
types of resume processes.

Note, this commit does not include changes in romstage/bootblock to enable
suspend/resume feature. Simply adding functions to handle suspend/resume.

Verified by successfully building and booting Google/Snow firmware image.

Change-Id: I17a256afb99f2f8b5e0eac3393cdf6959b239341
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3129
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-25 19:31:09 +02:00
Hung-Te Lin 55c753d3a9 arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
To support suspend/resume, PHY control must be reset only on normal boot
path.  So add a new param "mem_reset" to specify that.

Verified to boot successfully on Google/Snow.

Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3128
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-25 19:27:48 +02:00
Siyuan Wang 175ad4aa6e AMD Thatcher: ConnectorTypeDP supports both DP and HDMI
It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors.
I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter.
Video and audio are OK. Hot plugging is also supported.

This commit partially reverts commit >AMD Thatcher: Fix PCIE link issues< (7f23aeb0) [1].

[1] http://review.coreboot.org/3011

Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3088
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-23 17:35:26 +02:00
Ronald G. Minnich 2810afa57d GOOGLE/SNOW: get graphics working
This adds support for display bring-up on Snow. It
includes framebuffer initialization and LCD enable functions.

Change-Id: I16e711c97e9d02c916824f621e2313297448732b
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3116
Tested-by: build bot (Jenkins)
2013-04-23 04:41:23 +02:00
Vladimir Serbinenko 2c88cc0696 Intel microcode: Return when `microcode_updates` is `NULL`
Add a safety check in function `intel_update_microcode` to return when
accidentally `NULL` is passed as `microcode_updates`, which would lead
to a null pointer dereference later on.

    for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {

While at it, use `return NULL` for clarity in function
`intel_microcode_find` and include the header file `stddef.h`. for it.

The review of this patch had some more discussion on adding more
comments and more detailed error messages. But this should be done in
a separate patch.

For clarity here some history, on how this was found and what caused
the discussion and confusion.

Originally when Vladimir made this improvement, selecting
`CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob
`cpu_microcode_blob.bin` in CBFS resulted in a null pointer dereference
later on causing a crash.

    for (c = microcode_updates; m->hdrver; m = (const struct microcode *)c) {

Vladimir fixed this by returning if `microcode_updates` is `NULL`,
that means no file is found and successfully tested this on his
Lenovo X201.

When pushing the patch to Gerrit for review, the code was rewritten
though by Aaron in commit »intel microcode: split up microcode loading
stages« (98ffb426) [1], which also returns when no file is found. So
the other parts of the code were checked and the safety check as
described above is added.

[1] http://review.coreboot.org/2778

Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2990
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2013-04-23 03:30:22 +02:00
David Hendricks aee444f453 exynos5250: ungate the product ID register
This makes sure that the product ID (PRO_ID) register can be read
when the OS kernel is figuring out what kind of CPU it's running on.

For historical reference, the original U-Boot code seems to have
worked basically by accident here. The hardware has a quirk where by
reading the value before gating the IP block keeps the value
persistent. U-Boot reads the chip ID early on to distinguish between
chip family, but we do not mix code the same way so we do not read
the chip ID. Since the value has been read before the clock gating
happens, the value remains available for the kernel to use during the
decompression stage. We don't want to rely on that behavior when using
coreboot. Instead the kernel should gate unused IPs.

(credit to Gabe for finding symptom in the kernel)

Change-Id: Iaa21e6e718b9000b5558f568020f393779fd208e
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3121
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-04-23 03:20:44 +02:00
Ronald G. Minnich e8a91347b1 GOOGLE/SNOW: fix stupid paren error
This simple error led to corrupted graphics.
How annoying.

Change-Id: I2295c0df0f1d16014a603dc5d66bd4d72f3fb7c9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3120
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-04-22 20:35:52 +02:00
Paul Menzel 6974396261 AMD SB800 based boards: Use `#include <sb_cimx.h>` instead of `"sb_cimx.h"`
Due to

    $ more src/southbridge/amd/cimx/sb800/Makefile.inc
    […]
    romstage-y += cfg.c
    romstage-y += early.c
    romstage-y += smbus.c

    ramstage-y += cfg.c
    ramstage-y += late.c
    […]

`src/southbridge/amd/cimx/sb800/` is passed with the switch `-I` to
the compiler, where it is also going to find the header file
`sb_cimx.h`. Therefore use `#include <sb_cimx>` everywhere, which is
what some AMD SB800 based boards already do.

The only effect is, that the compiler will not needlessly look into
directories which do not contain the header file [1].

The following command was used for the replacement.

    $ git grep -l sb_cimx.h src/mainboard/ | xargs sed -i 's/#include "sb_cimx.h"/#include <sb_cimx.h>/'

[1] http://gcc.gnu.org/onlinedocs/cpp/Search-Path.html

Change-Id: I96ab34bac1524e6c38c85dfe9d99cb6ef55e6d7c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3118
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-20 18:57:20 +02:00
Stefan Reinauer 642b1db733 Eliminate use of pointers in coreboot table
Because pointers can be 32bit or 64bit big,
using them in the coreboot table requires the
OS and the firmware to operate in the same mode
which is not always the case. Hence, use 64bit
for all pointers stored in the coreboot table.
Guess we'll have to fix this up once we port to
the first 128bit machines.

Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3115
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-04-20 05:18:15 +02:00
David Hendricks 8d5bc9f772 google/snow: disable unused USB3.0 PLL to save power
This PLL is unused and can be disabled to save about 250mW.

Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3109
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19 23:10:05 +02:00
David Hendricks 9539932719 exynos5: eliminate lcd_base variable
The original imported code used "lcdbase" and "lcd_base" which quite
predictably caused confusion and bugs. Let's put an end to this little
bit of insanity.

Change-Id: I4f995482cfbff5f23bb296a1e6d35beccf5f8a91
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3114
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-19 20:13:54 +02:00
David Hendricks ec10ce8971 google/snow: Minor clean-ups for display setup code in ramstage
This just cleans up a few areas:
- Removed an unnecessary delay from exynos_dp_bridge_setup()
- The delay at the end of exynos_dp_bridge_init() is necessary, so
  removed the comment suggesting that it might not be.
- Simplified exynos_dp_hotplug

Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3113
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19 18:24:14 +02:00
David Hendricks 954d25484b google/snow: enable clock gating to save power
This enables clock gating to save power on unused IPs.

Change-Id: I9ab2a2535ebb91bb4110390a6f055a67146bdbf9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19 18:22:51 +02:00
Siyuan Wang 8a275c1810 AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI
This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1]
I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter.
Video and audio are OK. Hot plugging is also supported.

[1] http://review.coreboot.org/#/c/3088/

Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3090
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-19 18:17:13 +02:00
Ronald G. Minnich d83c117e86 exynos5250: get xres and yres out of the device tree and into the panel descriptor
We neglected to copy xres and yres out; now we do.

Change-Id: Icc4a8eb35799d156b11274f71bcfb4a1d10e01e3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3111
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-04-19 17:41:17 +02:00
David Hendricks 34240b06d8 [3/3] google/snow: enable TMU
This enables the thermal management unit (TMU) on Snow.

Change-Id: Idd76af40bf0a5408baf61ef2665fd52ae4e260ba
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3108
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-19 04:19:28 +02:00
David Hendricks cd14ed71bb [2/3] exynos5: modify thermal management unit code for coreboot
This updates the Exynos TMU code for coreboot:
- Remove dependency on device tree
- Add Makefile entries

Change-Id: I55e1b624d7c7b695b1253ec55f6ae3de8dc671bc
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3107
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-19 04:19:16 +02:00
David Hendricks 90a70093b1 [1/3] exynos5: import thermal management unit code
This simply imports the Exynos TMU driver from u-boot. It is not
built and thus should not break anything.

Change-Id: I7861132fbf97f864e4250ffbda1ef3843f296ddc
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3106
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-19 04:19:10 +02:00
David Hendricks b9e6e1ab35 exynos5: move power_enable_hw_thermal_trip() prototype
This moves the prototype for power_enable_hw_thermal_trip() to
a generic location so it can be used by generalized thermal
management code. The implementation will still be CPU-specific.

Change-Id: Iae449cb8c72c8441dedaf65b73db9898b4730cef
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3105
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-04-19 04:19:00 +02:00
Vladimir Serbinenko 45988dab6b spkmodem console
Change-Id: Ie497e4c8da05001ffe67c4a541bd24aa859ac0e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2987
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 22:47:59 +02:00
Dave Frodin 8a6f7a77f3 AMD/SB800: Define the GPP PCIe lane distribution
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
This fix was verified by openvoid on a AsRock E350M1 motherboard.

Change-Id: I0116c5f518e0d000be609013446e53da4112f586
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3104
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 18:35:12 +02:00
Mike Loptien ba7ed4b6a1 AMD Fam14: Split out the AMD Fam14 DSDT
Same splitting as done on Persimmon and ASRock.
Moving common DSDT code to common areas and adding
new files as necessary.  Boards updated are:
	Inagua
	Union-Station
	South-Station

Change-Id: I8c9eea62996b41cea23a9c16858c4249197f6216
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 02:49:49 +02:00
Denis 'GNUtoo' Carikli 4b213a8d1f Intel i945: ACPI: Add _OSC method
Add the ACPI Operating System Capabilities Method and let the
operation system control everything.

Commit »AMD Fam14 DSDT: Add OSC method« (00a0e76b) [1] is used as
a template.

The Lenovo X60 [2] running the Parabola GNU/Linux distribution [3] is
used for testing.

Before that change:

    $ dmesg | egrep -e OSC -e ASPM
    [    0.108036] pci_root PNP0A08:00: ACPI _OSC support notification failed, disabling PCIe ASPM
    [    0.108040] pci_root PNP0A08:00: Unable to request _OSC control (_OSC support mask: 0x08)
    [    0.118089] ACPI _OSC control for PCIe not granted, disabling ASPM
    [   16.874569] e1000e 0000:01:00.0: Disabling ASPM L0s L1

With that change:

    $ dmesg | egrep -e OSC -e ASPM
    [    0.107962] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d)
    [    0.108003] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted
    [    0.111052] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
    [   17.537970] e1000e 0000:01:00.0: Disabling ASPM L0s L1

[1] http://review.coreboot.org/2738
[2] http://www.coreboot.org/Lenovo_x60x
[3] https://parabolagnulinux.org/

Change-Id: I1caffa44eea447d553c01caaf431f2db241ea5ea
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 02:48:02 +02:00
Stefan Reinauer ab348528b5 ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT
This used to contain the path for the EC include files, but
those files are included in coreboot now.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369
Reviewed-on: https://gerrit.chromium.org/gerrit/47606
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3057
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-18 02:47:23 +02:00
David Hendricks 1fb11d105b armv7/exynos5250: Deprecate sdelay in favor of udelay
This gets rid of the clock-tick based sdelay in favor of udelay().
udelay() is more consistent and easier to work with, and this allows
us to carry one less variation of timers (and headers and sources...).

Every 1 unit in the sdelay() argument was assumed to cause a delay of
2 clock ticks (@1.7GHz). So the conversion factor is roughly:
sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6)
          = udelay((N * 2) / (1.7 * 10^3))

The sdelay() periods used were:
sdelay(100) --> udelay(1)
sdelay(0x10000) --> udelay(78) (rounded up to udelay(100))

There was one instance of sdelay(10000), which looked like sort of a
typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should
approximate to about 12us, so we'll stick with that for now and leave
a note.

Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3079
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17 23:06:40 +02:00
David Hendricks 1a0b5e1c05 google/snow: enable 32KHz sleep clock
Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3075
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-17 17:56:06 +02:00
Ronald G. Minnich 130aafacb0 Samsung/exynos5250: convert unsigned {int,char} to u32/u8
The types are (esp. int) are confusing at times as to size.
Make them definite as to size.

Change-Id: Id7808f1f61649ec0a3403c1afc3c2c3d4302b7fb
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3103
Tested-by: build bot (Jenkins)
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-04-17 02:28:14 +02:00
Siyuan Wang 88d0c7330e AMD Parmer: remove unused macros and turn off unused pcie port
1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE,
GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used.
This is based on >AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h< [1].

2) Disable unused PCIE port in devicetree.cb.
PCIE port 3 is not used in Parmer.
This is based on item 3 of >AMD Thatcher: Fix PCIE link issues< [2].

[1] http://review.coreboot.org/#/c/3087/
[2] http://review.coreboot.org/#/c/3011/

Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3099
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-16 17:49:04 +02:00
Vladimir Serbinenko 8c937c7e3c Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2
Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used
`1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same
value, instead makes it clear, that the APIC ID is 2.

[1] http://review.coreboot.org/853

Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3100
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-04-16 15:34:09 +02:00
Gabe Black 8a2bc62d4c snow: Return 0 from get_recovery_mode_from_vbnv.
This function isn't yet used for much, or perhaps anything, but where it
appears in the code it's ored with other values. Since we're not actually
retrieving anything, it might be best to return 0 so that the other values
that are being ored in can be expressed and this function can stay dormant
until it actually has something to do.

Change-Id: I6edc222a5c2d00ece2ecfad5191a615331eeaf16
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3098
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-04-16 11:11:53 +02:00
Gabe Black 5cda30845c snow: Report the state of the power button GPIO in the coreboot tables.
Change-Id: Ia7ce2b7342e186c565b92211e3ac15d80ce24b38
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3097
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-04-16 11:11:44 +02:00
Gabe Black e2b20f2d5a snow: Configure the power button as an input GPIO.
We need to read it to report its value to the payload. The kernel will
reconfigure it as an external interrupt, but we'll make it a regular input
for now.

Change-Id: I019bd2c2731144d3b7bb53fad0c2c903874f616c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3096
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-04-16 11:11:18 +02:00
Gabe Black acb9d44599 snow: Fix the name of some constants in romstage.c.
These names were inherited from chromeos.c where they've already been
fixed.

Change-Id: I7ad57b979b7b8f42f6bd68d1ecf887caba3fa3f1
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3095
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
2013-04-16 11:10:54 +02:00