Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.
Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This comment seems to have been copied off some QEMU board. As it would
not apply to any veyron variant, drop it.
Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few
minor typos.
Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to provide more consistent probing in future refactorings, pull out
the release from deep sleep path in STMicro's SPI flash probing function.
Call that function explicitly when RDID doesn't return anything at all.
The old STMicro parts, even if supporting RDID, won't decode that
instruction while in a deep power down state. Instead of re-issuing RDID after
the successful wake assume the id fixup is valid.
Change-Id: I46c47abcfb1376c1c3ce772f6f232857b8c54202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Also change some of the types to match the register widths
of the controller. It is expected that these prototypes
will be used with SMBus host controllers inside AMD chipsets
as well, thus the change of location.
Change-Id: I88fe834f3eee7b7bfeff02f91a1c25bb5aee9b65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38226
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Intel, accessing the SMBus register banks can be done via
IO and, since at least ICH10, via MMIO. We may want to use the
latter in the future.
Change-Id: I67fcbc7b6f6be61c93bc608e556a577ef9e52325
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Switch to use the more recent version in sb/intel/common.
Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Switch to use the more recent version in sb/intel/common.
Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Only smbuslib.c and spd_bin.c share the same prototypes for SMBUS
functions. Therefore, get_spd_smbus() currently only works with
soc/intel/.../smbuslib.c and can be implemented there locally.
This allows removal of <device/early_smbus.h>.
Change-Id: Ic2d9d83ede6388a01d40c6e4768f6bb6bf899c00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add back options that were lost on postcar migration. Some of them
seem to be required for IOMMU initialization.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie9cc772d7fcbefded8bab88f9960fef663dc7217
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add missing BeforeInitLate hooks in order to bring back certain options
that were lost on postcar migration. This will also allow to disable
CDIT again that caused AmdInitLate error on 00730F01.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1226e9c0c8a92920f2569ec0f85d0be0adcc9e30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Kconfig:
- use CAR NEM mode for tigerlake only as NEM Enhanced is under debug
- update GSPI, RP max device #s according to
PCH EDS#576591 vol1 rev1.2
- update UART M/N setting according to new PCH baseclock
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I04020d55f1063d521b15f8d0dabbd6f1dabf577c
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* Add function to generate unique _UID using CRC32
* Add function to write the _UID based on a device's ACPI path
ACPI devices that have the same _HID must use different _UID.
Linux doesn't care about _UID if it's not used.
Windows 10 verifies the ACPI code on boot and BSODs if two devices
with the same _HID share the same _UID.
Fixes BSOD seen on Windows 10.
Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Always write a _HID, even for disabled PNP devices.
Fixes a BSOD on Windows 10.
Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Ensure that the operation order is always the same. This results in
changes to the binary, but the effective result is the same.
Change-Id: I9772832c60089b35889df7298e20a2bd02b35b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch creates a common instance of northbridge.asl inside intel common
code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to
refer northbridge.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
Device(MCHC) presence after booting to OS.
Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer
being used in the code. There's a runtime check for supporting
fast read dual output mode of the spi flash. Remove the references
to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B.
Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove fixed IccMax values for all domains.
IccMax will be selected by CPU SKU in
fill_vr_domain_config function.
BUG=b:145094963
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to device and checked the log.
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add VR config IccMax, DC and AC loadline defaults for CML.
Add cpu_pl2_4_cfg to switch two kinds of VR design.
BUG🅱️145094963
BRANCH:none
TEST:build coreboot and fsp with enabled fw_debug.
Flashed to device and checked the log.
All VR configs were set correctly.
Change-Id: I3922bfad5c21dafc64fb05c7d9343b9835b58752
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
This patch adds CML-H 4+2 SA DID into systemagent.c and report
platform.
According to doc #605546:
CML-H (4+2) R1: 9B64h
BUG:none
BRANCH:none
TEST:build no error
Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit c9b13594eb removed the g_ prefix from
global variables, leaving the local "offset" variable shadowing the
global one. This commit partially reverts this by renaming one of the
occations and converting the flushing logic to work on the
global object.
Change-Id: I246ebdcfd3b973e6a4aa3c15fc5f32497dcf8398
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
After refactoring it is more a status variable rather than
a request.
Change-Id: I50b8099a08b556129416cea50f0ce6fafe6c14cc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only have a single call-site for this.
Change-Id: I7ab19c6ea4ef01334f4d229c5636b64f99c86119
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38182
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only have a single call-site for this.
Change-Id: Ia05a762691351b37cc59b39222fec737b29e913c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These are meaningless for boards without SIO devices.
Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A device object must contain either a _HID object or an _ADR object,
but should not contain both.
Change-Id: I727116cbc38fcd264c684da6ce766ea5e854f58c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
tune eDP delay time to 20 ms ensure satisfy panel spec
BUG=b:147270512
TEST=verify panel sequences by ODM.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes in this patch
1. Remove unused variables
2. Make use of absolute path
3. Define macros and use inside SA ASL
4. Rearrange code in nothbridge.asl to move MCRS object under _CRS
Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
The ACPI spec 6.3 chapter 6.1.10 states that _STR has to return a buffer
containing UTF-16 characters.
Add function to generate Unicode names and use it for _STR. It will
replace non-ASCII characters with '?'.
Use the introduced function in IPMI driver.
Fixes ACPI warning shown in fwts.
Change-Id: I16992bd449e3a51f6a8875731cd45a9f43de5c8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI flashes that support page programming mode had duplicated
the logic for writing in every driver. Add
spi_flash_cmd_write_page_program() and use the common implementation
to reduce code size that comes from duplication. The savings is
~2.5KiB per stage where the spi flash drivers are utilized.
Change-Id: Ie6db03fa8ad33789f1d07a718a769e4ca8bffe1d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.
Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.
You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID
Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.
Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works
No further validation is done on the firmware.
Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add VR config IccMax, DC and AC loadline defaults and voltage regulator
maximum for all CFL, CNL and WHL.
This supports mainboards with replaceable CPUs and provides sane defaults
for boards that are missing the devicetree overwrite.
Remove the default IccMax to make use of the introduced lookup-table.
Also change some hex values to decimal.
I couldn't find CML datasheet, so those are left out for now.
Used Doc #337344 and #338023 Section 7.
Change-Id: I1d2e174157d468830cc0baf2a2d8295ef61a1a63
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37466
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These should have been removed together with read_option().
Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38177
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make it consistent with the more used cmos_write().
Change-Id: I9cf643c770e9819de08dbede48b73f3d4fe15bd7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38178
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As on most other boards, use tabs to indent the devicetree.
Change-Id: If95f1ce6a5347658ecc32097a85b1b6bcc6a1114
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
I expect it to be easier to just remodel the support for i2c
multiplexers instead. Besides, there was no proper bounds for
pbus_num when accessing pbus_a[].
Change-Id: I17f33b308c01e48bc03b142550535c32862442ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is no documentation what hardware this was compatible
with.
Change-Id: I9bfada83388373962929f35794bca56132ee3d9e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is no documentation what hardware this was compatible
with.
Change-Id: Ie8832f1d7f4ca2bc8121f84b1ee564403cc69026
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The guarded prototypes are no longer implemented in the
tree.
Change-Id: I5bfedde2aaf691826e7537eceb8578a855800ea2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There was one user of SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS,
southbridge/intel/common/spi.c. Remove the define and encode
the 1 second timeout that it was wanting at the single use site.
Change-Id: If33a1a04bc4d3441e90bf0ca305ddf71c4f8bb88
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SST25VF064C supports page programming mode like other spi flash
parts in that there isn't an offset requirement. Remove this
check and single byte program because CMD_SST_BP (0x2) is the
same as page programming command. Lastly, for clariy purposes provide
a CMD_SST_PP to explicitly indicate page programming despite the
values (0x2) being the same as byte programming for the other parts.
Change-Id: I84eea0b044ccac6c6f26ea4cb42f4c13cf8f5173
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes all the duplicated code and logic and leverages
the existing ones in libraries themselves. The current side
effect is that protection cannot be fully enabled because the
read, write, and write enable command are not exposed in struct
spi_flash currently. That support can be revised if protection
scheme makes sense for our use-cases once it's better understood.
BUG=b:146928174
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8faf9cc719ee33dd9f03fb74b579b02bbc6a5e2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37957
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure display can't be selected by accident when NO_GFX_INIT is selected.
Change-Id: Iec5a47f84b8c776a45edc6f4b31a03b9ac714b4e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Let the linker trim unused net driver symbols when unused
in devicetree rather than being overly zealous in the Kconfig.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: Ie98d0f9f9b77cb9ee4e52f6c95b68bcbdd94f2cc
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
It is expected that smbuslib.c will be removed, leave the
parts we want to keep in smbus_early.c.
Change-Id: I21355fe95385d07c9f254fc80c90264a9539bb00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add missing Power Management 2, old and new GPIO functions to modify the
contents of these MMIO blocks.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Hide the fundamental BIOSRAM accessors to force use of the
memory space via abstraction functions.
Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up devicetree as nothing special is needed here.
BUG=b:142769041
BRANCH=none
TEST=builds
Change-Id: I0790631233fdcaa6a785d2cb41e79b8f2f469d44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Implement a free() that supports only the last malloc(). Rewind
the heap to the last allocation point if the ptr to be freed is
matching the end of heap before last malloc(). With current situation,
since free() is no-op, every call to malloc() is a memory leak.
BUG=b:140124451
TEST=Wrote a test function to do malloc and free operations.
Change-Id: I6d43cf54b79e6897cf6882335730b2310e4eae45
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not built, relies on SMBUS for SPD and we do not have
a globally defined spd_read_byte() prototype.
Change-Id: Ifb9d3aa31207cb5b99f475b70f52a03aca73432b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
While I was working on updating the headers to move copyrights into
the AUTHORS file, I got a request to switch to SPDX headers as well.
Linux has moved completely to SPDX headers, which are easier to
maintain, have good definitions, are very short, and can be checked
automatically. This is completely unlike our current header situation.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Unlike laptops and some trash cans, desktop boards do not have a lid.
Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}:
Don't use both of _ADR and _HID), but they don't provide any information
and are not referenced anywhere.
Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The majority of Socket AM1 APUs [1] - three out of five - have the integrated
VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID
is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC)
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of these are leftovers from the initial copy from Baytrail.
Change-Id: I1c437f34902400022ac6a5e95ff6168545ca557f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
NIDs 0x18 and 0x19 are flipped, and the verbs for NID 0x1b are instead
applied onto NID 0x1a. Fix that, so that it matches original Chromium
sources for the boards.
Change-Id: I20cc4b282602f8557fa4f25489adf899b7460a09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Looks like the subvendor verb for codec #3 is erroneously using zero as
its codec number. Fix that.
Change-Id: I760533c229287627dd0548a06300c376e045302c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Jasperlake".
2. Replace "icelake_rvp" with "jasperlake_rvp".
3. Rename "icl" with "jsl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
as tigerlake SOC hosts jasperlake code as well.
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
10. Replace icl_u and icl_y variant with jslrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per jasperlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 10MB BIOS region.
TEST=Build jasperlake rvp board
Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Let coreboot know there is a NIC device on the end so
that the mac from vpd is set at early boot.
Properly configure the link-leds in devicetree s.t.
valid values are written out to the register at initialization.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I76ce6d8a5a26842fcb2544ee96567fe0da8603b1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.
Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.
Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
To print times with 1 us resolution just adds unnecessary noise
when comparing logs across different boots. Furthermore, just
the printk itself is 1 ms if some slow console is enabled.
Change-Id: Ibea43124a1937f404a6e71fd9431086b2b72290a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For each boot_state, report the times spent interleaved
with other console output and remove the samples arrays.
The time spent to report the times to console is not
accounted for.
Change-Id: I0c847da98901c56b356b4a933d9ae865dada98b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. See
* src/southbridge/intel/*/lpc.c
Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gnvs structure was zeroed out before calling acpi_create_gnvs(...)
in the following files:
* src/southbridge/intel/*/lpc.c
Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.
This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.
Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent changes to the Atmel touchscreen driver in the mainline
kernel broke functionality with devices running upstream coreboot,
due relying on another driver (chromeos_laptop) which makes the
assumption that the i2c devices are be in PCI mode (as with the
stock Google firmware) rather than in ACPI mode as they are in
upstream coreboot.
Mitigate this by adding the required devicetree property so the
Atmel toushcreen driver will correctly attach without the use
of chromeos_laptop.
Test: build/boot peppy on 4.18+ kernel, verify touchscreen working
Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolò
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.
Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT).
Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Timeless build results in identical image for X230.
Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Timeless build results in identical image for X230.
Change-Id: Ia2bd26b97cb2ae77f29d8978f62d2f6be12b43e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch didn't change the resulting binary for an X230 when using
TIMELESS_BUILD=1
Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Assume that LIMIT_POWER is not requested if the ec does not support it.
Do this by checking the command code in the response message instead
of return value.
BUG=b:146165519
BRANCH=None
TEST=Boot puff with EC which does not support LIMIT_POWER param.
Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already.
Change-Id: I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When checking that command and data fit in the FIFO, don't count the first
byte. The command doesn't go through the FIFO.
TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550
Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martinroth@google.com>
free() is not needed since the memory is not dynamically allocated.
Change-Id: I90659722aaca6ced1e1cbc3db4180b0811205e95
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The gnvs structure was zeroed out already in the following files:
* src/southbridge/intel/i82801ix/lpc.c (t400 and x200)
* src/southbridge/intel/i82801gx/lpc.c (thinkcentre_a58)
Change-Id: Id7d552e1c4084a0b36b98f9627a85a75c8b90e81
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
We found the driver binding failure issue could be cleared with 100ms
of "reset_delay_ms". Needs further check with device vendor, anyway it
seems the IC need some time before communication after de-assertion of
reset.
BUG=b:129159369
BRANCH=firmware-hatch-12672.B
TEST=Verified driver bound successfully.
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Iccb33c13c9a390a2c971325c74c0c4ad4b08618e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are no symmetrical headerfiles for other arch/ and
after ROMCC_BOOTBLOCK and walkcbfs() removal this file
ended up empty.
Change-Id: Ice3047630ced1f1471775411b93be6383f53e8bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power
limits to reasonable defaults and can wedge the AP by browning out at
the end of vboot.
BRANCH=none
BUG=b:146165519
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Codec vendor ID was copy/pasted from Haswell, should be
0x80862808. Subsystem ID for Intel Mini-HD is always 0x80860101.
Change-Id: Idf4446d3437de0dc533baa3b2b4eb49f816807a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
related LTE GPIOs:
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:146843935
BRANCH=octopus
TEST=build and verify on the DUT with LTE
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Ief6c993ede2bb4b3effbb05cfe22b7af4fcf7faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
get_board_sku to smm stage.
fix Power_off section power sequence.
power_off_lte_module() should run in smm stage, add variant.c in smm stage.
also move get_board_sku() to mainboard_misc.c so that we can use it in smm stage
and ramstage.
BUG=b:144327240
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I287ba1cb092a95b3a9dd1f960a3b84fd85b9b221
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37649
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits.
Restore the PM bits when exit s0ix/Sx.
BUG=b:144002424
TEST=Check GPIO PM bits when enter/exit s0ix are expected
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a new driver to support reading a board serial number from
a text file in CBFS and injecting into the SMBIOS tables.
Allow driver to be selected at the .config level and not require
inclusion at the board level.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Revert two of the changes made in
"arch|cpu/x86: Add Kconfig option for x86 reset vector"
I6a814f7179ee4251aeeccb2555221616e944e03d
The Intel FIT pointer and the ID section should be offsets from the
top of flash, and aren't inherently tied to the reset vector or to
bootblock.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The APOB NV region holds the save data for resuming. Omit it if the
mainboard doesn't use HAVE_ACPI_RESUME.
The APOB information will also be board-specific so remove the
default values.
Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
300ns
According to SI team and vendor request, need to tune I2C bus
0 data hold time more than 300ns
BUG=b:146163044
TEST=build firmware and measure I2C bus 0 data hold time
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I75e33419cbaef746487de6ee8628d07cf08adaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37322
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Eve's VBT from v211 to v221, and change the backlight
control type from PWM to VESA eDP/AUX. This allows the OS to
select the proper backlight control type for the panel.
Test: Eve backlight control now functional under Windows 10
(Linux requires some pending patches to fix)
Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In https://review.coreboot.org/c/coreboot/+/37459
(commit fcd8c9e99e) which moves power/reset
pin control of FPMCU to var/board/ramstage, but does not implement it for
dratini/jinlon. So, add it in dratini/jinlon.
BUG=b:146366921
TEST=emerge-hatch coreboot
Change-Id: I1b6dbe4ba0a1242aa64346410beed4152b4f457f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37833
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes below clean-up for report_cpu_info() function.
1. Remove unused variables.
3. Reuse fill_processor_name.
TEST = Successfully able to boot hatch and verify the
cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz"
Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like TCO
configuration and SMBus init into romstage/pch.c in order to maintain only
required chipset programming for bootblock and verstage.
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot hatch successfully.
Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch renames pch_init function to bootblock_pch_init and
romstage_pch_init according to the stage it is defined in.
TEST=Able to build and boot soraka successfully.
Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The change applies the DPTF parameters received from the thermal team.
BUG=b:146540028
TEST=build and verified by thermal team.
Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions
to wire SuperSpeed-capable ports to XHCI in its devicetree, causing
these ports being wired to the second EHCI, and only working as USB
2.0 ports. The missing register definitions are added to fix that.
Tested on my ga-b75-d3v board.
Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Location of _start16bit in entry16.inc is about to see some changes,
lets make sure they don't break the alignment requirement here.
Change-Id: Id8a0964982387e5321e8c89254922e1242cf85ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c',
following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The same default values are used if the values are not present in devicetree.
Change-Id: Ic910cdc8077e1b3e98eadc77a2d1fa0f9cb38e5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Michael Niewöhner
If the board doesn't provide VRconfig in devicetree make sure to use
the lookup table for IccMax instead of defaults for some mobile SoC.
Also use decimal values instead of hex.
Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37598
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_C15 group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_A* group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To be safe for now, don't differentiate between SKUs and use lower
values to ensure board won't be browned out.
BUG=b:143246320
TEST=none
BRANCH=none
Change-Id: I041ebaa33bf2582386198290e625099ba8e2f3c9
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37651
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the values to be set in a .config
BUG=none
TEST=Was able to set the value from a .config and built careena firmware
Change-Id: I757e4b9a0b80ff42c1f49143a44f15550366fd0b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37879
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generally work towards a more loose baseboard definition by moving out
some original assumptions to be board specifics. Specifically Puff does
not have the MAX98357A speaker amp and enabling the driver winds up
generating incorrect SSDT tables that confuse the kernel. Since
devicetree inherits the chip from device node in base and an override
will also inherit the chip and thus dispatch the unwanted fill_ssdt fn
call.
V.2: lean on linker to drop max98357a driver when not in dt.
BRANCH=none
BUG=b:146519004
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37909
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Two things here:
i. ) FSP requires that function 0 be enabled whenever any non-zero
functions hang under the same bus:device.
ii.) FSP reorders function 6 RP to be function 0 if function 0 is
indeed unused.
BUG=b:146437819
BRANCH=none
TEST=none
Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Make use of introduced SSDT config mode access
* Make use of introduced SSDT mutex
* Provide ACPI functions to safely access SIO config space
* Implement method to query LDN enable state
* Implement method to set LDN enable state
* Use introduced functions to implement _DIS and _STA in the device
* Update documentation
Tested on Aspeed AST2500 and Linux 5.2.
Manually verified ACPI code that generates no errors in Linux.
Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add functions to write ACPI SSDT code for entering and leaving
the config mode.
To be used by ACPI generators.
Tested on Linux 5.2 using the Aspeed SSDT generator.
Change-Id: I14b55b885f1c384536bafafed39ad399639868e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
As discussed in CB:35077, since both measured boot and verified boot
depends on vboot library, it had better to introduce a dedicated flag
CONFIG_VBOOT_LIB to control the building and linking of the vboot
library, and make other flags needing vboot library select it. Only
the actual verification stuff should be conditional on CONFIG_VBOOT.
Change-Id: Ia1907a11c851ee45a70582e02bdbe08fb18cc6a4
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.
BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PCI devices starting from 18 are processor configuration devices for each
node and are not a bus itself.
According to ACPI specification 6.3 section 6.1.5:
"... _HID object must be used to describe any device that will be
enumerated by OSPM. OSPM only enumerates a device when no bus enumerator
can detect the device ID. ... Use the _ADR object to describe devices
enumerated by bus enumerators other than OSPM."
PCI device 18 with its functions has a standard enumerator, which is PCI
enumerator so it needs a _ADR. Create a separate ACPI device for the
processor configuration space. This fixes the ACPI compliance problem
from CB:36318.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MIC1 NID is configured incorrectly because of a typo. The value is 7
digits instead of 8. This is corrected by this patch.
No issues are known because of this (the MIC is not connected).
BUG=N/A
TEST=build
Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of
the chipset specific FSP structures.
Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.
BUG=NA
TEST= Build and verified logo is displayed on Facebook FBG1701
Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37791
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to remove min/max() from <stdlib.h>.
Change-Id: Ica03d9aec8a81f57709abcac655dfb0ebce3f8c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37818
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use MIN() and MAX() defined in commonlib/helpers.h
Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No improvement was measured with this applied.
Change-Id: I99166e03f2580828c66305326f5141d956707f08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37754
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding extra USB configuration since Puff has different USB ports compared to hatch
BRANCH=none
BUG=b:146437609
TEST=none
Change-Id: I42ef6b6b718274953711c84ebe90971f108501fa
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Missing bus init for RTL8111H ethernet chip hanging on bus.
V.2: Include admendments from Kangheui.
BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Seems nothing special is needed here from coreboot.
V.2: Fix typo as well in speed map.
BRANCH=none
BUG=b:143047058
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ief750f98677b2017af78fb0b5bc98e1492dedbe4
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the old Stoney Ridge postcar stack frame setup. Reduce
romstage.c to basic functionality. Until AGESA's reporting of
memory configuration is available, use the TOM register as an
indicator for the top of usable memory.
Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
No AGESA v5 binaryPI features are still present in the picasso directory.
Remove the PI and S3 selects. Remove DCACHE symbols. Remove all vboot
options until the new PSP-based solution is developed.
Change-Id: I6542578afafc0ee3c3117a971b1a021dbe53f42c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar
from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It was possible to have NO_STAGE_CACHE=n and at the same time have
TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a
failing attempt to load STAGE_POSTCAR from the stage cache, but not
loading it from CBFS either.
Make it a three-way choice between different STAGE_CACHE options.
For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer
needed to have functional ACPI S3 resume and it is not allowed
se use keyword select for symbols inside choice blocks.
Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ends of a PCIe link may advertise different Max_Payload_Size in
their PCIe Express Capabilities, Device Capabilities block.
For correct operation, both ends of the link need to have their
Device Control Max_Payload_Size programmed to match and not
exceed the other end's Device Capabilities.
Fixes: https://ticket.coreboot.org/issues/218
Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which
are chipset specific.
Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.
BUG=NA
TEST= Build and verified logo is displayed on Facebook Monolith
Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current build rules require adding blank acpi_tables in some of the
mainboards (eg. octopus, hatch). Update the build rules to compile the
acpi_tables.c only if it is present. This will help to avoid adding
blank acpi_tables.c source file.
BUG=None
TEST=Build test with octopus and hatch without blank acpi_table.c file.
Change-Id: I7dfacc6f4c737699b22acd96e17c9426d33574bd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Implemented according to IPMI "Platform Management
FRU Information Storage Definition" specification
v1.0 for reading FRU data Product Info Area and
Board Info Area.
SMBIOS data can be updated with the FRU data.
Tested on OCP Mono Lake.
Change-Id: Id6353f5ce3f7ddd3bb161b91364b3cf276d020b8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
(cherry picked from commit 8ac46b937c)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37095
Emmc spec, JEDEC Standard No. 84-B51, section 6.6.2.3, selection
flow of HS400 using Enhanced Strobe states that host should change
frequency to ≤ 52MHz when switching to HS speed mode first. In
current code, mmc_select_hs400() calls mmc_select_hs() to do this,
however caps are not cleared, so when switching from HS200 to HS400,
caps will still have DRVR_CAP_HS200, and mmc_recalculate_clock() will
set 200Mhz instead of ≤ 52MHz. As a result, switching to HS400 will
intermittently fail.
BUG=b:140124451
TEST=Switch speed from HS200 to HS400 on WHL RVP.
Change-Id: Ie639c7616105cca638417d7bc1db95b561afb7af
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37775
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion only supports on board dimm. Remove the spd read from
SMBus. Since CB:37678 remove the Wilco 1.0 CML variants, weak function
is not needed.
BUG=b:140068267
TEST=boot into OS without issue
BRANCH=none
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I662f87ccf48ba470998fa28fb14c9985673cb37d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37780
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion supports D3 hot not D3 cold. Remove the code which used
for Wilco 1.0 CML.
BUG=b:140068267
TEST=boot into OS without any issues
BRANCH=none
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifc83fae7ac462d3e6595742d96952c2a2607c88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Mike Wiitala <mwiitala@google.com>
Angel Pons